https://github.com/sstwcw created
https://github.com/llvm/llvm-project/pull/71353
If a line contains a comment outside of (fake) parentheses, the part following
it is indented according to `CurrentState.Indent`. A Verilog case label and
the statement that follows are broken with mustBreakBefore. So the part that
follows the case label needs some special handling. Previously, that variable
was left out. So the indentation was wrong when there was a comment.
old:
```Verilog
case (data)
16'd0:
result = //
10'b0111111111;
endcase
case (data)
16'd0:
//
//
result = //
10'b0111111111;
endcase
```
new:
```Verilog
case (data)
16'd0:
result = //
10'b0111111111;
endcase
case (data)
16'd0:
//
//
result = //
10'b0111111111;
endcase
```
>From 0f191a5972b1e937cdf63994e438cd769e758919 Mon Sep 17 00:00:00 2001
From: sstwcw <su3e8a96kzl...@posteo.net>
Date: Mon, 6 Nov 2023 03:26:02 +0000
Subject: [PATCH] [clang-format] Indent Verilog case statements with comments
If a line contains a comment outside of (fake) parentheses, the part
following it is indented according to `CurrentState.Indent`. A Verilog
case label and the statement that follows are broken with
mustBreakBefore. So the part that follows the case label needs some
special handling. Previously, that variable was left out. So the
indentation was wrong when there was a comment.
old:
```Verilog
case (data)
16'd0:
result = //
10'b0111111111;
endcase
case (data)
16'd0:
//
//
result = //
10'b0111111111;
endcase
```
new:
```Verilog
case (data)
16'd0:
result = //
10'b0111111111;
endcase
case (data)
16'd0:
//
//
result = //
10'b0111111111;
endcase
```
---
clang/lib/Format/ContinuationIndenter.cpp | 5 ++++-
clang/unittests/Format/FormatTestVerilog.cpp | 14 ++++++++++++++
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Format/ContinuationIndenter.cpp
b/clang/lib/Format/ContinuationIndenter.cpp
index 3a829cdedb77fc7..17a039abb30f8da 100644
--- a/clang/lib/Format/ContinuationIndenter.cpp
+++ b/clang/lib/Format/ContinuationIndenter.cpp
@@ -1208,8 +1208,10 @@ unsigned ContinuationIndenter::getNewLineColumn(const
LineState &State) {
// Indentation of the statement following a Verilog case label is taken care
// of in moveStateToNextToken.
- if (Style.isVerilog() && Keywords.isVerilogEndOfLabel(Previous))
+ if (Style.isVerilog() && PreviousNonComment &&
+ Keywords.isVerilogEndOfLabel(*PreviousNonComment)) {
return State.FirstIndent;
+ }
if (Style.BreakBeforeBraces == FormatStyle::BS_Whitesmiths &&
State.Line->First->is(tok::kw_enum)) {
@@ -1612,6 +1614,7 @@ unsigned
ContinuationIndenter::moveStateToNextToken(LineState &State,
State.NextToken->MustBreakBefore &&
Keywords.isVerilogEndOfLabel(Current)) {
State.FirstIndent += Style.IndentWidth;
+ CurrentState.Indent = State.FirstIndent;
}
unsigned Penalty =
diff --git a/clang/unittests/Format/FormatTestVerilog.cpp
b/clang/unittests/Format/FormatTestVerilog.cpp
index 1c2692467987d9b..9d5306c039ec334 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -344,6 +344,20 @@ TEST_F(FormatTestVerilog, Case) {
" longfunction( //\n"
" arg);\n"
"endcase");
+ verifyFormat("case (data)\n"
+ " 16'd0:\n"
+ " //\n"
+ " result = //\n"
+ " 10'b0111111111;\n"
+ "endcase");
+ verifyFormat("case (data)\n"
+ " 16'd0:\n"
+ " //\n"
+ "\n"
+ " //\n"
+ " result = //\n"
+ " 10'b0111111111;\n"
+ "endcase");
Style = getDefaultStyle();
Style.ContinuationIndentWidth = 1;
verifyFormat("case (data)\n"
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