[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

SamTebbs33 wrote: > FYI I pushed > [3a9cc17](https://github.com/llvm/llvm-project/commit/3a9cc17ca088267348e4b4a6e64a88a38ae9c6e4) > to hopefully unbreak the build. Thank you! https://github.com/llvm/llvm-project/pull/71688 ___ cfe-commits mailing l

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

nikic wrote: FYI I pushed https://github.com/llvm/llvm-project/commit/3a9cc17ca088267348e4b4a6e64a88a38ae9c6e4 to hopefully unbreak the build. https://github.com/llvm/llvm-project/pull/71688 ___ cfe-commits mailing list cfe-commits@lists.llvm.org htt

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

https://github.com/SamTebbs33 closed https://github.com/llvm/llvm-project/pull/71688 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

@@ -1987,8 +1987,26 @@ defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">; // SME intrinsics which operate only on vectors and do not require ZA should be added here, // as they could possibly become SVE instructions in the future. +multiclass MinMaxIntr {

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

https://github.com/SamTebbs33 edited https://github.com/llvm/llvm-project/pull/71688 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

@@ -1987,8 +1987,26 @@ defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">; // SME intrinsics which operate only on vectors and do not require ZA should be added here, // as they could possibly become SVE instructions in the future. +multiclass MinMaxIntr {

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

https://github.com/kmclaughlin-arm edited https://github.com/llvm/llvm-project/pull/71688 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

https://github.com/kmclaughlin-arm approved this pull request. Thanks @SamTebbs33, I just have one small suggestion but otherwise this LGTM. https://github.com/llvm/llvm-project/pull/71688 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https:/

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

@@ -296,5 +296,28 @@ multiclass ZAAddSub { } } + +// SME2 - MIN, MAX + +multiclass MinMaxIntr { + def SVS # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "csil", MergeNone, "aa

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

@@ -0,0 +1,1562 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -D__ARM_FEATURE_SME -D__ARM_FEATURE_SME2 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llv

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

@@ -296,5 +296,28 @@ multiclass ZAAddSub { } } + +// SME2 - MIN, MAX + +multiclass MinMaxIntr { + def SVS # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "csil", MergeNone, "aa

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

@@ -0,0 +1,1562 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -D__ARM_FEATURE_SME -D__ARM_FEATURE_SME2 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llv

[clang] [Clang][SME2] Add single and multi min and max builtins (PR #71688)

llvmbot wrote: @llvm/pr-subscribers-clang Author: Sam Tebbs (SamTebbs33) Changes Adds the following SME2 builtins: svmin_single_(s8|s16|s32|s64)_x(2|4) svmin_single_(u8|u16|u32|u64)_x(2|4) svmin_single_(f16|f32|f64)_x(2|4) svmin_(s8|s16|s32|s64)_x(2|4) svmin_(u8|u16|u3