================
@@ -1987,8 +1987,26 @@ defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl",
"aarch64_sve_revd">;
// SME intrinsics which operate only on vectors and do not require ZA should
be added here,
// as they could possibly become SVE instructions in the future.
+multiclass MinMaxIntr<string i, string zm, string mul, string t> {
+ def SVS # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "csil",
MergeNone, "aarch64_sve_s" # i # zm # "_" # mul, [IsStreaming], []>;
+ def SVU # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t,
"UcUsUiUl", MergeNone, "aarch64_sve_u" # i # zm # "_" # mul, [IsStreaming], []>;
+ def SVF # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "hfd",
MergeNone, "aarch64_sve_f" # i # zm # "_" # mul, [IsStreaming], []>;
+}
+
let TargetGuard = "sme2" in {
// == ADD (vectors) ==
def SVADD_SINGLE_X2 : SInst<"svadd[_single_{d}_x2]", "22d", "cUcsUsiUilUl",
MergeNone, "aarch64_sve_add_single_x2", [IsStreaming], []>;
def SVADD_SINGLE_X4 : SInst<"svadd[_single_{d}_x4]", "44d", "cUcsUsiUilUl",
MergeNone, "aarch64_sve_add_single_x4", [IsStreaming], []>;
+
+// == SMAX / UMAX / FMAX ==
+ defm MAX_SINGLE_X2 : MinMaxIntr<"max", "_single", "x2", "22d">;
+ defm MAX_MULTI_X2 : MinMaxIntr<"max", "", "x2", "222">;
+ defm MAX_SINGLE_X4 : MinMaxIntr<"max", "_single", "x4", "44d">;
+ defm MAX_MULTI_X4 : MinMaxIntr<"max", "", "x4", "444">;
+
+// == SMIN / UMIN / FMIN ==
+ defm MIN_SINGLE_X2 : MinMaxIntr<"min", "_single", "x2", "22d">;
+ defm MIN_MULTI_X2 : MinMaxIntr<"min", "", "x2", "222">;
+ defm MIN_SINGLE_X4 : MinMaxIntr<"min", "_single", "x4", "44d">;
+ defm MIN_MULTI_X4 : MinMaxIntr<"min", "", "x4", "444">;
----------------
SamTebbs33 wrote:
Thank you, I agree. I've done that now and will go ahead and merge.
https://github.com/llvm/llvm-project/pull/71688
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