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Closed by commit rG5ba931a84a34: [Mips] Add intrinsics for 4-byte and 8-byte
MSA loads/stores. (authored by mbrkusanin).
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mbrkusanin updated this revision to Diff 243775.
mbrkusanin edited the summary of this revision.
mbrkusanin added a comment.
- Rebase
- Rename **ldrq_w** to **ldr_w**; Rename **strq_w** to **str_w**.
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atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.
Looking good to me as-is.
- Current naming is okay. But what do you think about reducing name of
//quarter// intrinsics: `__builtin_msa_ldr_w` instead of
`__builtin_msa_ldrq_w`? Will it
mbrkusanin added a comment.
Not yet, a proposal was made to both GCC and LLVM and as far as I can tell no
work was done on GCC yet. If we accept these names I'll let them know so we end
up with matching names.
As for 4/8 byte loads, in case of having them implemented as **ld** plus some
extra
mbrkusanin added a comment.
Rebase.
Not yet, a proposal was made to both GCC and LLVM and as far as I can tell no
work was done on that yet. If we accept these names I'll let them know so we
end up with matching names.
As for 4/8 byte loads, in case of having them implemented as **ld** plus so
mbrkusanin updated this revision to Diff 243153.
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Files:
clang/include/clang/Basic/BuiltinsMips.def
clang/lib/Headers/msa.h
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsMips.
atanasyan added a comment.
I see, thanks. Is there the same or similar functionality in GCC?
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___
cfe-commits mai
mbrkusanin added a comment.
We could do that for loads. For example on Mips32r5 (where we need most
instructions) for intrinsic **ldr_d** instead of:
lwr $1, 16($5)
lwl $1, 19($5)
lwr $2, 20($5)
lwl $2, 23($5)
fill.w $w0, $1
insert
atanasyan added a comment.
Is it possible to emulate these new intrinsics using existing ones and some
additional code? Is code generated in this case much larger/slower then the
code generated by the new intrinsics?
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mbrkusanin added a comment.
A few notes/questions:
1. Generated code was tested with Qemu:
- For mips32r5 Qemu provides p5600
- For mips64r6 Qemu provides i6400
- For mips64r5 there is no cpu on Qemu with MSA and it appears that there
won't be any hardware with Mips64r5 and MSA.
- For mi
mbrkusanin created this revision.
mbrkusanin added reviewers: atanasyan, petarj, sdardis, mstojanovic.
mbrkusanin added projects: LLVM, clang.
Herald added subscribers: cfe-commits, jrtc27, hiraditya, arichardson.
New intrinisics are implemented for when we need to port SIMD code from other
arhit
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