This revision was automatically updated to reflect the committed changes.
Closed by commit rGb77d6f51ba4e: [RISCV] Add Scheduling information for Zfh to
SiFive7 model (authored by michaelmaitland).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D149498
michaelmaitland updated this revision to Diff 518925.
michaelmaitland added a comment.
Rebase.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D149498/new/
https://reviews.llvm.org/D149498
Files:
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
Index: l
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.
LGTM
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D149498/new/
https://reviews.llvm.org/D149498
___
michaelmaitland added inline comments.
Comment at: clang/test/Driver/riscv-cpus.c:176
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-tar
craig.topper added inline comments.
Comment at: clang/test/Driver/riscv-cpus.c:176
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target
michaelmaitland updated this revision to Diff 518089.
michaelmaitland added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Add zfh to `clang/test/Driver/riscv-cpus.c`
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D1
