[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

[Michael Maitland via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb77d6f51ba4e: [RISCV] Add Scheduling information for Zfh to 
SiFive7 model (authored by michaelmaitland).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149498/new/

https://reviews.llvm.org/D149498

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td


Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -110,6 +110,7 @@
 def : WriteRes<WriteSTH, [SiFive7PipeA]>;
 def : WriteRes<WriteSTW, [SiFive7PipeA]>;
 def : WriteRes<WriteSTD, [SiFive7PipeA]>;
+def : WriteRes<WriteFST16, [SiFive7PipeA]>;
 def : WriteRes<WriteFST32, [SiFive7PipeA]>;
 def : WriteRes<WriteFST64, [SiFive7PipeA]>;
 
@@ -121,6 +122,7 @@
 }
 
 let Latency = 2 in {
+def : WriteRes<WriteFLD16, [SiFive7PipeA]>;
 def : WriteRes<WriteFLD32, [SiFive7PipeA]>;
 def : WriteRes<WriteFLD64, [SiFive7PipeA]>;
 }
@@ -136,6 +138,22 @@
 def : WriteRes<WriteAtomicLDD, [SiFive7PipeA]>;
 }
 
+// Half precision.
+let Latency = 5 in {
+def : WriteRes<WriteFAdd16, [SiFive7PipeB]>;
+def : WriteRes<WriteFMul16, [SiFive7PipeB]>;
+def : WriteRes<WriteFMA16, [SiFive7PipeB]>;
+}
+let Latency = 3 in {
+def : WriteRes<WriteFSGNJ16, [SiFive7PipeB]>;
+def : WriteRes<WriteFMinMax16, [SiFive7PipeB]>;
+}
+
+let Latency = 14, ResourceCycles = [1, 13] in {
+def :  WriteRes<WriteFDiv16, [SiFive7PipeB, SiFive7FDiv]>;
+def :  WriteRes<WriteFSqrt16, [SiFive7PipeB, SiFive7FDiv]>;
+}
+
 // Single precision.
 let Latency = 5 in {
 def : WriteRes<WriteFAdd32, [SiFive7PipeB]>;
@@ -170,21 +188,33 @@
 
 // Conversions
 let Latency = 3 in {
+def : WriteRes<WriteFCvtI32ToF16, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtI32ToF32, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtI32ToF64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtI64ToF16, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtI64ToF32, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtI64ToF64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF16ToI32, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF16ToI64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF16ToF32, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF16ToF64, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtF32ToI32, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtF32ToI64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF32ToF16, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtF32ToF64, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtF64ToI32, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtF64ToI64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCvtF64ToF16, [SiFive7PipeB]>;
 def : WriteRes<WriteFCvtF64ToF32, [SiFive7PipeB]>;
 
+def : WriteRes<WriteFClass16, [SiFive7PipeB]>;
 def : WriteRes<WriteFClass32, [SiFive7PipeB]>;
 def : WriteRes<WriteFClass64, [SiFive7PipeB]>;
+def : WriteRes<WriteFCmp16, [SiFive7PipeB]>;
 def : WriteRes<WriteFCmp32, [SiFive7PipeB]>;
 def : WriteRes<WriteFCmp64, [SiFive7PipeB]>;
+def : WriteRes<WriteFMovI16ToF16, [SiFive7PipeB]>;
+def : WriteRes<WriteFMovF16ToI16, [SiFive7PipeB]>;
 def : WriteRes<WriteFMovI32ToF32, [SiFive7PipeB]>;
 def : WriteRes<WriteFMovF32ToI32, [SiFive7PipeB]>;
 def : WriteRes<WriteFMovI64ToF64, [SiFive7PipeB]>;
@@ -224,36 +254,55 @@
 def : ReadAdvance<ReadAtomicSTD, 0>;
 def : ReadAdvance<ReadFStoreData, 0>;
 def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFAdd16, 0>;
 def : ReadAdvance<ReadFAdd32, 0>;
 def : ReadAdvance<ReadFAdd64, 0>;
+def : ReadAdvance<ReadFMul16, 0>;
+def : ReadAdvance<ReadFMA16, 0>;
 def : ReadAdvance<ReadFMul32, 0>;
 def : ReadAdvance<ReadFMul64, 0>;
 def : ReadAdvance<ReadFMA32, 0>;
 def : ReadAdvance<ReadFMA64, 0>;
+def : ReadAdvance<ReadFDiv16, 0>;
 def : ReadAdvance<ReadFDiv32, 0>;
 def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt16, 0>;
 def : ReadAdvance<ReadFSqrt32, 0>;
 def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp16, 0>;
 def : ReadAdvance<ReadFCmp32, 0>;
 def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ16, 0>;
 def : ReadAdvance<ReadFSGNJ32, 0>;
 def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax16, 0>;
 def : ReadAdvance<ReadFMinMax32, 0>;
 def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF16ToI32, 0>;
+def : ReadAdvance<ReadFCvtF16ToI64, 0>;
 def : ReadAdvance<ReadFCvtF32ToI32, 0>;
 def : ReadAdvance<ReadFCvtF32ToI64, 0>;
 def : ReadAdvance<ReadFCvtF64ToI32, 0>;
 def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF16, 0>;
 def : ReadAdvance<ReadFCvtI32ToF32, 0>;
 def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF16, 0>;
 def : ReadAdvance<ReadFCvtI64ToF32, 0>;
 def : ReadAdvance<ReadFCvtI64ToF64, 0>;
 def : ReadAdvance<ReadFCvtF32ToF64, 0>;
 def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFCvtF16ToF32, 0>;
+def : ReadAdvance<ReadFCvtF32ToF16, 0>;
+def : ReadAdvance<ReadFCvtF16ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF16, 0>;
+def : ReadAdvance<ReadFMovF16ToI16, 0>;
+def : ReadAdvance<ReadFMovI16ToF16, 0>;
 def : ReadAdvance<ReadFMovF32ToI32, 0>;
 def : ReadAdvance<ReadFMovI32ToF32, 0>;
 def : ReadAdvance<ReadFMovF64ToI64, 0>;
 def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass16, 0>;
 def : ReadAdvance<ReadFClass32, 0>;
 def : ReadAdvance<ReadFClass64, 0>;
 
@@ -446,5 +495,4 @@
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedZfh;
 }

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