[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli marked an inline comment as done. fpetrogalli added inline comments. Comment at: llvm/include/llvm/TargetParser/CMakeLists.txt:3 +tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/) +add_public_tablegen_target(RISCVT

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

sebastian-ne added a comment. FYI, the CMake file should use `PROJECT_SOURCE_DIR` instead of `CMAKE_SOURCE_DIR`, otherwise it breaks builds that use CMake’s add_subdirectory. I put up D141521 to fix that. Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. In D137517#4045337 , @jrtc27 wrote: > In D137517#4045315 , @fpetrogalli > wrote: > >> In D137517#4045299 , @jrtc27 wrote: >> >>> In D137517#4

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

jrtc27 added a comment. In D137517#4045315 , @fpetrogalli wrote: > In D137517#4045299 , @jrtc27 wrote: > >> In D137517#4042875 , @fpetrogalli >> wrote: >> >>> In D137517

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli marked an inline comment as done. fpetrogalli added a comment. In D137517#4045299 , @jrtc27 wrote: > In D137517#4042875 , @fpetrogalli > wrote: > >> In D137517#4042758

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

jrtc27 added a comment. In D137517#4042875 , @fpetrogalli wrote: > In D137517#4042758 , @fpetrogalli > wrote: > >> After submitting this, I had to revert it >>

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper added inline comments. Comment at: llvm/include/llvm/TargetParser/CMakeLists.txt:3 +tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/) +add_public_tablegen_target(RISCVTargetParserTableGen) + fpetr

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli marked an inline comment as done. fpetrogalli added inline comments. Comment at: llvm/include/llvm/TargetParser/CMakeLists.txt:3 +tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/) +add_public_tablegen_target(RISCVT

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

thakis added inline comments. Comment at: llvm/include/llvm/TargetParser/CMakeLists.txt:3 +tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/) +add_public_tablegen_target(RISCVTargetParserTableGen) + All other t

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. In D137517#4042758 , @fpetrogalli wrote: > After submitting this, I had to revert it > > because of failures like > https://lab.llvm.or

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. After submitting this, I had to revert it because of failures like https://lab.llvm.org/buildbot/#/builders/225/builds/12367/steps/5/logs/stdio Repository: rG LLVM Github Mono

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

This revision was automatically updated to reflect the committed changes. Closed by commit rGcf7a8305a2b4: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen. (authored by fpetrogalli). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 487962. fpetrogalli added a comment. Formatting changes in RISCV.td (NFC). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 Files: clang/lib/Basic/Targets/RISCV.

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

jrtc27 added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:581 + list f = []> + : ProcessorModel; + Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https:

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 ___

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. Gentle ping! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 486223. fpetrogalli added a comment. [NFC] Restore empty line before end of namespace. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 Files: clang/lib/Basic/Ta

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 486222. fpetrogalli added a comment. I have addressed last round of review from @craig.topper and @pcwang-thead: 1. Renamed the RISCV-specific classes for the ProcessorModel. 2. Swapped `tunef` with `f` in `RISCVTuneProcessorModel`. 3. Fixed comment. 4. A

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:568 -def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>; -def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; +class RISCVProcessorModelPROCRISCVProcessorModel? RISCVP

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:572 + string default_march = "", + list tunef = []> : ProcessorModel { + string DefaultMarch = default_march; 80 columns

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. @craig.topper @lenary @barannikov88 @pcwang-thead - New Year's gentle ping :) Thank you, Francesco Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 __

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 485858. fpetrogalli added a comment. Fix pre-merge check at https://buildkite.com/llvm-project/premerge-checks/builds/128468#0185724f-5ade-4603-99ce-f417efb546e8 (missing header inclusion): C:\ws\w3\llvm-project\premerge-checks\llvm\include\llvm/Targ

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 485852. fpetrogalli added a comment. NFC - just an update on top of current `main`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 Files: clang/lib/Basic/Targe

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. > @pcwang-thead, may I ask you to own these further optimisations of the > generative process, and submit a patch for it after the current patch lands? > I'd happily review it! > > The reason I am asking this is because the current patch is mostly dealing > with ma

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. In D137517#4012449 , @pcwang-thead wrote: > In D137517#4012307 , @craig.topper > wrote: > >> In D137517#4012298 , @pcwang-thead >> wrote: >

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484795. fpetrogalli added a comment. I added some fixes to make it work when building with modules (`-DLLVM_ENABLE_MODULES=On`). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.ll

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. In D137517#4012307 , @craig.topper wrote: > In D137517#4012298 , @pcwang-thead > wrote: > >> In D137517#4009175 , @fpetrogalli >> wrote: >

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper added a comment. In D137517#4012298 , @pcwang-thead wrote: > In D137517#4009175 , @fpetrogalli > wrote: > >> @pcwang-thead, I addressed some of your comments. >> >> The value of `EnumFeatures` is no

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

pcwang-thead added a comment. In D137517#4009175 , @fpetrogalli wrote: > @pcwang-thead, I addressed some of your comments. > > The value of `EnumFeatures` is now computed dynamicaly from the > `Features` field of the `Processor` class. Thanks! That soun

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added inline comments. Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:52 + for (auto &Def : Map) { +const auto &Record = Def.second; +if (Record->isSubClassOf("RISCVProcessorModelTUNE_PROC")) barannikov88 wrote: > fpetrogalli wrote

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484664. fpetrogalli marked an inline comment as done. fpetrogalli added a comment. Remove all `auto` types in the emitter. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. In D137517#4009328 , @jrtc27 wrote: > Hm, this means that llvm/lib/Target/$TARGET/$TARGET.td needs to remain > working (or at least mostly working, things like ISel patterns can fail to > type check) in order for Clang to bu

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

barannikov88 added inline comments. Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:52 + for (auto &Def : Map) { +const auto &Record = Def.second; +if (Record->isSubClassOf("RISCVProcessorModelTUNE_PROC")) fpetrogalli wrote: > barannikov88 wrot

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484658. fpetrogalli marked an inline comment as done. fpetrogalli added a comment. Remove `RISCVTargetParser.def` from the module map. Follow the guidelines on using namespace llvm

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484655. fpetrogalli added a comment. Restore the following... -const auto *Record = Def.second; +const auto &Record = Def.second; ... to prevent this error: /<...>/llvm-project/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:38:17: error: v

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484654. fpetrogalli marked an inline comment as done. fpetrogalli added a comment. ops - this was wrong: /Users/fpetrogalli/projects/cpu-defs/upstream/llvm-project/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:38:17: error: variable 'Record' with type

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli marked an inline comment as done. fpetrogalli added inline comments. Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:52 + for (auto &Def : Map) { +const auto &Record = Def.second; +if (Record->isSubClassOf("RISCVProcessorModelTUNE_PROC")) --

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli marked an inline comment as done. fpetrogalli added inline comments. Comment at: llvm/lib/TargetParser/CMakeLists.txt:29 +# LLVMTargetParser. See https://stackoverflow.com/a/25681179 +target_include_directories(LLVMTargetParser PUBLIC $) barannikov88

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

barannikov88 added inline comments. Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:16 +#include +namespace llvm { + fpetrogalli wrote: > barannikov88 wrote: > > This [[ > > https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-implem

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added inline comments. Comment at: llvm/utils/TableGen/RISCVTargetDefEmitter.cpp:15 +#include "llvm/TableGen/Record.h" +#include +namespace llvm { barannikov88 wrote: > [[ > https://llvm.org/docs/CodingStandards.html#include-iostream-is-forbidden |

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484649. fpetrogalli marked 5 inline comments as done. fpetrogalli added a comment. I submitted some of the cleanup suggested by @barannikov88 - thank you! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

barannikov88 added inline comments. Comment at: llvm/lib/TargetParser/CMakeLists.txt:29 +# LLVMTargetParser. See https://stackoverflow.com/a/25681179 +target_include_directories(LLVMTargetParser PUBLIC $) Will it work if RISC-V target is not compiled-in? This do

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484564. fpetrogalli added a comment. Same NFC - restore an empty line change... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https://reviews.llvm.org/D137517 Files: clang/lib/Basic/Targets/R

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484563. fpetrogalli added a comment. NFC - I just restored an empty line to prevent modifying a file that is not being touched by the patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137517/new/ https:

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484561. fpetrogalli added a comment. There is no need to use `target_include_directories(LLVMRISCVDesc PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)` for components that are not related to the RISC-V target. Thank you @lenary for the suggestion! Repositor

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

jrtc27 added a comment. Hm, this means that llvm/lib/Target/$TARGET/$TARGET.td needs to remain working (or at least mostly working, things like ISel patterns can fail to type check) in order for Clang to build, since we're now introducing a dependency on llvm/lib/Target/$TARGET in Clang where t

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

lenary added inline comments. Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) fpetrogalli wrote: > lenary wrote: > > fpetrogalli wrote: > > > craig.topp

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a subscriber: aprantl. fpetrogalli added inline comments. Comment at: llvm/include/llvm/module.modulemap:420 textual header "Support/CSKYTargetParser.def" -textual header "Support/RISCVTargetParser.def" textual header "Support/TargetOpcodes.def" --

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli marked an inline comment as done. fpetrogalli added inline comments. Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) lenary wrote: > fpetrog

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484391. fpetrogalli added a comment. @pcwang-thead, I addressed some of your comments. The value of `EnumFeatures` is now computed dynamicaly from the `Features` field of the `Processor` class. As for generating `MArch` out of the `Features` field, @crai

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli updated this revision to Diff 484380. fpetrogalli marked 8 inline comments as done. fpetrogalli added a comment. 1. I have split the RISCV bits of the target parser out of TargetParser.cpp so that none of the non-RISCV components need to include the folder with the autogenerated .inc

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

lenary added inline comments. Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) fpetrogalli wrote: > craig.topper wrote: > > fpetrogalli wrote: > > > lena

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added inline comments. Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) craig.topper wrote: > fpetrogalli wrote: > > lenary wrote: > > > crai

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper added inline comments. Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) fpetrogalli wrote: > lenary wrote: > > craig.topper wrote: > > > Why

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

fpetrogalli added a comment. Hi - gentle ping on reviewing this Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) lenary wrote: > craig.topper wrote: >

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

lenary added a comment. One comment on the build changes, I don't have opinions on the RISC-V changes. Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/)

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

craig.topper added inline comments. Comment at: llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt:19 +target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetParser/) Why do we need to touch CMake file that aren't RISC-V? ===