[PATCH] D128712: [clang-format] Handle Verilog modules

2022-07-28 Thread sstwcw via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rG6db0c18b1af6: [clang-format] Handle Verilog modules (authored by sstwcw). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D128712/new/ https://reviews.llvm.org

[PATCH] D128712: [clang-format] Handle Verilog modules

2022-07-11 Thread sstwcw via Phabricator via cfe-commits
sstwcw marked 2 inline comments as done. sstwcw added inline comments. Comment at: clang/lib/Format/UnwrappedLineParser.cpp:4072 +Keywords.kw_randsequence)) { +AddLevels += Style.IndentCaseLabels; +nextToken(); HazardyKnusp

[PATCH] D128712: [clang-format] Handle Verilog modules

2022-07-11 Thread sstwcw via Phabricator via cfe-commits
sstwcw updated this revision to Diff 443791. sstwcw added a comment. - take out check - use boolean as boolean Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D128712/new/ https://reviews.llvm.org/D128712 Files: clang/lib/Format/FormatToken.h cla

[PATCH] D128712: [clang-format] Handle Verilog modules

2022-07-11 Thread Björn Schäpers via Phabricator via cfe-commits
HazardyKnusperkeks added inline comments. Comment at: clang/lib/Format/UnwrappedLineParser.cpp:4040 +void UnwrappedLineParser::parseVerilogSensitivityList() { + if (!FormatTok->is(tok::at)) +return; I prefer to make such checks before calling the function. B

[PATCH] D128712: [clang-format] Handle Verilog modules

2022-07-11 Thread sstwcw via Phabricator via cfe-commits
sstwcw updated this revision to Diff 443605. sstwcw edited the summary of this revision. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D128712/new/ https://reviews.llvm.org/D128712 Files: clang/lib/Format/FormatToken.h clang/lib/Format/TokenAnnot

[PATCH] D128712: [clang-format] Handle Verilog modules

2022-06-28 Thread Björn Schäpers via Phabricator via cfe-commits
HazardyKnusperkeks added inline comments. Comment at: clang/lib/Format/FormatToken.h:1742 + /// Returns whether \p Tok is a Verilog keyword that opens a module, etc. + bool isVerilogHier(const FormatToken &Tok) const { +if (Tok.endsSequence(kw_function, kw_with)) --

[PATCH] D128712: [clang-format] Handle Verilog modules

2022-06-28 Thread sstwcw via Phabricator via cfe-commits
sstwcw created this revision. sstwcw added reviewers: HazardyKnusperkeks, MyDeveloperDay, curdeius, owenpan. Herald added a project: All. sstwcw requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. Now things inside hierarchies like modules and