https://github.com/eopXD approved this pull request.
Looks good since we have just landed #74949.
https://github.com/llvm/llvm-project/pull/74950
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https://github.com/eopXD approved this pull request.
Looks good.
If I understand correctly, you mean that `vbool64_t` should emit diagnosis of
requiring `zve64x` and should not emit error of `zve32x.`
https://github.com/llvm/llvm-project/pull/74949
_
eopXD wrote:
The intrinsics for vector crypto is not a formalized version yet. To be safe, I
think we should have an experimental tag to guard the intrinsics, while the
extension is ratified and do indeed don't need the experimental.
https://github.com/llvm/llvm-project/pull/74213
@@ -1101,7 +1101,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
-const unsigned NUM_PREDEF_TYPE_IDS = 500;
+const unsigned NUM_PREDEF_TYPE_IDS = 502;
eopXD wrote:
Yes you are right. My mistake her
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/72370
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>From 8a3db304250683dcd03cc56a5332d03ecdcff140 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Wed, 15 Nov 2023 18:10:54 -0800
Subject: [PATCH 1/2] [Clang][RISCV] Type alignment for the type recording
required extension
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/72463
>From 8a3db304250683dcd03cc56a5332d03ecdcff140 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Wed, 15 Nov 2023 18:10:54 -0800
Subject: [PATCH 1/2] [Clang][RISCV] Type alignment for the type recording
required extension
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/72463
>From 2091781c4cf201e078a702bdd17bc66a3a608177 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Tue, 14 Nov 2023 00:52:47 -0800
Subject: [PATCH 1/3] [Clang][RISCV] Simplify variable name and its guarded
condition. NFC
Z
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/72463
>From 2091781c4cf201e078a702bdd17bc66a3a608177 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Tue, 14 Nov 2023 00:52:47 -0800
Subject: [PATCH 1/2] [Clang][RISCV] Simplify variable name and its guarded
condition. NFC
Z
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/72463
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https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/72463
First few commits are NFC, and then followed by commits to add intrinsics to
support the RVV Bfloat16 types.
Intrinsics specification:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/293
>From 2091781c4cf
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67089
>From 0c449af2049f32103a4f7edf5852f317f6454a23 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 23:17:22 -0700
Subject: [PATCH] [Clang][RISCV] Remove duplicate functions
isRVVSizelessBuiltinType. NFC
`i
eopXD wrote:
Ping.
https://github.com/llvm/llvm-project/pull/67089
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@@ -1101,7 +1101,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
-const unsigned NUM_PREDEF_TYPE_IDS = 500;
+const unsigned NUM_PREDEF_TYPE_IDS = 502;
eopXD wrote:
I extended `NUM_PREDEF_TYPE_IDS`
@@ -1101,7 +1101,7 @@ enum PredefinedTypeIDs {
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
-const unsigned NUM_PREDEF_TYPE_IDS = 500;
+const unsigned NUM_PREDEF_TYPE_IDS = 502;
eopXD wrote:
It is not the problem of 502 or 6
https://github.com/eopXD closed https://github.com/llvm/llvm-project/pull/72370
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eopXD wrote:
@antmox The test case failure should be resolved with the latest commit. Its
not any indeterminate result detected by CI, just that I missed an update to
the test case that is expecting deterministic TypeID.
If CI passed, based on previous approval, should be good and safe to land
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/72370
>From 78e3ab20f5e527563b7645635b7147fdda8ba4b9 Mon Sep 17 00:00:00 2001
From: "Yueh-Ting (eop) Chen"
Date: Wed, 15 Nov 2023 13:50:14 +0800
Subject: [PATCH 1/3] [Clang][RISCV] Introduce tuple types for RVV bfloat16
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/72370
>From 78e3ab20f5e527563b7645635b7147fdda8ba4b9 Mon Sep 17 00:00:00 2001
From: "Yueh-Ting (eop) Chen"
Date: Wed, 15 Nov 2023 13:50:14 +0800
Subject: [PATCH 1/3] [Clang][RISCV] Introduce tuple types for RVV bfloat16
https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/72370
This PR attempts to recommit the PR (#72216) with a safe-bounded TypeID that
will not cause indeterminate results for the compiler.
>From 78e3ab20f5e527563b7645635b7147fdda8ba4b9 Mon Sep 17 00:00:00 2001
From: "Yue
https://github.com/eopXD closed https://github.com/llvm/llvm-project/pull/72367
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https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/72367
This reverts commit 8434b0b9d39b7ffcd1f7f7b5746151e293620e0d. #72216
This commit broke the multiple buildbots, looks like the extension in
`NUM_PREDEF_TYPE_IDS` might have broken some inheriting usages, causing
i
https://github.com/eopXD closed https://github.com/llvm/llvm-project/pull/72216
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https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/72216
The first commit extends the capacity from the compiler infrastructure, and the
second commit continues the effort in #71140 to introduce tuple types for
bfloat16.
>From e34bbbf5ebd1444aab843f3919faf68ae8d1cda9 Mo
eopXD wrote:
Approval is upon addressing Craig's comment.
https://github.com/llvm/llvm-project/pull/71140
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https://github.com/eopXD approved this pull request.
Sorry I did not do this before you.
The patch looks good, I would say we also need tuples of bf16 for completeness.
But I will be adding a suite of intrinsics around BFloat16
(https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/293) so w
https://github.com/eopXD closed https://github.com/llvm/llvm-project/pull/70355
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@@ -1,4 +1,4 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 3
eopXD wrote:
I guess this is something new
eopXD wrote:
A gentle ping now that we have this inside the spec.
https://github.com/llvm/llvm-project/pull/70355
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@@ -7,534 +7,2189 @@
#include
-// CHECK-RV64-LABEL: define dso_local
@test_vundefined_f16mf4
-// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-LABEL: define dso_local
@test_vundefined_f16mf4(
+// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry
@@ -0,0 +1,57 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding
--mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-
eopXD wrote:
Ping.
https://github.com/llvm/llvm-project/pull/67089
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eopXD wrote:
Change: Rebase upon change of parent PR.
https://github.com/llvm/llvm-project/pull/67109
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>From 6f232ccd6dd273b9eecec7f583877a3a5a3696c3 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH 1/3] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for in
eopXD wrote:
Change: Updated the approach to get pass inline asm verifications and handle
them correctly under `EmitAsmStores`.
https://github.com/llvm/llvm-project/pull/67018
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@@ -2524,11 +2551,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultRegIsFlagReg.push_back(IsFlagReg);
llvm::Type *Ty = ConvertTypeForMem(QTy);
+ ResultTruncRegTypes.push_back(Ty);
+
+ // Expressing the type as a structure in inline asm ca
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67018
>From 6f232ccd6dd273b9eecec7f583877a3a5a3696c3 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline
eopXD wrote:
> Does this mean the backend register allocation will pick a large LMUL
> register the same size as the whole tuple and force the register to be overly
> aligned? For example an lmul=1 seg2 tuple can use v0+v1, or v1+v2, or v2+v3,
> etc. But lmul=2 can only use v0+v1, v2+v3, v4+v5
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67109
>From dc77e5c7bca87badecc314b24cab4c10be0e02fa Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH 1/3] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for in
https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67018
>From dc77e5c7bca87badecc314b24cab4c10be0e02fa Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67109
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https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/67109
This PR is based on #67018. This PR fixes compilation issue for RVV tuple types
as InputOperands for inline asm.
---
Currently the compiler generates https://godbolt.org/z/djebPfqxf for tuple type
as inline asm i
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67018
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https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/67089
`isRVVSizelessBuiltinType` and `isRVVType` has the same functionality. This
commit removes the former since we have more variants available in `isRVVType`.
>From 483240e16d800e52783dcfaf52eae81fb1dfca7c Mon Sep 17
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67018
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>From a26eb9fe0c09fc0fd504d261874630d8b5edae26 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67018
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>From 565785dd4938355c738a792676f8c4b1f9684329 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline
https://github.com/eopXD created https://github.com/llvm/llvm-project/pull/67018
This commit fixes compilation issue for RVV tuple types as OutputOperand for
inline asm. The LLVM IR generated by the test case added is currently not
handled successfully in the backend, which also needs a fix too
https://github.com/eopXD approved this pull request.
https://github.com/llvm/llvm-project/pull/66330
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@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v %s
+// REQUIRES: riscv-registered-target
+
+// expected-no-diagnostics
+
+#include
eopXD wrote:
I think we can't :(
https://github.com/llvm/llvm-project/pull/66330
__
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v %s
+// REQUIRES: riscv-registered-target
+
+// expected-no-diagnostics
+
+#include
eopXD wrote:
Does this test case help verify we have `sifive_vector.h` installed?
https://github.com/llvm/l
https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/66330
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eopXD wrote:
> > Maybe test coverage with `-I %resource_dir`?
>
> Which file should I place the test?
`clang/test/Headers/`
https://github.com/llvm/llvm-project/pull/66330
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@@ -629,7 +629,7 @@ TEST(getTargetFeatureForExtension,
RetrieveTargetFeatureFromOneExt) {
TEST(RiscvExtensionsHelp, CheckExtensions) {
std::string ExpectedOutput =
-R"(All available -march extensions for RISC-V
+ R"(All available -march extensions for RISC-V
--
eopXD wrote:
Sorry, that was a mis-statement. There are two counter extensions you are
bumping.
Anyway, rewording the commit message is a nit from me.
https://github.com/llvm/llvm-project/pull/66323
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eopXD wrote:
Your commit bumps both the counter and timer extension, which makes your commit
message inaccurate.
https://github.com/llvm/llvm-project/pull/66323
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eopXD wrote:
Maybe test coverage?
https://github.com/llvm/llvm-project/pull/66330
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eopXD wrote:
@jrtc27 Anymore comments before merging this?
https://github.com/llvm/llvm-project/pull/65778
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https://github.com/llvm/llvm-project/pull/65778:
>From 91e607dd38475ceae604c794e40bd1721aa7dae4 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Fri, 8 Sep 2023 09:59:25 -0700
Subject: [PATCH] [Clang][RISCV] Use Decl for checkRVVTypeSupport
Using ValueDecl will cause
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https://github.com/llvm/llvm-project/pull/65778:
>From 90764baf1616f4a150a10f63df0b0ea6bde0a86a Mon Sep 17 00:00:00 2001
From: eopXD
Date: Fri, 8 Sep 2023 09:59:25 -0700
Subject: [PATCH] [Clang][RISCV] Use Decl for checkRVVTypeSupport
Using ValueDecl will cause
https://github.com/eopXD updated
https://github.com/llvm/llvm-project/pull/65778:
>From 8226aecca0e5ebcf17465122cd2df6cfd1b5e5c9 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Fri, 8 Sep 2023 09:59:25 -0700
Subject: [PATCH] [Clang][RISCV] Use Decl for checkRVVTypeSupport
Using ValueDecl will cause
https://github.com/eopXD updated
https://github.com/llvm/llvm-project/pull/65778:
>From ebffa141090d5274db8a88b5450325e34316a18b Mon Sep 17 00:00:00 2001
From: eopXD
Date: Fri, 8 Sep 2023 09:59:25 -0700
Subject: [PATCH] [Clang][RISCV] Use Decl for checkRVVTypeSupport
Using ValueDecl will cause
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https://github.com/eopXD created
https://github.com/llvm/llvm-project/pull/65778:
Using ValueDecl will cause error for OpenMP. Decl should do the work.
>From 559c8a27f34c983822bb00dfd45c71798c7ecb36 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Fri, 8 Sep 2023 09:59:25 -0700
Subject: [PATCH] [Cla
https://github.com/eopXD review_requested
https://github.com/llvm/llvm-project/pull/65778
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https://github.com/eopXD review_requested
https://github.com/llvm/llvm-project/pull/65778
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