eopXD wrote: > Does this mean the backend register allocation will pick a large LMUL > register the same size as the whole tuple and force the register to be overly > aligned? For example an lmul=1 seg2 tuple can use v0+v1, or v1+v2, or v2+v3, > etc. But lmul=2 can only use v0+v1, v2+v3, v4+v5, etc.
Yes you are correct. The current approach will set restrictions since we will allocate the registers to be the multiplier of the LMUL in the back end. Let me try and work through how I can break them up. https://github.com/llvm/llvm-project/pull/67018 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
