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https://github.com/llvm/llvm-project/pull/80303
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https://github.com/vpykhtin created
https://github.com/llvm/llvm-project/pull/80303
This reverts https://github.com/llvm/llvm-project/pull/78429 and reapplies
https://github.com/llvm/llvm-project/pull/71556 with added lit test constraint:
`REQUIRES: amdgpu-registered-target`
>From 5c85b0b869
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>From 871f5eca90d9b3699faeef1b7847c6ea48981910 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Mon, 20 Nov 2023 15:22:16 +0100
Subject: [PATCH] add instcombine rule
---
clang/test/CodeGenOpenCL/builtins-am
vpykhtin wrote:
Gentle ping.
https://github.com/llvm/llvm-project/pull/71556
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>From b6204d32554f082821da100043bf872b62f1740b Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Mon, 20 Nov 2023 15:22:16 +0100
Subject: [PATCH] add instcombine rule
---
clang/test/CodeGenOpenCL/builtins-am
https://github.com/vpykhtin approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/73920
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@@ -0,0 +1,27 @@
+// REQUIRES: amdgpu-registered-target
+// XFAIL: *
+// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -aux-triple
x86_64-pc-windows-msvc -target-cpu gfx900 -x hip -emit-llvm -fcuda-is-device -o
- %s | FileCheck %s
+// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -aux-t
vpykhtin wrote:
This is ready to be submitted if there're no objections.
https://github.com/llvm/llvm-project/pull/71556
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>From 526c635b3f70fd779f0919c5c40acd017a0f800e Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Mon, 20 Nov 2023 15:22:16 +0100
Subject: [PATCH 1/3] add instcombine rule
---
.../CodeGenOpenCL/builtins-amdgc
@@ -961,6 +961,18 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
return IC.replaceInstUsesWith(II,
Constant::getNullValue(II.getType()));
}
}
+if (ST->isWave32() && II.getType()->getIntegerBitWidth() == 64) {
+ // %
vpykhtin wrote:
I'm going to rebase it on top of
https://github.com/llvm/llvm-project/pull/73779 to show test changes.
https://github.com/llvm/llvm-project/pull/71556
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>From 526c635b3f70fd779f0919c5c40acd017a0f800e Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Mon, 20 Nov 2023 15:22:16 +0100
Subject: [PATCH 1/2] add instcombine rule
---
.../CodeGenOpenCL/builtins-amdgc
vpykhtin wrote:
- Undo the assert per Jay's comment for -O0 mode.
- Restored the original test and added runs with opt to it.
https://github.com/llvm/llvm-project/pull/71556
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>From 526c635b3f70fd779f0919c5c40acd017a0f800e Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Mon, 20 Nov 2023 15:22:16 +0100
Subject: [PATCH] add instcombine rule
---
.../CodeGenOpenCL/builtins-amdgcn-wa
@@ -2314,9 +2314,8 @@ void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
SDValue VCMP = Cond->getOperand(0);
auto CC = cast(Cond->getOperand(2))->get();
auto *CRHS = dyn_cast(Cond->getOperand(1));
-if ((CC == ISD::SETEQ || CC == ISD::SETNE) && CRHS && CRHS->isZe
vpykhtin wrote:
Removed unrelated changes.
https://github.com/llvm/llvm-project/pull/71556
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>From f4ff530d27334a8ba8c986d321efd4ab751b6476 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Mon, 20 Nov 2023 15:22:16 +0100
Subject: [PATCH 1/2] run opt instcombine pass in the test
---
.../AMDGPU/llvm.
https://github.com/vpykhtin updated
https://github.com/llvm/llvm-project/pull/71556
>From 1d71de2784084e75ed2b2f3bd1ad042d8801c226 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Mon, 20 Nov 2023 15:20:03 +0100
Subject: [PATCH 1/6] move tests to the appropriate place
---
.../GlobalISel/ll
@@ -1,32 +1,31 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa
-amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs
-start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-use
@@ -425,29 +414,41 @@ bool GCNRewritePartialRegUses::rewriteReg(Register Reg)
const {
return false;
for (MachineOperand &MO : Range) {
-if (MO.getSubReg() == AMDGPU::NoSubRegister) // Whole reg used, quit.
+if (MO.getSubReg() == AMDGPU::NoSubRegister) // Whole r
@@ -425,29 +414,41 @@ bool GCNRewritePartialRegUses::rewriteReg(Register Reg)
const {
return false;
for (MachineOperand &MO : Range) {
vpykhtin wrote:
Yes, it avoids any processing for unsuitable registers. Replaced the loop with
any_of.
https://gith
vpykhtin wrote:
> I think the code change looks fine. I left a few questions inline about
> existing code -- you don't necessarily need to address these.
>
> Could you regenerate the tests as a separate NFC commit (or PR), so this PR
> only shows test changes from the code change?
Thank you f
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>From fc1457d4856b3f4ae0a080a451669e344b0b1354 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Tue, 17 Oct 2023 20:50:48 +0200
Subject: [PATCH 1/4] [SimplifyCFG] Add test on prevent merging cbranch to
cbran
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@@ -180,6 +190,13 @@ class GCNDownwardRPTracker : public GCNRPTracker {
MachineBasicBlock::const_iterator getNext() const { return NextMI; }
+ // Return MaxPressure and clear it.
+ decltype(MaxPressure) moveMaxPressure() {
vpykhtin wrote:
Done.
https://
@@ -128,14 +128,7 @@ class GCNRPTracker {
void clearMaxPressure() { MaxPressure.clear(); }
- GCNRegPressure getPressure() const { return CurPressure; }
-
- // returns MaxPressure, resetting it
- decltype(MaxPressure) moveMaxPressure() {
-auto Res = MaxPressure;
-
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>From e2254cb744adb65685edeb2373f900368c11c11a Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Thu, 2 Nov 2023 20:39:11 +0100
Subject: [PATCH 1/3] [AMDGPU] Fix GCNUpwardRPTracker.
---
.../Target/AMDGPU/GCN
vpykhtin wrote:
Guys, I really need this change submitted, I'm going to submit it on monday if
there're no objections.
https://github.com/llvm/llvm-project/pull/69375
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vpykhtin wrote:
Thanks Nicolai!
https://github.com/llvm/llvm-project/pull/68714
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vpykhtin wrote:
> I've been puzzling over the rationale for looking at `MD_unpredictable`. How
> can a branch that is heavily biased to one side be unpredictable?
I'm curious either, I just decided to follow a 'standard' pattern in this
source.
https://github.com/llvm/llvm-project/pull/69375
vpykhtin wrote:
> Though, on second thought, shouldn't there be some wave64 tests?
I added a couple of ballot.i64 in wave32 mode tests to
AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll and
AMDGPU/llvm.amdgcn.ballot.i32.ll with the
https://github.com/llvm/llvm-project/pull/68714/commits/6e865d146
vpykhtin wrote:
I've removed live-through registers printing from this PR and will submit it
separately.
https://github.com/llvm/llvm-project/pull/70031
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vpykhtin wrote:
Should we move on and submit this patch? @jayfoad do you have concerns about
live-through register set computation or others? I believe fixing trackers
should go to another PR.
https://github.com/llvm/llvm-project/pull/70031
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vpykhtin wrote:
With the latest commit I added a guard to skip _ballot.i64_ in wave32 mode
because it's lowered with _i64 AMDGPUISD::SETCC_ - this should be fixed with
i32 result similar to ICMP/FCMP intrinsics. After a fix that follows this PR
I'm going to turn the guard into assert - TODO is
@@ -396,3 +396,115 @@ true:
false:
ret i32 33
}
+
+declare i32 @llvm.amdgcn.icmp.i32(i1, i1, i32)
+
+define amdgpu_cs i32
@branch_divergent_simulated_negated_ballot_ne_zero_and(i32 %v1, i32 %v2) {
+; CHECK-LABEL: branch_divergent_simulated_negated_ballot_ne_zero_and:
+; CHEC
vpykhtin wrote:
@nikic or other reviewers, do you have objections to submit this patch?
https://github.com/llvm/llvm-project/pull/69375
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vpykhtin wrote:
@nikic or other reviewers, do you have objections to submit this patch?
https://github.com/llvm/llvm-project/pull/69375
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>From fc1457d4856b3f4ae0a080a451669e344b0b1354 Mon Sep 17 00:00:00 2001
From: Valery Pykhtin
Date: Tue, 17 Oct 2023 20:50:48 +0200
Subject: [PATCH 1/4] [SimplifyCFG] Add test on prevent merging cbranch to
cbran
vpykhtin accepted this revision.
vpykhtin added a comment.
Sorry for a deelay, LGTM either.
https://reviews.llvm.org/D23992
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Author: vpykhtin
Date: Fri Aug 19 07:54:31 2016
New Revision: 279235
URL: http://llvm.org/viewvc/llvm-project?rev=279235&view=rev
Log:
[AMDGPU] add s_incperflevel/s_decperflevel builtins
Differential revision: https://reviews.llvm.org/D23668
Modified:
cfe/trunk/include/clang/Basic/BuiltinsAM
vpykhtin added a subscriber: vpykhtin.
vpykhtin added a comment.
Hi,
is there an intention to make this SPIR 2.0 (provisional) conformant? This
would require changing resulting builtin names, changing pipe argument to
"struct opencl.pipe*" and adding two trailing "size, alignment" parameters. I
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