https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149360
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>From 10b9379f759506e4e1e3c1cab1191ed386609ebe Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 13:03:14 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_f32` on gfx1250
Co-authored-by:
https://github.com/shiltian edited
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shiltian wrote:
### Merge activity
* **Jul 17, 6:41 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149355).
https://github.com/llvm/llvm-project/pull/149355
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shiltian wrote:
Oh nice catch. Thanks.
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shiltian wrote:
but we do have `v_cos_bf16` in `llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s`?
https://github.com/llvm/llvm-project/pull/149355
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>From 29b54575b3e64372750466dfafab971697f402f1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 12:45:33 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sin_bf16_e64` on gfx1250
Co-authored
shiltian wrote:
* **#149355** https://app.graphite.dev/github/pr/llvm/llvm-project/149355?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/149
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149355
Co-authored-by: Mekhanoshin, Stanislav
>From a6b7ccf491c4d88b18bfdba0dbf839030df189ec Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 12:45:33 -0400
Subject: [PATCH] [AMDGPU] Add support for
@@ -610,7 +610,7 @@ void StmtPrinter::VisitObjCAtTryStmt(ObjCAtTryStmt *Node) {
}
}
- if (auto *FS = static_cast(Node->getFinallyStmt())) {
+ if (auto *FS = Node->getFinallyStmt()) {
shiltian wrote:
If there is no cast, then we'd want to use the type
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/149338
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https://github.com/llvm/llvm-project/pull/149340
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/149339
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>From 8012a2d62f910c81a38c1c8d1de1a5bbd797d22f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 16 Jul 2025 23:48:48 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sin_bf16` on gfx1250
Co-authored-by:
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shiltian wrote:
### Merge activity
* **Jul 17, 12:41 PM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149229).
https://github.com/llvm/llvm-project/pull/149229
__
@@ -252,6 +252,15 @@ TARGET_BUILTIN(__builtin_amdgcn_flat_atomic_fmax_f64,
"dd*0d", "t", "gfx90a-inst
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_f64, "dd*3d", "t",
"gfx90a-insts")
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_f32, "ff*3f", "t", "gfx8-insts")
+TARGET_BUI
@@ -25,4 +25,27 @@ define amdgpu_ps void @llvm_log2_bf16_s(ptr addrspace(1)
%out, bfloat inreg %src
ret void
}
+define amdgpu_ps void @llvm_exp2_bf16_v(ptr addrspace(1) %out, bfloat %src) {
+; GCN-LABEL: llvm_exp2_bf16_v:
+; GCN: ; %bb.0:
+; GCN-NEXT:v_exp_bf16_e3
shiltian wrote:
* **#149194** https://app.graphite.dev/github/pr/llvm/llvm-project/149194?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/149
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149194
Co-authored-by: Mekhanoshin, Stanislav
>From 296077854b4bcad36f9b924da1dbfe4376d8b4d5 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 16 Jul 2025 17:31:42 -0400
Subject: [PATCH] [AMDGPU] Add support for
shiltian wrote:
* **#148916** https://app.graphite.dev/github/pr/llvm/llvm-project/148916?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/148
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/148916
Co-authored-by: Mekhanoshin, Stanislav
>From b0c51e4f67e0740d916d1596ced8f93228d93b1c Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 15 Jul 2025 14:10:18 -0400
Subject: [PATCH] [AMDGPU] Add support for
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/148871
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shiltian wrote:
FWIW, the crash still exists.
https://github.com/llvm/llvm-project/pull/147425
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>From f75f85e997f95bd29e244e199d16c89dffca1232 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 14 Jul 2025 12:56:54 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_bf16` on gfx1250
Co-authored-by
@@ -2,169 +2,69 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble
-show-encoding < %s | FileChec
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/147425
>From 2c36f0664993d54841245fe62d062af3b7332c97 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 14 Jul 2025 12:56:54 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_bf16` on gfx1250
Co-authored-by
@@ -704,12 +704,12 @@ void diagnoseUnknownMMRAASName(const MachineInstr &MI,
StringRef AS) {
DiagnosticInfoUnsupported(Fn, Str.str(), MI.getDebugLoc(), DS_Warning));
}
-/// Reads \p MI's MMRAs to parse the "amdgpu-as" MMRA.
+/// Reads \p MI's MMRAs to parse the "amdgpu-
shiltian wrote:
This PR is messed up at this moment.
https://github.com/llvm/llvm-project/pull/147425
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@@ -266,7 +266,7 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple
&Triple,
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
CUMode = !(GPUFeatures & llvm::AMDGPU::FEATURE_WGP);
- for (auto F : {"image-insts", "gws", "vmem-to-lds-load-insts"})
+ for (auto F : {
https://github.com/shiltian approved this pull request.
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@@ -2,51 +2,41 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble
-show-encoding < %s | FileCheck
@@ -2,51 +2,41 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble
-show-encoding < %s | FileCheck
shiltian wrote:
For some reason there is a crash in
`llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll`.
```
LLVM ERROR: Cannot select: t28: ch = store<(store (s16) into %ir.out.load,
addrspace 1)> t0, t27, t30, undef:i64
t27: i16 = bitcast t21
t21: bf16 = llvm.amdgcn.tanh TargetConstant:i64<
@@ -13658,6 +13658,7 @@ bool SITargetLowering::isCanonicalized(Register Reg,
const MachineFunction &MF,
case Intrinsic::amdgcn_frexp_mant:
case Intrinsic::amdgcn_fdot2:
case Intrinsic::amdgcn_trig_preop:
+case Intrinsic::amdgcn_tanh:
shiltian w
@@ -13658,6 +13658,7 @@ bool SITargetLowering::isCanonicalized(Register Reg,
const MachineFunction &MF,
case Intrinsic::amdgcn_frexp_mant:
case Intrinsic::amdgcn_fdot2:
case Intrinsic::amdgcn_trig_preop:
+case Intrinsic::amdgcn_tanh:
shiltian w
@@ -1432,6 +1442,26 @@ static bool runImpl(Module &M, AnalysisGetter &AG,
TargetMachine &TM,
} else if (auto *CmpX = dyn_cast(&I)) {
A.getOrCreateAAFor(
IRPosition::value(*CmpX->getPointerOperand()));
+ } else if (auto *II = dyn_cast(&I)) {
+
@@ -5501,7 +5505,32 @@ struct AAAlignCallSiteReturned final
using Base = AACalleeToCallSite;
AAAlignCallSiteReturned(const IRPosition &IRP, Attributor &A)
: Base(IRP, A) {}
+ ChangeStatus updateImpl(Attributor &A) override {
+SmallVector Values;
+SmallVector
@@ -85,7 +85,7 @@ __amdgpu_buffer_rsrc_t
test_amdgcn_make_buffer_p0_nullptr(short stride, int num,
// CHECK-LABEL: @test_amdgcn_make_buffer_p1_nullptr(
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call ptr addrspace(8)
@llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr
https://github.com/shiltian approved this pull request.
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https://github.com/llvm/llvm-project/pull/146987
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shiltian wrote:
I see. That makes sense. Worth a release note item.
https://github.com/llvm/llvm-project/pull/146594
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@@ -83,6 +83,84 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
case AMDGPU::BI__builtin_amdgcn_update_dpp: {
return checkMovDPPFunctionCall(TheCall, 6, 2);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin
@@ -83,6 +83,84 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
case AMDGPU::BI__builtin_amdgcn_update_dpp: {
return checkMovDPPFunctionCall(TheCall, 6, 2);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin
@@ -635,5 +635,66 @@ TARGET_BUILTIN(__builtin_amdgcn_bitop3_b16, "IUi",
"nc", "bitop3-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf16_f32, "V2yV2yfUiIb", "nc",
"f32-to-f16bf16-cvt-sr-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc",
"f32-to-
shiltian wrote:
Why not stick with `--offload-arch` for generic use? I'm not really sure about
the motivation.
https://github.com/llvm/llvm-project/pull/146594
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https://github.com/llvm/llvm-project/pull/146409
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https://github.com/llvm/llvm-project/pull/146547
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@@ -1214,6 +1214,12 @@ void __kmp_serialized_parallel(ident_t *loc, kmp_int32
global_tid) {
// Reset for next parallel region
this_thr->th.th_set_proc_bind = proc_bind_default;
+ // OpenMP 6.0 12.1.2 requires the num_threads 'strict' modifier to also have
+ // effect wh
@@ -1214,6 +1214,12 @@ void __kmp_serialized_parallel(ident_t *loc, kmp_int32
global_tid) {
// Reset for next parallel region
this_thr->th.th_set_proc_bind = proc_bind_default;
+ // OpenMP 6.0 12.1.2 requires the num_threads 'strict' modifier to also have
+ // effect wh
shiltian wrote:
Please split the PR into three: front end, device runtime, and libomp for
faster and better review.
https://github.com/llvm/llvm-project/pull/146346
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@@ -1214,6 +1214,12 @@ void __kmp_serialized_parallel(ident_t *loc, kmp_int32
global_tid) {
// Reset for next parallel region
this_thr->th.th_set_proc_bind = proc_bind_default;
+ // OpenMP 6.0 12.1.2 requires the num_threads 'strict' modifier to also have
+ // effect wh
https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/146305
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>From 51e5e4593f24771ee818e273f76092a05e2fb98a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:02 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_bf8` on gfx1250
Co-authored-
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/146305
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>From 1be2863da610906403bf436d33a3114a13f40daa Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:12 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_fp8` on gfx1250
Co-authored-
shiltian wrote:
### Merge activity
* **Jun 30, 11:47 AM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/146302).
https://github.com/llvm/llvm-project/pull/146302
__
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/146302
>From 8b078d8346b7c9e949700d7e5c2a4ec9e29a2138 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:12 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_fp8` on gfx1250
Co-authored-
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/146302
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>From befea46e97c499f3b1ad0e3ac17ecadebc74acc1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 29 Jun 2025 23:47:12 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_cvt_f16_fp8` on gfx1250
Co-authored-
shiltian wrote:
Oh indeed! I didn't notice that…
https://github.com/llvm/llvm-project/pull/146302
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shiltian wrote:
> > Co-authored-by: Shilei Tian [i...@tianshilei.me](mailto:i...@tianshilei.me)
>
> Co authored by yourself?
Yes, because if you check the commit, the author is @rampitec.
https://github.com/llvm/llvm-project/pull/146302
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shiltian wrote:
* **#146302** https://app.graphite.dev/github/pr/llvm/llvm-project/146302?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/146
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/146302
Co-authored-by: Shilei Tian
>From ed3e22a2edc87f68c19ed8b27527ee09dda795cf Mon Sep 17 00:00:00 2001
From: "Mekhanoshin, Stanislav"
Date: Sun, 29 Jun 2025 22:58:17 -0400
Subject: [PATCH] [AMDGPU] Add support f
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146289
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146220
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shiltian wrote:
### Merge activity
* **Jun 25, 8:56 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/145747).
https://github.com/llvm/llvm-project/pull/145747
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@@ -1381,7 +1399,7 @@ static bool runImpl(Module &M, AnalysisGetter &AG,
TargetMachine &TM,
&AAAMDMaxNumWorkgroups::ID, &AAAMDWavesPerEU::ID, &AAAMDGPUNoAGPR::ID,
&AACallEdges::ID, &AAPointerInfo::ID, &AAPotentialConstantValues::ID,
&AAUnderlyingObjects::I
@@ -5500,7 +5504,34 @@ struct AAAlignCallSiteReturned final
using Base = AACalleeToCallSite;
AAAlignCallSiteReturned(const IRPosition &IRP, Attributor &A)
: Base(IRP, A) {}
+ ChangeStatus updateImpl(Attributor &A) override {
+SmallVector Values;
+const auto &
@@ -5500,7 +5504,34 @@ struct AAAlignCallSiteReturned final
using Base = AACalleeToCallSite;
AAAlignCallSiteReturned(const IRPosition &IRP, Attributor &A)
: Base(IRP, A) {}
+ ChangeStatus updateImpl(Attributor &A) override {
+SmallVector Values;
+const auto &
@@ -5500,7 +5504,34 @@ struct AAAlignCallSiteReturned final
using Base = AACalleeToCallSite;
AAAlignCallSiteReturned(const IRPosition &IRP, Attributor &A)
: Base(IRP, A) {}
+ ChangeStatus updateImpl(Attributor &A) override {
+SmallVector Values;
+const auto &
@@ -5500,7 +5504,34 @@ struct AAAlignCallSiteReturned final
using Base = AACalleeToCallSite;
AAAlignCallSiteReturned(const IRPosition &IRP, Attributor &A)
: Base(IRP, A) {}
+ ChangeStatus updateImpl(Attributor &A) override {
+SmallVector Values;
+const auto &
@@ -1044,82 +1040,78 @@ void
Driver::CreateOffloadingDeviceToolChains(Compilation &C,
<< OpenMPTargets->getAsString(C.getInputArgs());
return;
}
+
+ // Make sure these show up in a deterministic order.
+ std::multiset OpenMPTriples;
f
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/145549
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@@ -1044,82 +1040,78 @@ void
Driver::CreateOffloadingDeviceToolChains(Compilation &C,
<< OpenMPTargets->getAsString(C.getInputArgs());
return;
}
+
+ // Make sure these show up in a deterministic order.
+ std::multiset OpenMPTriples;
f
@@ -1044,82 +1040,78 @@ void
Driver::CreateOffloadingDeviceToolChains(Compilation &C,
<< OpenMPTargets->getAsString(C.getInputArgs());
return;
}
+
+ // Make sure these show up in a deterministic order.
+ std::multiset OpenMPTriples;
f
@@ -1044,82 +1040,78 @@ void
Driver::CreateOffloadingDeviceToolChains(Compilation &C,
<< OpenMPTargets->getAsString(C.getInputArgs());
return;
}
+
+ // Make sure these show up in a deterministic order.
+ std::multiset OpenMPTriples;
f
Miguel =?utf-8?q?C=C3=A1rdenas?= ,
Miguel =?utf-8?q?C=C3=A1rdenas?= ,
Miguel =?utf-8?q?C=C3=A1rdenas?=
Message-ID:
In-Reply-To:
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/145365
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@@ -683,6 +683,206 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateInsertElement(I0, A, 1);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin_amdgcn_image_load_1darray_v4f32_i32:
+ case A
@@ -683,6 +683,206 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateInsertElement(I0, A, 1);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin_amdgcn_image_load_1darray_v4f32_i32:
+ case A
@@ -128,6 +160,16 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
return false;
}
+bool SemaAMDGPU::checkImageImmArgFunctionCall(CallExpr *TheCall,
+ unsigned ArgCount) {
+ llvm::APSInt Result;
+ if (!(Se
@@ -83,6 +83,38 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
case AMDGPU::BI__builtin_amdgcn_update_dpp: {
return checkMovDPPFunctionCall(TheCall, 6, 2);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/145152
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https://github.com/shiltian approved this pull request.
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/144939
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https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/144914
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shiltian wrote:
> Bit of a hack it seems
It is a hack (or workaround). The correct approach would be either to redesign
the lowering of LDS, or create another flavor of ThinLTO. Neither of it can be
done in a reasonably short amount of time.
https://github.com/llvm/llvm-project/pull/144914
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shiltian wrote:
* **#144914** https://app.graphite.dev/github/pr/llvm/llvm-project/144914?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/144
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/144914
On AMDGPU, we need an extra argument `-avail-extern-gv-in-addrspace-to-local=3`
to privatize LDS global variables when ThinLTO is enabled.
>From bf7b936421379ae7e043360c6515136660e2e550 Mon Sep 17 00:00:00 2001
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