https://github.com/nibrunieAtSi5 updated
https://github.com/llvm/llvm-project/pull/128243
>From d2c64fd7605eb1e2e6756f3c01960bfa8ee55da9 Mon Sep 17 00:00:00 2001
From: Nicolas Brunie
Date: Sat, 25 Jan 2025 09:39:47 -0800
Subject: [PATCH 1/2] [RISC-V] prototyping support for Zvbc32e and Zvkgs
*
@@ -1075,7 +1075,9 @@ constexpr static RISCVExtBit RISCVBitPositions[] = {
{"zimop", 1, 1}, {"zca", 1, 2},
{"zcb", 1, 3},{"zcd", 1, 4},
{"zcf", 1, 5},{"zcmop", 1, 6},
-{"zawrs", 1, 7}};
+{"zawrs", 1, 7}, {"zvbc32e", 1, 8},
+{"zv
https://github.com/nibrunieAtSi5 updated
https://github.com/llvm/llvm-project/pull/128243
>From d2c64fd7605eb1e2e6756f3c01960bfa8ee55da9 Mon Sep 17 00:00:00 2001
From: Nicolas Brunie
Date: Sat, 25 Jan 2025 09:39:47 -0800
Subject: [PATCH] [RISC-V] prototyping support for Zvbc32e and Zvkgs
* Add
https://github.com/nibrunieAtSi5 edited
https://github.com/llvm/llvm-project/pull/128243
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nibrunieAtSi5 wrote:
Actually, it looks like most of the support may have already been added as part
of
https://github.com/llvm/llvm-project/commit/a80a90e34b1f26422ebf56e922abe2c193607c81
https://github.com/llvm/llvm-project/pull/128243
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nibrunieAtSi5 wrote:
This PR is built has a porting to main of a branch which was originally created
on top of llvm 18.1.8 tag (the top tag in riscv-gnu-toolchain when this effort
was started). It looks like a few changes (including opcodes for the Zvkgs) did
not make it properly to the port.
https://github.com/nibrunieAtSi5 created
https://github.com/llvm/llvm-project/pull/128243
⚠️ this PR is still a work in progress, much work is still required before it
is ready for review (help / feedback appreciated anyway).
This PR introduces support for a couple of vector crypto extensions
