https://github.com/nibrunieAtSi5 updated
https://github.com/llvm/llvm-project/pull/128243
>From d2c64fd7605eb1e2e6756f3c01960bfa8ee55da9 Mon Sep 17 00:00:00 2001
From: Nicolas Brunie <nibru...@gmail.com>
Date: Sat, 25 Jan 2025 09:39:47 -0800
Subject: [PATCH] [RISC-V] prototyping support for Zvbc32e and Zvkgs
* Adding Zvbc32e / Zvkgs support in extension declarations
* tablegen definitions for Zvbc32e
* Adding RVV_REQ_Zvkgs definition
[Zvbc32e/Zvkgs] introducing some changes required for fast track vector crypto
extensions
more changes
Adding Zvkgs instrinsics
Adding zvkgs + zvbc32e in RISC-V supported extensions (RISCVISAInfo.cpp)
Adding zvkgs + zvbc32e in RISC-V supported extensions (RISCVISAInfo.cpp)
---
clang/include/clang/Basic/riscv_vector.td | 17 +++++++++++++++++
.../clang/Support/RISCVVIntrinsicUtils.h | 4 +++-
clang/lib/Sema/SemaRISCV.cpp | 2 ++
clang/utils/TableGen/RISCVVEmitter.cpp | 2 ++
llvm/docs/RISCVUsage.rst | 2 ++
llvm/include/llvm/IR/IntrinsicsRISCV.td | 16 +++++++++++++++-
llvm/lib/TargetParser/RISCVISAInfo.cpp | 4 +++-
7 files changed, 44 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index c4d2afe407516..a012026af9112 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2791,6 +2791,17 @@ multiclass RVVSignedWidenBinBuiltinSetVwsll
[["vv", "Uw", "UwUvUv"],
["vx", "Uw", "UwUvz"]]>;
+// intrinsic class for an instruction with integer operand up
+// up to 32-bit wide
+multiclass RVVIntMax32BinBuiltinSet
+ : RVVOutOp1BuiltinSet<NAME, "csi",
+ [["vv", "v", "vvv"],
+ ["vx", "v", "vve"]]>,
+ RVVOutOp1BuiltinSet<NAME, "csi",
+ [["vv", "Uv", "UvUvUv"],
+ ["vx", "Uv", "UvUvUe"]]>;
+
+
let UnMaskedPolicyScheme = HasPassthruOperand in {
// zvkb
let RequiredFeatures = ["Zvkb"] in {
@@ -2817,6 +2828,12 @@ let UnMaskedPolicyScheme = HasPassthruOperand in {
defm vclmul : RVVInt64BinBuiltinSet;
defm vclmulh : RVVInt64BinBuiltinSet;
}
+
+ // zvbc32e
+ let RequiredFeatures = ["Zvbc32e", "Experimental"] in {
+ defm vclmul : RVVIntMax32BinBuiltinSet ;
+ defm vclmulh : RVVIntMax32BinBuiltinSet;
+ }
}
let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 4819fc144f4dc..74ed4f369d693 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -504,7 +504,9 @@ enum RVVRequire : uint32_t {
RVV_REQ_Zvfbfwma = 1 << 16,
RVV_REQ_Zvfbfmin = 1 << 17,
RVV_REQ_Zvfh = 1 << 18,
- RVV_REQ_Experimental = 1 << 19,
+ RVV_REQ_Zvbc32e = 1 << 19,
+ RVV_REQ_Zvkgs = 1 << 20,
+ RVV_REQ_Experimental = 1 << 21,
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Experimental)
};
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 8a5037d045125..b06101b488666 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -224,6 +224,8 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
{"zvfbfwma", RVV_REQ_Zvfbfwma},
{"zvfbfmin", RVV_REQ_Zvfbfmin},
{"zvfh", RVV_REQ_Zvfh},
+ {"zvbc32e", RVV_REQ_Zvbc32e},
+ {"zvkgs", RVV_REQ_Zvkgs},
{"experimental", RVV_REQ_Experimental}};
// Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index 0cdde20060b63..adca044fb08c0 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -793,6 +793,8 @@ void RVVEmitter::createRVVIntrinsics(
.Case("Zvfbfmin", RVV_REQ_Zvfbfmin)
.Case("Zvfh", RVV_REQ_Zvfh)
.Case("Experimental", RVV_REQ_Experimental)
+ .Case("Zvbc32e", RVV_REQ_Zvbc32e)
+ .Case("Zvkgs", RVV_REQ_Zvkgs)
.Default(RVV_REQ_None);
assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
SR.RequiredExtensions |= RequireExt;
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 09fb59f94e84d..a1183e464276e 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -220,6 +220,7 @@ on support follow.
``Ztso`` Supported
``Zvbb`` Supported
``Zvbc`` Supported (`See note <#riscv-vector-crypto-note>`__)
+ ``Zvbc32e`` Supported (`See note <#riscv-vector-crypto-note>`__)
``Zve32x`` (`Partially <#riscv-vlen-32-note>`__) Supported
``Zve32f`` (`Partially <#riscv-vlen-32-note>`__) Supported
``Zve64x`` Supported
@@ -231,6 +232,7 @@ on support follow.
``Zvfhmin`` Supported
``Zvkb`` Supported
``Zvkg`` Supported (`See note <#riscv-vector-crypto-note>`__)
+ ``Zvkgs`` Supported (`See note <#riscv-vector-crypto-note>`__)
``Zvkn`` Supported (`See note <#riscv-vector-crypto-note>`__)
``Zvknc`` Supported (`See note <#riscv-vector-crypto-note>`__)
``Zvkned`` Supported (`See note <#riscv-vector-crypto-note>`__)
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td
b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 99cb557d9aa09..1dcbb93296ebe 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -327,6 +327,16 @@ let TargetPrefix = "riscv" in {
let VLOperand = 2;
}
+ // For destination vector type is the same as the source vector type
+ // Input: (passthru, vector_in, vector_in/scalar_in, vl, policy)
+ class RISCVBinaryAASUnMaskedZvk
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty,
+ llvm_anyint_ty, LLVMMatchType<2>],
+ [ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
+ let VLOperand = 3;
+ }
+
multiclass RISCVUnaryAAUnMaskedZvk<bit HasVV = 1, bit HasVS = 1> {
if HasVV then
def "int_riscv_" # NAME # "_vv" : RISCVUnaryAAUnMaskedZvk<IsVS=0>;
@@ -1847,7 +1857,7 @@ let TargetPrefix = "riscv" in {
defm vcpopv : RISCVUnaryAA;
defm vwsll : RISCVBinaryABX;
- // Zvbc
+ // Zvbc / Zvbc32e
defm vclmul : RISCVBinaryAAX;
defm vclmulh : RISCVBinaryAAX;
@@ -1855,6 +1865,10 @@ let TargetPrefix = "riscv" in {
def int_riscv_vghsh : RISCVBinaryAAXUnMaskedZvk;
def int_riscv_vgmul_vv : RISCVUnaryAAUnMaskedZvk<IsVS=0>;
+ // Zvkgs
+ def int_riscv_vghsh_vs : RISCVBinaryAASUnMaskedZvk;
+ def int_riscv_vgmul_vs : RISCVUnaryAAUnMaskedZvk<IsVS=1>;
+
// Zvkned
defm vaesdf : RISCVUnaryAAUnMaskedZvk;
defm vaesdm : RISCVUnaryAAUnMaskedZvk;
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index c78d60fd86b3f..e413d9c1629da 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -1044,7 +1044,9 @@ constexpr static RISCVExtBit RISCVBitPositions[] = {
{"zimop", 1, 1}, {"zca", 1, 2},
{"zcb", 1, 3}, {"zcd", 1, 4},
{"zcf", 1, 5}, {"zcmop", 1, 6},
- {"zawrs", 1, 7}};
+ {"zawrs", 1, 7}, {"zvbc32e", 1, 8},
+ {"zvkgs", 1, 9}
+ };
std::pair<int, int> RISCVISAInfo::getRISCVFeaturesBitsInfo(StringRef Ext) {
// Note that this code currently accepts mixed case extension names, but
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