@@ -49,6 +49,10 @@ enum class VFISAKind {
AVX, // x86 AVX
AVX2, // x86 AVX2
AVX512, // x86 AVX512
+ RVVM1,// RISC-V Vector Extension LMUL=1
+ RVVM2,// RISC-V Vector Extension LMUL=2
+ RVVM4,// RISC-V Vector Extension LMUL=
@@ -236,6 +236,79 @@ TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGVdN4v_log",
FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVbN4v_logf", FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVdN8v_logf", FIXED(8), "_ZGV_LLVM_N8v")
+#elif defined(TLI_
https://github.com/mga-sc requested changes to this pull request.
Finally, libmvec is still not ported to RISC-V (today check glibc ToT with
`--enable-mathvec`). I think we should wait for this and also wait for commit
to
[riscv-elf-psabi-doc](https://github.com/riscv-non-isa/riscv-elf-psabi-d
@@ -109,11 +109,11 @@ static void addMappingsFromTLI(const TargetLibraryInfo
&TLI, CallInst &CI) {
TLI.getWidestVF(ScalarName, WidestFixedVF, WidestScalableVF);
for (bool Predicated : {false, true}) {
-for (ElementCount VF = ElementCount::getFixed(2);
@@ -110,7 +114,7 @@
// CHECK-ENABLED-LAST: math errno enabled by '-ffp-model=strict' after it was
implicitly disabled by '-fveclib=ArmPL', this may limit the utilization of the
vector library [-Wmath-errno-enabled-with-veclib]
/* Verify no warning when math-errno is re-enabl
https://github.com/mga-sc edited
https://github.com/llvm/llvm-project/pull/119844
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mga-sc wrote:
I can't merge this PR.
@topperc , could please merge it.
https://github.com/llvm/llvm-project/pull/114014
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mga-sc wrote:
@mikhailramalho , @topperc , ping
https://github.com/llvm/llvm-project/pull/114014
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mga-sc wrote:
> @mga-sc I'm trying to run some experiments with your PR and will post as soon
> as they are done, but can I ask you to add the following code to your PR? So
> that clang can accept -fveclib=SLEEF when building for riscv64
>
> ```
> diff --git a/clang/lib/Driver/ToolChains/Clang
