================ @@ -49,6 +49,10 @@ enum class VFISAKind { AVX, // x86 AVX AVX2, // x86 AVX2 AVX512, // x86 AVX512 + RVVM1, // RISC-V Vector Extension LMUL=1 + RVVM2, // RISC-V Vector Extension LMUL=2 + RVVM4, // RISC-V Vector Extension LMUL=4 + RVVM8, // RISC-V Vector Extension LMUL=8 ---------------- mga-sc wrote:
Are you sure we need to enable all of them (now enabled only one for each RISC-V and AArch64)? https://github.com/llvm/llvm-project/pull/119844 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits