[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

Jim added inline comments. Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:3 +// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d \ +// RUN: -target-feature +f -target-feature +d -disable-O0-optnone \ +// RUN: -mvscale-min=4 -mvscale-max=4 -emit-llv

[PATCH] D158402: [Clang][RISCV] Add vcreate intrinsics for RVV tuple types

Jim added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2833 } + let Name = "vcreate_v", + UnMaskedPolicyScheme = NonePolicy, Can we add a blank line before this. Comment at: clang/include/clang/Basic/riscv_vec

[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

Jim added inline comments. Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:3 +// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d \ +// RUN: -target-feature +f -target-feature +d -disable-O0-optnone \ +// RUN: -mvscale-min=4 -mvscale-max=4 -emit-llv

[PATCH] D157353: [RISCV] Remove pre-defined macro test for b extension. NFC.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG767ca3a70d6d: [RISCV] Remove pre-defined macro test for b extension. NFC. (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE LA

[PATCH] D157353: [RISCV] Remove pre-defined macro test for b extension. NFC.

Jim created this revision. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, si

[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:33 +let Uses = [SSP] in { +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +class RV_SSPop _rd, bits<5> _rs1, string opcodestr, string argstr> : Two `let` lines can be merg

[PATCH] D156686: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

This revision was automatically updated to reflect the committed changes. Closed by commit rG1c1066797c5b: [AST] Simplify Type::isSizelessBuiltinType(). NFC. (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156686/new/ https://review

[PATCH] D156686: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

Jim updated this revision to Diff 545921. Jim added a comment. Address comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156686/new/ https://reviews.llvm.org/D156686 Files: clang/lib/AST/Type.cpp Index: clang/lib/AST/Type.cpp

[PATCH] D156686: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

Jim created this revision. Herald added subscribers: ctetreau, s.egerton, simoncook. Herald added a project: All. Jim requested review of this revision. Herald added subscribers: cfe-commits, wangpc. Herald added a project: clang. Reuse isSVESizelessBuiltinType() and isRVVSizelessBuiltinType().

[PATCH] D156507: [RISCV] Upgrade Zihintntl extension to version 1.0 and move out of experimental state.

Jim created this revision. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, jdoerfert, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, s

[PATCH] D154596: [RISCV] Fix required features checking with empty string

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG8fe0449ac990: [RISCV] Fix required features checking with empty string (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D154596: [RISCV] Fix required features checking with empty string

Jim added a comment. In D154596#4499757 , @wangpc wrote: > In D154596#4499718 , @Jim wrote: > >> In D154596#4499647 , @wangpc wrote: >> >>> Can you give an example of intr

[PATCH] D154596: [RISCV] Fix required features checking with empty string

Jim added a comment. In D154596#4499647 , @wangpc wrote: > Can you give an example of intrinsic that doesn't require any extra extension > enabled? Like read/write csr intrinsics that we add for convenient usage doesn't need any extra extension enabled

[PATCH] D154596: [RISCV] Fix required features checking with empty string

Jim added a comment. Kindly ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154596/new/ https://reviews.llvm.org/D154596 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org

[PATCH] D154596: [RISCV] Fix required features checking with empty string

Jim created this revision. Herald added subscribers: jobnoorman, VincentWu, vkmr, luismarques, sameer.abuasal, s.egerton, benna, psnobl, PkmX, rogfer01, shiva0217, kito-cheng, simoncook, arichardson. Herald added a project: All. Jim requested review of this revision. Herald added subscribers: cfe

[PATCH] D153235: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG612b7e10a9af: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi (authored by Jim). Changed prior to commit: https://r

[PATCH] D153235: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUi/iULi

Jim updated this revision to Diff 532790. Jim added a comment. Address comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153235/new/ https://reviews.llvm.org/D153235 Files: clang/include/clang/Basic/BuiltinsRISCV.def clang/test/CodeGen/RI

[PATCH] D153235: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUi/iULi

Jim created this revision. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, si

[PATCH] D150945: [RISCV] Add missing test for ctz_32 on RV64

This revision was automatically updated to reflect the committed changes. Closed by commit rG33d3d51d77a7: [RISCV] Add missing test for ctz_32 on RV64 (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150945/new/ https://reviews.llvm.

[PATCH] D150945: [RISCV] Add missing test for ctz_32 on RV64

Jim created this revision. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, si

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. In D95588#3622052 , @sunshaoce wrote: > Hello @Jim! We are developing the P extension, are you still maintaining this > patch? Or would you mind co-development together? Yes, I am still on developing the P extension. But it seems spe

[PATCH] D128604: [RISCV] Support Zbpbo extension v0.9.11

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:471 + Sched<[WriteCMix, ReadCMix, ReadCMix, ReadCMix]>; def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">, Sched<[WriteFSReg, ReadFSReg, ReadFSReg, Re

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.96

Jim updated this revision to Diff 433612. Jim added a comment. Herald added subscribers: sunshaoce, StephenFan, arichardson. Herald added a project: All. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108189/new/ https://reviews.llvm.org/D108

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim marked an inline comment as done. Jim added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll:4360 ; LMULMAX1-RV64-NEXT:vid.v v10 +; LMULMAX1-RV64-NEXT:vadd.vi v11, v10, 2 +; LMULMAX1-RV64-NEXT:lui a2, %hi(.LCPI132_2)

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim marked 2 inline comments as done. Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:909 + +// kmar64 has a aliased instruction kmada32 belong to zpn sub-extension on RV64. +let DecoderNamespace = "RISCV32Zpsfoperand_", Jim wrote

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.96

Jim updated this revision to Diff 407770. Jim added a comment. Herald added a subscriber: pcwang-thead. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108189/new/ https://reviews.llvm.org/D108189 Files: clang/test/Driver/riscv-arch.c cla

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:557 + +let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in +def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add Is register pair only on RV32 for used as f64? Reposi

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555 +def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add GPR)>; +def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add +X10_PD, X12_PD, X14_PD, X16_PD, Is XLenRI correct for GPR

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.96

Jim added a comment. Herald added a subscriber: eopXD. In D108189#3188343 , @zixuan-wu wrote: > Hi, @Jim. > What time is P extension going to upstream to community since it's been no > update for some months? Hi @zixuan-wu, From RVP 0.9.7, it has lots

[PATCH] D116509: [Builtins] Add missing the macro 'y' description in comments

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG9b70ddaff6e1: [Builtins] Add missing the macro 'y' description in comments (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE L

[PATCH] D116509: [Builtins] Add missing the macro 'y' description in comments

Jim created this revision. Jim requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D116509 Files: clang/include/clang/Basic/Builtins.def Index: clang/include/clang/Basic/Built

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim marked 7 inline comments as done. Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:909 + +// kmar64 has a aliased instruction kmada32 belong to zpn sub-extension on RV64. +let DecoderNamespace = "RISCV32Zpsfoperand_", jrtc27 wr

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. In D95588#3003090 , @Jim wrote: > Any feedback? I think this patch is good enough to be accepted. Ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Any feedback? I think this patch is good enough to be accepted. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.93

Jim updated this revision to Diff 372058. Jim added a comment. Update to 0.96 and remove Zprvsfextra Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108189/new/ https://reviews.llvm.org/D108189 Files: clang/test/Driver/riscv-arch.c clang/test/Pr

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Hi, @jrtc27 About the concern the invalid combination RV32 + zprvsfextra on riscv attribute, I upload a patch D108189 based on @kito-cheng 's patch D105168 to forbid emitting rv32+zprvsfextra arch stri

[PATCH] D108189: [RISCV] Add arch attribute support for P extension

Jim updated this revision to Diff 370484. Jim added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Base on D105168 to support arch features, arch attributes and preprocessor definitions. Repository: rG LLVM Github Monorepo

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

Jim added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:416 +ExtensionInfoIterator->Version.Minor); + if (ExtName == "e") { +if (XLen != 32) Could this checking put before ISAInfo->addExtension... Reposi

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

Jim added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:387 +ExtensionInfoIterator->Version.Minor); + if (ExtName == "e") +HasE = true; Does this need to check it is invalid if XLen is 64? ==

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim marked an inline comment as done. Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:186-188 + [FeatureExtZpsfoperand, +FeatureExtZpn, +FeatureExtZprvsfextra]>; jrtc27 wr

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Hi @jrtc27, any further feedback? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

Jim updated this revision to Diff 365359. Jim added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95589/new/ https://reviews.llvm.org/D95589 Files: clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/test/Driver/riscv-arch.c In

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

Jim updated this revision to Diff 365358. Jim added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95590/new/ https://reviews.llvm.org/D95590 Files: clang/lib/Basic/Targets/RISCV.cpp clang/lib/Basic/Targets/RISCV.h clang/tes

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Kindly ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.ll

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

Jim updated this revision to Diff 363372. Jim added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95589/new/ https://reviews.llvm.org/D95589 Files: clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/test/Driver/riscv-arch.c In

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

Jim updated this revision to Diff 363371. Jim added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95590/new/ https://reviews.llvm.org/D95590 Files: clang/lib/Basic/Targets/RISCV.cpp clang/lib/Basic/Targets/RISCV.h clang/tes

[PATCH] D107248: [RISCV] Define preprocessor definitions for 'P' extension

Jim created this revision. Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso,

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. @jrtc27 Any more feedback? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org ht

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim marked 8 inline comments as done. Jim added inline comments. Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:442 + +if (STI.getFeatureBits()[RISCV::FeatureExtZpsfoperand] && +!STI.getFeatureBits()[RISCV::Feature64Bit]) { jrtc2

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. In D95588#2898470 , @jrtc27 wrote: > Oh, technically none of the clang changes belong in this patch. Those are for > the Clang driver and preprocessor, not the MC layer which is purely llvm. I move the clang changes to D95589

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

Jim updated this revision to Diff 361088. Jim added a comment. Recover it. Split arch version for P extension of D95588 to this. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95589/new/ https://reviews.llvm.org/D9

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

Jim updated this revision to Diff 361087. Jim added a comment. Recover it. Split preprocessor definitions part of D95588 to this. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95590/new/ https://reviews.llvm.org/D

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69 +def sub_lo : SubRegIndex<32>; +def sub_hi : SubRegIndex<32, 32>; Jim wrote: > luismarques wrote: > > jrtc27 wrote: > > > This assumes RV32, and is not clear it applies to regi

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69 +def sub_lo : SubRegIndex<32>; +def sub_hi : SubRegIndex<32, 32>; luismarques wrote: > jrtc27 wrote: > > This assumes RV32, and is not clear it applies to register pairs > What

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Any comments? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.l

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. ping? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

Jim added a comment. Any comments? Thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95588/new/ https://reviews.llvm.org/D95588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.l

[PATCH] D103313: [RISCV][Clang] Implement support for zmmul-experimental

Jim added a comment. It should add arch string tests such as in clang/test/Driver/riscv-arch.c. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103313/new/ https://reviews.llvm.org/D103313 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D101426: [RISCV] Update subset naming convertion for the latest spec

Jim added a comment. GCC has been updated from https://github.com/gcc-mirror/gcc/commit/ca1a9763a1f635d2687ebd5009dd61d4fd0ab5fb#diff-622e89d94803bb804711d5d492a5d4dfa60399bd7a5a7e70a49155534aa6a81f Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D101

[PATCH] D101426: [RISCV] Update subset naming convertion for the latest spec

Jim created this revision. Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso,

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added a comment. In D99158#2695125 , @craig.topper wrote: > Also can you please explain the vector codegen plan at a high level? Do you > intend to support auto vectorization or just using vector_size in C? Currently, it just supports vector type op

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 338414. Jim added a comment. Fix typo. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews.llvm.org/D99158 Files: clang/include/clang/AST/ASTContext.h clang/include/clang/Basic/Builtins.de

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:762 + for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) +setOperationAction(Opc, VT, Expand); + craig.topper wrote: > You probably need handling for insert_vect

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 338017. Jim added a comment. 1. Updating D99158 : [RISCV][WIP] Implement intrinsics for P extension # 2. Enter a brief description of the changes included in this update. 3. The first line is used as subject, next lines as comment

[PATCH] D100266: [RISCV][Clang] Add vmv and vfmv series intrinsic functions.

Jim accepted this revision. Jim added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100266/new/ https://reviews.llvm.org/D100266 ___ cfe-commits mailing list cfe-commits@lists.llvm.org ht

[PATCH] D100266: [RISCV][Clang] Add vmv and vfmv series intrinsic functions.

Jim added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1217 +defm vmv_x : RVVOp0BuiltinSet<"vmv_x_s", "csil", + [["s", "ve", "ev"], +["s", "UvUe", "UeUv"]]>; Inden

[PATCH] D100266: [RISCV][Clang] Add vmv and vfmv series intrinsic functions.

Jim added a reviewer: Jim. Jim added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:993 +defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csil", + [["v", "Uv", "UvUv"]]>; +defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilfd"

[PATCH] D71541: [NFC] [Clang]: fix spelling mistake in assert message

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG8a2d375a77bf: [NFC] [Clang]: fix spelling mistake in assert message (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACT

[PATCH] D71541: [NFC] [Clang]: fix spelling mistake in assert message

Jim updated this revision to Diff 336752. Jim added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71541/new/ https://reviews.llvm.org/D71541 Files: clang/lib/AST/VTableBuilder.cpp Index: clang/lib/AST/VTableBuilder.cpp ==

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:706 + + setOperationAction(ISD::BITCAST, VT, Legal); + Jim wrote: > craig.topper wrote: > > What about bitcast from float/double to any of these vector types? I'm > > guess t

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 335428. Jim added a comment. Subtarget.hasStdExtP() -> Subtarget.hasStdExtZpn() for addRegisterClass CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews.llvm.org/D99158 Files: clang/include/clang/AST/ASTContext.h clang/include/

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:17944 + + // P extension +#define EMIT_BUILTIN(NAME, INT) \ I have concern here. It has lots of duplicate code if the code style is the same as B in the top. And the name of macro is not goo

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

Jim abandoned this revision. Jim added a comment. Herald added a subscriber: vkmr. Merge this patch into https://reviews.llvm.org/D95588 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95589/new/ https://reviews.llvm.org/D95589 _

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

Jim abandoned this revision. Jim added a comment. Herald added a subscriber: vkmr. Merge this patch into https://reviews.llvm.org/D95588 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95590/new/ https://reviews.llvm.org/D95590 _

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:706 + + setOperationAction(ISD::BITCAST, VT, Legal); + craig.topper wrote: > What about bitcast from float/double to any of these vector types? I'm guess > that's not legal.

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim updated this revision to Diff 335416. Jim edited the summary of this revision. Jim added a comment. Address comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews.llvm.org/D99158 Files: clang/include/clang/AST/ASTContext.h clang/include/clang/Basic/B

[PATCH] D99320: [RISCV] [1/2] Add intrinsic for Zbb extension

Jim added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:26 + +} // TargetPrefix = "riscv" + How about put it between Atomics and Vector to follow canonical order? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://

[PATCH] D99631: [RISCV] Refine pre-define macro tests

This revision was automatically updated to reflect the committed changes. Closed by commit rG32ca5a037ab9: [RISCV] Refine pre-define macro tests (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99631/new/ https://reviews.llvm.org/D99

[PATCH] D99009: [RISCV] [1/2] Add intrinsic for Zbr extension

Jim added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:28 +TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr") +TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr") + I don't know why it does

[PATCH] D99631: [RISCV] Refine pre-define macro tests

Jim created this revision. Jim added reviewers: craig.topper, simoncook, HsiangKai. Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, jfb, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, sh

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

Jim added a comment. In D99158#2645796 , @craig.topper wrote: > What are we gaining from making the intrinsics use vector types if no vector > operations are supported other than the intrinsics? Why can't we just use an > xlen integer type? It can supp

[PATCH] D98923: [Driver] Pass -fexperimental-strict-floating-point to cc1 if it is specified

Jim abandoned this revision. Jim added a comment. In D98923#2638061 , @craig.topper wrote: > Isn't OPT_fexperimental_strict_floating_point marked as a CC1Option in > Options.td. Can the driver even recognize it? > > Can you use -Xclang -fexperimental-str

[PATCH] D98923: [Driver] Pass -fexperimental-strict-floating-point to cc1 if it is specified

Jim created this revision. Jim added a reviewer: kpn. Jim requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. In my case, it has to enable strict floating-point by driver for default unsupported target. Repository: rG LLVM Github Monorepo

[PATCH] D98682: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG678241795c95: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp (authored by Jim). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D98682: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

Jim updated this revision to Diff 330888. Jim added a comment. Address @craig.topper 's comment. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98682/new/ https://reviews.llvm.org/D98682 Files: clang/include/clang/Basic/BuiltinsRISCV.def clang/utils/TableGen/RISCVVEmitter.cpp Inde

[PATCH] D98682: [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

Jim created this revision. Jim added reviewers: khchen, craig.topper. Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

Jim added inline comments. Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1744 + // which multi-lib should be used. + return ScanGCCMultilibConfig(D, TargetTriple, Path, Args, MultilibOutput, + Result); scanGCCMultilibConfig ? R

[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

Jim added inline comments. Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1703 +} + } + Ms.emplace_back(Multilib); Do you have plan to support other kind of options to build multilib? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

Jim added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:89 +#define BUILTIN(ID, TYPE, ATTRS) \ + {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, +#include "clang/Basic/BuiltinsRISCV.def" Should

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

Jim added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:89 +#define BUILTIN(ID, TYPE, ATTRS) \ + {"__builtin_rvv_" #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, +#include "clang/Basic/BuiltinsRISCV.def" --

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

Jim added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2 -RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n") -RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n") -RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n") -RISCVV_BUILTIN(va

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

Jim added inline comments. Comment at: llvm/docs/CommandGuide/tblgen.rst:141 - Generate RISCV compressed instructions. + Generate RISC-V compressed instructions. It is typo fix. Could you fix it in a separate patch? Repository: rG LLVM Github Monorepo

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

Jim added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2 -RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n") -RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n") -RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n") -RISCVV_BUILTIN(va

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

Jim added inline comments. Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:11127 +def err_riscvv_builtin_not_useable : Error< + "builtin requires 'V' extension support to be enabled">; } // end of sema component. Add blank line. Is it "err_riscvv_

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

Jim added inline comments. Comment at: clang/test/CodeGen/RISCV/vadd.c:22 +{ +return __builtin_rvv_vadd_vv_i8m1_vl(arg_0, arg_1, arg_2); +} Is it necessary with prefix "__builtin_"? Refer to https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv_intrinsi

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

Jim created this revision. Jim added reviewers: craig.topper, HsiangKai, kito-cheng, jrtc27, luismarques. Herald added subscribers: frasercrmck, NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zz

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

Jim created this revision. Jim added reviewers: craig.topper, HsiangKai, jrtc27, kito-cheng, luismarques. Herald added subscribers: frasercrmck, NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zz

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