[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

frasercrmck abandoned this revision. frasercrmck added a comment. Herald added a subscriber: luke. Superseded by D139873 amongst others Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107290/new/ https://reviews.llv

[PATCH] D142144: [RISCV][Driver] Add -mrvv-vector-bits= option similar to -msve-vector-bits=

frasercrmck accepted this revision. frasercrmck added a comment. This revision is now accepted and ready to land. LGTM other than test header comment that needs changed. Comment at: clang/test/Driver/riscv-rvv-vector-bits.c:2 +// ---

[PATCH] D142144: [RISCV][Driver] Add -mrvv-vector-bits= option similar to -msve-vector-bits=

frasercrmck added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:2150 + Args.MakeArgString("-mvscale-min=" + llvm::Twine(VScaleMin))); +} else if (!Val.equals("scalable")) { + // Handle the unsupported values passed to mrvv-vector-bits. -

[PATCH] D142144: [RISCV][Driver] Add -rvv-vector-bits= option similar to -sve-vector-bits=

frasercrmck added inline comments. Comment at: clang/include/clang/Driver/Options.td:3587 + HelpText<"Specify the size in bits of an RVV vector register. Defaults to the" + " vector length agnostic value of \"scalable\". Also accepts \"zvl\"" + " to use the

[PATCH] D137516: [TargetSupport] Move TargetParser API in a separate LLVM component.

frasercrmck added a comment. In D137516#3911245 , @arsenm wrote: > I think this is fine, but think the name needs to be bikeshedded. "Target" > and "Support" are already overloaded enough as it is. Is there anything else > that would really ever go into

[PATCH] D116735: [RISCV] Adjust RV64I data layout by using n32:64 in layout string

frasercrmck accepted this revision. frasercrmck added a comment. LGTM other than a nit, but I concur that a comment in AutoUpgrade would be nice. Comment at: llvm/docs/ReleaseNotes.rst:123 +* i32 is now a native type in the datalayout string. This enables + LoopStrengthReduce

[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

frasercrmck added a comment. I agree with @reames, though I do think the patch description could use a rewrite. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D116735/new/ https://reviews.llvm.org/D116735 ___

[PATCH] D136106: [clang][RISCV] Set vscale_range attribute based on VLEN

frasercrmck accepted this revision. frasercrmck added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136106/new/ https://reviews.llvm.org/D136106 ___ cfe-commits mailing list cfe

[PATCH] D130689: [LLVM] Update C++ standard to 17

frasercrmck added inline comments. Comment at: llvm/docs/ReleaseNotes.rst:55 +This means that the the following versions are now required to build LLVM +and there is no way to supress this error. + `suppress` Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

frasercrmck added a comment. Just nits from me. Comment at: clang/include/clang/Sema/RISCVIntrinsicManager.h:9 +// +// This file defines the RISCVIntrinsicManager, which handle RISC-V vector +// intrinsic functions. `handles` Comment at: clan

[PATCH] D124062: [RISCV][Clang][NFC] Update vid intrinsic tests.

frasercrmck accepted this revision. frasercrmck added a comment. This revision is now accepted and ready to land. Were they perhaps passing because `i64 [[VL:%.*]]` was matching the `, i64 0` too? Seems like a flaw in the checks generated by the script, but I can see how the majority of the time

[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

frasercrmck added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:101 + } else { +RVVBitsMin = RVVVectorBitsMinOpt; +RVVBitsMax = RVVVectorBitsMaxOpt; craig.topper wrote: > frasercrmck wrote: > > frasercrmck wrote: > > > craig.t

[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

frasercrmck updated this revision to Diff 404016. frasercrmck added a comment. rebase check for zvl feature strings alongside vscale_range Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107290/new/ https://reviews.llvm.org/D107290 Files: clang/li

[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

frasercrmck added a comment. In D107290#3268949 , @paulwalker-arm wrote: > Does this mean `RISCVTTIImpl::getMaxVScale()` can be removed? Good question. I'm unsure at this stage. At hinted at in the description, `getMaxVScale` can make use of backend-sp

[PATCH] D118253: [RISCV] Add the passthru operand for some RVV nomask unary and nullary intrinsics.

frasercrmck accepted this revision. frasercrmck added a comment. This revision is now accepted and ready to land. LGTM, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D118253/new/ https://reviews.llvm.org/D118253

[PATCH] D107290: [RISCV] Add support for the vscale_range attribute

frasercrmck added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vscale-range.ll:162 + +attributes #0 = { vscale_range(2,1024) } +attributes #1 = { vscale_range(4,1024) } khchen wrote: > I'm thinking do we need to test zvl and vscale_range

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

frasercrmck updated this revision to Diff 402572. frasercrmck added a comment. Herald added a subscriber: pcwang-thead. rebase take minimum from zvl extensions allow backend options to override attribute values add extra testing Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

frasercrmck added a comment. LGTM too. Though the commit title and message has hyphens in places I wouldn't expect them. `macros` and `builtins` is fine. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:797 // Init RISC-V extensions for (const auto &T : OutInTypes) {

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

frasercrmck added inline comments. Herald added subscribers: eopXD, VincentWu, luke957, achieveartificialintelligence. Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:101 + } else { +RVVBitsMin = RVVVectorBitsMinOpt; +RVVBitsMax = RVVVectorBitsMaxOpt; -

[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

frasercrmck added a comment. Thanks for the patch! Not sure the best way to review this. The tests are passing, which is a good sign. One option could be to split the "meaningful" changes into a separate diff for easier viewing? We probably don't need to see all the test RUN line changes, for e

[PATCH] D117647: [RISCV] Add destination operand for RVV nomask load intrinsics.

frasercrmck added a comment. Thanks, LGTM. As a heads up, I've pinched the use of `_TU` as a suffix in D117561 . The conflicts should be minor (one location) for whichever patch is merged second. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTIO

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

frasercrmck added a comment. If we're bumping it to 1.0, does that mean it's no longer "experimental"? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112987/new/ https://reviews.llvm.org/D112987 ___ cfe-c

[PATCH] D117647: [RISCV] Add destination operand for RVV nomask load intrinsics.

frasercrmck added a comment. Is "destination operand" the terminology we want? I'd have thought "passthru" was more conventional. Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1194 Operands.push_back(Node->getOperand(CurOp++)); + if (Node->getOperand(Cu

[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

frasercrmck added a comment. LGTM but I don't have full scope on the builtins side of things. I'd also add a missing word to the title: "Change TARGET_BUILTIN //to// require ..." Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112613/new/ https://re

[PATCH] D115709: [RISCV] Remove Vamo Extention

frasercrmck added a comment. I think it'd be helpful for the description to note why this is being removed, what happened to the extension, etc. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115709/new/ https://reviews.llvm.org/D115709 __

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

frasercrmck added inline comments. Comment at: clang/test/Preprocessor/riscv-target-features.c:230 +// RUN: | FileCheck --check-prefix=CHECK-V-MINVLEN %s +// CHECK-V-MINVLEN: __riscv_v_min_vlen 128 Are we able to test non-default values of `__riscv_v_min_vlen` he

[PATCH] D111062: [RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.

frasercrmck accepted this revision. frasercrmck added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luke957. Thanks @khchen, that's great. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111062/new/ http

[PATCH] D111062: [RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.

frasercrmck added inline comments. Herald added a reviewer: luke957. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c:97 // CHECK-RV64-LABEL: @test_vmandnot_mm_b8( +// CHECK-RV64-LABEL: @test_vmandn_mm_b8( Was this test manually updated?

[PATCH] D112534: [PoC][RISCV] Use an attribute to declare C intrinsics with different policy.

frasercrmck added a comment. Herald added a reviewer: luke957. Just nits from me at this stage. Comment at: clang/include/clang/Basic/AttrDocs.td:2150 + let Content = [{ +Users could use the attribute to specify the policy of destination tail and +destination inactive masked-o

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

frasercrmck added a comment. I think the rest of my comments would be to do with `zvl` so I'll leave it there to avoid repetition. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:65 + unsigned getMinVLen() const { return MinVLen; } + unsigned getMaxEew() const { return

[PATCH] D112398: [RISCV] Add ABI testing for Float16.

frasercrmck added a comment. It looks as though all checks are checking the same thing? Presumably this is expected? I wonder if allowing an extra combined check (`--check-prefixes=CHECK,CHECK-ZFH-ILP32F` or something) would make it more obvious when things *are* different between the different

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

frasercrmck added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:182 +def FeatureExtZve32x +: SubtargetFeature<"experimental-zve32x", "HasStdExtZve32x", "true", craig.topper wrote: > frasercrmck wrote: > > Do we need to define distinct `Subtarg

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

frasercrmck added a comment. Don't we need to teach ISel some tricks before we consider these extensions supported? E.g., we need to stop i64 vectors being legal under zve32x or zve32f. Comment at: llvm/lib/Target/RISCV/RISCV.td:182 +def FeatureExtZve32x +: SubtargetFeat

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

frasercrmck added a comment. Minor typo in the description: `differnet` Does this help with compile times, binary sizes, etc? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112102/new/ https://reviews.llvm.org/D112102 _

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

frasercrmck added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll:1358 +; CHECK-NEXT:vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT:vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT:ret HsiangKai wrote: > vmerge.vvm is for integer vect

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

frasercrmck added a comment. In D105690#3044417 , @HsiangKai wrote: > I think we could restart to review this patch. Thanks for bringing it up - I've lost track of the various 1.0 patches. This one LGTM from what I can tell. Repository: rG LLVM Gith

[PATCH] D111062: [RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.

frasercrmck added a comment. LGTM in general. My comments are all about comments. I know the old names are kept as aliases but I still think it's better to reference the "real" instructions where we can. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2468

[PATCH] D106044: [RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.

frasercrmck accepted this revision. frasercrmck added a comment. LGTM in principle but `aliases.s` is apparently failing with something that looks relevant. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106044/new/ https://reviews.llvm.org/D106044

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

frasercrmck added a comment. In D93298#3014160 , @jrtc27 wrote: > The amount of duplication here really depresses me and is only going to get > worse once codegen is added, but TableGen isn't able to have operands that > use different register classes ba

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

frasercrmck added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:101 + } else { +RVVBitsMin = RVVVectorBitsMinOpt; +RVVBitsMax = RVVVectorBitsMaxOpt; craig.topper wrote: > If clang always emits the attribute, are these options

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

frasercrmck added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:349 + unsigned VLENMax = 65536; + return std::make_pair(VLENMin / 64, VLENMax / 64); +} craig.topper wrote: > Should we move RVVBitsPerBlock to RISCVTargetParser.def? Or some other

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

frasercrmck updated this revision to Diff 369416. frasercrmck marked 2 inline comments as done. frasercrmck added a comment. Herald added a subscriber: dexonsmith. - rebase - move V VLEN bits-per-block (64), min (128), max (65536) defines into TargetParser.h - clean up assertions Repository:

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

frasercrmck added a comment. Ah no, my mistake. This would be a drop in functionality if `getMaxVScale` is removed, since its replacement only checks the IR attribute and will not be affected by our backend flags. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://revie

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

frasercrmck added a comment. This may be as far as we can take this patch without exposing RVV vectors bit control to the user/driver and having to worry about the concerns that spring from that: linking objects compiled with different RVV vector bits options, LTO, etc. I believe that with the

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

frasercrmck updated this revision to Diff 367232. frasercrmck added a comment. Herald added subscribers: llvm-commits, hiraditya. Herald added a project: LLVM. update usage in vein of AArch64: - use vscale_range attribute to determine RVV vector bits min/max values - if no attribute is present, u

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

frasercrmck added a comment. Sorry, I can't find if we wrote it down in some other patch -- and someone can correct me if I'm wrong -- but in one of the recent LLVM RISC-V sync-up calls we agreed that we'd skip v0.10-rc and move straight to supporting v1.0 when it's made final. So I think this

[PATCH] D106939: [RISCV] If the maskedoff is vundefined(), use ta, ma for vsetvli.

frasercrmck added a comment. In D106939#2915784 , @HsiangKai wrote: > In D106939#2915134 , @HsiangKai > wrote: > >> In D106939#2912807 , @frasercrmck >> wrote: >> >>> LG

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

frasercrmck created this revision. frasercrmck added reviewers: craig.topper, rogfer01, HsiangKai, evandro, arcbbb, khchen. Herald added subscribers: vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, j

[PATCH] D106277: [SVE] Remove the interface for getMaxVScale in favour of the IR attributes

frasercrmck added inline comments. Comment at: clang/lib/Basic/Targets/AArch64.h:100 + Optional> + getVScaleRange(const LangOptions &LangOpts) const; + This clang-tidy warning needs satisfied. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D106277: [SVE] Remove the interface for getMaxVScale in favour of the IR attributes

frasercrmck added a comment. In D106277#2913136 , @paulwalker-arm wrote: > @craig.topper can you share RISCV plans around supporting vscale_range? In > essence we'd like to deprecate the TTI method and have LLVM IR contain all > relevant information w

[PATCH] D106939: [RISCV] If the maskedoff is vundefined(), use ta, ma for vsetvli.

frasercrmck added a comment. LGTM but there are test failures. Is that just a whole load of `mu->ma` changes that have been omitted for a smaller diff? Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:379 bool ForceTailAgnostic = RISCVII::doesForceTailAgnostic(TSFla

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

frasercrmck added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:127 + +bool RISCVISAInfo::isSupportedExtensionFeature(StringRef Ext) { + bool IsExperimental = stripExperimentalPrefix(Ext); This looks like a `find_if` if that'd make it any simple

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

frasercrmck added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:555 +defvar Xlen32EEWList = [["8", "(Log2EEW:3)"], +["16", "(Log2EEW:4)"], jrtc27 wrote: > Ignoring whether the change is actually correct, this sho

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

frasercrmck added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:10 /// This file describes the RISC-V instructions from the standard 'V' Vector /// extension, version 0.10. /// This version is still experimental as the 'V' extension hasn't been

[PATCH] D106049: [RISCV] Update to vfredusum.vs and vfwredusum.vs according to v1.0-rc1.

frasercrmck added a comment. Duplicate of D105690 ? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106049/new/ https://reviews.llvm.org/D106049 ___ cfe-commits mailing li

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

frasercrmck added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vfredusum-rv32.ll:1 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \

[PATCH] D104822: [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

frasercrmck added a comment. What's supposed to happen if the provided index is invalid? I'm suspecting we'd currently get a IR verification error on the insert/extract indices. I'm wondering if we can/should catch that earlier? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D103603: [Sema][RISCV] Allow ?: to select Typedef BuiltinType in C

frasercrmck added a comment. In D103603#2795899 , @kito-cheng wrote: > Testcase for AArch64/SVE: > > #include > > svint8_t a(); > __SVInt8_t b(); > > svint8_t foo(int cond){ > return cond ? a(): b(); > } Could that AArch64 test also

[PATCH] D100819: [RISCV] Implement the vneg.v builtin.

frasercrmck added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1048 + return Cmp < 0; + // Some mask intrinsics use the same IRName as unmasked. + // Sort the unmasked intrinsics first. -

[PATCH] D100611: [RISCV] Add new attribute __clang_riscv_builtin_alias for intrinsics.

frasercrmck accepted this revision. frasercrmck added a comment. This revision is now accepted and ready to land. LGTM. Anything else would be wondering if it can be merged/genericised with Arm somehow but that's not a blocker. Comment at: clang/include/clang/Basic/AttrDocs.td

[PATCH] D100611: [RISCV] Add new attribute __clang_riscv_builtin_alias for intrinsics.

frasercrmck added inline comments. Comment at: clang/include/clang/Basic/AttrDocs.td:2141 +in RVV builtins, and still be recognized as clang builtins equivalent to the +underlying name. For example, ``riscv_vector.h`` declares the function ``vget`` with +``__attribute__((__clang

[PATCH] D100611: [RISCV] Add new attribute __clang_riscv_builtin_alias for intrinsics.

frasercrmck added a comment. Is this idea that this will later be "automatically" applied to builtins in `riscv_vector.h`? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100611/new/ https://reviews.llvm.org/D100611

[PATCH] D99984: [RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.

frasercrmck accepted this revision. frasercrmck added inline comments. This revision is now accepted and ready to land. Comment at: clang/lib/Basic/Targets/RISCV.cpp:259 .Case("riscv64", Is64Bit) + .Case("64bit", Is64Bit) .Case("m", HasM) craig

[PATCH] D99984: [RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.

frasercrmck added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:259 .Case("riscv64", Is64Bit) + .Case("64bit", Is64Bit) .Case("m", HasM) What's the difference between this new feature and `riscv64` above? Repository: rG LLV

[PATCH] D99482: [PoC][Clang][CodeGen] Do not use getelementptr for scalable struct.

frasercrmck added a comment. Are there any tests for this? Comment at: clang/lib/CodeGen/CGCall.cpp:1299 bool DestIsVolatile) { // Prefer scalar stores to first-class aggregate stores. if (llvm::StructType *STy = dyn_cast(Val->get

[PATCH] D99590: [Clang] Do not use memcpy for scalable struct copy.

frasercrmck added inline comments. Comment at: clang/include/clang/AST/Type.h:4627 + /// Recursively check all fields in the record for sizeless. If any field + /// is sizeless type, return true. Otherwise, return false. + bool hasSizelessFields() const; nit:

[PATCH] D99158: [RISCV][WIP] Implement intrinsics for P extension

frasercrmck added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:715-732 +if (Subtarget.is64Bit()) { + addTypeForP(MVT::v8i8, MVT::i64); + addTypeForP(MVT::v4i16, MVT::i64); + addTypeForP(MVT::v2i32, MVT::i64); +} else { + add

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

frasercrmck accepted this revision. frasercrmck added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95680/new/ https://reviews.llvm.org/D95680 ___ cfe-commits mailing list cfe-commits@lis

[PATCH] D95002: [RISCV] Update B extension version to 0.93.

frasercrmck added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:732 // There's no encoding for roli in the current version of the 'B' extension // (v0.92) as it can be implemented with rori by negating the immediate. let Predicates = [HasStdExtZbbOrZbp]

[PATCH] D94617: [RISCV] Add Zba feature and move add.uw and slli.uw to it.

frasercrmck accepted this revision. frasercrmck added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94617/new/ https://reviews.llvm.org/D94617 ___

[PATCH] D90928: [OpenCL] Check for extension string extension lookup

This revision was automatically updated to reflect the committed changes. Closed by commit rG7793db35ca2c: [OpenCL] Check for extension string extension lookup (authored by erik2020, committed by frasercrmck). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm