[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-26 Thread Deric Cheung via cfe-commits
@@ -738,6 +739,16 @@ def UMin : DXILOp<40, binary> { let attributes = [Attributes]; } +def UAddc : DXILOp<44, binaryWithCarryOrBorrow > { + let Doc = "Unsigned 32-bit integer arithmetic add with carry. uaddc(a,b) = (a+b, a+b overflowed ? 1 : 0)"; + let intrinsics = [Intri

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-26 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127137 >From 4fae5642c6e8e305cdc687b4968ba5eabaa44b50 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 01/14] Add the AddUint64 HLSL builtin function - Defines the AddUi

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-26 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127137 >From 4fae5642c6e8e305cdc687b4968ba5eabaa44b50 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 01/13] Add the AddUint64 HLSL builtin function - Defines the AddUi

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-26 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127137 >From 4fae5642c6e8e305cdc687b4968ba5eabaa44b50 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 01/13] Add the AddUint64 HLSL builtin function - Defines the AddUi

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
@@ -0,0 +1,71 @@ +; RUN: opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; CHECK: %dx.types.i32c = type { i32, i1 } + +define noundef i32 @test_UAddc(i32 noundef %a, i32 noundef %b) { +; CHECK-LABEL: define noundef i32 @test_UAddc( +

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
@@ -0,0 +1,71 @@ +; RUN: opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; CHECK: %dx.types.i32c = type { i32, i1 } + +define noundef i32 @test_UAddc(i32 noundef %a, i32 noundef %b) { +; CHECK-LABEL: define noundef i32 @test_UAddc( +

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
@@ -0,0 +1,71 @@ +; RUN: opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; CHECK: %dx.types.i32c = type { i32, i1 } + +define noundef i32 @test_UAddc(i32 noundef %a, i32 noundef %b) { +; CHECK-LABEL: define noundef i32 @test_UAddc( +

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
@@ -0,0 +1,88 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; Code here is an excerpt of clang/test/CodeGenHLSL/builtins/Add

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
Icohedron wrote: > The SPIRV test case isn't sufficent. Two reasons. > > 1. Since you are not using `__builtin_addc ` Your codegen path for > `uadd.with.overflow` is custom to HLSL. Your emitter is in > `EmitHLSLBuiltinExpr`. > 2. `llvm/test/CodeGen/SPIRV/llvm-intrinsics/uadd.with.overflow.ll`

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127137 >From 4fae5642c6e8e305cdc687b4968ba5eabaa44b50 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 01/12] Add the AddUint64 HLSL builtin function - Defines the AddUi

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127137 >From 4fae5642c6e8e305cdc687b4968ba5eabaa44b50 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 01/11] Add the AddUint64 HLSL builtin function - Defines the AddUi

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
@@ -738,6 +739,16 @@ def UMin : DXILOp<40, binary> { let attributes = [Attributes]; } +def UAddc : DXILOp<44, binaryWithCarryOrBorrow > { + let Doc = "Unsigned 32-bit integer arithmetic add with carry. uaddc(a,b) = (a+b, a+b overflowed ? 1 : 0)"; + let intrinsics = [Intri

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
@@ -738,6 +739,16 @@ def UMin : DXILOp<40, binary> { let attributes = [Attributes]; } +def UAddc : DXILOp<44, binaryWithCarryOrBorrow > { + let Doc = "Unsigned 32-bit integer arithmetic add with carry. uaddc(a,b) = (a+b, a+b overflowed ? 1 : 0)"; + let intrinsics = [Intri

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-25 Thread Deric Cheung via cfe-commits
@@ -738,6 +739,16 @@ def UMin : DXILOp<40, binary> { let attributes = [Attributes]; } +def UAddc : DXILOp<44, binaryWithCarryOrBorrow > { + let Doc = "Unsigned 32-bit integer arithmetic add with carry. uaddc(a,b) = (a+b, a+b overflowed ? 1 : 0)"; + let intrinsics = [Intri

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-24 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127137 >From 4fae5642c6e8e305cdc687b4968ba5eabaa44b50 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 1/8] Add the AddUint64 HLSL builtin function - Defines the AddUint

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-24 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron closed https://github.com/llvm/llvm-project/pull/125599 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-24 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/125599 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-24 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/125599 >From ff7e6425913d77a66ff47335b6ee0f84f2741034 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 3 Feb 2025 23:10:16 + Subject: [PATCH 1/5] Reapply "Reland "[HLSL] Implement the `reflect` HLSL function"

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-22 Thread Deric Cheung via cfe-commits
Icohedron wrote: > LGTM regarding previous HWASAN crash, which is gone Thank you for fixing the issue! I will revert the patches then. https://github.com/llvm/llvm-project/pull/125599 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lis

[clang] [test] Remove `-emit-llvm` from the `and-errors.hlsl` test to avoid writing to a potentially write-protected directory (PR #128047)

2025-02-20 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron created https://github.com/llvm/llvm-project/pull/128047 @mikaelholmen [mentioned](https://github.com/llvm/llvm-project/pull/127098#discussion_r1962897888) that the `-emit-llvm` argument isn't necessary for the `and-errors.hlsl` test and may cause issues due to wr

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-20 Thread Deric Cheung via cfe-commits
@@ -0,0 +1,23 @@ +// RUN: %clang_cc1 -finclude-default-header -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s \ +// RUN: -emit-llvm -O1 -verify Icohedron wrote: Yes, I will make a PR to fix this https://github.com/llvm/llvm-project/pull/127098 _

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-19 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/125599 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-19 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/125599 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-19 Thread Deric Cheung via cfe-commits
Icohedron wrote: Because the "underlying" -- though still not fully understood -- cause of the test failure under hwasan was found (refer to my [comment](https://github.com/llvm/llvm-project/issues/124045#issuecomment-2669906382) from issue #124045), I have re-added support for running the tes

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-19 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/125599 >From ff7e6425913d77a66ff47335b6ee0f84f2741034 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 3 Feb 2025 23:10:16 + Subject: [PATCH 1/3] Reapply "Reland "[HLSL] Implement the `reflect` HLSL function"

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-19 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127137 >From 4fae5642c6e8e305cdc687b4968ba5eabaa44b50 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 1/6] Add the AddUint64 HLSL builtin function - Defines the AddUint

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-19 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127098 >From e78176bdcc3d0bf93ace334f68da3dce6f6cd78f Mon Sep 17 00:00:00 2001 From: Icohedron Date: Wed, 12 Feb 2025 21:24:00 + Subject: [PATCH 1/7] Implement the 'and' HLSL function --- clang/include/clang/Ba

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-19 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127098 >From e78176bdcc3d0bf93ace334f68da3dce6f6cd78f Mon Sep 17 00:00:00 2001 From: Icohedron Date: Wed, 12 Feb 2025 21:24:00 + Subject: [PATCH 1/6] Implement the 'and' HLSL function --- clang/include/clang/Ba

[clang] [HLSL] Bug fix crash using Array Parameters when De-sugaring is the same as canonicalizing (PR #127670)

2025-02-18 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127670 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Bug fix crash using Array Parameters when De-sugaring is the same as canonicalizing (PR #127670)

2025-02-18 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron approved this pull request. https://github.com/llvm/llvm-project/pull/127670 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Bug fix crash using Array Parameters when De-sugaring is the same as canonicalizing (PR #127670)

2025-02-18 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron commented: Looks fine to me, but this change doesn't only affect HLSL does it? The function `getArrayParameterType` in `ASTContext.cpp` doesn't look like it is HLSL-specific. I wonder if a similar bug occurs within C/C++. https://github.com/llvm/llvm-project/pull/1

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-18 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127137 >From 4fae5642c6e8e305cdc687b4968ba5eabaa44b50 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 1/5] Add the AddUint64 HLSL builtin function - Defines the AddUint

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-18 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127098 >From 5b093ca42fdc24f89bfccac25e6f2e17155432f6 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Wed, 12 Feb 2025 21:24:00 + Subject: [PATCH 1/6] Implement the 'and' HLSL function --- clang/include/clang/Ba

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-15 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-15 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-15 Thread Deric Cheung via cfe-commits
@@ -2245,6 +2245,36 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { break; } + case Builtin::BI__builtin_hlsl_and: { +if (SemaRef.checkArgCount(TheCall, 2)) + return true; +if (CheckVectorElementCallArgs(&SemaRef, TheCal

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -finclude-default-header -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s \ +// RUN: -emit-llvm -O1 -verify + +bool test_too_few_arg(bool a) { + return __builtin_hlsl_and(a); + // expected-error@-1 {{too few arguments to function call

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -2245,6 +2245,17 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { break; } + case Builtin::BI__builtin_hlsl_and: { +if (SemaRef.checkArgCount(TheCall, 2)) + return true; +if (CheckVectorElementCallArgs(&SemaRef, TheCal

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127098 >From 5b093ca42fdc24f89bfccac25e6f2e17155432f6 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Wed, 12 Feb 2025 21:24:00 + Subject: [PATCH 1/6] Implement the 'and' HLSL function --- clang/include/clang/Ba

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -2079,6 +2079,14 @@ static bool CheckFloatingOrIntRepresentation(Sema *S, CallExpr *TheCall) { checkAllSignedTypes); } +static bool CheckBoolRepresentation(Sema *S, CallExpr *TheCall) { + auto checkAllBoolTypes = [](clang::QualType Pass

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127098 >From 5b093ca42fdc24f89bfccac25e6f2e17155432f6 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Wed, 12 Feb 2025 21:24:00 + Subject: [PATCH 1/5] Implement the 'and' HLSL function --- clang/include/clang/Ba

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -2079,6 +2079,14 @@ static bool CheckFloatingOrIntRepresentation(Sema *S, CallExpr *TheCall) { checkAllSignedTypes); } +static bool CheckBoolRepresentation(Sema *S, CallExpr *TheCall) { + auto checkAllBoolTypes = [](clang::QualType Pass

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -2079,6 +2079,14 @@ static bool CheckFloatingOrIntRepresentation(Sema *S, CallExpr *TheCall) { checkAllSignedTypes); } +static bool CheckBoolRepresentation(Sema *S, CallExpr *TheCall) { + auto checkAllBoolTypes = [](clang::QualType Pass

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127098 >From 5b093ca42fdc24f89bfccac25e6f2e17155432f6 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Wed, 12 Feb 2025 21:24:00 + Subject: [PATCH 1/4] Implement the 'and' HLSL function --- clang/include/clang/Ba

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127137 >From 4fae5642c6e8e305cdc687b4968ba5eabaa44b50 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 1/4] Add the AddUint64 HLSL builtin function - Defines the AddUint

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127098 >From 5b093ca42fdc24f89bfccac25e6f2e17155432f6 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Wed, 12 Feb 2025 21:24:00 + Subject: [PATCH 1/4] Implement the 'and' HLSL function --- clang/include/clang/Ba

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -2229,6 +2241,41 @@ static bool CheckResourceHandle( // returning an ExprError bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { switch (BuiltinID) { + case Builtin::BI__builtin_hlsl_adduint64: { +if (SemaRef.checkArgCount(TheCall, 2))

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -2229,6 +2241,41 @@ static bool CheckResourceHandle( // returning an ExprError bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { switch (BuiltinID) { + case Builtin::BI__builtin_hlsl_adduint64: { +if (SemaRef.checkArgCount(TheCall, 2))

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -finclude-default-header -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s \ +// RUN: -emit-llvm -O1 -verify + +bool test_too_few_arg(bool a) { + return __builtin_hlsl_and(a); + // expected-error@-1 {{too few arguments to function call

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/127098 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -finclude-default-header -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s \ +// RUN: -emit-llvm -O1 -verify + +bool test_too_few_arg(bool a) { + return __builtin_hlsl_and(a); + // expected-error@-1 {{too few arguments to function call

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -0,0 +1,27 @@ +// RUN: %clang_cc1 -finclude-default-header -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s \ +// RUN: -emit-llvm -O1 -verify + +bool test_too_few_arg(bool a) { + return __builtin_hlsl_and(a); + // expected-error@-1 {{too few arguments to function call

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -2245,6 +2245,17 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { break; } + case Builtin::BI__builtin_hlsl_and: { +if (SemaRef.checkArgCount(TheCall, 2)) + return true; +if (CheckVectorElementCallArgs(&SemaRef, TheCal

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -2229,6 +2241,41 @@ static bool CheckResourceHandle( // returning an ExprError bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { switch (BuiltinID) { + case Builtin::BI__builtin_hlsl_adduint64: { +if (SemaRef.checkArgCount(TheCall, 2))

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-14 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127137 >From 4fae5642c6e8e305cdc687b4968ba5eabaa44b50 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 1/3] Add the AddUint64 HLSL builtin function - Defines the AddUint

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -10655,6 +10655,8 @@ def err_second_argument_to_cwsc_not_pointer : Error< def err_vector_incorrect_num_elements : Error< "%select{too many|too few}0 elements in vector %select{initialization|operand}3 (expected %1 elements, have %2)">; +def err_invalid_even_odd_vector_el

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -2229,6 +2241,41 @@ static bool CheckResourceHandle( // returning an ExprError bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { switch (BuiltinID) { + case Builtin::BI__builtin_hlsl_adduint64: { +if (SemaRef.checkArgCount(TheCall, 2))

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-14 Thread Deric Cheung via cfe-commits
@@ -2245,6 +2245,17 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { break; } + case Builtin::BI__builtin_hlsl_and: { +if (SemaRef.checkArgCount(TheCall, 2)) + return true; +if (CheckVectorElementCallArgs(&SemaRef, TheCal

[clang] [llvm] [HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (PR #127137)

2025-02-13 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron created https://github.com/llvm/llvm-project/pull/127137 Fixes #99205. - Implements the HLSL intrinsic `AddUint64` used to perform unsigned 64-bit integer addition by using pairs of unsigned 32-bit integers instead of native 64-bit types - The LLVM intrinsic `ua

[clang] [HLSL] Implement the 'and' HLSL function (PR #127098)

2025-02-13 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/127098 >From 5b093ca42fdc24f89bfccac25e6f2e17155432f6 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Wed, 12 Feb 2025 21:24:00 + Subject: [PATCH 1/3] Implement the 'and' HLSL function --- clang/include/clang/Ba

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-11 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/125319 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-11 Thread Deric Cheung via cfe-commits
Icohedron wrote: To get the PR up and running, I am just marking hwasan as unsupported for now. A proper fix will be implemented later. The Issue #124045 will remain open to track this. https://github.com/llvm/llvm-project/pull/125599 ___ cfe-commits

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-11 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron ready_for_review https://github.com/llvm/llvm-project/pull/125599 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-10 Thread Deric Cheung via cfe-commits
@@ -0,0 +1,40 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s + +; CHECK: %dx.types.i32c = type { i32, i1 } Icohedron wrote: Perhaps I made the incorrect assumption that UAddc only accepts scalars. In the current imple

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-10 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/125599 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Reland "[HLSL] Implement the reflect HLSL function" (PR #125599)

2025-02-10 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/125599 >From dc616212f496098776d30f56151213d530917ba2 Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 3 Feb 2025 23:10:16 + Subject: [PATCH 1/2] Reapply "Reland "[HLSL] Implement the `reflect` HLSL function"

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-06 Thread Deric Cheung via cfe-commits
@@ -19105,6 +19105,51 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, return nullptr; switch (BuiltinID) { + case Builtin::BI__builtin_hlsl_adduint64: { Icohedron wrote: Do you think it is something I should do for this implementati

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-05 Thread Deric Cheung via cfe-commits
@@ -12553,6 +12553,8 @@ def err_std_initializer_list_malformed : Error< "%0 layout not recognized. Must be a non-polymorphic class type with no bases and two fields: a 'const E *' and either another 'const E *' or a 'std::size_t'">; // HLSL Diagnostics +def err_hlsl_adduin

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-05 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/125319 >From 1e194fdf6dc731276cd867501708b348e3bbc97c Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 1/8] Implement AddUint64 HLSL codegen and sema --- clang/include/

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-05 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/125319 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-05 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/125319 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-05 Thread Deric Cheung via cfe-commits
@@ -10623,7 +10623,7 @@ def err_second_argument_to_cwsc_not_pointer : Error< "second argument to __builtin_call_with_static_chain must be of pointer type">; def err_vector_incorrect_num_elements : Error< - "%select{too many|too few}0 elements in vector %select{initializat

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-05 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/125319 >From 1e194fdf6dc731276cd867501708b348e3bbc97c Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 1/6] Implement AddUint64 HLSL codegen and sema --- clang/include/

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-05 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/125319 >From 1e194fdf6dc731276cd867501708b348e3bbc97c Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 1/6] Implement AddUint64 HLSL codegen and sema --- clang/include/

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-04 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron updated https://github.com/llvm/llvm-project/pull/125319 >From 1e194fdf6dc731276cd867501708b348e3bbc97c Mon Sep 17 00:00:00 2001 From: Icohedron Date: Mon, 27 Jan 2025 11:18:09 -0800 Subject: [PATCH 1/5] Implement AddUint64 HLSL codegen and sema --- clang/include/

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-04 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/125319 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-04 Thread Deric Cheung via cfe-commits
@@ -359,18 +359,21 @@ class OpLowerer { return lowerToBindAndAnnotateHandle(F); } - Error replaceSplitDoubleCallUsages(CallInst *Intrin, CallInst *Op) { + Error replaceExtractElementTypeOfCallUsages(CallInst *Intrin, CallInst *Op) { for (Use &U : make_early_inc_ra

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-04 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/125319 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)

2025-02-04 Thread Deric Cheung via cfe-commits
https://github.com/Icohedron edited https://github.com/llvm/llvm-project/pull/125319 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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