[clang] [llvm][RISCV] Add frm range check for xsfvfnrclipxfqf (PR #172135)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/172135 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add BFloat16 to mangleRISCVFixedRVVVectorType. (PR #172095)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/172095 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm][RISCV] Add frm range check for xsfvfnrclipxfqf (PR #172135)

@@ -1440,6 +1444,12 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_mu: + case RISCVVector:

[clang] [llvm][RISCV] Add bf16 vfabs and vfneg intrinsics for zvfbfa. (PR #172130)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/172130 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AST][RISCV] Preserve RISC-V intrinsic pragma in AST (PR #171981)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/171981 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Intrinsic Support for RISC-V P extension (PR #157044)

@@ -1898,6 +1898,259 @@ let TargetPrefix = "riscv" in { let TargetPrefix = "riscv" in def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; +//===--===// +// Packed SIMD + +let

[clang] [llvm] [RISCV] Intrinsic Support for RISC-V P extension (PR #157044)

@@ -1898,6 +1898,259 @@ let TargetPrefix = "riscv" in { let TargetPrefix = "riscv" in def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; +//===--===// +// Packed SIMD + +let

[clang] [llvm] [RISCV] Intrinsic Support for RISC-V P extension (PR #157044)

@@ -1898,6 +1898,259 @@ let TargetPrefix = "riscv" in { let TargetPrefix = "riscv" in def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; +//===--===// +// Packed SIMD + +let

[clang] [AST][RISCV] Preserve RISC-V intrinsic pragma in AST (PR #171981)

@@ -9063,6 +9074,11 @@ void ASTReader::UpdateSema() { PointersToMembersPragmaLocation); } SemaObj->CUDA().ForceHostDeviceDepth = ForceHostDeviceDepth; + if (!RISCVVecIntrinsicPragma.empty()) { +SemaObj->RISCV().DeclareRVVBuiltins = RISCVVecIntrinsicPragma[0]; -

[clang] [AST][RISCV] Preserve RISC-V intrinsic pragma in AST (PR #171981)

@@ -5232,6 +5233,15 @@ void ASTWriter::WriteModuleFileExtension(Sema &SemaRef, Stream.ExitBlock(); } +void ASTWriter::WriteRISCVIntrinsicPragmas(Sema &SemaRef) { + RecordData Record; + Record.push_back(SemaRef.RISCV().DeclareRVVBuiltins); + Record.push_back(SemaRef.RISCV(

[clang] [llvm] [RISCV] Update P extension to the 018 version of the spec. (PR #170399)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/170399 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Propeller support for RISC-V (PR #170992)

@@ -89,6 +89,15 @@ RISCVInstrInfo::RISCVInstrInfo(const RISCVSubtarget &STI) #define GET_INSTRINFO_HELPERS #include "RISCVGenInstrInfo.inc" +void RISCVInstrInfo::insertNoop(MachineBasicBlock &MBB, +MachineBasicBlock::iterator MI) const { + Debu

[clang] [llvm] [RISCV] Add Propeller support for RISC-V (PR #170992)

@@ -6128,6 +6128,13 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, << A->getAsString(Args) << A->getValue(); else A->render(Args, CmdArgs); +} else if (Triple.isRISCV() && Triple.isOSBinFormatELF()) { + // Add RISC-V support

[clang] [llvm] [RISCV] Add Svrsw60t59b extension (PR #132321)

topperc wrote: > Please can you add information about this to llvm/docs/RISCVUsage.rst ? Looks like RISCVUsage.rst is there. Are you looking for something more? https://github.com/llvm/llvm-project/pull/132321 ___ cfe-commits mailing list cfe-commits@

[clang] [llvm] [RISCV] Update P extension to the 018 version of the spec. (PR #170399)

topperc wrote: > > `Also, because extensions Zba and Zbb are now assumed to be required for > > Base P, this version removes these scalar instructions that exist in Zba > > and Zbb: SH1ADD SEXT.B SEXT.H MIN MINU MAX MAXU REV8 CLZ CLZW` > > does is mean `P` implies `Zba` and `Zbb`? > > This is

[clang] [llvm] [RISCV][Zicfilp] Enable Zicfilp CFI compiler behaviors by looking at module flags (PR #152121)

topperc wrote: > Whether modeling per-Module behavior with TM.STI is not suitable, since > TM.STI is never intended to be in sync with and serve only one specific > Module? TM.STI is set based on what arguments are passed to the -mcpu and -mattr `cl::opt` in LLVM. clang does not always set th

[clang] [llvm] [RISCV][Zicfilp] Enable Zicfilp CFI compiler behaviors by looking at module flags (PR #152121)

topperc wrote: @mylai-mtk reverse ping. Can you rebase this patch? https://github.com/llvm/llvm-project/pull/152121 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Update Zvqdotq to v0.1 (PR #170648)

topperc wrote: > > I think I'm missing something. The release version is v0.0.1, not v0.1. As > > we don't seem to support three digit versions, isn't our only option > > truncation? > > Looks like our options are > > 1. Fix ld to use a different value for unknown version, but that would make

[clang] [llvm] [RISCV] Update Zvqdotq to v0.1 (PR #170648)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/170648 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Update P extension to the 018 version of the spec. (PR #170399)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/170399 >From 9d80d516bdeab8cc8e2efd64d5973260182463a5 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 2 Dec 2025 13:45:19 -0800 Subject: [PATCH 1/2] [RISCV] Update P extension to the 018 version of the spec. h

[clang] [llvm] [RISCV][llvm] Support Smpmpmt version 0.6 (PR #166322)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/166322 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][llvm] Support Smpmpmt version 0.6 (PR #166322)

@@ -352,6 +351,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zvqdotq`` LLVM implements the `0.0.1 draft specification `__. +``experimental-smpmpmt`` + LL

[clang] [RISCV] Set __GCC_CONSTRUCTIVE_SIZE/__GCC_DESTRUCTIVE_SIZE to 64 (PR #162986)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/162986 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Set __GCC_CONSTRUCTIVE_SIZE/__GCC_DESTRUCTIVE_SIZE to 64 (PR #162986)

@@ -0,0 +1,12 @@ +// REQUIRES: riscv-registered-target topperc wrote: Does this really require riscv-register-target? It doesn't run backend code generation. https://github.com/llvm/llvm-project/pull/162986 ___ cfe-co

[clang] [llvm] [GlobalOpt] Add TTI interface useFastCCForInternalCall for FASTCC (PR #164768)

topperc wrote: > 2 only happens when users use __attribute__((target(""))), but user > cannot use a if it doesn't exist at all. As long as we define a new > fastcc implementation together when defining the new feature, there won't be > a problem. It can also happen in LTO if differen

[clang] [llvm] [RISCV][llvm] Support Smpmpmt version 0.6 (PR #166322)

@@ -139,6 +139,7 @@ on support follow. ``Smepmp``Supported ``Smmpm`` Supported ``Smnpm`` Supported + ``Smpmpmt`` Supported topperc wrote: Should be in the experimental extension section with a link to the spec.

[clang] [llvm] [RISCV][llvm] Support Smpmpmt version 0.6 (PR #166322)

https://github.com/topperc requested changes to this pull request. Extension isn't ratified yet so should be experimental. https://github.com/llvm/llvm-project/pull/166322 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/c

[clang] [llvm] [RISCV][llvm] Support Smpmpmt version 0.6 (PR #166322)

@@ -956,6 +956,9 @@ def FeatureStdExtSsdbltrp def FeatureStdExtSmepmp : RISCVExtension<1, 0, "Enhanced Physical Memory Protection">; +def FeatureStdExtSmpmpmt +: RISCVExtension<0, 6, "PMP-based Memory Types Extension">; topperc wrote: Shouldn't this b

[clang] [llvm] [RISCV][llvm] Support Smpmpmt version 0.6 (PR #166322)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/166322 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Add big-endian RISC-V target support (PR #165599)

@@ -255,6 +255,8 @@ class LLVM_LIBRARY_VISIBILITY FreeBSDTargetInfo : public OSTargetInfo { break; case llvm::Triple::loongarch64: case llvm::Triple::riscv64: +case llvm::Triple::riscv32be: topperc wrote: Why is riscv32be here, but riscv32 i

[clang] [clang][RISCV] Add big-endian RISC-V target support (PR #165599)

@@ -1732,16 +1734,20 @@ static void findRISCVBareMetalMultilibs(const Driver &D, .flag(Twine("-march=", Element.march).str()) .flag(Twine("-mabi=", Element.mabi).str())); } + + std::string EndiannessSuffix = TargetTriple.isLittleEndian() ? "" : "be";

[clang] [clang][RISCV] Add big-endian RISC-V target support (PR #165599)

@@ -513,6 +515,8 @@ class LLVM_LIBRARY_VISIBILITY OpenBSDTargetInfo : public OSTargetInfo { break; case llvm::Triple::loongarch64: case llvm::Triple::riscv64: +case llvm::Triple::riscv32be: topperc wrote: Why is riscv32be here, but riscv32 i

[clang] [clang][RISCV] Add big-endian RISC-V target support (PR #165599)

@@ -1789,7 +1795,8 @@ static void findRISCVMultilibs(const Driver &D, .FilterOut(NonExistent); Multilib::flags_list Flags; - bool IsRV64 = TargetTriple.getArch() == llvm::Triple::riscv64; + bool IsRV64 = (TargetTriple.getArch() == llvm::Triple::riscv64 || ---

[clang] [llvm] [RISCV] Support Zvfofp4min assembler version 0.1 (PR #164820)

https://github.com/topperc requested changes to this pull request. Missing update of RISCVUsage.rst https://github.com/llvm/llvm-project/pull/164820 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo

[clang] [llvm] [RISCV] Support Zvfofp4min assembler version 0.1 (PR #164820)

@@ -1838,5 +1838,8 @@ let Predicates = [HasVInstructionsI64, IsRV64] in { } } // Predicates = [HasVInstructionsI64, IsRV64] +let Predicates = [HasStdExtZvfofp4min] in topperc wrote: Please create RISCVInstrInfoZvfofp4min.td so we have a place to put the ise

[clang] [llvm] [RISCV] Support Zvfofp4min assembler version 0.1 (PR #164820)

@@ -740,6 +740,14 @@ def HasStdExtZvfbfminOrZvfofp8min "'Zvfbfmin' (Vector BF16 Converts) or " "'Zvfofp8min' (Vector OFP8 Converts)">; +def FeatureStdExtZvfofp4min +: RISCVExperimentalExtension<0, 1, "OFP4 conversion extens

[clang] [llvm] [RISCV] Support Zvfofp4min assembler version 0.1 (PR #164820)

@@ -740,6 +740,14 @@ def HasStdExtZvfbfminOrZvfofp8min "'Zvfbfmin' (Vector BF16 Converts) or " "'Zvfofp8min' (Vector OFP8 Converts)">; +def FeatureStdExtZvfofp4min +: RISCVExperimentalExtension<0, 1, "OFP4 conversion extens

[clang] [RISCV] Support XSfmm C intrinsics (PR #143070)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/143070 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [llvm][clang] Add intrinsic support for cbo.zero instruction (Zicboz ISA extension) (PR #164822)

@@ -0,0 +1,30 @@ +/*=== riscv_cmo.h - RISC-V CMO intrinsics === + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-

[clang] [llvm] [RISCV][MC] Introduce XSfvfexp* and XSfvfbfexpa* extensions and their MC supports (PR #164349)

@@ -1334,6 +1334,44 @@ def HasVendorXSfvfnrclipxfqf AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf), "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">; +// Note: XSfvfbfexp16e depends on either Zvfbfmin _or_ Zvfbfa, wh

[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

@@ -0,0 +1,22 @@ +// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32ia -x c -E -dM %s \ +// RUN: -o - | FileCheck %s +// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i_zalrsc -x c -E \ +// RUN: -dM %s -o - | FileCheck %s +// RUN: %clang --target=riscv64-un

[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

@@ -308,7 +308,65 @@ class PseudoMaskedAMOMinMaxPat (AMOInst GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt, timm:$ordering)>; -let Predicates = [HasStdExtA] in { +let Predicates = [HasStdExtZalrsc, NoStdExtZaamo] in { topperc wrote: Ther

[clang] [RISCV] Support XSfmm C intrinsics (PR #143070)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/143070 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support XSfmm C intrinsics (PR #143070)

@@ -708,8 +708,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15) || SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 4); } - case RISCVVector::BI__builtin_rvv_sf_vtzero_t: -return

[clang] [RISCV] Support XSfmm C intrinsics (PR #143070)

@@ -19,4 +19,8 @@ void test(vfloat32m8_t arg0, vuint8m8_t arg1) { __riscv_sf_mm_e5m2_e4m3(20, arg1, arg1, 1, 2, 3); /* expected-error {{argument value 20 is outside the valid range [0, 15]}} */ __riscv_sf_mm_u_u(24, arg1, arg1, 1, 2, 3); /* expected-error {{argument value

[clang] [RISCV] Support XSfmm C intrinsics (PR #143070)

@@ -708,8 +708,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15) || SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 4); } - case RISCVVector::BI__builtin_rvv_sf_vtzero_t: -return

[clang] [llvm] [RISCV] Support Zvfbfa codegen and C intrinsics (PR #161158)

@@ -288,9 +288,10 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool hasVInstructionsI64() const { return HasStdExtZve64x; } bool hasVInstructionsF16Minimal() const { return HasStdExtZvfhmin; } bool hasVInstructionsF16() const { return HasStdExtZvfh; } - bool

[clang] [clang][Driver] Support Outline Flags on RISC-V and X86 (PR #163664)

@@ -2916,12 +2916,16 @@ void tools::addMachineOutlinerArgs(const Driver &D, if (Arg *A = Args.getLastArg(options::OPT_moutline, options::OPT_mno_outline)) { if (A->getOption().matches(options::OPT_moutline)) { - // We only support -mout

[clang] [llvm] [RISCV] Support Zvfbfa codegen and C intrinsics (PR #161158)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/161158 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support XSfmm C intrinsics (PR #143070)

@@ -679,6 +685,50 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, return CheckVSetVL(1, 2); case RISCVVector::BI__builtin_rvv_vsetvlimax: return CheckVSetVL(0, 1); + case RISCVVector::BI__builtin_rvv_sf_vsettnt: + case RISCVVector::BI__builtin_rvv

[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

@@ -29572,6 +36161,22 @@ define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT:addi sp, sp, 48 ; RV64I-NEXT:ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB175_1: # =>This

[clang] [llvm] [RISCV] Support Zvfbfa codegen and C intrinsics (PR #161158)

https://github.com/topperc requested changes to this pull request. This crashes commuting FMA instructions. We need to update findCommutedOpIndices and commuteInstructionImpl https://github.com/llvm/llvm-project/pull/161158 ___ cfe-commits mailing lis

[clang] [llvm] [RISCV] Support Zvfbfa codegen and C intrinsics (PR #161158)

@@ -44,6 +44,337 @@ let Predicates = [HasStdExtZvfbfminOrZvfofp8min] in { let mayRaiseFPException = true, Predicates = [HasStdExtZvfbfwma] in defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM; +defset list AllWidenableIntToBFloatVectors = { topperc wrote: `

[clang] [RISCV] Add missing CHECK lines for Zkt to sifive-p450/p470/p670 test. NFC (PR #161393)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/161393 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support Zvfbfa codegen and C intrinsics (PR #161158)

@@ -164,6 +164,7 @@ struct DemandedFields { // If this is true, we demand that VTYPE is set to some legal state, i.e. that // vill is unset. bool VILL = false; + bool UseAltFmt = false; topperc wrote: `Use` is redundant in the field name. The struct is

[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

@@ -28602,6 +34891,21 @@ define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64I-NEXT:addi sp, sp, 48 ; RV64I-NEXT:ret ; +; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic: +; RV64I-ZALRSC: # %bb.0: +; RV64I-ZALRSC-NEXT: .LBB165_1: # =>This In

[clang] [llvm] [RISCV] Support Zvfbfa codegen and C intrinsics (PR #161158)

@@ -44,6 +44,337 @@ let Predicates = [HasStdExtZvfbfminOrZvfofp8min] in { let mayRaiseFPException = true, Predicates = [HasStdExtZvfbfwma] in defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM; +defset list AllWidenableIntToBFloatVectors = { + def : VTypeInfoToWide; + def :

[clang] [llvm] [RISCV] Remove Zicntr from sifive-p450/p470/p670. (PR #161444)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/161444 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] support BITINT with mixed-type (PR #156592)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/156592 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

@@ -24483,6 +24483,26 @@ ISD::NodeType RISCVTargetLowering::getExtendForAtomicCmpSwapArg() const { return Subtarget.hasStdExtZacas() ? ISD::ANY_EXTEND : ISD::SIGN_EXTEND; } +ISD::NodeType RISCVTargetLowering::getExtendForAtomicRMWArg(unsigned Op) const { + // Zaamo will u

[clang] [RISCV] Add missing CHECK lines for Zkt to sifive-p450/p470/p670 test. NFC (PR #161393)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/161393 None >From d498c8104b51b96115a190f955cbaa6adcd65210 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 30 Sep 2025 07:59:38 -0700 Subject: [PATCH] [RISCV] Add missing CHECK lines for Zkt to sifive-p450/p47

[clang] [llvm] [RISCV] Remove Zicntr from sifive-p450/p470/p670. (PR #161444)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/161444 These cores don't implement the `time` CSR. They require SBI to trap and emulate it which is allowed by RVA20U. >From 257dc5f4b78600b0be2adf5de3cdb7fe7fbdf452 Mon Sep 17 00:00:00 2001 From: Craig Topper Date:

[clang] [llvm] [RISCV] Support Zvfbfa codegen and C intrinsics (PR #161158)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/161158 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support Zvfbfa codegen and C intrinsics (PR #161158)

@@ -324,6 +327,9 @@ static bool areCompatibleVTYPEs(uint64_t CurVType, uint64_t NewVType, if (Used.MaskPolicy && RISCVVType::isMaskAgnostic(CurVType) != RISCVVType::isMaskAgnostic(NewVType)) return false; + if (Used.UseAltFmt == true &&

[clang] [llvm] [RISCV] Bump Zalasr version to 0.9. (PR #162329)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/162329 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

@@ -285,6 +378,34 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI, .addReg(ScratchReg) .addImm(-1); break; + case AtomicRMWInst::Min: +BuildMI(LoopMBB, DL, TII->get(RISCV::MIN), ScratchReg) +.addReg(DestReg) +

[clang] [llvm] [RISCV] Support Zvfbfa codegen and C intrinsics (PR #161158)

@@ -364,7 +368,7 @@ defset list AllVectors = { def VF16M4: GroupVTypeInfo; def VF16M8: GroupVTypeInfo; + V_M8, f16, FPR16>; topperc wrote: Stray formatting change https://github.com/llvm/llvm-project/pull/1

[clang] [llvm] [RISCV] Support Zvfbfa codegen and C intrinsics (PR #161158)

topperc wrote: @4vtomat I've pushed code to handle _ALT FMA and vfwadd/vfwsub in commuting and the three address instruction pass to match what we do for the non-_ALT instructions. https://github.com/llvm/llvm-project/pull/161158 ___ cfe-commits mail

[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

@@ -429,7 +429,20 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) { } SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { - SDValue Op2 = GetPromotedInteger(N->getOperand(2)); + SDValue Op2 = N->getOperand(2); + switch(TLI.getExtendForAto

[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/163672 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

@@ -192,8 +192,11 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__riscv_muldiv"); } - if (ISAInfo->hasExtension("a")) { + // The "a" extension is composed of "zalrsc" and "zaamo" + if (ISAInfo->hasExtension("zalrsc") && ISAIn

[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

@@ -308,7 +308,67 @@ class PseudoMaskedAMOMinMaxPat (AMOInst GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt, timm:$ordering)>; -let Predicates = [HasStdExtA] in { +let Predicates = [HasStdExtZalrsc, NoStdExtZaamo] in { + +let Size = 16 in { +def PseudoAtom

[clang] [llvm] [RISCV][LLVM] Enable atomics for 'Zalrsc' (PR #163672)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/163672 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support Zvfbfa codegen and C intrinsics (PR #161158)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/161158 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][Driver][RISCV] Rename `getRISCFeaturesFromMcpu`. NFCI (PR #162545)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/162545 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Remove break after return in RISCVVEmitter.cpp. NFC (PR #161599)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/161599 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Remove break after return in RISCVVEmitter.cpp. NFC (PR #161599)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/161599 None >From 545b45e2cf09189fc7e92fd8901614971d642ced Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 1 Oct 2025 15:39:21 -0700 Subject: [PATCH] [RISCV] Remove break after return in RISCVVEmitter.cpp. NFC

[clang] [clang][RISCV] support BITINT with mixed-type (PR #156592)

@@ -680,22 +680,22 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed, if (const auto *ED = Ty->getAsEnumDecl()) Ty = ED->getIntegerType(); -// All integral types are promoted to XLen width -if (Size < XLen && Ty->isIntegralOrEnumerat

[clang] [llvm] [RISCV] Add MC layer support for Andes XAndesVSIntH extension. (PR #159514)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/159514 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] support BITINT with mixed-type (PR #156592)

@@ -680,22 +680,22 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed, if (const auto *ED = Ty->getAsEnumDecl()) Ty = ED->getIntegerType(); -// All integral types are promoted to XLen width -if (Size < XLen && Ty->isIntegralOrEnumerat

[clang] [clang][RISCV] support BITINT with mixed-type (PR #156592)

@@ -680,14 +680,11 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed, if (const auto *ED = Ty->getAsEnumDecl()) Ty = ED->getIntegerType(); -// All integral types are promoted to XLen width -if (Size < XLen && Ty->isIntegralOrEnumerat

[clang] [llvm] [RISCV] Add MVendorID, MArchID, and MImpID for sifive-p550. (PR #159465)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/159465 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support for Zvabd fast-track proposal (PR #124239)

@@ -20594,6 +20645,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, if (SDValue V = combineVqdotAccum(N, DAG, Subtarget)) return V; return combineToVWMACC(N, DAG, Subtarget); + case RISCVISD::VWADDU_VL: topperc wrote: ok https://

[clang] [llvm] [RISCV] Add MVendorID, MArchID, and MImpID for sifive-p550. (PR #159465)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/159465 >From 5450ee627726fe89312a9223ea27ff5251c86caf Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 17 Sep 2025 15:01:47 -0700 Subject: [PATCH 1/2] [RISCV] Add MVendorID, MArchID, and MImpID for sifive-p550.

[clang] [llvm] [RISCV] Implement MC support for Zvfofp8min extension (PR #157014)

https://github.com/topperc approved this pull request. LGTM with the version number issue fixed. https://github.com/llvm/llvm-project/pull/157014 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cf

[clang] [llvm] RISCV: the builtins support for MIPS RV64 P8700 execution control . (PR #159246)

@@ -0,0 +1,20 @@ +//===- IntrinsicsRISCVXMIPS.td - Defines MIPS intrinsics ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[clang] [llvm] RISCV: the builtins support for MIPS RV64 P8700 execution control . (PR #159246)

@@ -0,0 +1,20 @@ +//===- IntrinsicsRISCVXMIPS.td - Defines MIPS intrinsics ---*- tablegen -*-===// topperc wrote: Limit line to 80 columns https://github.com/llvm/llvm-project/pull/159246 ___ cfe-commits mailing l

[clang] [llvm] [RISCV] Support for Zvabd fast-track proposal (PR #124239)

@@ -20594,6 +20645,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, if (SDValue V = combineVqdotAccum(N, DAG, Subtarget)) return V; return combineToVWMACC(N, DAG, Subtarget); + case RISCVISD::VWADDU_VL: topperc wrote: What about V

[clang] [llvm] RISCV: the builtins support for MIPS RV64 P8700 execution control . (PR #159246)

@@ -0,0 +1,27 @@ +//==- BuiltinsRISCVXMIPS.td - RISC-V MIPS Builtin database*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Enabled debug entry support by default (PR #157703)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/157703 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add MC support of Zibi experimental extension (PR #127463)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/127463 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [flang] [llvm] [RISCV] Make "target-feature +i" explicit (PR #157835)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/157835 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Enabled debug entry support by default (PR #157703)

@@ -0,0 +1,74 @@ +;; Test RISC-V 64 bit: topperc wrote: Why only testing 64 bit? https://github.com/llvm/llvm-project/pull/157703 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/m

[clang] [llvm] [RISCV][MC] Add MC support of Zibi experimental extension (PR #127463)

@@ -0,0 +1,44 @@ +//===-- RISCVInstrInfoZibi.td - 'Zibi' instructions *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [llvm] [RISCV] Enabled debug entry support by default (PR #157703)

@@ -0,0 +1,74 @@ +;; Test RISC-V 64 bit: +; RUN: llc -emit-call-site-info -stop-after=livedebugvalues -mtriple=riscv64-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK64 +; RUN: llc -force-instr-ref-livedebugvalues=1 -emit-call-site-info -stop-after=livedebugvalues -mtriple

[clang] [llvm] [RISCV][Zicfilp] Enable Zicfilp CFI compiler behaviors by looking at module flags (PR #152121)

topperc wrote: The features in STI.TM are basically all 0 in LTO linking. It’s populated by mcpu and mattr backend command line options. Clang sets them when generating IR, but they aren’t set during LTO linking. For LTO, everything needs to be in IR. Each Function gets its own target-cpu and

[clang] [clang][RISCV] support BITINT with mixed-type (PR #156592)

@@ -696,6 +693,11 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed, /*ByVal=*/false); } +// All integral types are promoted to XLen width +if (Size < XLen && Ty->isIntegralOrEnumerationType()) { + return extendType(Ty, CG

[clang] [clang][RISCV] support BITINT with mixed-type (PR #156592)

@@ -680,14 +680,11 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed, if (const auto *ED = Ty->getAsEnumDecl()) Ty = ED->getIntegerType(); -// All integral types are promoted to XLen width -if (Size < XLen && Ty->isIntegralOrEnumerat

[clang] [clang][RISCV] support BITINT with mixed-type (PR #156592)

@@ -680,14 +680,11 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed, if (const auto *ED = Ty->getAsEnumDecl()) Ty = ED->getIntegerType(); -// All integral types are promoted to XLen width -if (Size < XLen && Ty->isIntegralOrEnumerat

[clang] [llvm] [RISCV][MC] Add MC support of Zibi experimental extension (PR #127463)

@@ -78,6 +78,12 @@ def FeatureStdExtE : RISCVExtension<2, 0, "Embedded Instruction Set with 16 GPRs">, RISCVExtensionBitmask<0, 4>; +def FeatureStdExtZibi +: RISCVExperimentalExtension<0, 1, "Branch with Immediate">; +def HasStdExtZibi : Predicate<"Subtarget->has

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