https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/170399
>From 9d80d516bdeab8cc8e2efd64d5973260182463a5 Mon Sep 17 00:00:00 2001 From: Craig Topper <[email protected]> Date: Tue, 2 Dec 2025 13:45:19 -0800 Subject: [PATCH 1/2] [RISCV] Update P extension to the 018 version of the spec. https://www.jhauser.us/RISCV/ext-P/ --- llvm/docs/RISCVUsage.rst | 3 + llvm/lib/Target/RISCV/RISCVFeatures.td | 22 +- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 2 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 28 +- llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 89 ++- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 43 +- llvm/lib/Target/RISCV/RISCVSubtarget.h | 4 +- llvm/test/CodeGen/RISCV/attributes.ll | 4 +- llvm/test/CodeGen/RISCV/rv32p.ll | 670 +----------------- llvm/test/CodeGen/RISCV/rv64p.ll | 629 ---------------- llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll | 18 +- llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll | 24 +- llvm/test/MC/RISCV/attribute-arch.s | 8 +- llvm/test/MC/RISCV/rv32i-invalid.s | 4 +- llvm/test/MC/RISCV/rv32p-invalid.s | 9 +- llvm/test/MC/RISCV/rv32p-valid.s | 127 ++-- llvm/test/MC/RISCV/rv64p-valid.s | 98 +-- .../TargetParser/RISCVISAInfoTest.cpp | 2 +- 18 files changed, 189 insertions(+), 1595 deletions(-) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index a21f03d389444..8f360a97ba9d9 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -333,6 +333,9 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised. +``experimental-p`` + LLVM implements the `018 draft specification <https://www.jhauser.us/RISCV/ext-P/>`__. + ``experimental-zalasr`` LLVM implements the `0.9 draft specification <https://github.com/riscv/riscv-zalasr/releases/tag/v0.9>`__. diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 4fc776fcdeb9a..20b9af5a5ae0b 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1106,38 +1106,18 @@ def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">, // Packed SIMD Extensions def FeatureStdExtP - : RISCVExperimentalExtension<0, 15, + : RISCVExperimentalExtension<0, 18, "'Base P' (Packed SIMD)">; def HasStdExtP : Predicate<"Subtarget->hasStdExtP()">, AssemblerPredicate<(all_of FeatureStdExtP), "'Base P' (Packed SIMD)">; -def HasStdExtZbaOrP - : Predicate<"Subtarget->hasStdExtZba() || Subtarget->hasStdExtP()">, - AssemblerPredicate<(any_of FeatureStdExtZba, FeatureStdExtP), - "'Zba' (Address Generation Instructions) or " - "'Base P' (Packed-SIMD)">; - -def HasStdExtZbbOrP - : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtP()">, - AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtP), - "'Zbb' (Basic Bit-Manipulation) or " - "'Base P' (Packed-SIMD)">; - def HasStdExtZbkbOrP : Predicate<"Subtarget->hasStdExtZbkb() || Subtarget->hasStdExtP()">, AssemblerPredicate<(any_of FeatureStdExtZbkb, FeatureStdExtP), "'Zbkb' (Bitmanip instructions for Cryptography) or " "'Base P' (Packed-SIMD)">; -def HasStdExtZbbOrZbkbOrP - : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb() || " - "Subtarget->hasStdExtP()">, - AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb, FeatureStdExtP), - "'Zbb' (Basic Bit-Manipulation) or " - "'Zbkb' (Bitmanip instructions for Cryptography) or " - "'Base P' (Packed-SIMD)">; - //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 7cf6f203fda89..9bc0d1280d968 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -1893,7 +1893,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { 0); MachineSDNode *PackDH = CurDAG->getMachineNode( - RISCV::PPACK_DH, DL, MVT::Untyped, {RegPair0, RegPair1}); + RISCV::PPAIRE_DB, DL, MVT::Untyped, {RegPair0, RegPair1}); SDValue Lo = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_even, DL, MVT::i32, SDValue(PackDH, 0)); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ab2652eac3823..f7db690030eed 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -336,9 +336,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); - if (!Subtarget.hasStdExtZbb() && !Subtarget.hasStdExtP() && - !Subtarget.hasVendorXTHeadBb() && !Subtarget.hasVendorXqcibm() && - !Subtarget.hasVendorXAndesPerf() && + if (!Subtarget.hasStdExtZbb() && !Subtarget.hasVendorXTHeadBb() && + !Subtarget.hasVendorXqcibm() && !Subtarget.hasVendorXAndesPerf() && !(Subtarget.hasVendorXCValu() && !Subtarget.is64Bit())) setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::i8, MVT::i16}, Expand); @@ -411,7 +410,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::BITREVERSE, MVT::i8, Custom); } - if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtP() || + if (Subtarget.hasStdExtZbb() || (Subtarget.hasVendorXCValu() && !Subtarget.is64Bit())) { setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT, Legal); @@ -422,9 +421,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom); } else { setOperationAction(ISD::CTTZ, XLenVT, Expand); - // If have a CLZW, but not CTZW, custom promote i32. - if (Subtarget.hasStdExtP() && Subtarget.is64Bit()) - setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom); } if (!Subtarget.hasCPOPLike()) { @@ -14997,24 +14993,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, bool IsCTZ = N->getOpcode() == ISD::CTTZ || N->getOpcode() == ISD::CTTZ_ZERO_UNDEF; - // Without Zbb, lower as 32 - clzw(~X & (X-1)) - if (IsCTZ && !Subtarget.hasStdExtZbb()) { - assert(Subtarget.hasStdExtP()); - - NewOp0 = DAG.getFreeze(NewOp0); - SDValue Not = DAG.getNOT(DL, NewOp0, MVT::i64); - SDValue Minus1 = DAG.getNode(ISD::SUB, DL, MVT::i64, NewOp0, - DAG.getConstant(1, DL, MVT::i64)); - SDValue And = DAG.getNode(ISD::AND, DL, MVT::i64, Not, Minus1); - SDValue CLZW = DAG.getNode(RISCVISD::CLZW, DL, MVT::i64, And); - SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i64, - DAG.getConstant(32, DL, MVT::i64), CLZW); - SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, Sub, - DAG.getValueType(MVT::i32)); - Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res)); - return; - } - unsigned Opc = IsCTZ ? RISCVISD::CTZW : RISCVISD::CLZW; SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp0); Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res)); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index 599358368594f..4515a8d0f42d0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -632,8 +632,8 @@ let Predicates = [HasStdExtP] in { def PSUB_H : RVPBinary_rr<0b1000, 0b00, 0b000, "psub.h">; def PSUB_B : RVPBinary_rr<0b1000, 0b10, 0b000, "psub.b">; - def PDIF_H : RVPBinary_rr<0b1001, 0b00, 0b000, "pdif.h">; - def PDIF_B : RVPBinary_rr<0b1001, 0b10, 0b000, "pdif.b">; + def PABD_H : RVPBinary_rr<0b1001, 0b00, 0b000, "pabd.h">; + def PABD_B : RVPBinary_rr<0b1001, 0b10, 0b000, "pabd.b">; def PSSUB_H : RVPBinary_rr<0b1010, 0b00, 0b000, "pssub.h">; def PSSUB_B : RVPBinary_rr<0b1010, 0b10, 0b000, "pssub.b">; @@ -641,8 +641,8 @@ let Predicates = [HasStdExtP] in { def PASUB_H : RVPBinary_rr<0b1011, 0b00, 0b000, "pasub.h">; def PASUB_B : RVPBinary_rr<0b1011, 0b10, 0b000, "pasub.b">; - def PDIFU_H : RVPBinary_rr<0b1101, 0b00, 0b000, "pdifu.h">; - def PDIFU_B : RVPBinary_rr<0b1101, 0b10, 0b000, "pdifu.b">; + def PABDU_H : RVPBinary_rr<0b1101, 0b00, 0b000, "pabdu.h">; + def PABDU_B : RVPBinary_rr<0b1101, 0b10, 0b000, "pabdu.b">; def PSSUBU_H : RVPBinary_rr<0b1110, 0b00, 0b000, "pssubu.h">; def PSSUBU_B : RVPBinary_rr<0b1110, 0b10, 0b000, "pssubu.b">; @@ -700,9 +700,9 @@ let Predicates = [HasStdExtP] in { def SRX : RVPTernary_rrr<0b0101, 0b11, 0b001, "srx">; def PMULU_H_B01 : RVPBinary_rr<0b0110, 0b00, 0b001, "pmulu.h.b01">; - def PDIFSUMU_B : RVPBinary_rr<0b0110, 0b10, 0b001, "pdifsumu.b">; + def PABDSUMU_B : RVPBinary_rr<0b0110, 0b10, 0b001, "pabdsumu.b">; - def PDIFSUMAU_B : RVPTernary_rrr<0b0111, 0b10, 0b001, "pdifsumau.b">; + def PABDSUMAU_B : RVPTernary_rrr<0b0111, 0b10, 0b001, "pabdsumau.b">; } // Predicates = [HasStdExtP] let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in { def MUL_H01 : RVPBinary_rr<0b0010, 0b01, 0b001, "mul.h01">; @@ -832,32 +832,25 @@ let Predicates = [HasStdExtP, IsRV64] in { // Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27. // Here we include the 0 in the f field to reduce number of tablegen classes. let Predicates = [HasStdExtP] in { - def PPACK_H : RVPBinary_rr<0b0000, 0b00, 0b100, "ppack.h">; + def PPAIRE_B : RVPBinary_rr<0b0000, 0b00, 0b100, "ppaire.b">; - def PPACKBT_H : RVPBinary_rr<0b0010, 0b00, 0b100, "ppackbt.h">; + def PPAIREO_B : RVPBinary_rr<0b0010, 0b00, 0b100, "ppaireo.b">; + def PPAIREO_H : RVPBinary_rr<0b0010, 0b01, 0b100, "ppaireo.h">; - def PPACKTB_H : RVPBinary_rr<0b0100, 0b00, 0b100, "ppacktb.h">; + def PPAIROE_B : RVPBinary_rr<0b0100, 0b00, 0b100, "ppairoe.b">; + def PPAIROE_H : RVPBinary_rr<0b0100, 0b01, 0b100, "ppairoe.h">; - def PPACKT_H : RVPBinary_rr<0b0110, 0b00, 0b100, "ppackt.h">; + def PPAIRO_B : RVPBinary_rr<0b0110, 0b00, 0b100, "ppairo.b">; + def PPAIRO_H : RVPBinary_rr<0b0110, 0b01, 0b100, "ppairo.h">; } // Predicates = [HasStdExtP] -let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in { - def PACKBT_RV32 : RVPBinary_rr<0b0010, 0b01, 0b100, "packbt">; - - def PACKTB_RV32 : RVPBinary_rr<0b0100, 0b01, 0b100, "packtb">; - - def PACKT_RV32 : RVPBinary_rr<0b0110, 0b01, 0b100, "packt">; -} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" let Predicates = [HasStdExtP, IsRV64] in { - def PPACK_W : RVPBinary_rr<0b0000, 0b01, 0b100, "ppack.w">; + def PPAIRE_H : RVPBinary_rr<0b0000, 0b01, 0b100, "ppaire.h">; - def PPACKBT_W : RVPBinary_rr<0b0010, 0b01, 0b100, "ppackbt.w">; - def PACKBT_RV64 : RVPBinary_rr<0b0010, 0b11, 0b100, "packbt">; + def PPAIREO_W : RVPBinary_rr<0b0010, 0b11, 0b100, "ppaireo.w">; - def PPACKTB_W : RVPBinary_rr<0b0100, 0b01, 0b100, "ppacktb.w">; - def PACKTB_RV64 : RVPBinary_rr<0b0100, 0b11, 0b100, "packtb">; + def PPAIROE_W : RVPBinary_rr<0b0100, 0b11, 0b100, "ppairoe.w">; - def PPACKT_W : RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">; - def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">; + def PPAIRO_W : RVPBinary_rr<0b0110, 0b11, 0b100, "ppairo.w">; } // Predicates = [HasStdExtP, IsRV64] let Predicates = [HasStdExtP] in { @@ -1385,8 +1378,8 @@ let Predicates = [HasStdExtP, IsRV32] in { def PSUB_DB : RVPPairBinary_rr<0b1000, 0b10, "psub.db">; def SUBD : RVPPairBinary_rr<0b1000, 0b11, "subd">; - def PDIF_DH : RVPPairBinary_rr<0b1001, 0b00, "pdif.dh">; - def PDIF_DB : RVPPairBinary_rr<0b1001, 0b10, "pdif.db">; + def PABD_DH : RVPPairBinary_rr<0b1001, 0b00, "pabd.dh">; + def PABD_DB : RVPPairBinary_rr<0b1001, 0b10, "pabd.db">; def PSSUB_DH : RVPPairBinary_rr<0b1010, 0b00, "pssub.dh">; def PSSUB_DW : RVPPairBinary_rr<0b1010, 0b01, "pssub.dw">; @@ -1396,8 +1389,8 @@ let Predicates = [HasStdExtP, IsRV32] in { def PASUB_DW : RVPPairBinary_rr<0b1011, 0b01, "pasub.dw">; def PASUB_DB : RVPPairBinary_rr<0b1011, 0b10, "pasub.db">; - def PDIFU_DH : RVPPairBinary_rr<0b1101, 0b00, "pdifu.dh">; - def PDIFU_DB : RVPPairBinary_rr<0b1101, 0b10, "pdifu.db">; + def PABDU_DH : RVPPairBinary_rr<0b1101, 0b00, "pabdu.dh">; + def PABDU_DB : RVPPairBinary_rr<0b1101, 0b10, "pabdu.db">; def PSSUBU_DH : RVPPairBinary_rr<0b1110, 0b00, "pssubu.dh">; def PSSUBU_DW : RVPPairBinary_rr<0b1110, 0b01, "pssubu.dw">; @@ -1413,17 +1406,17 @@ let Predicates = [HasStdExtP, IsRV32] in { def PSSH1SADD_DH : RVPPairBinaryShift_rr<0b011, 0b00, "pssh1sadd.dh">; def PSSH1SADD_DW : RVPPairBinaryShift_rr<0b011, 0b01, "pssh1sadd.dw">; - def PPACK_DH : RVPPairBinaryPack_rr<0b000, 0b00, "ppack.dh">; - def PPACK_DW : RVPPairBinaryPack_rr<0b000, 0b01, "ppack.dw">; + def PPAIRE_DB : RVPPairBinaryPack_rr<0b000, 0b00, "ppaire.db">; + def PPAIRE_DH : RVPPairBinaryPack_rr<0b000, 0b01, "ppaire.dh">; - def PPACKBT_DH : RVPPairBinaryPack_rr<0b001, 0b00, "ppackbt.dh">; - def PPACKBT_DW : RVPPairBinaryPack_rr<0b001, 0b01, "ppackbt.dw">; + def PPAIREO_DB : RVPPairBinaryPack_rr<0b001, 0b00, "ppaireo.db">; + def PPAIREO_DH : RVPPairBinaryPack_rr<0b001, 0b01, "ppaireo.dh">; - def PPACKTB_DH : RVPPairBinaryPack_rr<0b010, 0b00, "ppacktb.dh">; - def PPACKTB_DW : RVPPairBinaryPack_rr<0b010, 0b01, "ppacktb.dw">; + def PPAIROE_DB : RVPPairBinaryPack_rr<0b010, 0b00, "ppairoe.db">; + def PPAIROE_DH : RVPPairBinaryPack_rr<0b010, 0b01, "ppairoe.dh">; - def PPACKT_DH : RVPPairBinaryPack_rr<0b011, 0b00, "ppackt.dh">; - def PPACKT_DW : RVPPairBinaryPack_rr<0b011, 0b01, "ppackt.dw">; + def PPAIRO_DB : RVPPairBinaryPack_rr<0b011, 0b00, "ppairo.db">; + def PPAIRO_DH : RVPPairBinaryPack_rr<0b011, 0b01, "ppairo.dh">; def PAS_DHX : RVPPairBinaryExchanged_rr<0b0000, 0b00, "pas.dhx">; def PSA_DHX : RVPPairBinaryExchanged_rr<0b0000, 0b10, "psa.dhx">; @@ -1511,15 +1504,15 @@ let Predicates = [HasStdExtP] in { def: Pat<(XLenVecI16VT (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_H GPR:$rs1, GPR:$rs2)>; def: Pat<(XLenVecI16VT (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_H GPR:$rs1, GPR:$rs2)>; def: Pat<(XLenVecI16VT (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_H GPR:$rs1, GPR:$rs2)>; - + // 8-bit absolute difference patterns - def: Pat<(XLenVecI8VT (abds GPR:$rs1, GPR:$rs2)), (PDIF_B GPR:$rs1, GPR:$rs2)>; - def: Pat<(XLenVecI8VT (abdu GPR:$rs1, GPR:$rs2)), (PDIFU_B GPR:$rs1, GPR:$rs2)>; - + def: Pat<(XLenVecI8VT (abds GPR:$rs1, GPR:$rs2)), (PABD_B GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI8VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_B GPR:$rs1, GPR:$rs2)>; + // 16-bit absolute difference patterns - def: Pat<(XLenVecI16VT (abds GPR:$rs1, GPR:$rs2)), (PDIF_H GPR:$rs1, GPR:$rs2)>; - def: Pat<(XLenVecI16VT (abdu GPR:$rs1, GPR:$rs2)), (PDIFU_H GPR:$rs1, GPR:$rs2)>; - + def: Pat<(XLenVecI16VT (abds GPR:$rs1, GPR:$rs2)), (PABD_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_H GPR:$rs1, GPR:$rs2)>; + // 8-bit logical shift left patterns def: Pat<(XLenVecI8VT (shl GPR:$rs1, (XLenVecI8VT (splat_vector uimm3:$shamt)))), (PSLLI_B GPR:$rs1, uimm3:$shamt)>; @@ -1602,22 +1595,22 @@ let Predicates = [HasStdExtP, IsRV64] in { (XLenVT GPR:$c), (XLenVT GPR:$d), (XLenVT undef), (XLenVT undef), (XLenVT undef), (XLenVT undef))), - (PPACK_W (PPACK_H GPR:$a, GPR:$b), (PPACK_H GPR:$c, GPR:$d))>; + (PPAIRE_H (PPAIRE_B GPR:$a, GPR:$b), (PPAIRE_B GPR:$c, GPR:$d))>; def : Pat<(v8i8 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b), (XLenVT GPR:$c), (XLenVT GPR:$d), (XLenVT GPR:$e), (XLenVT GPR:$f), (XLenVT GPR:$g), (XLenVT GPR:$h))), - (PACK(PPACK_W (PPACK_H GPR:$a, GPR:$b), (PPACK_H GPR:$c, GPR:$d)), - (PPACK_W (PPACK_H GPR:$e, GPR:$f), (PPACK_H GPR:$g, GPR:$h)))>; + (PACK (PPAIRE_H (PPAIRE_B GPR:$a, GPR:$b), (PPAIRE_B GPR:$c, GPR:$d)), + (PPAIRE_H (PPAIRE_B GPR:$e, GPR:$f), (PPAIRE_B GPR:$g, GPR:$h)))>; def : Pat<(v4i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b), (XLenVT undef), (XLenVT undef))), - (PPACK_W GPR:$a, GPR:$b)>; + (PPAIRE_H GPR:$a, GPR:$b)>; def : Pat<(v4i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b), (XLenVT GPR:$c), (XLenVT GPR:$d))), - (PACK (PPACK_W GPR:$a, GPR:$b), (PPACK_W GPR:$c, GPR:$d))>; + (PACK (PPAIRE_H GPR:$a, GPR:$b), (PPAIRE_H GPR:$c, GPR:$d))>; def : Pat<(v2i32 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b))), (PACK GPR:$a, GPR:$b)>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td index 5429c2a1a21b0..673894db56129 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -276,10 +276,9 @@ def XNOR : ALU_rr<0b0100000, 0b100, "xnor", Commutable=1>, Sched<[WriteIALU, ReadIALU, ReadIALU]>; } // Predicates = [HasStdExtZbbOrZbkb] -let Predicates = [HasStdExtZbaOrP] in +let Predicates = [HasStdExtZba] in { def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">, Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>; -let Predicates = [HasStdExtZba] in { def SH2ADD : ALU_rr<0b0010000, 0b100, "sh2add">, Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>; def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">, @@ -351,32 +350,30 @@ def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[WriteXPERM, ReadXPERM, ReadXPERM]>; } // Predicates = [HasStdExtZbkx] -let Predicates = [HasStdExtZbbOrP], IsSignExtendingOpW = 1 in +let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in { def CLZ : Unary_r<0b011000000000, 0b001, "clz">, Sched<[WriteCLZ, ReadCLZ]>; -let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in { def CTZ : Unary_r<0b011000000001, 0b001, "ctz">, Sched<[WriteCTZ, ReadCTZ]>; def CPOP : Unary_r<0b011000000010, 0b001, "cpop">, Sched<[WriteCPOP, ReadCPOP]>; } // Predicates = [HasStdExtZbb] -let Predicates = [HasStdExtZbbOrP, IsRV64], IsSignExtendingOpW = 1 in +let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in { def CLZW : UnaryW_r<0b011000000000, 0b001, "clzw">, Sched<[WriteCLZ32, ReadCLZ32]>; -let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in { def CTZW : UnaryW_r<0b011000000001, 0b001, "ctzw">, Sched<[WriteCTZ32, ReadCTZ32]>; def CPOPW : UnaryW_r<0b011000000010, 0b001, "cpopw">, Sched<[WriteCPOP32, ReadCPOP32]>; } // Predicates = [HasStdExtZbb, IsRV64] -let Predicates = [HasStdExtZbbOrP], IsSignExtendingOpW = 1 in { +let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in { def SEXT_B : Unary_r<0b011000000100, 0b001, "sext.b">, Sched<[WriteIALU, ReadIALU]>; def SEXT_H : Unary_r<0b011000000101, 0b001, "sext.h">, Sched<[WriteIALU, ReadIALU]>; -} // Predicates = [HasStdExtZbbOrP] +} // Predicates = [HasStdExtZbb] let Predicates = [HasStdExtZbc] in { def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr", Commutable=1>, @@ -390,7 +387,7 @@ def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh", Commutable=1>, Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>; } // Predicates = [HasStdExtZbcOrZbkc] -let Predicates = [HasStdExtZbbOrP] in { +let Predicates = [HasStdExtZbb] in { def MIN : ALU_rr<0b0000101, 0b100, "min", Commutable=1>, Sched<[WriteIMinMax, ReadIMinMax, ReadIMinMax]>; def MINU : ALU_rr<0b0000101, 0b101, "minu", Commutable=1>, @@ -399,7 +396,7 @@ def MAX : ALU_rr<0b0000101, 0b110, "max", Commutable=1>, Sched<[WriteIMinMax, ReadIMinMax, ReadIMinMax]>; def MAXU : ALU_rr<0b0000101, 0b111, "maxu", Commutable=1>, Sched<[WriteIMinMax, ReadIMinMax, ReadIMinMax]>; -} // Predicates = [HasStdExtZbbOrP] +} // Predicates = [HasStdExtZbb] let Predicates = [HasStdExtZbkbOrP] in def PACK : ALU_rr<0b0000100, 0b100, "pack">, @@ -424,15 +421,15 @@ def ZEXT_H_RV64 : RVBUnaryR<0b0000100, 0b100, OPC_OP_32, "zext.h">, Sched<[WriteIALU, ReadIALU]>; } // Predicates = [HasStdExtZbb, IsRV64] -let Predicates = [HasStdExtZbbOrZbkbOrP, IsRV32] in { +let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in { def REV8_RV32 : Unary_r<0b011010011000, 0b101, "rev8">, Sched<[WriteREV8, ReadREV8]>; -} // Predicates = [HasStdExtZbbOrZbkbOrP, IsRV32] +} // Predicates = [HasStdExtZbbOrZbkb, IsRV32] -let Predicates = [HasStdExtZbbOrZbkbOrP, IsRV64] in { +let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in { def REV8_RV64 : Unary_r<0b011010111000, 0b101, "rev8">, Sched<[WriteREV8, ReadREV8]>; -} // Predicates = [HasStdExtZbbOrZbkbOrP, IsRV64] +} // Predicates = [HasStdExtZbbOrZbkb, IsRV64] let Predicates = [HasStdExtZbb] in { def ORC_B : Unary_r<0b001010000111, 0b101, "orc.b">, @@ -599,20 +596,14 @@ def : PatGpr<riscv_zip, ZIP_RV32, i32>; def : PatGpr<riscv_unzip, UNZIP_RV32, i32>; } // Predicates = [HasStdExtZbkb, IsRV32] -let Predicates = [HasStdExtZbbOrP] in { -def : PatGpr<ctlz, CLZ>; -} - let Predicates = [HasStdExtZbb] in { +def : PatGpr<ctlz, CLZ>; def : PatGpr<cttz, CTZ>; def : PatGpr<ctpop, CPOP>; } // Predicates = [HasStdExtZbb] -let Predicates = [HasStdExtZbbOrP, IsRV64] in { -def : PatGpr<riscv_clzw, CLZW>; -} - let Predicates = [HasStdExtZbb, IsRV64] in { +def : PatGpr<riscv_clzw, CLZW>; def : PatGpr<riscv_ctzw, CTZW>; def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>; @@ -620,22 +611,22 @@ def : Pat<(i64 (riscv_negw_max GPR:$rs1)), (MAX GPR:$rs1, (XLenVT (SUBW (XLenVT X0), GPR:$rs1)))>; } // Predicates = [HasStdExtZbb, IsRV64] -let Predicates = [HasStdExtZbbOrP] in { +let Predicates = [HasStdExtZbb] in { def : Pat<(XLenVT (sext_inreg GPR:$rs1, i8)), (SEXT_B GPR:$rs1)>; def : Pat<(XLenVT (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>; } // Predicates = [HasStdExtZbb] -let Predicates = [HasStdExtZbbOrP] in { +let Predicates = [HasStdExtZbb] in { def : PatGprGpr<smin, MIN>; def : PatGprGpr<smax, MAX>; def : PatGprGpr<umin, MINU>; def : PatGprGpr<umax, MAXU>; } // Predicates = [HasStdExtZbb] -let Predicates = [HasStdExtZbbOrZbkbOrP, IsRV32] in +let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in def : PatGpr<bswap, REV8_RV32, i32>; -let Predicates = [HasStdExtZbbOrZbkbOrP, IsRV64] in +let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in def : PatGpr<bswap, REV8_RV64, i64>; let Predicates = [HasStdExtZbkb] in { diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index c16b23e290df1..ae6ca970c0c49 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -186,7 +186,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { } bool hasCLZLike() const { - return HasStdExtZbb || HasStdExtP || HasVendorXTHeadBb || + return HasStdExtZbb || HasVendorXTHeadBb || (HasVendorXCVbitmanip && !IsRV64); } bool hasCTZLike() const { @@ -196,7 +196,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { return HasStdExtZbb || (HasVendorXCVbitmanip && !IsRV64); } bool hasREV8Like() const { - return HasStdExtZbb || HasStdExtZbkb || HasStdExtP || HasVendorXTHeadBb; + return HasStdExtZbb || HasStdExtZbkb || HasVendorXTHeadBb; } bool hasBEXTILike() const { return HasStdExtZbs || HasVendorXTHeadBs; } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index f26d4f09c92fb..2fb063af8f8c8 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -462,7 +462,7 @@ ; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0" ; RV32SMCTR: .attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0" ; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0" -; RV32P: .attribute 5, "rv32i2p1_p0p15" +; RV32P: .attribute 5, "rv32i2p1_p0p18" ; RV32ZIBI: .attribute 5, "rv32i2p1_zibi0p1" ; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0" @@ -613,7 +613,7 @@ ; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0" ; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0" ; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0" -; RV64P: .attribute 5, "rv64i2p1_p0p15" +; RV64P: .attribute 5, "rv64i2p1_p0p18" ; RV64ZIBI: .attribute 5, "rv64i2p1_zibi0p1" ; RVI20U32: .attribute 5, "rv32i2p1" diff --git a/llvm/test/CodeGen/RISCV/rv32p.ll b/llvm/test/CodeGen/RISCV/rv32p.ll index 8a81846da9da2..a0ba9f1d91b9d 100644 --- a/llvm/test/CodeGen/RISCV/rv32p.ll +++ b/llvm/test/CodeGen/RISCV/rv32p.ll @@ -2,269 +2,6 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -define i32 @ctlz_i32(i32 %a) nounwind { -; CHECK-LABEL: ctlz_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: clz a0, a0 -; CHECK-NEXT: ret - %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false) - ret i32 %1 -} - -define i64 @ctlz_i64(i64 %a) nounwind { -; CHECK-LABEL: ctlz_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: bnez a1, .LBB1_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: clz a0, a0 -; CHECK-NEXT: addi a0, a0, 32 -; CHECK-NEXT: li a1, 0 -; CHECK-NEXT: ret -; CHECK-NEXT: .LBB1_2: -; CHECK-NEXT: clz a0, a1 -; CHECK-NEXT: li a1, 0 -; CHECK-NEXT: ret - %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false) - ret i64 %1 -} - -define i32 @cttz_i32(i32 %a) nounwind { -; CHECK-LABEL: cttz_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: beqz a0, .LBB2_2 -; CHECK-NEXT: # %bb.1: # %cond.false -; CHECK-NEXT: addi a1, a0, -1 -; CHECK-NEXT: not a0, a0 -; CHECK-NEXT: and a0, a0, a1 -; CHECK-NEXT: clz a0, a0 -; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: sub a0, a1, a0 -; CHECK-NEXT: ret -; CHECK-NEXT: .LBB2_2: -; CHECK-NEXT: li a0, 32 -; CHECK-NEXT: ret - %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false) - ret i32 %1 -} - -define i64 @cttz_i64(i64 %a) nounwind { -; CHECK-LABEL: cttz_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: or a2, a0, a1 -; CHECK-NEXT: beqz a2, .LBB3_3 -; CHECK-NEXT: # %bb.1: # %cond.false -; CHECK-NEXT: bnez a0, .LBB3_4 -; CHECK-NEXT: # %bb.2: # %cond.false -; CHECK-NEXT: addi a0, a1, -1 -; CHECK-NEXT: not a1, a1 -; CHECK-NEXT: and a0, a1, a0 -; CHECK-NEXT: clz a0, a0 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: j .LBB3_5 -; CHECK-NEXT: .LBB3_3: -; CHECK-NEXT: li a1, 0 -; CHECK-NEXT: li a0, 64 -; CHECK-NEXT: ret -; CHECK-NEXT: .LBB3_4: -; CHECK-NEXT: addi a1, a0, -1 -; CHECK-NEXT: not a0, a0 -; CHECK-NEXT: and a0, a0, a1 -; CHECK-NEXT: clz a0, a0 -; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: .LBB3_5: # %cond.false -; CHECK-NEXT: sub a0, a1, a0 -; CHECK-NEXT: li a1, 0 -; CHECK-NEXT: ret - %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false) - ret i64 %1 -} - -define i32 @sextb_i32(i32 %a) nounwind { -; CHECK-LABEL: sextb_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sext.b a0, a0 -; CHECK-NEXT: ret - %shl = shl i32 %a, 24 - %shr = ashr exact i32 %shl, 24 - ret i32 %shr -} - -define i64 @sextb_i64(i64 %a) nounwind { -; CHECK-LABEL: sextb_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: sext.b a0, a0 -; CHECK-NEXT: srai a1, a0, 31 -; CHECK-NEXT: ret - %shl = shl i64 %a, 56 - %shr = ashr exact i64 %shl, 56 - ret i64 %shr -} - -define i32 @sexth_i32(i32 %a) nounwind { -; CHECK-LABEL: sexth_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sext.h a0, a0 -; CHECK-NEXT: ret - %shl = shl i32 %a, 16 - %shr = ashr exact i32 %shl, 16 - ret i32 %shr -} - -define i64 @sexth_i64(i64 %a) nounwind { -; CHECK-LABEL: sexth_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: sext.h a0, a0 -; CHECK-NEXT: srai a1, a0, 31 -; CHECK-NEXT: ret - %shl = shl i64 %a, 48 - %shr = ashr exact i64 %shl, 48 - ret i64 %shr -} - -define i32 @min_i32(i32 %a, i32 %b) nounwind { -; CHECK-LABEL: min_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: min a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp slt i32 %a, %b - %cond = select i1 %cmp, i32 %a, i32 %b - ret i32 %cond -} - -; As we are not matching directly i64 code patterns on RV32 some i64 patterns -; don't have yet any matching bit manipulation instructions on RV32. -; This test is presented here in case future expansions of the Bitmanip -; extensions introduce instructions suitable for this pattern. - -define i64 @min_i64(i64 %a, i64 %b) nounwind { -; CHECK-LABEL: min_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: beq a1, a3, .LBB9_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: slt a4, a1, a3 -; CHECK-NEXT: beqz a4, .LBB9_3 -; CHECK-NEXT: j .LBB9_4 -; CHECK-NEXT: .LBB9_2: -; CHECK-NEXT: sltu a4, a0, a2 -; CHECK-NEXT: bnez a4, .LBB9_4 -; CHECK-NEXT: .LBB9_3: -; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: mv a1, a3 -; CHECK-NEXT: .LBB9_4: -; CHECK-NEXT: ret - %cmp = icmp slt i64 %a, %b - %cond = select i1 %cmp, i64 %a, i64 %b - ret i64 %cond -} - -define i32 @max_i32(i32 %a, i32 %b) nounwind { -; CHECK-LABEL: max_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: max a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp sgt i32 %a, %b - %cond = select i1 %cmp, i32 %a, i32 %b - ret i32 %cond -} - -; As we are not matching directly i64 code patterns on RV32 some i64 patterns -; don't have yet any matching bit manipulation instructions on RV32. -; This test is presented here in case future expansions of the Bitmanip -; extensions introduce instructions suitable for this pattern. - -define i64 @max_i64(i64 %a, i64 %b) nounwind { -; CHECK-LABEL: max_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: beq a1, a3, .LBB11_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: slt a4, a3, a1 -; CHECK-NEXT: beqz a4, .LBB11_3 -; CHECK-NEXT: j .LBB11_4 -; CHECK-NEXT: .LBB11_2: -; CHECK-NEXT: sltu a4, a2, a0 -; CHECK-NEXT: bnez a4, .LBB11_4 -; CHECK-NEXT: .LBB11_3: -; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: mv a1, a3 -; CHECK-NEXT: .LBB11_4: -; CHECK-NEXT: ret - %cmp = icmp sgt i64 %a, %b - %cond = select i1 %cmp, i64 %a, i64 %b - ret i64 %cond -} - -define i32 @minu_i32(i32 %a, i32 %b) nounwind { -; CHECK-LABEL: minu_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i32 %a, %b - %cond = select i1 %cmp, i32 %a, i32 %b - ret i32 %cond -} - -; As we are not matching directly i64 code patterns on RV32 some i64 patterns -; don't have yet any matching bit manipulation instructions on RV32. -; This test is presented here in case future expansions of the Bitmanip -; extensions introduce instructions suitable for this pattern. - -define i64 @minu_i64(i64 %a, i64 %b) nounwind { -; CHECK-LABEL: minu_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: beq a1, a3, .LBB13_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: sltu a4, a1, a3 -; CHECK-NEXT: beqz a4, .LBB13_3 -; CHECK-NEXT: j .LBB13_4 -; CHECK-NEXT: .LBB13_2: -; CHECK-NEXT: sltu a4, a0, a2 -; CHECK-NEXT: bnez a4, .LBB13_4 -; CHECK-NEXT: .LBB13_3: -; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: mv a1, a3 -; CHECK-NEXT: .LBB13_4: -; CHECK-NEXT: ret - %cmp = icmp ult i64 %a, %b - %cond = select i1 %cmp, i64 %a, i64 %b - ret i64 %cond -} - -define i32 @maxu_i32(i32 %a, i32 %b) nounwind { -; CHECK-LABEL: maxu_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: maxu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ugt i32 %a, %b - %cond = select i1 %cmp, i32 %a, i32 %b - ret i32 %cond -} - -; As we are not matching directly i64 code patterns on RV32 some i64 patterns -; don't have yet any matching bit manipulation instructions on RV32. -; This test is presented here in case future expansions of the Bitmanip -; extensions introduce instructions suitable for this pattern. - -define i64 @maxu_i64(i64 %a, i64 %b) nounwind { -; CHECK-LABEL: maxu_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: beq a1, a3, .LBB15_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: sltu a4, a3, a1 -; CHECK-NEXT: beqz a4, .LBB15_3 -; CHECK-NEXT: j .LBB15_4 -; CHECK-NEXT: .LBB15_2: -; CHECK-NEXT: sltu a4, a2, a0 -; CHECK-NEXT: bnez a4, .LBB15_4 -; CHECK-NEXT: .LBB15_3: -; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: mv a1, a3 -; CHECK-NEXT: .LBB15_4: -; CHECK-NEXT: ret - %cmp = icmp ugt i64 %a, %b - %cond = select i1 %cmp, i64 %a, i64 %b - ret i64 %cond -} - define i32 @abs_i32(i32 %x) { ; CHECK-LABEL: abs_i32: ; CHECK: # %bb.0: @@ -277,417 +14,14 @@ define i32 @abs_i32(i32 %x) { define i64 @abs_i64(i64 %x) { ; CHECK-LABEL: abs_i64: ; CHECK: # %bb.0: -; CHECK-NEXT: bgez a1, .LBB17_2 +; CHECK-NEXT: bgez a1, .LBB1_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: snez a2, a0 ; CHECK-NEXT: neg a0, a0 ; CHECK-NEXT: neg a1, a1 ; CHECK-NEXT: sub a1, a1, a2 -; CHECK-NEXT: .LBB17_2: +; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: ret %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) ret i64 %abs } - -define i32 @zexth_i32(i32 %a) nounwind { -; CHECK-LABEL: zexth_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: slli a0, a0, 16 -; CHECK-NEXT: srli a0, a0, 16 -; CHECK-NEXT: ret - %and = and i32 %a, 65535 - ret i32 %and -} - -define i64 @zexth_i64(i64 %a) nounwind { -; CHECK-LABEL: zexth_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: slli a0, a0, 16 -; CHECK-NEXT: srli a0, a0, 16 -; CHECK-NEXT: li a1, 0 -; CHECK-NEXT: ret - %and = and i64 %a, 65535 - ret i64 %and -} - -define i32 @bswap_i32(i32 %a) nounwind { -; CHECK-LABEL: bswap_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: rev8 a0, a0 -; CHECK-NEXT: ret - %1 = tail call i32 @llvm.bswap.i32(i32 %a) - ret i32 %1 -} - -define i64 @bswap_i64(i64 %a) { -; CHECK-LABEL: bswap_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: rev8 a2, a1 -; CHECK-NEXT: rev8 a1, a0 -; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: ret - %1 = call i64 @llvm.bswap.i64(i64 %a) - ret i64 %1 -} - -define i32 @srai_slli(i16 signext %0) { -; CHECK-LABEL: srai_slli: -; CHECK: # %bb.0: -; CHECK-NEXT: slli a0, a0, 25 -; CHECK-NEXT: srai a0, a0, 31 -; CHECK-NEXT: ret - %2 = shl i16 %0, 9 - %sext = ashr i16 %2, 15 - %3 = sext i16 %sext to i32 - ret i32 %3 -} - -define i32 @srai_slli2(i16 signext %0) { -; CHECK-LABEL: srai_slli2: -; CHECK: # %bb.0: -; CHECK-NEXT: slli a0, a0, 25 -; CHECK-NEXT: srai a0, a0, 30 -; CHECK-NEXT: ret - %2 = shl i16 %0, 9 - %sext = ashr i16 %2, 14 - %3 = sext i16 %sext to i32 - ret i32 %3 -} -define i8 @sub_if_uge_i8(i8 %x, i8 %y) { -; CHECK-LABEL: sub_if_uge_i8: -; CHECK: # %bb.0: -; CHECK-NEXT: zext.b a2, a0 -; CHECK-NEXT: sub a0, a0, a1 -; CHECK-NEXT: zext.b a0, a0 -; CHECK-NEXT: minu a0, a2, a0 -; CHECK-NEXT: ret - %cmp = icmp ult i8 %x, %y - %select = select i1 %cmp, i8 0, i8 %y - %sub = sub nuw i8 %x, %select - ret i8 %sub -} - -define i16 @sub_if_uge_i16(i16 %x, i16 %y) { -; CHECK-LABEL: sub_if_uge_i16: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a2, 16 -; CHECK-NEXT: sub a1, a0, a1 -; CHECK-NEXT: addi a2, a2, -1 -; CHECK-NEXT: and a0, a0, a2 -; CHECK-NEXT: and a1, a1, a2 -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i16 %x, %y - %select = select i1 %cmp, i16 0, i16 %y - %sub = sub nuw i16 %x, %select - ret i16 %sub -} - -define i32 @sub_if_uge_i32(i32 %x, i32 %y) { -; CHECK-LABEL: sub_if_uge_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sub a1, a0, a1 -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i32 %x, %y - %select = select i1 %cmp, i32 0, i32 %y - %sub = sub nuw i32 %x, %select - ret i32 %sub -} - -define i64 @sub_if_uge_i64(i64 %x, i64 %y) { -; CHECK-LABEL: sub_if_uge_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: beq a1, a3, .LBB27_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: sltu a4, a1, a3 -; CHECK-NEXT: j .LBB27_3 -; CHECK-NEXT: .LBB27_2: -; CHECK-NEXT: sltu a4, a0, a2 -; CHECK-NEXT: .LBB27_3: -; CHECK-NEXT: addi a4, a4, -1 -; CHECK-NEXT: and a3, a4, a3 -; CHECK-NEXT: and a2, a4, a2 -; CHECK-NEXT: sltu a4, a0, a2 -; CHECK-NEXT: sub a1, a1, a3 -; CHECK-NEXT: sub a1, a1, a4 -; CHECK-NEXT: sub a0, a0, a2 -; CHECK-NEXT: ret - %cmp = icmp ult i64 %x, %y - %select = select i1 %cmp, i64 0, i64 %y - %sub = sub nuw i64 %x, %select - ret i64 %sub -} - -define i128 @sub_if_uge_i128(i128 %x, i128 %y) { -; CHECK-LABEL: sub_if_uge_i128: -; CHECK: # %bb.0: -; CHECK-NEXT: lw a3, 4(a1) -; CHECK-NEXT: lw a4, 8(a1) -; CHECK-NEXT: lw a5, 12(a1) -; CHECK-NEXT: lw a6, 4(a2) -; CHECK-NEXT: lw t0, 12(a2) -; CHECK-NEXT: lw a7, 8(a2) -; CHECK-NEXT: beq a5, t0, .LBB28_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: sltu t1, a5, t0 -; CHECK-NEXT: j .LBB28_3 -; CHECK-NEXT: .LBB28_2: -; CHECK-NEXT: sltu t1, a4, a7 -; CHECK-NEXT: .LBB28_3: -; CHECK-NEXT: lw a1, 0(a1) -; CHECK-NEXT: lw a2, 0(a2) -; CHECK-NEXT: beq a3, a6, .LBB28_5 -; CHECK-NEXT: # %bb.4: -; CHECK-NEXT: sltu t2, a3, a6 -; CHECK-NEXT: j .LBB28_6 -; CHECK-NEXT: .LBB28_5: -; CHECK-NEXT: sltu t2, a1, a2 -; CHECK-NEXT: .LBB28_6: -; CHECK-NEXT: xor t3, a5, t0 -; CHECK-NEXT: xor t4, a4, a7 -; CHECK-NEXT: or t3, t4, t3 -; CHECK-NEXT: beqz t3, .LBB28_8 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mv t2, t1 -; CHECK-NEXT: .LBB28_8: -; CHECK-NEXT: addi t3, t2, -1 -; CHECK-NEXT: and t2, t3, t0 -; CHECK-NEXT: and t0, t3, a2 -; CHECK-NEXT: and t1, t3, a6 -; CHECK-NEXT: sltu a2, a1, t0 -; CHECK-NEXT: and a7, t3, a7 -; CHECK-NEXT: mv a6, a2 -; CHECK-NEXT: beq a3, t1, .LBB28_10 -; CHECK-NEXT: # %bb.9: -; CHECK-NEXT: sltu a6, a3, t1 -; CHECK-NEXT: .LBB28_10: -; CHECK-NEXT: sub t3, a4, a7 -; CHECK-NEXT: sltu a4, a4, a7 -; CHECK-NEXT: sub a5, a5, t2 -; CHECK-NEXT: sub a3, a3, t1 -; CHECK-NEXT: sub a1, a1, t0 -; CHECK-NEXT: sltu a7, t3, a6 -; CHECK-NEXT: sub a5, a5, a4 -; CHECK-NEXT: sub a4, t3, a6 -; CHECK-NEXT: sub a3, a3, a2 -; CHECK-NEXT: sub a2, a5, a7 -; CHECK-NEXT: sw a1, 0(a0) -; CHECK-NEXT: sw a3, 4(a0) -; CHECK-NEXT: sw a4, 8(a0) -; CHECK-NEXT: sw a2, 12(a0) -; CHECK-NEXT: ret - %cmp = icmp ult i128 %x, %y - %select = select i1 %cmp, i128 0, i128 %y - %sub = sub nuw i128 %x, %select - ret i128 %sub -} - -define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) { -; CHECK-LABEL: sub_if_uge_multiuse_select_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sltu a2, a0, a1 -; CHECK-NEXT: addi a2, a2, -1 -; CHECK-NEXT: and a1, a2, a1 -; CHECK-NEXT: sub a0, a0, a1 -; CHECK-NEXT: sll a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i32 %x, %y - %select = select i1 %cmp, i32 0, i32 %y - %sub = sub nuw i32 %x, %select - %shl = shl i32 %sub, %select - ret i32 %shl -} - -define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) { -; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sub a2, a0, a1 -; CHECK-NEXT: minu a2, a0, a2 -; CHECK-NEXT: bltu a0, a1, .LBB30_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: li a0, 4 -; CHECK-NEXT: sll a0, a2, a0 -; CHECK-NEXT: ret -; CHECK-NEXT: .LBB30_2: -; CHECK-NEXT: li a0, 2 -; CHECK-NEXT: sll a0, a2, a0 -; CHECK-NEXT: ret - %cmp = icmp ult i32 %x, %y - %select = select i1 %cmp, i32 0, i32 %y - %sub = sub nuw i32 %x, %select - %select2 = select i1 %cmp, i32 2, i32 4 - %shl = shl i32 %sub, %select2 - ret i32 %shl -} - -define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 %x, i32 %y, ptr %z) { -; CHECK-LABEL: sub_if_uge_multiuse_cmp_store_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sltu a3, a0, a1 -; CHECK-NEXT: sub a1, a0, a1 -; CHECK-NEXT: xori a3, a3, 1 -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: sw a3, 0(a2) -; CHECK-NEXT: ret - %cmp = icmp uge i32 %x, %y - %conv = zext i1 %cmp to i32 - store i32 %conv, ptr %z, align 4 - %select = select i1 %cmp, i32 %y, i32 0 - %sub = sub nuw i32 %x, %select - ret i32 %sub -} - -define i8 @sub_if_uge_C_i8(i8 zeroext %x) { -; CHECK-LABEL: sub_if_uge_C_i8: -; CHECK: # %bb.0: -; CHECK-NEXT: addi a1, a0, -13 -; CHECK-NEXT: zext.b a1, a1 -; CHECK-NEXT: minu a0, a1, a0 -; CHECK-NEXT: ret - %cmp = icmp ugt i8 %x, 12 - %sub = add i8 %x, -13 - %conv4 = select i1 %cmp, i8 %sub, i8 %x - ret i8 %conv4 -} - -define i16 @sub_if_uge_C_i16(i16 zeroext %x) { -; CHECK-LABEL: sub_if_uge_C_i16: -; CHECK: # %bb.0: -; CHECK-NEXT: addi a1, a0, -251 -; CHECK-NEXT: slli a1, a1, 16 -; CHECK-NEXT: srli a1, a1, 16 -; CHECK-NEXT: minu a0, a1, a0 -; CHECK-NEXT: ret - %cmp = icmp ugt i16 %x, 250 - %sub = add i16 %x, -251 - %conv4 = select i1 %cmp, i16 %sub, i16 %x - ret i16 %conv4 -} - -define i32 @sub_if_uge_C_i32(i32 signext %x) { -; CHECK-LABEL: sub_if_uge_C_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a1, 1048560 -; CHECK-NEXT: addi a1, a1, 15 -; CHECK-NEXT: add a1, a0, a1 -; CHECK-NEXT: minu a0, a1, a0 -; CHECK-NEXT: ret - %cmp = icmp ugt i32 %x, 65520 - %sub = add i32 %x, -65521 - %cond = select i1 %cmp, i32 %sub, i32 %x - ret i32 %cond -} - -define i64 @sub_if_uge_C_i64(i64 %x) { -; CHECK-LABEL: sub_if_uge_C_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: li a2, 1 -; CHECK-NEXT: beq a1, a2, .LBB35_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: sltiu a2, a1, 2 -; CHECK-NEXT: xori a2, a2, 1 -; CHECK-NEXT: j .LBB35_3 -; CHECK-NEXT: .LBB35_2: -; CHECK-NEXT: lui a2, 172127 -; CHECK-NEXT: addi a2, a2, 511 -; CHECK-NEXT: sltu a2, a2, a0 -; CHECK-NEXT: .LBB35_3: -; CHECK-NEXT: neg a2, a2 -; CHECK-NEXT: andi a3, a2, -2 -; CHECK-NEXT: add a1, a1, a3 -; CHECK-NEXT: lui a3, 876449 -; CHECK-NEXT: addi a3, a3, -512 -; CHECK-NEXT: and a2, a2, a3 -; CHECK-NEXT: add a2, a0, a2 -; CHECK-NEXT: sltu a0, a2, a0 -; CHECK-NEXT: add a1, a1, a0 -; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: ret - %cmp = icmp ugt i64 %x, 4999999999 - %sub = add i64 %x, -5000000000 - %cond = select i1 %cmp, i64 %sub, i64 %x - ret i64 %cond -} - -define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) { -; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a2, 16 -; CHECK-NEXT: lui a3, 1048560 -; CHECK-NEXT: addi a2, a2, -16 -; CHECK-NEXT: addi a3, a3, 15 -; CHECK-NEXT: sltu a2, a2, a0 -; CHECK-NEXT: add a3, a0, a3 -; CHECK-NEXT: minu a0, a3, a0 -; CHECK-NEXT: sw a2, 0(a1) -; CHECK-NEXT: ret - %cmp = icmp ugt i32 %x, 65520 - %conv = zext i1 %cmp to i32 - store i32 %conv, ptr %z, align 4 - %sub = add i32 %x, -65521 - %cond = select i1 %cmp, i32 %sub, i32 %x - ret i32 %cond -} - -define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) { -; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a2, 1048560 -; CHECK-NEXT: addi a2, a2, 15 -; CHECK-NEXT: add a2, a0, a2 -; CHECK-NEXT: minu a0, a2, a0 -; CHECK-NEXT: sw a2, 0(a1) -; CHECK-NEXT: ret - %sub = add i32 %x, -65521 - store i32 %sub, ptr %z, align 4 - %cmp = icmp ugt i32 %x, 65520 - %cond = select i1 %cmp, i32 %sub, i32 %x - ret i32 %cond -} - -define i32 @sub_if_uge_C_swapped_i32(i32 %x) { -; CHECK-LABEL: sub_if_uge_C_swapped_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a1, 1048560 -; CHECK-NEXT: addi a1, a1, 15 -; CHECK-NEXT: add a1, a0, a1 -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i32 %x, 65521 - %sub = add i32 %x, -65521 - %cond = select i1 %cmp, i32 %x, i32 %sub - ret i32 %cond -} - -define i7 @sub_if_uge_C_nsw_i7(i7 %a) { -; CHECK-LABEL: sub_if_uge_C_nsw_i7: -; CHECK: # %bb.0: -; CHECK-NEXT: ori a0, a0, 51 -; CHECK-NEXT: andi a1, a0, 127 -; CHECK-NEXT: addi a0, a0, 17 -; CHECK-NEXT: andi a0, a0, 92 -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: ret - %x = or i7 %a, 51 - %c = icmp ugt i7 %x, -18 - %add = add nsw i7 %x, 17 - %s = select i1 %c, i7 %add, i7 %x - ret i7 %s -} - -define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) { -; CHECK-LABEL: sub_if_uge_C_swapped_nsw_i7: -; CHECK: # %bb.0: -; CHECK-NEXT: ori a0, a0, 51 -; CHECK-NEXT: andi a1, a0, 127 -; CHECK-NEXT: addi a0, a0, 17 -; CHECK-NEXT: andi a0, a0, 92 -; CHECK-NEXT: minu a0, a1, a0 -; CHECK-NEXT: ret - %x = or i7 %a, 51 - %c = icmp ult i7 %x, -17 - %add = add nsw i7 %x, 17 - %s = select i1 %c, i7 %x, i7 %add - ret i7 %s -} diff --git a/llvm/test/CodeGen/RISCV/rv64p.ll b/llvm/test/CodeGen/RISCV/rv64p.ll index ec242294c3036..cc75aae35c96f 100644 --- a/llvm/test/CodeGen/RISCV/rv64p.ll +++ b/llvm/test/CodeGen/RISCV/rv64p.ll @@ -2,288 +2,6 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -define signext i32 @ctlz_i32(i32 signext %a) nounwind { -; CHECK-LABEL: ctlz_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: clzw a0, a0 -; CHECK-NEXT: ret - %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false) - ret i32 %1 -} - -define signext i32 @log2_i32(i32 signext %a) nounwind { -; CHECK-LABEL: log2_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: clzw a0, a0 -; CHECK-NEXT: li a1, 31 -; CHECK-NEXT: sub a0, a1, a0 -; CHECK-NEXT: ret - %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false) - %2 = sub i32 31, %1 - ret i32 %2 -} - -define signext i32 @log2_ceil_i32(i32 signext %a) nounwind { -; CHECK-LABEL: log2_ceil_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: clzw a0, a0 -; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: sub a0, a1, a0 -; CHECK-NEXT: ret - %1 = sub i32 %a, 1 - %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) - %3 = sub i32 32, %2 - ret i32 %3 -} - -define signext i32 @findLastSet_i32(i32 signext %a) nounwind { -; CHECK-LABEL: findLastSet_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: clzw a1, a0 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: xori a1, a1, 31 -; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: or a0, a0, a1 -; CHECK-NEXT: ret - %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true) - %2 = xor i32 31, %1 - %3 = icmp eq i32 %a, 0 - %4 = select i1 %3, i32 -1, i32 %2 - ret i32 %4 -} - -define i32 @ctlz_lshr_i32(i32 signext %a) { -; CHECK-LABEL: ctlz_lshr_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: srliw a0, a0, 1 -; CHECK-NEXT: clzw a0, a0 -; CHECK-NEXT: ret - %1 = lshr i32 %a, 1 - %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) - ret i32 %2 -} - -define i64 @ctlz_i64(i64 %a) nounwind { -; CHECK-LABEL: ctlz_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: clz a0, a0 -; CHECK-NEXT: ret - %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false) - ret i64 %1 -} - -define signext i32 @cttz_i32(i32 signext %a) nounwind { -; CHECK-LABEL: cttz_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: beqz a0, .LBB6_2 -; CHECK-NEXT: # %bb.1: # %cond.false -; CHECK-NEXT: addi a1, a0, -1 -; CHECK-NEXT: not a0, a0 -; CHECK-NEXT: and a0, a0, a1 -; CHECK-NEXT: clzw a0, a0 -; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: sub a0, a1, a0 -; CHECK-NEXT: ret -; CHECK-NEXT: .LBB6_2: -; CHECK-NEXT: li a0, 32 -; CHECK-NEXT: ret - %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false) - ret i32 %1 -} - -define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind { -; CHECK-LABEL: cttz_zero_undef_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: addi a1, a0, -1 -; CHECK-NEXT: not a0, a0 -; CHECK-NEXT: and a0, a0, a1 -; CHECK-NEXT: clzw a0, a0 -; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: sub a0, a1, a0 -; CHECK-NEXT: ret - %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true) - ret i32 %1 -} - -define signext i32 @findFirstSet_i32(i32 signext %a) nounwind { -; CHECK-LABEL: findFirstSet_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: addi a1, a0, -1 -; CHECK-NEXT: not a2, a0 -; CHECK-NEXT: and a1, a2, a1 -; CHECK-NEXT: li a2, 32 -; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: clzw a1, a1 -; CHECK-NEXT: sub a2, a2, a1 -; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: or a0, a0, a2 -; CHECK-NEXT: ret - %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true) - %2 = icmp eq i32 %a, 0 - %3 = select i1 %2, i32 -1, i32 %1 - ret i32 %3 -} - -define signext i32 @ffs_i32(i32 signext %a) nounwind { -; CHECK-LABEL: ffs_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: addi a1, a0, -1 -; CHECK-NEXT: not a2, a0 -; CHECK-NEXT: and a1, a2, a1 -; CHECK-NEXT: li a2, 33 -; CHECK-NEXT: seqz a0, a0 -; CHECK-NEXT: clzw a1, a1 -; CHECK-NEXT: sub a2, a2, a1 -; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: and a0, a0, a2 -; CHECK-NEXT: ret - %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true) - %2 = add i32 %1, 1 - %3 = icmp eq i32 %a, 0 - %4 = select i1 %3, i32 0, i32 %2 - ret i32 %4 -} - -define i64 @cttz_i64(i64 %a) nounwind { -; CHECK-LABEL: cttz_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: beqz a0, .LBB10_2 -; CHECK-NEXT: # %bb.1: # %cond.false -; CHECK-NEXT: addi a1, a0, -1 -; CHECK-NEXT: not a0, a0 -; CHECK-NEXT: and a0, a0, a1 -; CHECK-NEXT: clz a0, a0 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: sub a0, a1, a0 -; CHECK-NEXT: ret -; CHECK-NEXT: .LBB10_2: -; CHECK-NEXT: li a0, 64 -; CHECK-NEXT: ret - %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false) - ret i64 %1 -} - -define signext i32 @sextb_i32(i32 signext %a) nounwind { -; CHECK-LABEL: sextb_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sext.b a0, a0 -; CHECK-NEXT: ret - %shl = shl i32 %a, 24 - %shr = ashr exact i32 %shl, 24 - ret i32 %shr -} - -define i64 @sextb_i64(i64 %a) nounwind { -; CHECK-LABEL: sextb_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: sext.b a0, a0 -; CHECK-NEXT: ret - %shl = shl i64 %a, 56 - %shr = ashr exact i64 %shl, 56 - ret i64 %shr -} - -define signext i32 @sexth_i32(i32 signext %a) nounwind { -; CHECK-LABEL: sexth_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sext.h a0, a0 -; CHECK-NEXT: ret - %shl = shl i32 %a, 16 - %shr = ashr exact i32 %shl, 16 - ret i32 %shr -} - -define i64 @sexth_i64(i64 %a) nounwind { -; CHECK-LABEL: sexth_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: sext.h a0, a0 -; CHECK-NEXT: ret - %shl = shl i64 %a, 48 - %shr = ashr exact i64 %shl, 48 - ret i64 %shr -} - -define signext i32 @min_i32(i32 signext %a, i32 signext %b) nounwind { -; CHECK-LABEL: min_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: min a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp slt i32 %a, %b - %cond = select i1 %cmp, i32 %a, i32 %b - ret i32 %cond -} - -define i64 @min_i64(i64 %a, i64 %b) nounwind { -; CHECK-LABEL: min_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: min a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp slt i64 %a, %b - %cond = select i1 %cmp, i64 %a, i64 %b - ret i64 %cond -} - -define signext i32 @max_i32(i32 signext %a, i32 signext %b) nounwind { -; CHECK-LABEL: max_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: max a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp sgt i32 %a, %b - %cond = select i1 %cmp, i32 %a, i32 %b - ret i32 %cond -} - -define i64 @max_i64(i64 %a, i64 %b) nounwind { -; CHECK-LABEL: max_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: max a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp sgt i64 %a, %b - %cond = select i1 %cmp, i64 %a, i64 %b - ret i64 %cond -} - -define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind { -; CHECK-LABEL: minu_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i32 %a, %b - %cond = select i1 %cmp, i32 %a, i32 %b - ret i32 %cond -} - -define i64 @minu_i64(i64 %a, i64 %b) nounwind { -; CHECK-LABEL: minu_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i64 %a, %b - %cond = select i1 %cmp, i64 %a, i64 %b - ret i64 %cond -} - -define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind { -; CHECK-LABEL: maxu_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: maxu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ugt i32 %a, %b - %cond = select i1 %cmp, i32 %a, i32 %b - ret i32 %cond -} - -define i64 @maxu_i64(i64 %a, i64 %b) nounwind { -; CHECK-LABEL: maxu_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: maxu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ugt i64 %a, %b - %cond = select i1 %cmp, i64 %a, i64 %b - ret i64 %cond -} - define i32 @abs_i32(i32 %x) { ; CHECK-LABEL: abs_i32: ; CHECK: # %bb.0: @@ -310,350 +28,3 @@ define i64 @abs_i64(i64 %x) { %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) ret i64 %abs } - -define signext i32 @bswap_i32(i32 signext %a) nounwind { -; CHECK-LABEL: bswap_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: rev8 a0, a0 -; CHECK-NEXT: srai a0, a0, 32 -; CHECK-NEXT: ret - %1 = tail call i32 @llvm.bswap.i32(i32 %a) - ret i32 %1 -} - -; Similar to bswap_i32 but the result is not sign extended. -define void @bswap_i32_nosext(i32 signext %a, ptr %x) nounwind { -; CHECK-LABEL: bswap_i32_nosext: -; CHECK: # %bb.0: -; CHECK-NEXT: rev8 a0, a0 -; CHECK-NEXT: srli a0, a0, 32 -; CHECK-NEXT: sw a0, 0(a1) -; CHECK-NEXT: ret - %1 = tail call i32 @llvm.bswap.i32(i32 %a) - store i32 %1, ptr %x - ret void -} - -define i64 @bswap_i64(i64 %a) { -; CHECK-LABEL: bswap_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: rev8 a0, a0 -; CHECK-NEXT: ret - %1 = call i64 @llvm.bswap.i64(i64 %a) - ret i64 %1 -} - -define i64 @srai_slli(i16 signext %0) { -; CHECK-LABEL: srai_slli: -; CHECK: # %bb.0: -; CHECK-NEXT: slli a0, a0, 57 -; CHECK-NEXT: srai a0, a0, 63 -; CHECK-NEXT: ret - %2 = shl i16 %0, 9 - %sext = ashr i16 %2, 15 - %3 = sext i16 %sext to i64 - ret i64 %3 -} - -define i64 @srai_slli2(i16 signext %0) { -; CHECK-LABEL: srai_slli2: -; CHECK: # %bb.0: -; CHECK-NEXT: slli a0, a0, 57 -; CHECK-NEXT: srai a0, a0, 62 -; CHECK-NEXT: ret - %2 = shl i16 %0, 9 - %sext = ashr i16 %2, 14 - %3 = sext i16 %sext to i64 - ret i64 %3 -} - -define signext i32 @func0000000000000001(i32 signext %0, i8 signext %1) #0 { -; CHECK-LABEL: func0000000000000001: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: slli a1, a1, 59 -; CHECK-NEXT: srai a1, a1, 63 -; CHECK-NEXT: addw a0, a1, a0 -; CHECK-NEXT: ret -entry: - %2 = shl i8 %1, 3 - %3 = ashr i8 %2, 7 - %4 = sext i8 %3 to i32 - %5 = add nsw i32 %4, %0 - ret i32 %5 -} - -define i8 @sub_if_uge_i8(i8 %x, i8 %y) { -; CHECK-LABEL: sub_if_uge_i8: -; CHECK: # %bb.0: -; CHECK-NEXT: zext.b a2, a0 -; CHECK-NEXT: sub a0, a0, a1 -; CHECK-NEXT: zext.b a0, a0 -; CHECK-NEXT: minu a0, a2, a0 -; CHECK-NEXT: ret - %cmp = icmp ult i8 %x, %y - %select = select i1 %cmp, i8 0, i8 %y - %sub = sub nuw i8 %x, %select - ret i8 %sub -} - -define i16 @sub_if_uge_i16(i16 %x, i16 %y) { -; CHECK-LABEL: sub_if_uge_i16: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a2, 16 -; CHECK-NEXT: sub a1, a0, a1 -; CHECK-NEXT: addi a2, a2, -1 -; CHECK-NEXT: and a0, a0, a2 -; CHECK-NEXT: and a1, a1, a2 -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i16 %x, %y - %select = select i1 %cmp, i16 0, i16 %y - %sub = sub nuw i16 %x, %select - ret i16 %sub -} - -define i32 @sub_if_uge_i32(i32 %x, i32 %y) { -; CHECK-LABEL: sub_if_uge_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sext.w a2, a0 -; CHECK-NEXT: subw a0, a0, a1 -; CHECK-NEXT: minu a0, a2, a0 -; CHECK-NEXT: ret - %cmp = icmp ult i32 %x, %y - %select = select i1 %cmp, i32 0, i32 %y - %sub = sub nuw i32 %x, %select - ret i32 %sub -} - -define i64 @sub_if_uge_i64(i64 %x, i64 %y) { -; CHECK-LABEL: sub_if_uge_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: sub a1, a0, a1 -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i64 %x, %y - %select = select i1 %cmp, i64 0, i64 %y - %sub = sub nuw i64 %x, %select - ret i64 %sub -} - -define i128 @sub_if_uge_i128(i128 %x, i128 %y) { -; CHECK-LABEL: sub_if_uge_i128: -; CHECK: # %bb.0: -; CHECK-NEXT: beq a1, a3, .LBB36_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: sltu a4, a1, a3 -; CHECK-NEXT: j .LBB36_3 -; CHECK-NEXT: .LBB36_2: -; CHECK-NEXT: sltu a4, a0, a2 -; CHECK-NEXT: .LBB36_3: -; CHECK-NEXT: addi a4, a4, -1 -; CHECK-NEXT: and a3, a4, a3 -; CHECK-NEXT: and a2, a4, a2 -; CHECK-NEXT: sltu a4, a0, a2 -; CHECK-NEXT: sub a1, a1, a3 -; CHECK-NEXT: sub a1, a1, a4 -; CHECK-NEXT: sub a0, a0, a2 -; CHECK-NEXT: ret - %cmp = icmp ult i128 %x, %y - %select = select i1 %cmp, i128 0, i128 %y - %sub = sub nuw i128 %x, %select - ret i128 %sub -} - -define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) { -; CHECK-LABEL: sub_if_uge_multiuse_select_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sext.w a2, a1 -; CHECK-NEXT: sext.w a3, a0 -; CHECK-NEXT: sltu a2, a3, a2 -; CHECK-NEXT: addi a2, a2, -1 -; CHECK-NEXT: and a1, a2, a1 -; CHECK-NEXT: sub a0, a0, a1 -; CHECK-NEXT: sllw a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i32 %x, %y - %select = select i1 %cmp, i32 0, i32 %y - %sub = sub nuw i32 %x, %select - %shl = shl i32 %sub, %select - ret i32 %shl -} - -define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) { -; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sext.w a2, a1 -; CHECK-NEXT: sext.w a3, a0 -; CHECK-NEXT: subw a0, a0, a1 -; CHECK-NEXT: minu a0, a3, a0 -; CHECK-NEXT: bltu a3, a2, .LBB38_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: li a1, 4 -; CHECK-NEXT: sllw a0, a0, a1 -; CHECK-NEXT: ret -; CHECK-NEXT: .LBB38_2: -; CHECK-NEXT: li a1, 2 -; CHECK-NEXT: sllw a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i32 %x, %y - %select = select i1 %cmp, i32 0, i32 %y - %sub = sub nuw i32 %x, %select - %select2 = select i1 %cmp, i32 2, i32 4 - %shl = shl i32 %sub, %select2 - ret i32 %shl -} - -define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 signext %x, i32 signext %y, ptr %z) { -; CHECK-LABEL: sub_if_uge_multiuse_cmp_store_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: sltu a3, a0, a1 -; CHECK-NEXT: subw a1, a0, a1 -; CHECK-NEXT: xori a3, a3, 1 -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: sw a3, 0(a2) -; CHECK-NEXT: ret - %cmp = icmp uge i32 %x, %y - %conv = zext i1 %cmp to i32 - store i32 %conv, ptr %z, align 4 - %select = select i1 %cmp, i32 %y, i32 0 - %sub = sub nuw i32 %x, %select - ret i32 %sub -} - -define i8 @sub_if_uge_C_i8(i8 zeroext %x) { -; CHECK-LABEL: sub_if_uge_C_i8: -; CHECK: # %bb.0: -; CHECK-NEXT: addi a1, a0, -13 -; CHECK-NEXT: zext.b a1, a1 -; CHECK-NEXT: minu a0, a1, a0 -; CHECK-NEXT: ret - %cmp = icmp ugt i8 %x, 12 - %sub = add i8 %x, -13 - %conv4 = select i1 %cmp, i8 %sub, i8 %x - ret i8 %conv4 -} - -define i16 @sub_if_uge_C_i16(i16 zeroext %x) { -; CHECK-LABEL: sub_if_uge_C_i16: -; CHECK: # %bb.0: -; CHECK-NEXT: addi a1, a0, -251 -; CHECK-NEXT: slli a1, a1, 48 -; CHECK-NEXT: srli a1, a1, 48 -; CHECK-NEXT: minu a0, a1, a0 -; CHECK-NEXT: ret - %cmp = icmp ugt i16 %x, 250 - %sub = add i16 %x, -251 - %conv4 = select i1 %cmp, i16 %sub, i16 %x - ret i16 %conv4 -} - -define i32 @sub_if_uge_C_i32(i32 signext %x) { -; CHECK-LABEL: sub_if_uge_C_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a1, 1048560 -; CHECK-NEXT: addi a1, a1, 15 -; CHECK-NEXT: addw a1, a0, a1 -; CHECK-NEXT: minu a0, a1, a0 -; CHECK-NEXT: ret - %cmp = icmp ugt i32 %x, 65520 - %sub = add i32 %x, -65521 - %cond = select i1 %cmp, i32 %sub, i32 %x - ret i32 %cond -} - -define i64 @sub_if_uge_C_i64(i64 %x) { -; CHECK-LABEL: sub_if_uge_C_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a1, 1046192 -; CHECK-NEXT: addi a1, a1, -761 -; CHECK-NEXT: slli a1, a1, 9 -; CHECK-NEXT: add a1, a0, a1 -; CHECK-NEXT: minu a0, a1, a0 -; CHECK-NEXT: ret - %cmp = icmp ugt i64 %x, 4999999999 - %sub = add i64 %x, -5000000000 - %cond = select i1 %cmp, i64 %sub, i64 %x - ret i64 %cond -} - -define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) { -; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a2, 16 -; CHECK-NEXT: lui a3, 1048560 -; CHECK-NEXT: addi a2, a2, -16 -; CHECK-NEXT: addi a3, a3, 15 -; CHECK-NEXT: sltu a2, a2, a0 -; CHECK-NEXT: addw a3, a0, a3 -; CHECK-NEXT: minu a0, a3, a0 -; CHECK-NEXT: sw a2, 0(a1) -; CHECK-NEXT: ret - %cmp = icmp ugt i32 %x, 65520 - %conv = zext i1 %cmp to i32 - store i32 %conv, ptr %z, align 4 - %sub = add i32 %x, -65521 - %cond = select i1 %cmp, i32 %sub, i32 %x - ret i32 %cond -} - -define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) { -; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a2, 1048560 -; CHECK-NEXT: addi a2, a2, 15 -; CHECK-NEXT: addw a2, a0, a2 -; CHECK-NEXT: minu a0, a2, a0 -; CHECK-NEXT: sw a2, 0(a1) -; CHECK-NEXT: ret - %sub = add i32 %x, -65521 - store i32 %sub, ptr %z, align 4 - %cmp = icmp ugt i32 %x, 65520 - %cond = select i1 %cmp, i32 %sub, i32 %x - ret i32 %cond -} - -define i32 @sub_if_uge_C_swapped_i32(i32 signext %x) { -; CHECK-LABEL: sub_if_uge_C_swapped_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a1, 1048560 -; CHECK-NEXT: addi a1, a1, 15 -; CHECK-NEXT: addw a1, a0, a1 -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: ret - %cmp = icmp ult i32 %x, 65521 - %sub = add i32 %x, -65521 - %cond = select i1 %cmp, i32 %x, i32 %sub - ret i32 %cond -} - -define i7 @sub_if_uge_C_nsw_i7(i7 %a) { -; CHECK-LABEL: sub_if_uge_C_nsw_i7: -; CHECK: # %bb.0: -; CHECK-NEXT: ori a0, a0, 51 -; CHECK-NEXT: andi a1, a0, 127 -; CHECK-NEXT: addi a0, a0, 17 -; CHECK-NEXT: andi a0, a0, 92 -; CHECK-NEXT: minu a0, a0, a1 -; CHECK-NEXT: ret - %x = or i7 %a, 51 - %c = icmp ugt i7 %x, -18 - %add = add nsw i7 %x, 17 - %s = select i1 %c, i7 %add, i7 %x - ret i7 %s -} - -define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) { -; CHECK-LABEL: sub_if_uge_C_swapped_nsw_i7: -; CHECK: # %bb.0: -; CHECK-NEXT: ori a0, a0, 51 -; CHECK-NEXT: andi a1, a0, 127 -; CHECK-NEXT: addi a0, a0, 17 -; CHECK-NEXT: andi a0, a0, 92 -; CHECK-NEXT: minu a0, a1, a0 -; CHECK-NEXT: ret - %x = or i7 %a, 51 - %c = icmp ult i7 %x, -17 - %add = add nsw i7 %x, 17 - %s = select i1 %c, i7 %x, i7 %add - ret i7 %s -} diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll index f803f6aa09652..58fa978addb4f 100644 --- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll @@ -272,7 +272,7 @@ define void @test_pdif_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) { ; CHECK: # %bb.0: ; CHECK-NEXT: lw a1, 0(a1) ; CHECK-NEXT: lw a2, 0(a2) -; CHECK-NEXT: pdif.h a1, a1, a2 +; CHECK-NEXT: pabd.h a1, a1, a2 ; CHECK-NEXT: sw a1, 0(a0) ; CHECK-NEXT: ret %a = load <2 x i16>, ptr %a_ptr @@ -290,7 +290,7 @@ define void @test_pdifu_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) { ; CHECK: # %bb.0: ; CHECK-NEXT: lw a1, 0(a1) ; CHECK-NEXT: lw a2, 0(a2) -; CHECK-NEXT: pdifu.h a1, a1, a2 +; CHECK-NEXT: pabdu.h a1, a1, a2 ; CHECK-NEXT: sw a1, 0(a0) ; CHECK-NEXT: ret %a = load <2 x i16>, ptr %a_ptr @@ -308,7 +308,7 @@ define void @test_pdif_b(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) { ; CHECK: # %bb.0: ; CHECK-NEXT: lw a1, 0(a1) ; CHECK-NEXT: lw a2, 0(a2) -; CHECK-NEXT: pdif.b a1, a1, a2 +; CHECK-NEXT: pabd.b a1, a1, a2 ; CHECK-NEXT: sw a1, 0(a0) ; CHECK-NEXT: ret %a = load <4 x i8>, ptr %a_ptr @@ -326,7 +326,7 @@ define void @test_pdifu_b(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) { ; CHECK: # %bb.0: ; CHECK-NEXT: lw a1, 0(a1) ; CHECK-NEXT: lw a2, 0(a2) -; CHECK-NEXT: pdifu.b a1, a1, a2 +; CHECK-NEXT: pabdu.b a1, a1, a2 ; CHECK-NEXT: sw a1, 0(a0) ; CHECK-NEXT: ret %a = load <4 x i8>, ptr %a_ptr @@ -558,16 +558,16 @@ define void @test_non_const_splat_i16(ptr %ret_ptr, ptr %a_ptr, i16 %elt) { define void @test_build_vector_i8(i8 %a, i8 %c, i8 %b, i8 %d, ptr %ret_ptr) { ; CHECK-RV32-LABEL: test_build_vector_i8: ; CHECK-RV32: # %bb.0: -; CHECK-RV32-NEXT: ppack.dh a0, a0, a2 +; CHECK-RV32-NEXT: ppaire.db a0, a0, a2 ; CHECK-RV32-NEXT: pack a0, a0, a1 ; CHECK-RV32-NEXT: sw a0, 0(a4) ; CHECK-RV32-NEXT: ret ; ; CHECK-RV64-LABEL: test_build_vector_i8: ; CHECK-RV64: # %bb.0: -; CHECK-RV64-NEXT: ppack.h a1, a1, a3 -; CHECK-RV64-NEXT: ppack.h a0, a0, a2 -; CHECK-RV64-NEXT: ppack.w a0, a0, a1 +; CHECK-RV64-NEXT: ppaire.b a1, a1, a3 +; CHECK-RV64-NEXT: ppaire.b a0, a0, a2 +; CHECK-RV64-NEXT: ppaire.h a0, a0, a1 ; CHECK-RV64-NEXT: sw a0, 0(a4) ; CHECK-RV64-NEXT: ret %v0 = insertelement <4 x i8> poison, i8 %a, i32 0 @@ -587,7 +587,7 @@ define void @test_build_vector_i16(ptr %ret_ptr, i16 %a, i16 %b) { ; ; CHECK-RV64-LABEL: test_build_vector_i16: ; CHECK-RV64: # %bb.0: -; CHECK-RV64-NEXT: ppack.w a1, a1, a2 +; CHECK-RV64-NEXT: ppaire.h a1, a1, a2 ; CHECK-RV64-NEXT: sw a1, 0(a0) ; CHECK-RV64-NEXT: ret %v0 = insertelement <2 x i16> poison, i16 %a, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll index 9b021df8dd452..d15bcdb9c500f 100644 --- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll @@ -274,7 +274,7 @@ define void @test_pdif_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) { ; CHECK: # %bb.0: ; CHECK-NEXT: ld a1, 0(a1) ; CHECK-NEXT: ld a2, 0(a2) -; CHECK-NEXT: pdif.h a1, a1, a2 +; CHECK-NEXT: pabd.h a1, a1, a2 ; CHECK-NEXT: sd a1, 0(a0) ; CHECK-NEXT: ret %a = load <4 x i16>, ptr %a_ptr @@ -293,7 +293,7 @@ define void @test_pdifu_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) { ; CHECK: # %bb.0: ; CHECK-NEXT: ld a1, 0(a1) ; CHECK-NEXT: ld a2, 0(a2) -; CHECK-NEXT: pdifu.h a1, a1, a2 +; CHECK-NEXT: pabdu.h a1, a1, a2 ; CHECK-NEXT: sd a1, 0(a0) ; CHECK-NEXT: ret %a = load <4 x i16>, ptr %a_ptr @@ -311,7 +311,7 @@ define void @test_pdif_b(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) { ; CHECK: # %bb.0: ; CHECK-NEXT: ld a1, 0(a1) ; CHECK-NEXT: ld a2, 0(a2) -; CHECK-NEXT: pdif.b a1, a1, a2 +; CHECK-NEXT: pabd.b a1, a1, a2 ; CHECK-NEXT: sd a1, 0(a0) ; CHECK-NEXT: ret %a = load <8 x i8>, ptr %a_ptr @@ -329,7 +329,7 @@ define void @test_pdifu_b(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) { ; CHECK: # %bb.0: ; CHECK-NEXT: ld a1, 0(a1) ; CHECK-NEXT: ld a2, 0(a2) -; CHECK-NEXT: pdifu.b a1, a1, a2 +; CHECK-NEXT: pabdu.b a1, a1, a2 ; CHECK-NEXT: sd a1, 0(a0) ; CHECK-NEXT: ret %a = load <8 x i8>, ptr %a_ptr @@ -701,12 +701,12 @@ define void @test_build_vector_i8(ptr %ret_ptr, i8 %a, i8 %b, i8 %c, i8 %d, i8 % ; CHECK-LABEL: test_build_vector_i8: ; CHECK: # %bb.0: ; CHECK-NEXT: lbu t0, 0(sp) -; CHECK-NEXT: ppack.h a5, a5, a6 -; CHECK-NEXT: ppack.h a3, a3, a4 -; CHECK-NEXT: ppack.h a1, a1, a2 -; CHECK-NEXT: ppack.h a2, a7, t0 -; CHECK-NEXT: ppack.w a2, a5, a2 -; CHECK-NEXT: ppack.w a1, a1, a3 +; CHECK-NEXT: ppaire.b a5, a5, a6 +; CHECK-NEXT: ppaire.b a3, a3, a4 +; CHECK-NEXT: ppaire.b a1, a1, a2 +; CHECK-NEXT: ppaire.b a2, a7, t0 +; CHECK-NEXT: ppaire.h a2, a5, a2 +; CHECK-NEXT: ppaire.h a1, a1, a3 ; CHECK-NEXT: pack a1, a1, a2 ; CHECK-NEXT: sd a1, 0(a0) ; CHECK-NEXT: ret @@ -725,8 +725,8 @@ define void @test_build_vector_i8(ptr %ret_ptr, i8 %a, i8 %b, i8 %c, i8 %d, i8 % define void @test_build_vector_i16(ptr %ret_ptr, i16 %a, i16 %b, i16 %c, i16 %d) { ; CHECK-LABEL: test_build_vector_i16: ; CHECK: # %bb.0: -; CHECK-NEXT: ppack.w a3, a3, a4 -; CHECK-NEXT: ppack.w a1, a1, a2 +; CHECK-NEXT: ppaire.h a3, a3, a4 +; CHECK-NEXT: ppaire.h a1, a1, a2 ; CHECK-NEXT: pack a1, a1, a3 ; CHECK-NEXT: sd a1, 0(a0) ; CHECK-NEXT: ret diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index e41c9eac982a7..fb5f033262b57 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -501,8 +501,8 @@ .attribute arch, "rv32i_sdtrig1p0" # CHECK: attribute 5, "rv32i2p1_sdtrig1p0" -.attribute arch, "rv32i_p0p15" -# CHECK: attribute 5, "rv32i2p1_p0p15" +.attribute arch, "rv32i_p0p18" +# CHECK: attribute 5, "rv32i2p1_p0p18" -.attribute arch, "rv64i_p0p15" -# CHECK: attribute 5, "rv64i2p1_p0p15" +.attribute arch, "rv64i_p0p18" +# CHECK: attribute 5, "rv64i2p1_p0p18" diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s index 15622cd9554ce..7f57345c3223c 100644 --- a/llvm/test/MC/RISCV/rv32i-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-invalid.s @@ -192,8 +192,8 @@ fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the followi fadd.d a0, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer){{$}} fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer){{$}} flh ft0, (a0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}} -sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zba' (Address Generation Instructions) or 'Base P' (Packed-SIMD){{$}} -clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation) or 'Base P' (Packed-SIMD){{$}} +sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zba' (Address Generation Instructions){{$}} +clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation){{$}} clmul a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography){{$}} bset a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbs' (Single-Bit Instructions){{$}} pause # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zihintpause' (Pause Hint){{$}} diff --git a/llvm/test/MC/RISCV/rv32p-invalid.s b/llvm/test/MC/RISCV/rv32p-invalid.s index b00c39b8811dc..617499859f853 100644 --- a/llvm/test/MC/RISCV/rv32p-invalid.s +++ b/llvm/test/MC/RISCV/rv32p-invalid.s @@ -102,10 +102,11 @@ maccsu.w00 a4, s2, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the fol pmaccsu.w.h11 a0, a2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set maccsu.w11 t5, a4, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -ppack.w t5, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -ppackbt.w t5, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -ppacktb.w t5, t1, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -ppackt.w t3, a0, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +ppaire.h t5, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set + +ppaireo.w t5, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +ppairoe.w t5, t1, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +ppairo.w t3, a0, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set pli.dh a1, 1 # CHECK: :[[@LINE]]:8: error: register must be even pli.db s1, 1 # CHECK: :[[@LINE]]:8: error: register must be even diff --git a/llvm/test/MC/RISCV/rv32p-valid.s b/llvm/test/MC/RISCV/rv32p-valid.s index 3a41d0d237c2e..2a4ac159a64c8 100644 --- a/llvm/test/MC/RISCV/rv32p-valid.s +++ b/llvm/test/MC/RISCV/rv32p-valid.s @@ -4,45 +4,18 @@ # RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r --no-print-imm-hex - \ # RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s -# CHECK-ASM-AND-OBJ: clz a0, a1 -# CHECK-ASM: encoding: [0x13,0x95,0x05,0x60] -clz a0, a1 # CHECK-ASM-AND-OBJ: cls a1, a2 # CHECK-ASM: encoding: [0x93,0x15,0x36,0x60] cls a1, a2 -# CHECK-ASM-AND-OBJ: sext.b a2, a3 -# CHECK-ASM: encoding: [0x13,0x96,0x46,0x60] -sext.b a2, a3 -# CHECK-ASM-AND-OBJ: sext.h t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60] -sext.h t0, t1 # CHECK-ASM-AND-OBJ: abs a4, a5 # CHECK-ASM: encoding: [0x13,0x97,0x77,0x60] abs a4, a5 -# CHECK-ASM-AND-OBJ: rev8 s0, s1 -# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x69] -rev8 s0, s1 # CHECK-ASM-AND-OBJ: rev s2, s3 # CHECK-ASM: encoding: [0x13,0xd9,0xf9,0x69] rev s2, s3 -# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2 -# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20] -sh1add a0, a1, a2 # CHECK-ASM-AND-OBJ: pack s0, s1, s2 # CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09] pack s0, s1, s2 -# CHECK-ASM-AND-OBJ: min t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a] -min t0, t1, t2 -# CHECK-ASM-AND-OBJ: minu ra, sp, gp -# CHECK-ASM: encoding: [0xb3,0x50,0x31,0x0a] -minu ra, sp, gp -# CHECK-ASM-AND-OBJ: max t3, t4, t5 -# CHECK-ASM: encoding: [0x33,0xee,0xee,0x0b] -max t3, t4, t5 -# CHECK-ASM-AND-OBJ: maxu a4, a5, a6 -# CHECK-ASM: encoding: [0x33,0xf7,0x07,0x0b] -maxu a4, a5, a6 # CHECK-ASM-AND-OBJ: pslli.b a6, a7, 0 # CHECK-ASM: encoding: [0x1b,0xa8,0x88,0x80] pslli.b a6, a7, 0 @@ -205,12 +178,12 @@ psub.h t3, t4, t5 # CHECK-ASM-AND-OBJ: psub.b t0, t1, t2 # CHECK-ASM: encoding: [0xbb,0x02,0x73,0xc4] psub.b t0, t1, t2 -# CHECK-ASM-AND-OBJ: pdif.h t3, t4, t5 +# CHECK-ASM-AND-OBJ: pabd.h t3, t4, t5 # CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xc9] -pdif.h t3, t4, t5 -# CHECK-ASM-AND-OBJ: pdif.b t0, t1, t2 +pabd.h t3, t4, t5 +# CHECK-ASM-AND-OBJ: pabd.b t0, t1, t2 # CHECK-ASM: encoding: [0xbb,0x02,0x73,0xcc] -pdif.b t0, t1, t2 +pabd.b t0, t1, t2 # CHECK-ASM-AND-OBJ: pssub.h t3, t4, t5 # CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xd1] pssub.h t3, t4, t5 @@ -229,12 +202,12 @@ asub t1, a7, a0 # CHECK-ASM-AND-OBJ: pasub.b t0, t1, t2 # CHECK-ASM: encoding: [0xbb,0x02,0x73,0xdc] pasub.b t0, t1, t2 -# CHECK-ASM-AND-OBJ: pdifu.h t3, t4, t5 +# CHECK-ASM-AND-OBJ: pabdu.h t3, t4, t5 # CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xe9] -pdifu.h t3, t4, t5 -# CHECK-ASM-AND-OBJ: pdifu.b t0, t1, t2 +pabdu.h t3, t4, t5 +# CHECK-ASM-AND-OBJ: pabdu.b t0, t1, t2 # CHECK-ASM: encoding: [0xbb,0x02,0x73,0xec] -pdifu.b t0, t1, t2 +pabdu.b t0, t1, t2 # CHECK-ASM-AND-OBJ: pssubu.h t3, t4, t5 # CHECK-ASM: encoding: [0x3b,0x8e,0xee,0xf1] pssubu.h t3, t4, t5 @@ -283,15 +256,15 @@ pmulu.h.b01 t3, t4, t5 # CHECK-ASM-AND-OBJ: mulu.h01 t0, t1, t2 # CHECK-ASM: encoding: [0xbb,0x12,0x73,0xb2] mulu.h01 t0, t1, t2 -# CHECK-ASM-AND-OBJ: pdifsumu.b t3, t4, t5 +# CHECK-ASM-AND-OBJ: pabdsumu.b t3, t4, t5 # CHECK-ASM: encoding: [0x3b,0x9e,0xee,0xb5] -pdifsumu.b t3, t4, t5 +pabdsumu.b t3, t4, t5 # CHECK-ASM-AND-OBJ: maccu.h01 t3, t4, t5 # CHECK-ASM: encoding: [0x3b,0x9e,0xee,0xbb] maccu.h01 t3, t4, t5 -# CHECK-ASM-AND-OBJ: pdifsumau.b t3, t4, t5 +# CHECK-ASM-AND-OBJ: pabdsumau.b t3, t4, t5 # CHECK-ASM: encoding: [0x3b,0x9e,0xee,0xbd] -pdifsumau.b t3, t4, t5 +pabdsumau.b t3, t4, t5 # CHECK-ASM-AND-OBJ: psh1add.h a0, a1, a2 # CHECK-ASM: encoding: [0x3b,0xa5,0xc5,0xa0] psh1add.h a0, a1, a2 @@ -355,27 +328,27 @@ mulsu.h11 s8, s4, s0 # CHECK-ASM-AND-OBJ: maccsu.h11 s0, a2, s6 # CHECK-ASM: encoding: [0x3b,0x34,0x66,0xfb] maccsu.h11 s0, a2, s6 -# CHECK-ASM-AND-OBJ: ppack.h t1, a2, t5 +# CHECK-ASM-AND-OBJ: ppaire.b t1, a2, t5 # CHECK-ASM: encoding: [0x3b,0x43,0xe6,0x81] -ppack.h t1, a2, t5 -# CHECK-ASM-AND-OBJ: ppackbt.h t5, t3, s2 +ppaire.b t1, a2, t5 +# CHECK-ASM-AND-OBJ: ppaireo.b t5, t3, s2 # CHECK-ASM: encoding: [0x3b,0x4f,0x2e,0x91] -ppackbt.h t5, t3, s2 -# CHECK-ASM-AND-OBJ: packbt t1, t1, s2 +ppaireo.b t5, t3, s2 +# CHECK-ASM-AND-OBJ: ppaireo.h t1, t1, s2 # CHECK-ASM: encoding: [0x3b,0x43,0x23,0x93] -packbt t1, t1, s2 -# CHECK-ASM-AND-OBJ: ppacktb.h t1, t1, s0 +ppaireo.h t1, t1, s2 +# CHECK-ASM-AND-OBJ: ppairoe.b t1, t1, s0 # CHECK-ASM: encoding: [0x3b,0x43,0x83,0xa0] -ppacktb.h t1, t1, s0 -# CHECK-ASM-AND-OBJ: packtb t5, s0, a2 +ppairoe.b t1, t1, s0 +# CHECK-ASM-AND-OBJ: ppairoe.h t5, s0, a2 # CHECK-ASM: encoding: [0x3b,0x4f,0xc4,0xa2] -packtb t5, s0, a2 -# CHECK-ASM-AND-OBJ: ppackt.h t3, s0, s0 +ppairoe.h t5, s0, a2 +# CHECK-ASM-AND-OBJ: ppairo.b t3, s0, s0 # CHECK-ASM: encoding: [0x3b,0x4e,0x84,0xb0] -ppackt.h t3, s0, s0 -# CHECK-ASM-AND-OBJ: packt a2, t3, t1 +ppairo.b t3, s0, s0 +# CHECK-ASM-AND-OBJ: ppairo.h a2, t3, t1 # CHECK-ASM: encoding: [0x3b,0x46,0x6e,0xb2] -packt a2, t3, t1 +ppairo.h a2, t3, t1 # CHECK-ASM: encoding: [0x3b,0x5e,0x83,0x80] pm2add.h t3, t1, s0 # CHECK-ASM-AND-OBJ: pm4add.b t1, s2, t5 @@ -1191,12 +1164,12 @@ psub.db a4, a0, t5 # CHECK-ASM-AND-OBJ: subd a2, a4, t1 # CHECK-ASM: encoding: [0x1b,0x66,0x67,0xc6] subd a2, a4, t1 -# CHECK-ASM-AND-OBJ: pdif.dh t5, t1, t3 +# CHECK-ASM-AND-OBJ: pabd.dh t5, t1, t3 # CHECK-ASM: encoding: [0x1b,0x6f,0xc3,0xc9] -pdif.dh t5, t1, t3 -# CHECK-ASM-AND-OBJ: pdif.db t1, t5, a0 +pabd.dh t5, t1, t3 +# CHECK-ASM-AND-OBJ: pabd.db t1, t5, a0 # CHECK-ASM: encoding: [0x1b,0x63,0xaf,0xcc] -pdif.db t1, t5, a0 +pabd.db t1, t5, a0 # CHECK-ASM-AND-OBJ: pssub.dh s0, s2, s2 # CHECK-ASM: encoding: [0x1b,0x64,0x29,0xd1] pssub.dh s0, s2, s2 @@ -1215,12 +1188,12 @@ pasub.dw t1, s2, s2 # CHECK-ASM-AND-OBJ: pasub.db a0, a0, a0 # CHECK-ASM: encoding: [0x1b,0x65,0xa5,0xdc] pasub.db a0, a0, a0 -# CHECK-ASM-AND-OBJ: pdifu.dh t5, a4, a4 +# CHECK-ASM-AND-OBJ: pabdu.dh t5, a4, a4 # CHECK-ASM: encoding: [0x1b,0x6f,0xe7,0xe8] -pdifu.dh t5, a4, a4 -# CHECK-ASM-AND-OBJ: pdifu.db t1, t1, a4 +pabdu.dh t5, a4, a4 +# CHECK-ASM-AND-OBJ: pabdu.db t1, t1, a4 # CHECK-ASM: encoding: [0x1b,0x63,0xe3,0xec] -pdifu.db t1, t1, a4 +pabdu.db t1, t1, a4 # CHECK-ASM-AND-OBJ: pssubu.dh t5, t1, t5 # CHECK-ASM: encoding: [0x1b,0x6f,0xe3,0xf1] pssubu.dh t5, t1, t5 @@ -1251,30 +1224,30 @@ pssh1sadd.dh t3, a4, a0 # CHECK-ASM-AND-OBJ: pssh1sadd.dw t1, t1, a2 # CHECK-ASM: encoding: [0x1b,0x63,0xd3,0xb2] pssh1sadd.dw t1, t1, a2 -# CHECK-ASM-AND-OBJ: ppack.dh a2, t1, s2 +# CHECK-ASM-AND-OBJ: ppaire.db a2, t1, s2 # CHECK-ASM: encoding: [0x1b,0xe6,0x23,0x81] -ppack.dh a2, t1, s2 -# CHECK-ASM-AND-OBJ: ppack.dw t5, t3, a4 +ppaire.db a2, t1, s2 +# CHECK-ASM-AND-OBJ: ppaire.dh t5, t3, a4 # CHECK-ASM: encoding: [0x1b,0xef,0xee,0x82] -ppack.dw t5, t3, a4 -# CHECK-ASM-AND-OBJ: ppackbt.dh t1, t3, t1 +ppaire.dh t5, t3, a4 +# CHECK-ASM-AND-OBJ: ppaireo.db t1, t3, t1 # CHECK-ASM: encoding: [0x1b,0xe3,0x6e,0x90] -ppackbt.dh t1, t3, t1 -# CHECK-ASM-AND-OBJ: ppackbt.dw a4, t5, a2 +ppaireo.db t1, t3, t1 +# CHECK-ASM-AND-OBJ: ppaireo.dh a4, t5, a2 # CHECK-ASM: encoding: [0x1b,0xe7,0xcf,0x92] -ppackbt.dw a4, t5, a2 -# CHECK-ASM-AND-OBJ: ppacktb.dh a4, t1, a2 +ppaireo.dh a4, t5, a2 +# CHECK-ASM-AND-OBJ: ppairoe.db a4, t1, a2 # CHECK-ASM: encoding: [0x1b,0xe7,0xc3,0xa0] -ppacktb.dh a4, t1, a2 -# CHECK-ASM-AND-OBJ: ppacktb.dw a2, t5, s0 +ppairoe.db a4, t1, a2 +# CHECK-ASM-AND-OBJ: ppairoe.dh a2, t5, s0 # CHECK-ASM: encoding: [0x1b,0xe6,0x8f,0xa2] -ppacktb.dw a2, t5, s0 -# CHECK-ASM-AND-OBJ: ppackt.dh a0, a0, s0 +ppairoe.dh a2, t5, s0 +# CHECK-ASM-AND-OBJ: ppairo.db a0, a0, s0 # CHECK-ASM: encoding: [0x1b,0xe5,0x85,0xb0] -ppackt.dh a0, a0, s0 -# CHECK-ASM-AND-OBJ: ppackt.dw a4, a4, a2 +ppairo.db a0, a0, s0 +# CHECK-ASM-AND-OBJ: ppairo.dh a4, a4, a2 # CHECK-ASM: encoding: [0x1b,0xe7,0xc7,0xb2] -ppackt.dw a4, a4, a2 +ppairo.dh a4, a4, a2 # CHECK-ASM-AND-OBJ: pas.dhx t3, t3, s2 # CHECK-ASM: encoding: [0x1b,0xee,0x3e,0x81] pas.dhx t3, t3, s2 diff --git a/llvm/test/MC/RISCV/rv64p-valid.s b/llvm/test/MC/RISCV/rv64p-valid.s index a789f506da499..95dc5813910fc 100644 --- a/llvm/test/MC/RISCV/rv64p-valid.s +++ b/llvm/test/MC/RISCV/rv64p-valid.s @@ -4,57 +4,27 @@ # RUN: | llvm-objdump --triple=riscv64 --mattr=+experimental-p -M no-aliases --no-print-imm-hex -d -r - \ # RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s -# CHECK-ASM-AND-OBJ: clz a0, a1 -# CHECK-ASM: encoding: [0x13,0x95,0x05,0x60] -clz a0, a1 # CHECK-ASM-AND-OBJ: cls a1, a2 # CHECK-ASM: encoding: [0x93,0x15,0x36,0x60] cls a1, a2 -# CHECK-ASM-AND-OBJ: sext.b a2, a3 -# CHECK-ASM: encoding: [0x13,0x96,0x46,0x60] -sext.b a2, a3 -# CHECK-ASM-AND-OBJ: sext.h t0, t1 -# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60] -sext.h t0, t1 # CHECK-ASM-AND-OBJ: abs a4, a5 # CHECK-ASM: encoding: [0x13,0x97,0x77,0x60] abs a4, a5 # CHECK-ASM-AND-OBJ: rev16 s0, s1 # CHECK-ASM: encoding: [0x13,0xd4,0x04,0x6b] rev16 s0, s1 -# CHECK-ASM-AND-OBJ: rev8 s0, s1 -# CHECK-ASM: encoding: [0x13,0xd4,0x84,0x6b] -rev8 s0, s1 # CHECK-ASM-AND-OBJ: rev s2, s3 # CHECK-ASM: encoding: [0x13,0xd9,0xf9,0x6b] rev s2, s3 -# CHECK-ASM-AND-OBJ: clzw s0, s1 -# CHECK-ASM: encoding: [0x1b,0x94,0x04,0x60] -clzw s0, s1 # CHECK-ASM-AND-OBJ: clsw s2, s3 # CHECK-ASM: encoding: [0x1b,0x99,0x39,0x60] clsw s2, s3 # CHECK-ASM-AND-OBJ: absw s2, s3 # CHECK-ASM: encoding: [0x1b,0x99,0x79,0x60] absw s2, s3 -# CHECK-ASM-AND-OBJ: sh1add a0, a1, a2 -# CHECK-ASM: encoding: [0x33,0xa5,0xc5,0x20] -sh1add a0, a1, a2 # CHECK-ASM-AND-OBJ: pack s0, s1, s2 # CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09] pack s0, s1, s2 -# CHECK-ASM-AND-OBJ: min t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a] -min t0, t1, t2 -# CHECK-ASM-AND-OBJ: minu ra, sp, gp -# CHECK-ASM: encoding: [0xb3,0x50,0x31,0x0a] -minu ra, sp, gp -# CHECK-ASM-AND-OBJ: max t3, t4, t5 -# CHECK-ASM: encoding: [0x33,0xee,0xee,0x0b] -max t3, t4, t5 -# CHECK-ASM-AND-OBJ: maxu a4, a5, a6 -# CHECK-ASM: encoding: [0x33,0xf7,0x07,0x0b] -maxu a4, a5, a6 # CHECK-ASM-AND-OBJ: pslli.b a6, a7, 0 # CHECK-ASM: encoding: [0x1b,0xa8,0x88,0x80] pslli.b a6, a7, 0 @@ -271,12 +241,12 @@ psub.w t3, a0, s0 # CHECK-ASM-AND-OBJ: psub.b t5, t1, a4 # CHECK-ASM: encoding: [0x3b,0x0f,0xe3,0xc4] psub.b t5, t1, a4 -# CHECK-ASM-AND-OBJ: pdif.h t1, a4, a2 +# CHECK-ASM-AND-OBJ: pabd.h t1, a4, a2 # CHECK-ASM: encoding: [0x3b,0x03,0xc7,0xc8] -pdif.h t1, a4, a2 -# CHECK-ASM-AND-OBJ: pdif.b t3, t1, t5 +pabd.h t1, a4, a2 +# CHECK-ASM-AND-OBJ: pabd.b t3, t1, t5 # CHECK-ASM: encoding: [0x3b,0x0e,0xe3,0xcd] -pdif.b t3, t1, t5 +pabd.b t3, t1, t5 # CHECK-ASM-AND-OBJ: pssub.h a0, a2, t3 # CHECK-ASM: encoding: [0x3b,0x05,0xc6,0xd1] pssub.h a0, a2, t3 @@ -295,12 +265,12 @@ pasub.w t3, a2, a4 # CHECK-ASM-AND-OBJ: pasub.b s0, t3, s2 # CHECK-ASM: encoding: [0x3b,0x04,0x2e,0xdd] pasub.b s0, t3, s2 -# CHECK-ASM-AND-OBJ: pdifu.h t5, s0, a4 +# CHECK-ASM-AND-OBJ: pabdu.h t5, s0, a4 # CHECK-ASM: encoding: [0x3b,0x0f,0xe4,0xe8] -pdifu.h t5, s0, a4 -# CHECK-ASM-AND-OBJ: pdifu.b t3, a0, t5 +pabdu.h t5, s0, a4 +# CHECK-ASM-AND-OBJ: pabdu.b t3, a0, t5 # CHECK-ASM: encoding: [0x3b,0x0e,0xe5,0xed] -pdifu.b t3, a0, t5 +pabdu.b t3, a0, t5 # CHECK-ASM-AND-OBJ: pssubu.h t3, s2, a0 # CHECK-ASM: encoding: [0x3b,0x0e,0xa9,0xf0] pssubu.h t3, s2, a0 @@ -355,18 +325,18 @@ pmulu.h.b01 s2, a4, a0 # CHECK-ASM-AND-OBJ: pmulu.w.h01 t1, a4, a2 # CHECK-ASM: encoding: [0x3b,0x13,0xc7,0xb2] pmulu.w.h01 t1, a4, a2 -# CHECK-ASM-AND-OBJ: pdifsumu.b t3, t5, t3 +# CHECK-ASM-AND-OBJ: pabdsumu.b t3, t5, t3 # CHECK-ASM: encoding: [0x3b,0x1e,0xcf,0xb5] -pdifsumu.b t3, t5, t3 +pabdsumu.b t3, t5, t3 # CHECK-ASM-AND-OBJ: mulu.w01 t5, t1, t5 # CHECK-ASM: encoding: [0x3b,0x1f,0xe3,0xb7] mulu.w01 t5, t1, t5 # CHECK-ASM-AND-OBJ: pmaccu.w.h01 t5, t5, a4 # CHECK-ASM: encoding: [0x3b,0x1f,0xef,0xba] pmaccu.w.h01 t5, t5, a4 -# CHECK-ASM-AND-OBJ: pdifsumau.b s2, a2, a0 +# CHECK-ASM-AND-OBJ: pabdsumau.b s2, a2, a0 # CHECK-ASM: encoding: [0x3b,0x19,0xa6,0xbc] -pdifsumau.b s2, a2, a0 +pabdsumau.b s2, a2, a0 # CHECK-ASM-AND-OBJ: maccu.w01 a0, a0, t1 # CHECK-ASM: encoding: [0x3b,0x15,0x65,0xbe] maccu.w01 a0, a0, t1 @@ -496,39 +466,39 @@ pmaccsu.w.h11 a0, a2, t3 # CHECK-ASM-AND-OBJ: maccsu.w11 t5, a4, s2 # CHECK-ASM: encoding: [0x3b,0x3f,0x27,0xff] maccsu.w11 t5, a4, s2 -# CHECK-ASM-AND-OBJ: ppack.h s0, s0, s2 +# CHECK-ASM-AND-OBJ: ppaire.b s0, s0, s2 # CHECK-ASM: encoding: [0x3b,0x44,0x24,0x81] -ppack.h s0, s0, s2 -# CHECK-ASM-AND-OBJ: ppack.w t5, a2, a4 +ppaire.b s0, s0, s2 +# CHECK-ASM-AND-OBJ: ppaire.h t5, a2, a4 # CHECK-ASM: encoding: [0x3b,0x4f,0xe6,0x82] -ppack.w t5, a2, a4 -# CHECK-ASM-AND-OBJ: ppackbt.h a4, s2, t3 +ppaire.h t5, a2, a4 +# CHECK-ASM-AND-OBJ: ppaireo.b a4, s2, t3 # CHECK-ASM: encoding: [0x3b,0x47,0xc9,0x91] -ppackbt.h a4, s2, t3 -# CHECK-ASM-AND-OBJ: ppackbt.w t5, s0, t5 +ppaireo.b a4, s2, t3 +# CHECK-ASM-AND-OBJ: ppaireo.h t5, s0, t5 # CHECK-ASM: encoding: [0x3b,0x4f,0xe4,0x93] -ppackbt.w t5, s0, t5 -# CHECK-ASM-AND-OBJ: packbt a0, t5, a0 +ppaireo.h t5, s0, t5 +# CHECK-ASM-AND-OBJ: ppaireo.w a0, t5, a0 # CHECK-ASM: encoding: [0x3b,0x45,0xaf,0x96] -packbt a0, t5, a0 -# CHECK-ASM-AND-OBJ: ppacktb.h t3, s0, t3 +ppaireo.w a0, t5, a0 +# CHECK-ASM-AND-OBJ: ppairoe.b t3, s0, t3 # CHECK-ASM: encoding: [0x3b,0x4e,0xc4,0xa1] -ppacktb.h t3, s0, t3 -# CHECK-ASM-AND-OBJ: ppacktb.w t5, t1, t1 +ppairoe.b t3, s0, t3 +# CHECK-ASM-AND-OBJ: ppairoe.h t5, t1, t1 # CHECK-ASM: encoding: [0x3b,0x4f,0x63,0xa2] -ppacktb.w t5, t1, t1 -# CHECK-ASM-AND-OBJ: packtb t5, a4, a4 +ppairoe.h t5, t1, t1 +# CHECK-ASM-AND-OBJ: ppairoe.w t5, a4, a4 # CHECK-ASM: encoding: [0x3b,0x4f,0xe7,0xa6] -packtb t5, a4, a4 -# CHECK-ASM-AND-OBJ: ppackt.h a0, t1, t5 +ppairoe.w t5, a4, a4 +# CHECK-ASM-AND-OBJ: ppairo.b a0, t1, t5 # CHECK-ASM: encoding: [0x3b,0x45,0xe3,0xb1] -ppackt.h a0, t1, t5 -# CHECK-ASM-AND-OBJ: ppackt.w t3, a0, s2 +ppairo.b a0, t1, t5 +# CHECK-ASM-AND-OBJ: ppairo.h t3, a0, s2 # CHECK-ASM: encoding: [0x3b,0x4e,0x25,0xb3] -ppackt.w t3, a0, s2 -# CHECK-ASM-AND-OBJ: packt a2, t3, t1 +ppairo.h t3, a0, s2 +# CHECK-ASM-AND-OBJ: ppairo.w a2, t3, t1 # CHECK-ASM: encoding: [0x3b,0x46,0x6e,0xb6] -packt a2, t3, t1 +ppairo.w a2, t3, t1 # CHECK-ASM-AND-OBJ: pm2add.h a4, t3, t5 # CHECK-ASM: encoding: [0x3b,0x57,0xee,0x81] pm2add.h a4, t3, t5 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index c55cd94048cc5..1a4bddafbb9c1 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1194,7 +1194,7 @@ R"(All available -march extensions for RISC-V xwchc 2.2 Experimental extensions - p 0.15 + p 0.18 zibi 0.1 zicfilp 1.0 This is a long dummy description zicfiss 1.0 >From 7f2e2337f7c8e5d99fca70ff738900dea5d6e3a5 Mon Sep 17 00:00:00 2001 From: Craig Topper <[email protected]> Date: Tue, 2 Dec 2025 18:41:15 -0800 Subject: [PATCH 2/2] fixup! Update print-supported-extensions-riscv.c --- clang/test/Driver/print-supported-extensions-riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 681c912bd1612..4a6dcacfdcfff 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -217,7 +217,7 @@ // CHECK-NEXT: xwchc 2.2 'Xwchc' (WCH/QingKe additional compressed opcodes) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions -// CHECK-NEXT: p 0.15 'P' ('Base P' (Packed SIMD)) +// CHECK-NEXT: p 0.18 'P' ('Base P' (Packed SIMD)) // CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate) // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
