https://github.com/AlexMaclean approved this pull request.
https://github.com/llvm/llvm-project/pull/135444
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https://github.com/AlexMaclean commented:
llvm changes LGTM, though I'm not too familiar with the MLIR portion of this
change.
https://github.com/llvm/llvm-project/pull/135444
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@@ -2381,25 +2387,38 @@ def INT_PTX_LDG_G_v4i32_ELE : VLDG_G_ELE_V4<"u32",
Int32Regs>;
def INT_PTX_LDG_G_v4f32_ELE : VLDG_G_ELE_V4<"f32", Float32Regs>;
-multiclass NG_TO_G {
- def "" : NVPTXInst<(outs Int32Regs:$result), (ins Int32Regs:$src),
- "cvta." # Str # ".u
@@ -3019,8 +3019,26 @@ SDValue NVPTXTargetLowering::LowerADDRSPACECAST(SDValue
Op,
unsigned SrcAS = N->getSrcAddressSpace();
unsigned DestAS = N->getDestAddressSpace();
if (SrcAS != llvm::ADDRESS_SPACE_GENERIC &&
- DestAS != llvm::ADDRESS_SPACE_GENERIC)
+ DestA
@@ -3019,8 +3019,26 @@ SDValue NVPTXTargetLowering::LowerADDRSPACECAST(SDValue
Op,
unsigned SrcAS = N->getSrcAddressSpace();
unsigned DestAS = N->getDestAddressSpace();
if (SrcAS != llvm::ADDRESS_SPACE_GENERIC &&
- DestAS != llvm::ADDRESS_SPACE_GENERIC)
+ DestA
@@ -25,6 +25,7 @@ enum AddressSpace : unsigned {
ADDRESS_SPACE_CONST = 4,
ADDRESS_SPACE_LOCAL = 5,
ADDRESS_SPACE_TENSOR = 6,
+ ADDRESS_SPACE_SHARED_CLUSTER = 7,
AlexMaclean wrote:
I think it would be good to rename `ADDRESS_SPACE_SHARED` to
`ADDRESS_SP
@@ -426,10 +426,7 @@ static std::optional evaluateIsSpace(Intrinsic::ID
IID, unsigned AS) {
case Intrinsic::nvvm_isspacep_shared:
return AS == NVPTXAS::ADDRESS_SPACE_SHARED;
AlexMaclean wrote:
If the address space is `ADDRESS_SPACE_SHARED_CLUSTER` this i
@@ -176,6 +176,7 @@ enum AddressSpace : AddressSpaceUnderlyingType {
Shared = 3,
AlexMaclean wrote:
Lets rename this to `SharedCTA` as well.
https://github.com/llvm/llvm-project/pull/135444
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@@ -426,10 +426,7 @@ static std::optional evaluateIsSpace(Intrinsic::ID
IID, unsigned AS) {
case Intrinsic::nvvm_isspacep_shared:
return AS == NVPTXAS::ADDRESS_SPACE_SHARED;
case Intrinsic::nvvm_isspacep_shared_cluster:
-// We can't tell shared from shared_cluster
@@ -2381,29 +2387,41 @@ def INT_PTX_LDG_G_v4i32_ELE : VLDG_G_ELE_V4<"u32",
Int32Regs>;
def INT_PTX_LDG_G_v4f32_ELE : VLDG_G_ELE_V4<"f32", Float32Regs>;
-multiclass NG_TO_G {
+multiclass NG_TO_G Preds = []> {
def "" : NVPTXInst<(outs Int32Regs:$result), (ins Int32Regs:$sr
@@ -0,0 +1,329 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc < %s -o - -mcpu=sm_90 -mattr=+ptx78 | FileCheck %s
+; RUN: %if ptxas-12.0 %{ llc < %s -mcpu=sm_90 -mattr=+ptx78| %ptxas-verify
-arch=sm_90 %}
+
+tar
@@ -3019,8 +3019,42 @@ SDValue NVPTXTargetLowering::LowerADDRSPACECAST(SDValue
Op,
unsigned SrcAS = N->getSrcAddressSpace();
unsigned DestAS = N->getDestAddressSpace();
if (SrcAS != llvm::ADDRESS_SPACE_GENERIC &&
- DestAS != llvm::ADDRESS_SPACE_GENERIC)
+ DestA
https://github.com/AlexMaclean commented:
Getting close to ready, a couple more places to update:
- NVPTXTargetTransformInfo.cpp: evaluateIsSpace
- NVPTXUsage.rst: Address Space section, add intrinsics you're modifying, such
as `mapa`, to the spec
https://github.com/llvm/llvm-project/pull/13544
@@ -0,0 +1,48 @@
+; RUN: llc -O0 < %s -mtriple=nvptx64 -mcpu=sm_80 | FileCheck %s
-check-prefixes=ALL,NOPTRCONV,CLS64
AlexMaclean wrote:
Use update_llc_test_checks for this test.
https://github.com/llvm/llvm-project/pull/135444
_
https://github.com/AlexMaclean edited
https://github.com/llvm/llvm-project/pull/135444
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@@ -1034,6 +1034,10 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned
BuiltinID,
case NVPTX::BI__nvvm_fmin_xorsign_abs_f16x2:
return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs_f16x2, BuiltinID, E,
*this);
+ case NVPTX::BI__nvvm_abs_bf16
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/135644
>From fd11c2b4c964a3fe336e3fcb106fca5bf9c7d2b2 Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Fri, 11 Apr 2025 17:59:50 +
Subject: [PATCH 1/6] [NVPTX] Cleaup and document nvvm.fabs intrinsics, adding
@@ -982,8 +982,9 @@ void NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
case ADDRESS_SPACE_SHARED:
Opc = TM.is64Bit() ? NVPTX::cvta_shared_64 : NVPTX::cvta_shared;
break;
-case ADDRESS_SPACE_DSHARED:
- Opc = TM.is64Bit() ? NVPTX::cvta_dshared_64 :
@@ -1034,6 +1034,10 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned
BuiltinID,
case NVPTX::BI__nvvm_fmin_xorsign_abs_f16x2:
return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs_f16x2, BuiltinID, E,
*this);
+ case NVPTX::BI__nvvm_abs_bf16
@@ -411,6 +412,13 @@ static Instruction
*convertNvvmIntrinsicToLlvm(InstCombiner &IC,
}
return nullptr;
}
+ case SPC_Fabs: {
+if (!II->getType()->isDoubleTy())
+ return nullptr;
+auto *Fabs = Intrinsic::getOrInsertDeclaration(
+II->getModule(),
@@ -309,6 +309,60 @@ space casted to this space), 1 is returned, otherwise 0 is
returned.
Arithmetic Intrinsics
-
+'``llvm.nvvm.fabs.*``' Intrinsic
+
+
+Syntax:
+"""
+
+.. code-block:: llvm
+
+declare float @llvm.nvv
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/135644
>From fd11c2b4c964a3fe336e3fcb106fca5bf9c7d2b2 Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Fri, 11 Apr 2025 17:59:50 +
Subject: [PATCH 1/5] [NVPTX] Cleaup and document nvvm.fabs intrinsics, adding
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/135644
>From fd11c2b4c964a3fe336e3fcb106fca5bf9c7d2b2 Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Fri, 11 Apr 2025 17:59:50 +
Subject: [PATCH 1/4] [NVPTX] Cleaup and document nvvm.fabs intrinsics, adding
@@ -1034,6 +1034,10 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned
BuiltinID,
case NVPTX::BI__nvvm_fmin_xorsign_abs_f16x2:
return MakeHalfType(Intrinsic::nvvm_fmin_xorsign_abs_f16x2, BuiltinID, E,
*this);
+ case NVPTX::BI__nvvm_abs_bf16
@@ -137,6 +137,7 @@ def hasAtomBitwise64 :
Predicate<"Subtarget->hasAtomBitwise64()">;
def hasAtomMinMax64 : Predicate<"Subtarget->hasAtomMinMax64()">;
def hasVote : Predicate<"Subtarget->hasVote()">;
def hasDouble : Predicate<"Subtarget->hasDouble()">;
+def hasClusters : Pred
@@ -2038,15 +2038,15 @@ multiclass F_ATOMIC_2_AS,
preds>;
defm _S : F_ATOMIC_2,
preds>;
- defm _DS : F_ATOMIC_2, !listconcat([hasSM<80>], preds)>;
+ defm _S_C : F_ATOMIC_2, !listconcat([hasSM<80>], preds)>;
AlexMaclean wrote:
The PTX doc seems to say this
@@ -982,8 +982,9 @@ void NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
case ADDRESS_SPACE_SHARED:
Opc = TM.is64Bit() ? NVPTX::cvta_shared_64 : NVPTX::cvta_shared;
break;
-case ADDRESS_SPACE_DSHARED:
- Opc = TM.is64Bit() ? NVPTX::cvta_dshared_64 :
@@ -0,0 +1,258 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc < %s -o - -mcpu=sm_90 -march=nvptx64 -mattr=+ptx80 | FileCheck %s
+; RUN: %if ptxas-12.0 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx80|
%pt
https://github.com/AlexMaclean commented:
Backend changes look reasonable so far. One concern I have with this change is
that until now we've assumed specific address-spaces are non-overlapping.
You've addressed some of the places where this assumption is encoded but I
think there are others y
@@ -0,0 +1,258 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc < %s -o - -mcpu=sm_90 -march=nvptx64 -mattr=+ptx80 | FileCheck %s
+; RUN: %if ptxas-12.0 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx80|
%pt
@@ -0,0 +1,258 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc < %s -o - -mcpu=sm_90 -march=nvptx64 -mattr=+ptx80 | FileCheck %s
+; RUN: %if ptxas-12.0 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx80|
%pt
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@@ -703,6 +703,46 @@ let hasSideEffects = false in {
defm CVT_to_tf32_rz_satf : CVT_TO_TF32<"rz.satfinite", [hasPTX<86>,
hasSM<100>]>;
defm CVT_to_tf32_rn_relu_satf : CVT_TO_TF32<"rn.relu.satfinite",
[hasPTX<86>, hasSM<100>]>;
defm CVT_to_tf32_rz_relu_satf : CVT_TO_TF
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https://github.com/llvm/llvm-project/pull/134345
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AlexMaclean wrote:
Merging on behalf of @YonahGoldberg at his request offline.
https://github.com/llvm/llvm-project/pull/134416
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@@ -1548,6 +1548,45 @@ let TargetPrefix = "nvvm" in {
Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoMem, IntrNoCallback]>;
def int_nvvm_e5m2x2_to_f16x2_rn_relu :
ClangBuiltin<"__nvvm_e5m2x2_to_f16x2_rn_relu">,
Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoM
https://github.com/AlexMaclean approved this pull request.
LGTM, please wait for @Artem-B's approval before landing.
https://github.com/llvm/llvm-project/pull/134416
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AlexMaclean wrote:
It seems like we already have perhaps too many mechanisms to control how sqrt
gets lowered. There is the `__nv_sqrtf` libdevice function which chooses
between specific (1:1 to PTX) intrinsics based on NVVMReflect and then there is
also `llvm.sqrt` and `nvvm.sqrt.f` which are
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@@ -2314,6 +2317,12 @@ static Value *upgradeNVVMIntrinsicCall(StringRef Name,
CallBase *CI,
Value *Val = CI->getArgOperand(1);
Rep = Builder.CreateAtomicRMW(AtomicRMWInst::FAdd, Ptr, Val, MaybeAlign(),
AtomicOrdering::SequentiallyConsi
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/134111
>From 46de785e801bf8ca87e01aee9ad0a13ac07a47d6 Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Tue, 1 Apr 2025 20:22:24 +
Subject: [PATCH] [NVPTX] Auto-Upgrade llvm.nvvm.atomic.load.{inc,dec}.32
---
@@ -703,6 +703,53 @@ let hasSideEffects = false in {
defm CVT_to_tf32_rz_satf : CVT_TO_TF32<"rz.satfinite", [hasPTX<86>,
hasSM<100>]>;
defm CVT_to_tf32_rn_relu_satf : CVT_TO_TF32<"rn.relu.satfinite",
[hasPTX<86>, hasSM<100>]>;
defm CVT_to_tf32_rz_relu_satf : CVT_TO_TF
@@ -1944,6 +1944,62 @@ def : Pat<(int_nvvm_e5m2x2_to_f16x2_rn Int16Regs:$a),
def : Pat<(int_nvvm_e5m2x2_to_f16x2_rn_relu Int16Regs:$a),
(CVT_f16x2_e5m2x2 $a, CvtRN_RELU)>;
+def : Pat<(int_nvvm_ff_to_e2m3x2_rn f32:$a, f32:$b),
+ (CVT_e2m3x2_f32 $a, $b, CvtRN)
@@ -1548,6 +1548,45 @@ let TargetPrefix = "nvvm" in {
Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoMem, IntrNoCallback]>;
def int_nvvm_e5m2x2_to_f16x2_rn_relu :
ClangBuiltin<"__nvvm_e5m2x2_to_f16x2_rn_relu">,
Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoM
@@ -1548,6 +1548,45 @@ let TargetPrefix = "nvvm" in {
Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoMem, IntrNoCallback]>;
def int_nvvm_e5m2x2_to_f16x2_rn_relu :
ClangBuiltin<"__nvvm_e5m2x2_to_f16x2_rn_relu">,
Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoM
@@ -2314,6 +2317,12 @@ static Value *upgradeNVVMIntrinsicCall(StringRef Name,
CallBase *CI,
Value *Val = CI->getArgOperand(1);
Rep = Builder.CreateAtomicRMW(AtomicRMWInst::FAdd, Ptr, Val, MaybeAlign(),
AtomicOrdering::SequentiallyConsi
@@ -2070,8 +2070,8 @@ defm INT_PTX_ATOMIC_UMIN_32 : F_ATOMIC_2_AS]>;
// atom_inc atom_dec
AlexMaclean wrote:
I think it makes sense to test the auto-upgrade rules and test the lowering of
the current syntax but not to maintain lowering tests using out-of-dat
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/127736
>From b637f2a9142aa9493e78f8d6e05b692b7175c123 Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Wed, 19 Feb 2025 02:26:23 +
Subject: [PATCH 1/3] [NVPTX] Convert vector function nvvm.annotations to
attr
@@ -5021,6 +5024,36 @@ bool llvm::UpgradeDebugInfo(Module &M) {
return Modified;
}
+static void upgradeNVVMFnVectorAttr(const StringRef Attr, const char DimC,
+GlobalValue *GV, const Metadata *V) {
+ Function *F = cast(GV);
+
+ constexpr
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/127736
>From 5ca8b82e146439453b51f990e4ed43f8bd2838eb Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Wed, 19 Feb 2025 02:26:23 +
Subject: [PATCH 1/3] [NVPTX] Convert vector function nvvm.annotations to
attr
AlexMaclean wrote:
> I think they will become something like:
>
> ```c++
> llvmFunc->addFnAttr("nvvm.maxntid", llvm::utostr(workgroupSize[0]));
> llvmFunc->addFnAttr("nvvm.maxntid", llvm::utostr(workgroupSize[1]));
> llvmFunc->addFnAttr("nvvm.maxntid", llvm::utostr(workgroupSize[2]));
> ```
Not
AlexMaclean wrote:
@hanhanW, @akuegel Heads up, if you're using any of these annotations, I expect
you'll need to update your respective out-of-tree frontends once this change
lands (similar to https://github.com/llvm/llvm-project/pull/119261).
Here's an example of what that might look like:
@@ -196,6 +198,36 @@ static std::optional getFnAttrParsedInt(const
Function &F,
: std::nullopt;
}
+static SmallVector getFnAttrParsedVector(const Function &F,
+ StringRef Attr) {
+ SmallVector V;
+ auto &Ctx
@@ -5059,6 +5092,18 @@ bool static upgradeSingleNVVMAnnotation(GlobalValue *GV,
StringRef K,
cast(GV)->addFnAttr("nvvm.maxnreg", llvm::utostr(CV));
return true;
}
+ if (K.consume_front("maxntid") && (K == "x" || K == "y" || K == "z")) {
AlexMaclean
@@ -196,6 +198,36 @@ static std::optional getFnAttrParsedInt(const
Function &F,
: std::nullopt;
}
+static SmallVector getFnAttrParsedVector(const Function &F,
+ StringRef Attr) {
+ SmallVector V;
+ auto &Ctx
@@ -5021,6 +5024,36 @@ bool llvm::UpgradeDebugInfo(Module &M) {
return Modified;
}
+static void upgradeNVVMFnVectorAttr(const StringRef Attr, const char DimC,
+GlobalValue *GV, const Metadata *V) {
+ Function *F = cast(GV);
+
+ constexpr
@@ -5021,6 +5024,36 @@ bool llvm::UpgradeDebugInfo(Module &M) {
return Modified;
}
+static void upgradeNVVMFnVectorAttr(const StringRef Attr, const char DimC,
+GlobalValue *GV, const Metadata *V) {
+ Function *F = cast(GV);
+
+ constexpr
@@ -5021,6 +5024,36 @@ bool llvm::UpgradeDebugInfo(Module &M) {
return Modified;
}
+static void upgradeNVVMFnVectorAttr(const StringRef Attr, const char DimC,
+GlobalValue *GV, const Metadata *V) {
+ Function *F = cast(GV);
+
+ constexpr
@@ -506,24 +507,15 @@ void NVPTXAsmPrinter::emitKernelFunctionDirectives(const
Function &F,
// If the NVVM IR has some of reqntid* specified, then output
// the reqntid directive, and set the unspecified ones to 1.
// If none of Reqntid* is specified, don't output reqnti
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/127736
>From fd8f342fa2b65f7604955c88e2b73e758dc17134 Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Wed, 19 Feb 2025 02:26:23 +
Subject: [PATCH 1/2] [NVPTX] Convert vector function nvvm.annotations to
attr
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/127736
>From fd8f342fa2b65f7604955c88e2b73e758dc17134 Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Wed, 19 Feb 2025 02:26:23 +
Subject: [PATCH] [NVPTX] Convert vector function nvvm.annotations to
attribut
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/127736
>From bae09a6c197306efce76080921843f2b67a6333c Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Wed, 19 Feb 2025 02:26:23 +
Subject: [PATCH] [NVPTX] Convert vector function nvvm.annotations to
attribut
https://github.com/AlexMaclean closed
https://github.com/llvm/llvm-project/pull/125908
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@@ -227,14 +228,14 @@ class NVVMDialectLLVMIRTranslationInterface
} else if (attribute.getName() ==
AlexMaclean wrote:
Yes, I plan to replace all !nvvm.annotations with attributes. This change is
already fairly large and I would prefer to avoid a single mon
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/125908
>From cb6ac07e72cc1361343470842793cf9bc4995a19 Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Wed, 5 Feb 2025 18:46:03 +
Subject: [PATCH 1/2] [NVPTX] Convert scalar function nvvm.annotations to
attri
@@ -179,6 +179,13 @@ static bool argHasNVVMAnnotation(const Value &Val,
return false;
}
+static std::optional getFnAttrParsedInt(const Function &F,
+ StringRef Attr) {
+ return F.hasFnAttribute(Attr)
+ ? std::opti
@@ -179,6 +179,13 @@ static bool argHasNVVMAnnotation(const Value &Val,
return false;
}
+static std::optional getFnAttrParsedIntOrNull(const Function &F,
+StringRef Attr) {
+ if (F.hasFnAttribute(Attr))
+return F.g
@@ -179,6 +179,13 @@ static bool argHasNVVMAnnotation(const Value &Val,
return false;
}
+static std::optional getFnAttrParsedIntOrNull(const Function &F,
AlexMaclean wrote:
Removed
https://github.com/llvm/llvm-project/pull/125908
__
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/125908
>From 12bdf8bfa72b10d1e8ccc305cd57c337f2799e52 Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Wed, 5 Feb 2025 18:46:03 +
Subject: [PATCH 1/2] [NVPTX] Convert scalar function nvvm.annotations to
attri
https://github.com/AlexMaclean updated
https://github.com/llvm/llvm-project/pull/125908
>From d66d8adac5cf32f7f9f5878799c0167d39f41df7 Mon Sep 17 00:00:00 2001
From: Alex Maclean
Date: Wed, 5 Feb 2025 18:46:03 +
Subject: [PATCH] [NVPTX] Convert scalar function nvvm.annotations to
attribute
https://github.com/AlexMaclean created
https://github.com/llvm/llvm-project/pull/125908
Replace some more nvvm.annotations with function attributes, auto-upgrading the
annotations as needed. These new attributes will be more idiomatic and
compile-time efficient than the annotations.
- !"maxc
https://github.com/AlexMaclean closed
https://github.com/llvm/llvm-project/pull/122320
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AlexMaclean wrote:
@jdoerfert / @arsenm ping for review when you have a moment
https://github.com/llvm/llvm-project/pull/122320
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@@ -10,8 +10,14 @@
// CHECK-NEXT:[[TMP0:%.*]] = load ptr, ptr [[RET_ADDR]], align 8
// CHECK-NEXT:store i32 1, ptr [[TMP0]], align 4
// CHECK-NEXT:ret void
+//
__attribute__((nvptx_kernel)) void foo(int *ret) {
*ret = 1;
}
-// CHECK: !0 = !{ptr @foo, !"kernel
AlexMaclean wrote:
@Artem-B ping for review
https://github.com/llvm/llvm-project/pull/120806
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AlexMaclean wrote:
> In MLIR, we also have other NVVM metadata such as `reqntid` and `maxntid`,
> among others. What is the plan for these? Will they remain as metadata, or
> will they be expressed differently?
Eventually, I hope to migrate all !nvvm.annotations, including `reqntid` and
`maxn
@@ -556,19 +556,16 @@ llvm.func @kernel_func() attributes {nvvm.kernel} {
llvm.return
}
-// CHECK: !nvvm.annotations =
-// CHECK-NOT: {ptr @nvvm_special_regs, !"kernel", i32 1}
-// CHECK: {ptr @kernel_func, !"kernel", i32 1}
+// CHECK: ptx_kernel void @kernel_func
--
https://github.com/AlexMaclean edited
https://github.com/llvm/llvm-project/pull/120806
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@@ -1270,77 +1270,21 @@ exit:
; MODULE: attributes #[[ATTR1:[0-9]+]] = { convergent nocallback nounwind }
; MODULE: attributes #[[ATTR2:[0-9]+]] = { convergent nocallback nofree
nounwind willreturn }
; MODULE: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind
https://github.com/AlexMaclean edited
https://github.com/llvm/llvm-project/pull/120806
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https://github.com/AlexMaclean ready_for_review
https://github.com/llvm/llvm-project/pull/120806
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https://github.com/AlexMaclean edited
https://github.com/llvm/llvm-project/pull/120806
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@@ -1270,77 +1270,21 @@ exit:
; MODULE: attributes #[[ATTR1:[0-9]+]] = { convergent nocallback nounwind }
; MODULE: attributes #[[ATTR2:[0-9]+]] = { convergent nocallback nofree
nounwind willreturn }
; MODULE: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind
@@ -1270,77 +1270,21 @@ exit:
; MODULE: attributes #[[ATTR1:[0-9]+]] = { convergent nocallback nounwind }
; MODULE: attributes #[[ATTR2:[0-9]+]] = { convergent nocallback nofree
nounwind willreturn }
; MODULE: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind
https://github.com/AlexMaclean edited
https://github.com/llvm/llvm-project/pull/119261
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https://github.com/AlexMaclean edited
https://github.com/llvm/llvm-project/pull/119261
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@@ -324,14 +326,15 @@ MaybeAlign getAlign(const Function &F, unsigned Index) {
F.getAttributes().getAttributes(Index).getStackAlignment())
return StackAlign;
- // If that is missing, check the legacy nvvm metadata
- std::vector Vs;
- bool retval = findAllNVVMA
@@ -10,7 +10,7 @@
extern "C"
__device__ void device_function() {}
-// CHECK-LABEL: define{{.*}} void @global_function
+// CHECK: define{{.*}} void @global_function{{.*}} #[[ATTR0:[0-9]+]]
AlexMaclean wrote:
Fixed
https://github.com/llvm/llvm-project/pull/119
@@ -324,14 +326,17 @@ MaybeAlign getAlign(const Function &F, unsigned Index) {
F.getAttributes().getAttributes(Index).getStackAlignment())
return StackAlign;
- // If that is missing, check the legacy nvvm metadata
- std::vector Vs;
- bool retval = findAllNVVMA
@@ -5911,31 +5911,21 @@ bool llvm::omp::isOpenMPKernel(Function &Fn) {
KernelSet llvm::omp::getDeviceKernels(Module &M) {
// TODO: Create a more cross-platform way of determining device kernels.
- NamedMDNode *MD = M.getNamedMetadata("nvvm.annotations");
KernelSet Kernel
@@ -5022,6 +5022,69 @@ bool llvm::UpgradeDebugInfo(Module &M) {
return Modified;
}
+bool static upgradeSingleNVVMAnnotation(GlobalValue *GV, StringRef K,
+const Metadata *V) {
+ if (K == "kernel") {
+assert(mdconst::extract(V)->ge
@@ -5022,6 +5022,69 @@ bool llvm::UpgradeDebugInfo(Module &M) {
return Modified;
}
+bool static upgradeSingleNVVMAnnotation(GlobalValue *GV, StringRef K,
+const Metadata *V) {
+ if (K == "kernel") {
+assert(mdconst::extract(V)->ge
@@ -5022,6 +5022,69 @@ bool llvm::UpgradeDebugInfo(Module &M) {
return Modified;
}
+bool static upgradeSingleNVVMAnnotation(GlobalValue *GV, StringRef K,
+const Metadata *V) {
+ if (K == "kernel") {
+assert(mdconst::extract(V)->ge
@@ -5022,6 +5022,69 @@ bool llvm::UpgradeDebugInfo(Module &M) {
return Modified;
}
+bool static upgradeSingleNVVMAnnotation(GlobalValue *GV, StringRef K,
+const Metadata *V) {
+ if (K == "kernel") {
+assert(mdconst::extract(V)->ge
@@ -1270,77 +1270,21 @@ exit:
; MODULE: attributes #[[ATTR1:[0-9]+]] = { convergent nocallback nounwind }
; MODULE: attributes #[[ATTR2:[0-9]+]] = { convergent nocallback nofree
nounwind willreturn }
; MODULE: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind
https://github.com/AlexMaclean edited
https://github.com/llvm/llvm-project/pull/119261
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