================
@@ -2314,6 +2317,12 @@ static Value *upgradeNVVMIntrinsicCall(StringRef Name,
CallBase *CI,
Value *Val = CI->getArgOperand(1);
Rep = Builder.CreateAtomicRMW(AtomicRMWInst::FAdd, Ptr, Val, MaybeAlign(),
AtomicOrdering::SequentiallyConsistent);
+ } else if (Name.consume_front("atomic.load.") && Name.consume_back(".32")) {
+ Value *Ptr = CI->getArgOperand(0);
+ Value *Val = CI->getArgOperand(1);
+ auto Op = Name == "inc" ? AtomicRMWInst::UIncWrap :
AtomicRMWInst::UDecWrap;
+ Rep = Builder.CreateAtomicRMW(Op, Ptr, Val, MaybeAlign(),
+ AtomicOrdering::SequentiallyConsistent);
----------------
AlexMaclean wrote:
Yea, I do wonder about this as well. This is consistent with how the rest of
the `atomicrmw` instructions are lowered, but I'm not sure it's correct. We're
lowering seq_cst atomicrmw without a syncscope to the PTX atom instruction
which has implied `.relaxed` ordering and `.gpu` scope.
https://github.com/llvm/llvm-project/pull/134111
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