[Bug binutils/27309] readelf --debug-dump=info --wide output changes in 2.36

https://sourceware.org/bugzilla/show_bug.cgi?id=27309 Martin Liska changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRMED

[Bug ld/27433] New: RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 Bug ID: 27433 Summary: RISC-V linker might lose relax opportunities since "again" doesn't work as expected Product: binutils Version: unspecified Status: NEW

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 --- Comment #1 from Nelson Chu --- Created attachment 13231 --> https://sourceware.org/bugzilla/attachment.cgi?id=13231&action=edit proposed solution -- You are receiving this mail because: You are on the CC list for the bug.

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 Nelson Chu changed: What|Removed |Added Target||riscv*-*-* -- You are receiving this ma

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 --- Comment #2 from Nelson Chu --- The attached is the proposed solution. We use a new boolean "restart_relax" to determine if we need to re-run the whole relax passes again from 0 to 2. Once we have deleted the code between relax pass 0 to

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 Nelson Chu changed: What|Removed |Added Attachment #13231|0 |1 is obsolete|

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 --- Comment #3 from Nelson Chu --- Created attachment 13232 --> https://sourceware.org/bugzilla/attachment.cgi?id=13232&action=edit proposed solution v2 Fixed the conflicts since the v1 patch is too old. After applying this patch, the "cal

[Bug binutils/27309] readelf --debug-dump=info --wide output changes in 2.36

https://sourceware.org/bugzilla/show_bug.cgi?id=27309 --- Comment #6 from Dmitry V. Levin --- Meanwhile, people started reporting that strace 5.11 does not build: https://lists.strace.io/pipermail/strace-devel/2021-February/010406.html I'll be redirecting them to this bug report. -- You are re

[Bug binutils/27309] readelf --debug-dump=info --wide output changes in 2.36

https://sourceware.org/bugzilla/show_bug.cgi?id=27309 Dmitry V. Levin changed: What|Removed |Added Resolution|INVALID |WONTFIX -- You are receiving this

[Bug ld/27432] erroneous symbol offsets taken with __ImageBase relocation using Microsoft COFF .OBJ linked to

https://sourceware.org/bugzilla/show_bug.cgi?id=27432 H.J. Lu changed: What|Removed |Added Assignee|unassigned at sourceware dot org |hjl.tools at gmail dot com Last r

[Bug ld/27432] erroneous symbol offsets taken with __ImageBase relocation using Microsoft COFF .OBJ linked to

https://sourceware.org/bugzilla/show_bug.cgi?id=27432 H.J. Lu changed: What|Removed |Added Attachment #13233|0 |1 is obsolete|

[Bug gas/27436] New: RISC-V inconsistent handling of rv32 shift with count > 32

https://sourceware.org/bugzilla/show_bug.cgi?id=27436 Bug ID: 27436 Summary: RISC-V inconsistent handling of rv32 shift with count > 32 Product: binutils Version: unspecified Status: NEW Severity: normal

[Bug gas/27436] RISC-V inconsistent handling of rv32 shift with count > 32

https://sourceware.org/bugzilla/show_bug.cgi?id=27436 Jim Wilson changed: What|Removed |Added Target||riscv*-*-* -- You are receiving this ma

[Bug gas/27436] RISC-V inconsistent handling of rv32 shift with count > 31

https://sourceware.org/bugzilla/show_bug.cgi?id=27436 Jim Wilson changed: What|Removed |Added Summary|RISC-V inconsistent |RISC-V inconsistent |h

[Bug gas/27436] RISC-V inconsistent handling of rv32 shift with count > 31

https://sourceware.org/bugzilla/show_bug.cgi?id=27436 --- Comment #1 from Jim Wilson --- that should be > 31 not > 32 -- You are receiving this mail because: You are on the CC list for the bug.

[Bug binutils/27158] RISC-V port still has UJ instruction type references

https://sourceware.org/bugzilla/show_bug.cgi?id=27158 --- Comment #2 from cvs-commit at gcc dot gnu.org --- The master branch has been updated by Nelson Chu : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5a9f5403c75c8ae1f4935a9a0904949f52d9e3aa commit 5a9f5403c75c8ae1f4935a9a09049