https://sourceware.org/bugzilla/show_bug.cgi?id=27436
Bug ID: 27436
Summary: RISC-V inconsistent handling of rv32 shift with count
> 32
Product: binutils
Version: unspecified
Status: NEW
Severity: normal
Priority: P2
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: wilson at gcc dot gnu.org
Target Milestone: ---
rohan:2255$ cat tmp.s
slli a0,a0,63
rohan:2256$ riscv32-unknown-elf-as -march=rv64g tmp.s
rohan:2257$ riscv32-unknown-elf-as -march=rv64gc tmp.s
rohan:2258$ riscv32-unknown-elf-as -march=rv32g tmp.s
tmp.s: Assembler messages:
tmp.s:1: Error: Improper shift amount (63)
rohan:2259$ riscv32-unknown-elf-as -march=rv32gc tmp.s
rohan:2260$ riscv32-unknown-elf-objdump -dr -Mno-aliases a.out
a.out: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: 157e c.slli a0,0x3f
rohan:2261$
An rv32 compressed shift with count greater than 32 is specified as NSE
(non-standard extension). So it isn't a valid shift, but rather an encoding
that can be used by any vendor for a non-standard extension. We allow hints to
be used for extensions, but those are encoded as nops. This is not a nop. I
think we should disallow this, and force someone who wants to use this encoding
for a NSE to either use .insn or use a local binutils patch.
If we disallow it, the fix is to make C> work the same as >, i.e. use xlen
instead of 64 when testing whether the shift count is valid.
--
You are receiving this mail because:
You are on the CC list for the bug.
