https://sourceware.org/bugzilla/show_bug.cgi?id=32462
--- Comment #3 from Michael Clark ---
a final check lifting the associated clauses from the Intel SDM:
- 'XCHG a,r 90+r' is well-specified and there is no note that
the instruction excludes EAX from the opcode reg field.
- Intel SDM docs f
https://sourceware.org/bugzilla/show_bug.cgi?id=32462
--- Comment #2 from Michael Clark ---
someone on LLVM discourse said on Intel, f3 90 is pause,
independent of REX.B. On AMD, it is pause only if REX.B
is clear. the behavior of rep xchg is unspecified.
so it seems that QEMU code snippet is co
https://sourceware.org/bugzilla/show_bug.cgi?id=32462
--- Comment #1 from Michael Clark ---
QEMU ignores REP prefix and treats REX.B PAUSE as 'xchg eax, r8d':
/* If REX_B is set, then this is xchg eax, r8d, not a nop. */
if (REX_B(s)) {
goto do_xchg_reg_eax;
}
if (prefix
