https://sourceware.org/bugzilla/show_bug.cgi?id=32462
--- Comment #3 from Michael Clark <michaeljclark at mac dot com> --- a final check lifting the associated clauses from the Intel SDM: - 'XCHG a,r 90+r' is well-specified and there is no note that the instruction excludes EAX from the opcode reg field. - Intel SDM docs for REX Prefixes state that "REX.B either modifies the base in the ModR/M r/m field or SIB base field; or it modifies the opcode reg field used for accessing GPRs." - Intel SDM docs for NOP state "The one-byte NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction." so far this all seems well specified, but it gets looser: - Intel SDM docs for PAUSE state "The PAUSE instruction provides a hint to the processor that the code sequence is a spin-wait loop." but it doesn't explicitly mention that the encoding is an alias mnemonic for "REP XCHG eax,eax" aka "REP NOP". and finally: - Intel SDM docs for REP state that "The F3H prefix is defined for the following instructions and undefined for the rest: F3H as REP/REPE/REPZ for string and input/output instruction. F3H is a mandatory prefix for POPCNT, LZCNT, and ADOX." so while it may remain ambiguous what the defined behavior of the instruction is, the disassembly seems clear based on PAUSE being REP NOP. PAUSE should also honor the same exclusion for REX.B as NOP does. the alias is overbroad. thus f3 41 90 should disassemble as 'REP XCHG r8d,eax' this is irrespective of any discussion about the instruction's behavioral semantics because the disassembly seems clear despite a potential silicon behavioral inconsistency due to erroneous and overbroad matching of the PAUSE hint. so I think the disassembly should read 'REP XCHG r8d,eax' because I believe the documentation supports this reading. although 'REP (bad) XCHG r8d,eax' may also be okay. -- You are receiving this mail because: You are on the CC list for the bug.
