Re: [Mesa-dev] docs: consistent language
On Mon, 2021-03-15 at 13:44 +0100, Erik Faye-Lund wrote: > TLDR; I'm proposing to standardize on US English in our public-facing > documentation. +1 J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: (rusticl) OpenCL command cling is not detecting GPU in raspberry pi 5
On Mon, 2025-01-13 at 16:24 +, Victor Labian Carro wrote: > Hello, > > I followed the instructions in > https://docs.mesa3d.org/rusticl.html#rusticl to install OpenCL in > Raspberry Pi 5. However, clinfo command is not showing any devices. > Can anyone help with suggestions? > What is showing clinfo? For reference, I've tried locally and it seems to work fine. Following the steps mentioned in the link, I've used the following options in meson `-Dgallium-drivers=vc4,v3d -Dvulkan-drivers=broadcom -Dgallium-rusticl- enable-drivers=v3d -Dgallium-rusticl=true -Dllvm=enabled - Drust_std=2021` I've also exported `RUSTICL_ENABLED=v3d` and ensured `libclc-15` is installed. With all above, `clinfo` exposes the V3D 7.1.7.0 device Cheers. J.A.
Re: [Mesa-dev] [ANNOUNCE] mesa 18.0.4
El 18 may. 2018 16:04, Andreas Boll escribió:2018-05-17 20:48 GMT+02:00 Juan A. Suarez Romero : > Mesa 18.0.4 is now available. > > In this release we have: > > r600 driver gets a fix for constant buffer boounds, which fixes rendering bugs > in Trine and Witcher 1. > > Several fixes for RADV driver: fixes around alpha channel in Pre-Vega, fix in > multisample image copies, and fixes around multilayer images in compute path. > > For the case of ANV/i965 drivers, also a couple of fixes, all of them around > ISP. On top, there are a couple of fixes relative to code emission around 16-bit > integers, and a a fix for a leak in blorp for Gen4 and Gen5. > > Speaking of leaks, there are also fixes for winsys/radeon/amdgpu and > pipe-loader.gets a couple of patches to fix a couple of leaks. > > SPIR-V part gets a patch to apply OriginUpperLeft to FragCoord. > > Mesa core gets a couple of patches to fix error handling in > get_framebuffer_parameteriv, and to add missing support for > glFogiv(GL_FOG_DISTANCE_MODE_NV). > > > Bas Nieuwenhuizen (3): > radv: Translate logic ops. > radv: Fix up 2_10_10_10 alpha sign. > radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega. > > Dave Airlie (3): > r600: fix constant buffer bounds. > radv: resolve all layers in compute resolve path. > radv: use compute path for multi-layer images. > > Deepak Rawat (1): > egl/x11: Send invalidate to driver on copy_region path in swap_buffer > > Ian Romanick (1): > mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV) > > Jan Vesely (8): > clover: Add explicit virtual destructor to argument class > eg/compute: Drop reference on code_bo in destructor. > r600: Cleanup constant buffers on context destruction > eg/compute: Drop reference to kernel_param bo in destructor > pipe-loader: Free driver_name in error path > gallium/auxiliary: Add helper function to count the number of entries in hash table > winsys/radeon: Destroy fd_hash table when the last winsys is removed. > winsys/amdgpu: Destroy dev_hash table when the last winsys is removed. > > Jason Ekstrand (1): > i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL > > Jose Maria Casanova Crespo (2): > intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediate > intel/compiler: fix brw_imm_w for negative 16-bit integers > > Juan A. Suarez Romero (8): > docs: add sha256 checksums for 18.0.3 > cherry-ignore: add explicit 18.1 only nominations > cherry-ignore: glsl: change ast_type_qualifier bitset size to work around GCC 5.4 bug > cherry-ignore: mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs > cherry-ignore: mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to TYPE_INT > cherry-ignore: radv/resolve: do fmask decompress on all layers. > Update version to 18.0.4 > docs: add release notes for 18.0.4 > > Kai Wasserbäch (1): > opencl: autotools: Fix linking order for OpenCL target > > Kenneth Graunke (1): > i965: Don't leak blorp on Gen4-5. > > Lionel Landwerlin (2): > i965: require pixel scoreboard stall prior to ISP disable > anv: emit pixel scoreboard stall before ISP disable > > Matthew Nicholls (1): > radv: fix multisample image copies > > Neil Roberts (1): > spirv: Apply OriginUpperLeft to FragCoord > > Rhys Perry (1): > mesa: fix error handling in get_framebuffer_parameteriv > > Ross Burton (1): > src/intel/Makefile.vulkan.am: add missing MKDIR_GEN > > git tag: mesa-18.0.4 > > https://mesa.freedesktop.org/archive/mesa-18.0.4.tar.gz > MD5: d47abf2d1b272b4ab936a7addf34cd00 mesa-18.0.4.tar.gz > SHA1: c58887e20ed7cdd6decdc552294da8db485d5e32 mesa-18.0.4.tar.gz > SHA256: d1dc3469faccdd73439479426952d71a9e8f684e8d03b6687063c12b13430801 mesa-18.0.4.tar.gz > SHA512: 7339d1e552475792a5f8e9f5374080e16774af50fd2cb9e960b987b0c6bdf14941b0927d5c882f473e5659d51bfb974cd0023d5f990fb95c3d0015dd7a342922 mesa-18.0.4.tar.gz > PGP: https://mesa.freedesktop.org/archive/mesa-18.0.4.tar.gz.sig > > https://mesa.freedesktop.org/archive/mesa-18.0.4.tar.xz > MD5: ef525adaff7f31bedd4c5134bc313da9 mesa-18.0.4.tar.xz > SHA1: 4bbee07d8eb42625f215f49d39a657fabdc2f29d mesa-18.0.4.tar.xz > SHA256: 1f3bcfe7cef0a5c20dae2b41df5d7e0a985e06be0183fa4d43b6068fcba2920f mesa-18.0.4.tar.xz > SHA512: f9a14be46c209661ceb318add1611481445d13b47e95c7a5d2a5e5ecfdd5d2c3fa9c2b16b30035bbb8d61ccc7cb65bfa6698ac8b040273e5ab045a951a67752c me
[Mesa-dev] [PATCH] nir/glsl_to_nir: use _mesa_fls() to compute num_textures
Replace the current loop by a direct call to _mesa_fls() function. It also fixes an implicit bug in the current code where num_textures seems to be one value less than it should be when sh->Program->SamplersUsed > 0. For instance, num_textures is 0 instead of 1 when sh->Program->SamplersUsed is 1. Signed-off-by: Juan A. Suarez Romero --- src/glsl/nir/glsl_to_nir.cpp | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index 57aba5b..5c3fcd1 100644 --- a/src/glsl/nir/glsl_to_nir.cpp +++ b/src/glsl/nir/glsl_to_nir.cpp @@ -30,6 +30,7 @@ #include "ir_visitor.h" #include "ir_hierarchical_visitor.h" #include "ir.h" +#include "main/imports.h" /* * pass to lower GLSL IR to NIR @@ -144,16 +145,10 @@ glsl_to_nir(const struct gl_shader_program *shader_prog, nir_lower_outputs_to_temporaries(shader); - /* TODO: Use _mesa_fls instead */ - unsigned num_textures = 0; - for (unsigned i = 0; i < 8 * sizeof(sh->Program->SamplersUsed); i++) - if (sh->Program->SamplersUsed & (1 << i)) - num_textures = i; - shader->info.name = ralloc_asprintf(shader, "GLSL%d", shader_prog->Name); if (shader_prog->Label) shader->info.label = ralloc_strdup(shader, shader_prog->Label); - shader->info.num_textures = num_textures; + shader->info.num_textures = _mesa_fls(sh->Program->SamplersUsed); shader->info.num_ubos = sh->NumUniformBlocks; shader->info.num_abos = shader_prog->NumAtomicBuffers; shader->info.num_ssbos = sh->NumShaderStorageBlocks; -- 2.4.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] nir/glsl_to_nir: use _mesa_fls() to compute num_textures
On Fri, 2015-11-06 at 12:21 -0800, Matt Turner wrote: > On Fri, Nov 6, 2015 at 8:27 AM, Juan A. Suarez Romero > Looks good to me, and we use _mesa_fls elsewhere to do this same > calculation. > > Reviewed-by: Matt Turner > > Jason, was there some reason we weren't doing this? I'm confused why > we would have had a one-line comment and a 4-line loop when the all > we > needed to do was call one functon? Anything new on this? Can we commit it? J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] nir/glsl_to_nir: use _mesa_fls() to compute num_textures
On Fri, 2015-11-13 at 07:37 -0800, Jason Ekstrand wrote: > I didn't want to pull a non-inline mesa function into NIR and add a > link dependency and I was too lazy to move it into util. But at this moment _mesa_fls() is an inline function. So I guess it is safe to push it, isn't it? J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] anv/pipeline: set ThreadDispatchEnable conditionally
Set 3DSTATE_WM/ThreadDispatchEnable bit on/off based on the same
conditions as used in the GL version.
Signed-off-by: Juan A. Suarez Romero
---
src/intel/vulkan/genX_pipeline.c | 49 +---
1 file changed, 26 insertions(+), 23 deletions(-)
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index e8cbd3c..55d1e55 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1174,6 +1174,26 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
}
}
+static inline bool
+has_color_buffer_write_enabled(const struct anv_pipeline *pipeline)
+{
+ const struct anv_shader_bin *shader_bin =
+ pipeline->shaders[MESA_SHADER_FRAGMENT];
+ if (!shader_bin)
+ return false;
+
+ const struct anv_pipeline_bind_map *bind_map = &shader_bin->bind_map;
+ for (int i = 0; i < bind_map->surface_count; i++) {
+ if (bind_map->surface_to_descriptor[i].set !=
+ ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS)
+ continue;
+ if (bind_map->surface_to_descriptor[i].index != UINT8_MAX)
+ return true;
+ }
+
+ return false;
+}
+
static void
emit_3dstate_wm(struct anv_pipeline *pipeline, struct anv_subpass *subpass,
const VkPipelineMultisampleStateCreateInfo *multisample)
@@ -1202,9 +1222,6 @@ emit_3dstate_wm(struct anv_pipeline *pipeline, struct
anv_subpass *subpass,
wm_prog_data->barycentric_interp_modes;
#if GEN_GEN < 8
- /* FIXME: This needs a lot more work, cf gen7 upload_wm_state(). */
- wm.ThreadDispatchEnable = true;
-
wm.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
wm.PixelShaderUsesSourceDepth= wm_prog_data->uses_src_depth;
wm.PixelShaderUsesSourceW= wm_prog_data->uses_src_w;
@@ -1220,6 +1237,12 @@ emit_3dstate_wm(struct anv_pipeline *pipeline, struct
anv_subpass *subpass,
wm.PixelShaderKillsPixel = subpass->has_ds_self_dep ||
wm_prog_data->uses_kill;
+ if (wm.PixelShaderComputedDepthMode != PSCDEPTH_OFF ||
+ wm_prog_data->has_side_effects ||
+ wm.PixelShaderKillsPixel ||
+ has_color_buffer_write_enabled(pipeline))
+wm.ThreadDispatchEnable = true;
+
if (samples > 1) {
wm.MultisampleRasterizationMode = MSRASTMODE_ON_PATTERN;
if (wm_prog_data->persample_dispatch) {
@@ -1338,26 +1361,6 @@ emit_3dstate_ps(struct anv_pipeline *pipeline,
}
}
-static inline bool
-has_color_buffer_write_enabled(const struct anv_pipeline *pipeline)
-{
- const struct anv_shader_bin *shader_bin =
- pipeline->shaders[MESA_SHADER_FRAGMENT];
- if (!shader_bin)
- return false;
-
- const struct anv_pipeline_bind_map *bind_map = &shader_bin->bind_map;
- for (int i = 0; i < bind_map->surface_count; i++) {
- if (bind_map->surface_to_descriptor[i].set !=
- ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS)
- continue;
- if (bind_map->surface_to_descriptor[i].index != UINT8_MAX)
- return true;
- }
-
- return false;
-}
-
#if GEN_GEN >= 8
static void
emit_3dstate_ps_extra(struct anv_pipeline *pipeline,
--
2.9.3
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[Mesa-dev] [PATCH 0/2] Fixes for B4G4R4A4 vulkan tests in Haswell
Pre-Broadwell devices does not support natively Vulkan B4G4R4A4, so we just fallback to another format using a different swizzle. But this is crashing a couple of tests in Vulkan CTS due the following: - We assert that alpha component will map to "one" or "alpha". But our new swizzle maps it to "blue". So let's consider this mapping (patch 01/02). - In ISL, we check that RENDER_SURFACE_STATE' channel selections for red, green and blue can only be a permutation of this channels (RGB, RBG, GRB, GBR, BRG, BGR). But our new swizzle is mapping "blue" to "alpha", so we have GRA. According to PRM, seems this check is not required for Haswell (at least, didn't found it in Haswell PRM). So let's run it for gen>=8 (patch 02/02). With both patches, we fix the following tests in Haswell: - dEQP-VK.api.image_clearing.clear_color_image.1d_b4g4r4a4_unorm_pack16 - dEQP-VK.api.image_clearing.clear_color_image.2d_b4g4r4a4_unorm_pack16 - dEQP-VK.api.image_clearing.clear_color_image.3d_b4g4r4a4_unorm_pack16 *** BLURB HERE *** Juan A. Suarez Romero (2): anv: allow blue in alpha component in swizzle for render isl: apply RENDER_SURFACE_STATE::Shader Channel assertions to gen>=8 src/intel/isl/isl_surface_state.c | 5 - src/intel/vulkan/anv_private.h| 14 ++ 2 files changed, 14 insertions(+), 5 deletions(-) -- 2.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] anv: allow blue in alpha component in swizzle for render
In pre-Broadwell devices, as B4G4R4A4 is not supported natively, we
workaround it by using a format with a more complex swizzle, that uses
blue in alpha component.
Signed-off-by: Juan A. Suarez Romero
---
src/intel/vulkan/anv_private.h | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 51e85c7..e9bf13c 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1559,13 +1559,19 @@ static inline struct isl_swizzle
anv_swizzle_for_render(struct isl_swizzle swizzle)
{
/* Sometimes the swizzle will have alpha map to one. We do this to fake
-* RGB as RGBA for texturing
+* RGB as RGBA for texturing.
+*
+* It can have also alpha to blue. This happens to workaround support for
+* B4G4R4A4 in gen < 8 devices, as this not supported natively.
*/
assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
- swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
+ swizzle.a == ISL_CHANNEL_SELECT_ALPHA ||
+ swizzle.a == ISL_CHANNEL_SELECT_BLUE);
- /* But it doesn't matter what we render to that channel */
- swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
+ /* But it doesn't matter what we render to that channel, except for the
+* B4G4R4A4 workaround */
+ if (swizzle.a == ISL_CHANNEL_SELECT_ONE)
+ swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
return swizzle;
}
--
2.9.3
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[Mesa-dev] [PATCH 2/2] isl: apply RENDER_SURFACE_STATE::Shader Channel assertions to gen>=8
We are applying several assertions to RENDER_SURFACE_STATE's shader
channels selection to gen>=8 and haswell devices.
But this assertions are not listed in Haswell PRMs.
Signed-off-by: Juan A. Suarez Romero
---
src/intel/isl/isl_surface_state.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_state.c
index 29ec289..fd683e4 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -452,7 +452,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev,
void *state,
#endif
#endif
-#if (GEN_GEN >= 8 || GEN_IS_HASWELL)
+#if GEN_GEN >= 8
if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
/* From the Sky Lake PRM Vol. 2d,
* RENDER_SURFACE_STATE::Shader Channel Select Red
@@ -485,6 +485,9 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev,
void *state,
*/
assert(info->view->swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
}
+#endif
+
+#if (GEN_GEN >= 8 || GEN_IS_HASWELL)
s.ShaderChannelSelectRed = info->view->swizzle.r;
s.ShaderChannelSelectGreen = info->view->swizzle.g;
s.ShaderChannelSelectBlue = info->view->swizzle.b;
--
2.9.3
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Re: [Mesa-dev] [PATCH 1/2] anv: allow blue in alpha component in swizzle for render
On Wed, 2017-02-08 at 09:27 -0800, Nanley Chery wrote:
> On Wed, Feb 08, 2017 at 01:31:54PM +0100, Juan A. Suarez Romero wrote:
> > In pre-Broadwell devices, as B4G4R4A4 is not supported natively, we
> > workaround it by using a format with a more complex swizzle, that uses
> > blue in alpha component.
> >
> > Signed-off-by: Juan A. Suarez Romero
> > ---
> > src/intel/vulkan/anv_private.h | 14 ++
> > 1 file changed, 10 insertions(+), 4 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
> > index 51e85c7..e9bf13c 100644
> > --- a/src/intel/vulkan/anv_private.h
> > +++ b/src/intel/vulkan/anv_private.h
> > @@ -1559,13 +1559,19 @@ static inline struct isl_swizzle
> > anv_swizzle_for_render(struct isl_swizzle swizzle)
> > {
> > /* Sometimes the swizzle will have alpha map to one. We do this to fake
> > -* RGB as RGBA for texturing
> > +* RGB as RGBA for texturing.
> > +*
> > +* It can have also alpha to blue. This happens to workaround support
> > for
> > +* B4G4R4A4 in gen < 8 devices, as this not supported natively.
> > */
> > assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
> > - swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
> > + swizzle.a == ISL_CHANNEL_SELECT_ALPHA ||
> > + swizzle.a == ISL_CHANNEL_SELECT_BLUE);
> >
> > - /* But it doesn't matter what we render to that channel */
> > - swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
> > + /* But it doesn't matter what we render to that channel, except for the
> > +* B4G4R4A4 workaround */
>
> I'm finding this commit message a tad confusing. Would you agree that
> replacing it with the following would be better?
>
> For RGB formats that have alpha mapped to one, we must remap the channel
> to alpha to satisfy the BDW+ surface state restriction.
>
Uhm... I don't think so. That is what the code was doing so far.
The commit just takes in account that alpha can be mapped to blue too.
And in this case, we keep the blue.
> Aside from the comment, this patch looks good to me.
>
> > + if (swizzle.a == ISL_CHANNEL_SELECT_ONE)
> > + swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
> >
> > return swizzle;
> > }
> > --
> > 2.9.3
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
>
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Re: [Mesa-dev] [PATCH 1/2] anv: allow blue in alpha component in swizzle for render
On Wed, 2017-02-08 at 10:53 -0800, Nanley Chery wrote:
> On Wed, Feb 08, 2017 at 06:42:44PM +0100, Juan A. Suarez Romero wrote:
> > On Wed, 2017-02-08 at 09:27 -0800, Nanley Chery wrote:
> > > On Wed, Feb 08, 2017 at 01:31:54PM +0100, Juan A. Suarez Romero wrote:
> > > > In pre-Broadwell devices, as B4G4R4A4 is not supported natively, we
> > > > workaround it by using a format with a more complex swizzle, that uses
> > > > blue in alpha component.
> > > >
> > > > Signed-off-by: Juan A. Suarez Romero
> > > > ---
> > > > src/intel/vulkan/anv_private.h | 14 ++
> > > > 1 file changed, 10 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/src/intel/vulkan/anv_private.h
> > > > b/src/intel/vulkan/anv_private.h
> > > > index 51e85c7..e9bf13c 100644
> > > > --- a/src/intel/vulkan/anv_private.h
> > > > +++ b/src/intel/vulkan/anv_private.h
> > > > @@ -1559,13 +1559,19 @@ static inline struct isl_swizzle
> > > > anv_swizzle_for_render(struct isl_swizzle swizzle)
> > > > {
> > > > /* Sometimes the swizzle will have alpha map to one. We do this to
> > > > fake
> > > > -* RGB as RGBA for texturing
> > > > +* RGB as RGBA for texturing.
> > > > +*
> > > > +* It can have also alpha to blue. This happens to workaround
> > > > support for
> > > > +* B4G4R4A4 in gen < 8 devices, as this not supported natively.
> > > > */
> > > > assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
> > > > - swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
> > > > + swizzle.a == ISL_CHANNEL_SELECT_ALPHA ||
> > > > + swizzle.a == ISL_CHANNEL_SELECT_BLUE);
> > > >
> > > > - /* But it doesn't matter what we render to that channel */
> > > > - swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
> > > > + /* But it doesn't matter what we render to that channel, except for
> > > > the
> > > > +* B4G4R4A4 workaround */
> > >
> > > I'm finding this commit message a tad confusing. Would you agree that
> > > replacing it with the following would be better?
> > >
> > > For RGB formats that have alpha mapped to one, we must remap the channel
> > > to alpha to satisfy the BDW+ surface state restriction.
> > >
> >
> > Uhm... I don't think so. That is what the code was doing so far.
> >
> > The commit just takes in account that alpha can be mapped to blue too.
> > And in this case, we keep the blue.
> >
>
> Oh, sorry, I meant code comment, not commit message. That would
> definitely not work as a commit message. Thoughts?
Yes, it works for me as code comment. Thanks!
With that change, can I consider you grant R-b?
J.A.
> >
> > > Aside from the comment, this patch looks good to me.
> > >
> > > > + if (swizzle.a == ISL_CHANNEL_SELECT_ONE)
> > > > + swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
> > > >
> > > > return swizzle;
> > > > }
> > > > --
> > > > 2.9.3
> > > >
> > > > ___
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> > > > mesa-dev@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > >
> > >
>
>
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Re: [Mesa-dev] [PATCH] intel/blorp: Swizzle clear colors on the CPU
On Wed, 2017-02-08 at 13:35 -0800, Jason Ekstrand wrote:
> This fixes the following Vulkan CTS tests on Haswell:
>
> - dEQP-VK.api.image_clearing.clear_color_image.1d_b4g4r4a4_unorm_pack16
> - dEQP-VK.api.image_clearing.clear_color_image.2d_b4g4r4a4_unorm_pack16
> - dEQP-VK.api.image_clearing.clear_color_image.3d_b4g4r4a4_unorm_pack16
> ---
I've tried, and it still crashes in assertion:
deqp-vk: anv_private.h:1565: anv_swizzle_for_render: Assertion
`swizzle.a == ISL_CHANNEL_SELECT_ONE || swizzle.a ==
ISL_CHANNEL_SELECT_ALPHA' failed.
It seems it still requires patch from https://lists.freedesktop.org/arc
hives/mesa-dev/2017-February/143480.html
There's a small typo also in a comment.
Other than that, it is:
Reviewed-by: Juan A. Suarez Romero .
BTW, I've also sent a couple of patches to fix these tests:
https://lists.freedesktop.org/archives/mesa-dev/2017-February/143479.ht
ml
Giving the above comment, I guess your preference is using patch 1/2
that I sent, and use this one you've sent instead of 2/2, right?
J.A.
> src/intel/blorp/blorp_clear.c | 45
> ++-
> 1 file changed, 27 insertions(+), 18 deletions(-)
>
> diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
> index 8ea22ac..e452713 100644
> --- a/src/intel/blorp/blorp_clear.c
> +++ b/src/intel/blorp/blorp_clear.c
> @@ -328,6 +328,23 @@ blorp_fast_clear(struct blorp_batch *batch,
> batch->blorp->exec(batch, ¶ms);
> }
>
> +static union isl_color_value
> +swizzle_color_value(union isl_color_value src, struct isl_swizzle swizzle)
> +{
> + union isl_color_value dst;
> +
> + assert((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4);
> + assert((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4);
> + assert((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4);
> + assert((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4);
> +
> + dst.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = src.u32[0];
> + dst.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = src.u32[1];
> + dst.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = src.u32[2];
> + dst.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = src.u32[3];
> +
> + return dst;
> +}
>
> void
> blorp_clear(struct blorp_batch *batch,
> @@ -346,6 +363,14 @@ blorp_clear(struct blorp_batch *batch,
> params.x1 = x1;
> params.y1 = y1;
>
> + /* Manually apply the clear destination swizzle. This way swizzled clears
> +* will work for swizzles which we can't normally use for rendering and it
> +* also ensures that they work on pre-Haswell hardware which can't swizlle
^^^
typo: swizzle
> +* at all.
> +*/
> + clear_color = swizzle_color_value(clear_color, swizzle);
> + swizzle = ISL_SWIZZLE_IDENTITY;
> +
> if (format == ISL_FORMAT_R9G9B9E5_SHAREDEXP) {
>clear_color.u32[0] = float3_to_rgb9e5(clear_color.f32);
>format = ISL_FORMAT_R32_UINT;
> @@ -353,24 +378,8 @@ blorp_clear(struct blorp_batch *batch,
>/* Broadwell and earlier cannot render to this format so we need to
> work
> * around it by swapping the colors around and using B4G4R4A4 instead.
> */
> -
> - /* First, we apply the swizzle. */
> - union isl_color_value old;
> - assert((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4);
> - assert((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4);
> - assert((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4);
> - assert((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4);
> - old.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = clear_color.u32[0];
> - old.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = clear_color.u32[1];
> - old.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = clear_color.u32[2];
> - old.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = clear_color.u32[3];
> - swizzle = ISL_SWIZZLE_IDENTITY;
> -
> - /* Now we re-order for the new format */
> - clear_color.u32[0] = old.u32[1];
> - clear_color.u32[1] = old.u32[2];
> - clear_color.u32[2] = old.u32[3];
> - clear_color.u32[3] = old.u32[0];
> + const struct isl_swizzle ARGB = ISL_SWIZZLE(ALPHA, RED, GREEN, BLUE);
> + clear_color = swizzle_color_value(clear_color, ARGB);
>format = ISL_FORMAT_B4G4R4A4_UNORM;
> }
>
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Re: [Mesa-dev] [PATCH 1/2] intel/blorp: Swizzle clear colors on the CPU
Reviewed-by: Juan A. Suarez Romero
On Thu, 2017-02-09 at 14:37 -0800, Jason Ekstrand wrote:
> It's trivial to swizzle clear colors on the CPU, easily deals with the
> hardware restrictions for render target swizzles, and makes swizzled
> clears work on all hardware as opposed to just HSW+.
> ---
> src/intel/blorp/blorp_clear.c | 48
> +++
> 1 file changed, 30 insertions(+), 18 deletions(-)
>
> diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
> index 8ea22ac..4d63bbe 100644
> --- a/src/intel/blorp/blorp_clear.c
> +++ b/src/intel/blorp/blorp_clear.c
> @@ -328,6 +328,26 @@ blorp_fast_clear(struct blorp_batch *batch,
> batch->blorp->exec(batch, ¶ms);
> }
>
> +static union isl_color_value
> +swizzle_color_value(union isl_color_value src, struct isl_swizzle swizzle)
> +{
> + union isl_color_value dst = { .u32 = { 0, } };
> +
> + /* We assign colors in ABGR order so that the first one will be taken in
> +* RGBA precedence order. According to the PRM docs for shader channel
> +* select, this matches Haswell hardware behavior.
> +*/
> + if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
> + dst.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = src.u32[3];
> + if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
> + dst.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = src.u32[2];
> + if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
> + dst.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = src.u32[1];
> + if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
> + dst.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = src.u32[0];
> +
> + return dst;
> +}
>
> void
> blorp_clear(struct blorp_batch *batch,
> @@ -346,6 +366,14 @@ blorp_clear(struct blorp_batch *batch,
> params.x1 = x1;
> params.y1 = y1;
>
> + /* Manually apply the clear destination swizzle. This way swizzled clears
> +* will work for swizzles which we can't normally use for rendering and it
> +* also ensures that they work on pre-Haswell hardware which can't swizlle
> +* at all.
> +*/
> + clear_color = swizzle_color_value(clear_color, swizzle);
> + swizzle = ISL_SWIZZLE_IDENTITY;
> +
> if (format == ISL_FORMAT_R9G9B9E5_SHAREDEXP) {
>clear_color.u32[0] = float3_to_rgb9e5(clear_color.f32);
>format = ISL_FORMAT_R32_UINT;
> @@ -353,24 +381,8 @@ blorp_clear(struct blorp_batch *batch,
>/* Broadwell and earlier cannot render to this format so we need to
> work
> * around it by swapping the colors around and using B4G4R4A4 instead.
> */
> -
> - /* First, we apply the swizzle. */
> - union isl_color_value old;
> - assert((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4);
> - assert((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4);
> - assert((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4);
> - assert((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4);
> - old.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = clear_color.u32[0];
> - old.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = clear_color.u32[1];
> - old.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = clear_color.u32[2];
> - old.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = clear_color.u32[3];
> - swizzle = ISL_SWIZZLE_IDENTITY;
> -
> - /* Now we re-order for the new format */
> - clear_color.u32[0] = old.u32[1];
> - clear_color.u32[1] = old.u32[2];
> - clear_color.u32[2] = old.u32[3];
> - clear_color.u32[3] = old.u32[0];
> + const struct isl_swizzle ARGB = ISL_SWIZZLE(ALPHA, RED, GREEN, BLUE);
> + clear_color = swizzle_color_value(clear_color, ARGB);
>format = ISL_FORMAT_B4G4R4A4_UNORM;
> }
>
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Re: [Mesa-dev] [PATCH 2/2] anv/blorp: Don't sanitize the swizzle for blorp_clear
On Thu, 2017-02-09 at 14:37 -0800, Jason Ekstrand wrote: > BLORP is now smart enough to handle any swizzle (even those that contain > ZERO or ONE) in a reasonable manner. Just let BLORP handle it. This > fixes the following Vulkan CTS tests on Haswell: > > - dEQP-VK.api.image_clearing.clear_color_image.1d_b4g4r4a4_unorm_pack16 > - dEQP-VK.api.image_clearing.clear_color_image.2d_b4g4r4a4_unorm_pack16 > - dEQP-VK.api.image_clearing.clear_color_image.3d_b4g4r4a4_unorm_pack16 > --- > src/intel/vulkan/anv_blorp.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c > index 759d2ae..4e7078b 100644 > --- a/src/intel/vulkan/anv_blorp.c > +++ b/src/intel/vulkan/anv_blorp.c > @@ -832,8 +832,7 @@ void anv_CmdClearColorImage( > } > > blorp_clear(&batch, &surf, > - src_format.isl_format, > - anv_swizzle_for_render(src_format.swizzle), > + src_format.isl_format, src_format.swizzle, > level, base_layer, layer_count, > 0, 0, level_width, level_height, > vk_to_isl_color(*pColor), color_write_disable); Great! With this patch, now we don't require my patch. Reviewed-by: Juan A. Suarez Romero ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 15/20] i965/vec4: consider subregister offset in live variables
On Thu, 2017-02-09 at 15:56 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez writes: > > > From: "Juan A. Suarez Romero" > > > > Take in account the offset value when getting the var from register. > > > > This is required when dealing with an operation that writes half of the > > register (like one d2x in IVB/BYT, which uses exec_size == 4). > > > > Note that for live analysis variables we need to stick to per-GRF > > analysis. In this case, we use var_from_reg() with GRF precision. > > This looks bogus to me. If the specified register had a non-zero > sub-GRF offset and we weren't taking it into account we have a bug. The > vec4 liveness analysis pass keeps track of dataflow with 32-bit > granularity these days so we want the variable index computation to be > done with the same precision. I would like to clarify that actually we are using the offset value when calculating var_from_reg(). The thing is about offsets that are less than a GRF; for instance, offsets that points to half of a register (offset == 16). In this case the offset does not affect the result, and it should. But I only did this fix for DCE and other optimizations, but not for liveness analysis. So I'll change it to also do in liveness analysis. J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] anv/formats: handle correctly multisamples in gen7
According to Ivybridge PRM, Volume 4 Part 1 p73, signed integer formats cannot be multisampled. Also in the same PRM p63, any format with greater than 64 bits per element cannot be multisampled. This fixes the following Vulkan CTS tests in Haswell: dEQP-VK.memory.requirements.image.regular_tiling_optimal dEQP-VK.memory.requirements.image.transient_tiling_optimal It also fixes crashes in the following Vulkan CTS tests in Haswell (becoming now skip): dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dms_fragment dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dms_vertex dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dmsarray_fragment dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dmsarray_vertex dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r16g16_sint.samples_4 dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r16g16_sint.samples_8 dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r32g32b32a32_sfloat.samples_4 dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r32g32b32a32_sfloat.samples_8 dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r16g16_sint.samples_4 dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r16g16_sint.samples_8 dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r32g32b32a32_sfloat.samples_4 dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r32g32b32a32_sfloat.samples_8 dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r16g16_sint.samples_4 dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r16g16_sint.samples_8 dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r32g32b32a32_sfloat.samples_4 dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r32g32b32a32_sfloat.samples_8 dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r16g16_sint.samples_4 dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r16g16_sint.samples_8 dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r32g32b32a32_sfloat.samples_4 dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r32g32b32a32_sfloat.samples_8 Signed-off-by: Juan A. Suarez Romero --- src/intel/vulkan/anv_device.c | 4 ++-- src/intel/vulkan/anv_formats.c | 32 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index d1a6cc8..a8ab8c3 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -622,12 +622,12 @@ void anv_GetPhysicalDeviceProperties( .maxFramebufferWidth = (1 << 14), .maxFramebufferHeight = (1 << 14), .maxFramebufferLayers = (1 << 11), - .framebufferColorSampleCounts = sample_counts, + .framebufferColorSampleCounts = devinfo->gen == 7 ? VK_SAMPLE_COUNT_1_BIT : sample_counts, .framebufferDepthSampleCounts = sample_counts, .framebufferStencilSampleCounts = sample_counts, .framebufferNoAttachmentsSampleCounts = sample_counts, .maxColorAttachments = MAX_RTS, - .sampledImageColorSampleCounts= sample_counts, + .sampledImageColorSampleCounts= devinfo->gen == 7 ? VK_SAMPLE_COUNT_1_BIT : sample_counts, .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT, .sampledImageDepthSampleCounts= sample_counts, .sampledImageStencilSampleCounts = sample_counts, diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c index 6005791..3eac931 100644 --- a/src/intel/vulkan/anv_formats.c +++ b/src/intel/vulkan/anv_formats.c @@ -561,6 +561,38 @@ anv_get_image_format_properties( sampleCounts = isl_device_get_sample_counts(&physical_device->isl_dev); } + /* +* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of +* Multisamples: +* +*- This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when +* all RT channels are not written. +* +* And errata from the Ivybridge PRM, Volume 4 Part 1 p77, +* RENDER_SURFACE_STATE, MCS Enable: +* +* This field must be set to 0 [MULTISAMPLECOUNT_1] for all SINT MSRTs +* when all RT channels are not written. +* +* Note that the above SINT restrictions apply only to *MSRTs* (that is, +* *multisampled* render targets). The restrictions seem to permit an MCS +* if the render target is singlesampled. +* +* From the IvyBridge PRM, Volume 4 Part 1 p63, SURFACE_STATE, Surface +* Format: +* +*If Number of Multisamples is set to a value other than +*MULTISAMPLECOUNT_1, this field cannot be set to the following +*formats: any format with greater than 64 bits per element, if Number +*of Multisamples is MULTISAMPLECOUNT_8, any compressed texture format +*(BC*), and any YCRCB* format. +*/ + if (physical_device->info.gen < 8 && + (isl_for
Re: [Mesa-dev] [PATCH] anv/formats: handle correctly multisamples in gen7
On Wed, 2017-02-15 at 10:24 -0800, Jason Ekstrand wrote: > On Wed, Feb 15, 2017 at 10:09 AM, Juan A. Suarez Romero > wrote: > > According to Ivybridge PRM, Volume 4 Part 1 p73, signed integer formats > > > > cannot be multisampled. > > > > > > > > Also in the same PRM p63, any format with greater than 64 bits per > > > > element cannot be multisampled. > > > > > > > > This fixes the following Vulkan CTS tests in Haswell: > > > > > > > > dEQP-VK.memory.requirements.image.regular_tiling_optimal > > > > dEQP-VK.memory.requirements.image.transient_tiling_optimal > > > > > > > > It also fixes crashes in the following Vulkan CTS tests in Haswell > > (becoming now > > > > skip): > > > > > > > > dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dms_fragment > > > > dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dms_vertex > > > > dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dmsarray_fragment > > > > dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dmsarray_vertex > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r16g16_sint.samples_4 > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r16g16_sint.samples_8 > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r32g32b32a32_sfloat.samples_4 > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r32g32b32a32_sfloat.samples_8 > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r16g16_sint.samples_4 > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r16g16_sint.samples_8 > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r32g32b32a32_sfloat.samples_4 > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r32g32b32a32_sfloat.samples_8 > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r16g16_sint.samples_4 > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r16g16_sint.samples_8 > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r32g32b32a32_sfloat.samples_4 > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r32g32b32a32_sfloat.samples_8 > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r16g16_sint.samples_4 > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r16g16_sint.samples_8 > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r32g32b32a32_sfloat.samples_4 > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r32g32b32a32_sfloat.samples_8 > > > > > > > > Signed-off-by: Juan A. Suarez Romero > > > > --- > > > > src/intel/vulkan/anv_device.c | 4 ++-- > > > > src/intel/vulkan/anv_formats.c | 32 > > > > 2 files changed, 34 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c > > > > index d1a6cc8..a8ab8c3 100644 > > > > --- a/src/intel/vulkan/anv_device.c > > > > +++ b/src/intel/vulkan/anv_device.c > > > > @@ -622,12 +622,12 @@ void anv_GetPhysicalDeviceProperties( > > > > .maxFramebufferWidth = (1 << 14), > > > > .maxFramebufferHeight = (1 << 14), > > > > .maxFramebufferLayers = (1 << 11), > > > > - .framebufferColorSampleCounts = sample_counts, > > > > + .framebufferColorSampleCounts = devinfo->gen == 7 ? > > VK_SAMPLE_COUNT_1_BIT : sample_counts, > > > > .framebufferDepthSampleCounts = sample_counts, > > > > .framebufferStencilSampleCounts = sample_counts, > > > > .framebufferNoAttachmentsSampleCounts = sample_counts, > > > > .maxColorAttachments = MAX_RTS, > > > > - .sampledImageColorSampleCounts = sample_counts, > > > > + .sampledImageColorSampleCounts = devinfo->gen == 7 ? > > VK_SAMPLE_COUNT_1_BIT : sample_counts, > > The Vulkan spec says we're supposed to support at least 1x and 4x on both of > these. > You're right. I didn't notice about this requirement. > So I guess the real question is what's the best choice that will let apps > run. My feeling is that setting these fields to 1x and 4x and then just > dying horribly if they use an i
Re: [Mesa-dev] [PATCH] anv/formats: handle correctly multisamples in gen7
On Thu, 2017-02-16 at 12:37 +0100, Juan A. Suarez Romero wrote: > On Wed, 2017-02-15 at 10:24 -0800, Jason Ekstrand wrote: > > On Wed, Feb 15, 2017 at 10:09 AM, Juan A. Suarez Romero > > wrote: > > > According to Ivybridge PRM, Volume 4 Part 1 p73, signed integer formats > > > > > > cannot be multisampled. > > > > > > > > > > > > Also in the same PRM p63, any format with greater than 64 bits per > > > > > > element cannot be multisampled. > > > > > > > > > > > > This fixes the following Vulkan CTS tests in Haswell: > > > > > > > > > > > > dEQP-VK.memory.requirements.image.regular_tiling_optimal > > > > > > dEQP-VK.memory.requirements.image.transient_tiling_optimal > > > > > > > > > > > > It also fixes crashes in the following Vulkan CTS tests in Haswell > > > (becoming now > > > > > > skip): > > > > > > > > > > > > dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dms_fragment > > > > > > dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dms_vertex > > > > > > dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dmsarray_fragment > > > > > > dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dmsarray_vertex > > > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r16g16_sint.samples_4 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r16g16_sint.samples_8 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r32g32b32a32_sfloat.samples_4 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r32g32b32a32_sfloat.samples_8 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r16g16_sint.samples_4 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r16g16_sint.samples_8 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r32g32b32a32_sfloat.samples_4 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r32g32b32a32_sfloat.samples_8 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r16g16_sint.samples_4 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r16g16_sint.samples_8 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r32g32b32a32_sfloat.samples_4 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r32g32b32a32_sfloat.samples_8 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r16g16_sint.samples_4 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r16g16_sint.samples_8 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r32g32b32a32_sfloat.samples_4 > > > > > > dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r32g32b32a32_sfloat.samples_8 > > > > > > > > > > > > Signed-off-by: Juan A. Suarez Romero > > > > > > --- > > > > > > src/intel/vulkan/anv_device.c | 4 ++-- > > > > > > src/intel/vulkan/anv_formats.c | 32 > > > > > > 2 files changed, 34 insertions(+), 2 deletions(-) > > > > > > > > > > > > diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c > > > > > > index d1a6cc8..a8ab8c3 100644 > > > > > > --- a/src/intel/vulkan/anv_device.c > > > > > > +++ b/src/intel/vulkan/anv_device.c > > > > > > @@ -622,12 +622,12 @@ void anv_GetPhysicalDeviceProperties( > > > > > > .maxFramebufferWidth = (1 << 14), > > > > > > .maxFramebufferHeight = (1 << 14), > > > > > > .maxFramebufferLayers = (1 << 11), > > > > > > - .framebufferColorSampleCounts = sample_counts, > > > > > > + .framebufferColorSampleCounts = devinfo->gen == 7 ? > > > VK_SAMPLE_COUNT_1_BIT : sample_counts, > > > > > > .framebufferDepthSampleCounts = sample_counts, > > > > > > .framebufferStencilSampleCounts = sample_counts, > > > > > > .framebufferNoAttachmentsSampleCounts = sample_counts, > > > > > > .maxColorAttachments
[Mesa-dev] [PATCH v2] anv/formats: handle correctly multisamples in gen7
According to Ivybridge PRM, Volume 4 Part 1 p73, signed integer formats
cannot be multisampled.
Also in the same PRM p63, any format with greater than 64 bits per
element cannot be multisampled.
This fixes the following Vulkan CTS tests in Haswell:
dEQP-VK.memory.requirements.image.regular_tiling_optimal
dEQP-VK.memory.requirements.image.transient_tiling_optimal
It also fixes crashes in the following Vulkan CTS tests in Haswell (becoming now
skip):
dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dms_fragment
dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dms_vertex
dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dmsarray_fragment
dEQP-VK.glsl.texture_functions.query.texturesamples.isampler2dmsarray_vertex
dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r16g16_sint.samples_4
dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r16g16_sint.samples_8
dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r32g32b32a32_sfloat.samples_4
dEQP-VK.pipeline.multisample.sampled_image.64x64_1.r32g32b32a32_sfloat.samples_8
dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r16g16_sint.samples_4
dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r16g16_sint.samples_8
dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r32g32b32a32_sfloat.samples_4
dEQP-VK.pipeline.multisample.sampled_image.64x64_4.r32g32b32a32_sfloat.samples_8
dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r16g16_sint.samples_4
dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r16g16_sint.samples_8
dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r32g32b32a32_sfloat.samples_4
dEQP-VK.pipeline.multisample.sampled_image.79x31_1.r32g32b32a32_sfloat.samples_8
dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r16g16_sint.samples_4
dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r16g16_sint.samples_8
dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r32g32b32a32_sfloat.samples_4
dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r32g32b32a32_sfloat.samples_8
v2:
- Vulkan spec says framebufferColorSampleCounts and
sampledImageColorSampleCounts must support 1x and 4x multisampling
(Jason)
- Add SINT restriction in isl_format_supports_multisampling() (Jason)
Signed-off-by: Juan A. Suarez Romero
---
src/intel/isl/isl_format.c | 22 +-
src/intel/vulkan/anv_formats.c | 4 +++-
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index 0452bf8..6fa30a7 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -526,16 +526,36 @@ isl_format_supports_multisampling(const struct
gen_device_info *devinfo,
* - any compressed texture format (BC*)
* - any YCRCB* format
*
+* These restrictions also apply on Ivybridge.
+*
* The restriction on the format's size is removed on Broadwell. Also,
* there is an exception for HiZ which we treat as a compressed format and
* is allowed to be multisampled on Broadwell and earlier.
+*
+* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
+* Multisamples:
+*
+*- This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when
+* all RT channels are not written.
+*
+* And errata from the Ivybridge PRM, Volume 4 Part 1 p77,
+* RENDER_SURFACE_STATE, MCS Enable:
+*
+* This field must be set to 0 [MULTISAMPLECOUNT_1] for all SINT MSRTs
+* when all RT channels are not written.
+*
+* Note that the above SINT restrictions apply only to *MSRTs* (that is,
+* *multisampled* render targets). The restrictions seem to permit an MCS
+* if the render target is singlesampled.
*/
if (format == ISL_FORMAT_HIZ) {
/* On SKL+, HiZ is always single-sampled even when the primary surface
* is multisampled. See also isl_surf_get_hiz_surf().
*/
return devinfo->gen <= 8;
- } else if (devinfo->gen < 8 && isl_format_get_layout(format)->bpb > 64) {
+ } else if (devinfo->gen < 8 &&
+ (isl_format_get_layout(format)->bpb > 64 ||
+ isl_format_has_sint_channel(format))) {
return false;
} else if (isl_format_is_compressed(format)) {
return false;
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 6005791..88f5e02 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -552,7 +552,9 @@ anv_get_image_format_properties(
goto unsupported;
}
- if (info->tiling == VK_IMAGE_TILING_OPTIMAL &&
+ if (isl_format_supports_multisampling(&physical_device->info,
+ anv_formats[info->format].isl_format)
&&
+ info->tiling == VK_IMAGE_TILING_OPTIMAL &&
info->type == VK_IMAGE_TYPE_2D &&
(format_feature_flags & (VK_FORMAT_FEATURE_COLOR_ATTACH
[Mesa-dev] [PATCH] anv: add support for allocating more than 1 block of memory
Current Anv allocator assign memory in terms of a fixed block size.
But there can be cases where this block is not enough for a memory
request, and thus several blocks must be assigned in a row.
This commit adds support for specifying how many blocks of memory must
be assigned.
This fixes a number dEQP-VK.pipeline.render_to_image.* tests that crash.
---
src/intel/vulkan/anv_allocator.c | 82 --
src/intel/vulkan/anv_batch_chain.c | 4 +-
src/intel/vulkan/anv_private.h | 8 +++-
3 files changed, 61 insertions(+), 33 deletions(-)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 45c663b..7e0f3d7 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -149,12 +149,14 @@ round_to_power_of_two(uint32_t value)
}
static bool
-anv_free_list_pop(union anv_free_list *list, void **map, int32_t *offset)
+anv_free_list_pop(union anv_free_list *list, void **map, int32_t *offset,
uint32_t n_blocks)
{
union anv_free_list current, new, old;
+ assert(n_blocks > 0 && n_blocks < 256);
+
current.u64 = list->u64;
- while (current.offset != EMPTY) {
+ while (current.offset != EMPTY && n_blocks <= current.n_blocks) {
/* We have to add a memory barrier here so that the list head (and
* offset) gets read before we read the map pointer. This way we
* know that the map pointer is valid for the given offset at the
@@ -177,16 +179,19 @@ anv_free_list_pop(union anv_free_list *list, void **map,
int32_t *offset)
}
static void
-anv_free_list_push(union anv_free_list *list, void *map, int32_t offset)
+anv_free_list_push(union anv_free_list *list, void *map, int32_t offset,
uint32_t n_blocks)
{
union anv_free_list current, old, new;
int32_t *next_ptr = map + offset;
+ assert(n_blocks > 0 && n_blocks < 256);
+
old = *list;
do {
current = old;
VG_NOACCESS_WRITE(next_ptr, current.offset);
new.offset = offset;
+ new.n_blocks = n_blocks;
new.count = current.count + 1;
old.u64 = __sync_val_compare_and_swap(&list->u64, current.u64, new.u64);
} while (old.u64 != current.u64);
@@ -500,30 +505,37 @@ fail:
static uint32_t
anv_block_pool_alloc_new(struct anv_block_pool *pool,
- struct anv_block_state *pool_state)
+ struct anv_block_state *pool_state,
+ uint32_t n_blocks)
{
struct anv_block_state state, old, new;
+ assert(n_blocks > 0 && n_blocks < 256);
+
while (1) {
- state.u64 = __sync_fetch_and_add(&pool_state->u64, pool->block_size);
- if (state.next < state.end) {
+ state.u64 = __sync_fetch_and_add(&pool_state->u64, n_blocks *
pool->block_size);
+ if (state.next > state.end) {
+ futex_wait(&pool_state->end, state.end);
+ continue;
+ } else if ((state.next + (n_blocks - 1) * pool->block_size) < state.end)
{
assert(pool->map);
return state.next;
- } else if (state.next == state.end) {
- /* We allocated the first block outside the pool, we have to grow it.
- * pool_state->next acts a mutex: threads who try to allocate now will
- * get block indexes above the current limit and hit futex_wait
- * below. */
- new.next = state.next + pool->block_size;
+ } else {
+ /* We allocated the firsts blocks outside the pool, we have to grow
+ * it. pool_state->next acts a mutex: threads who try to allocate
+ * now will get block indexes above the current limit and hit
+ * futex_wait below.
+ */
+ new.next = state.next + n_blocks * pool->block_size;
new.end = anv_block_pool_grow(pool, pool_state);
+ /* We assume that just growing once the pool is enough to fulfil the
+ * memory requirements
+ */
assert(new.end >= new.next && new.end % pool->block_size == 0);
old.u64 = __sync_lock_test_and_set(&pool_state->u64, new.u64);
if (old.next != state.next)
futex_wake(&pool_state->end, INT_MAX);
return state.next;
- } else {
- futex_wait(&pool_state->end, state.end);
- continue;
}
}
}
@@ -531,16 +543,21 @@ anv_block_pool_alloc_new(struct anv_block_pool *pool,
int32_t
anv_block_pool_alloc(struct anv_block_pool *pool)
{
+ return anv_block_pool_alloc_n(pool, 1);
+}
+
+int32_t
+anv_block_pool_alloc_n(struct anv_block_pool *pool, uint32_t n_blocks)
+{
int32_t offset;
- /* Try free list first. */
- if (anv_free_list_pop(&pool->free_list, &pool->map, &offset)) {
+ if (anv_free_list_pop(&pool->free_list, &pool->map, &offset, n_blocks)) {
assert(offset >= 0);
assert(pool->map);
return offset;
}
- return anv_block_pool_alloc_new(pool, &pool->state);
+ return anv_block_pool_alloc_new(pool, &pool->state, n_blocks);
}
/* Allocates a blo
Re: [Mesa-dev] [PATCH 10/95] i965/vec4: handle 32 and 64 bit channels in liveness analysis
On Fri, 2016-07-29 at 12:59 -0700, Francisco Jerez wrote:
> | for (unsigned i = 0; i < 2 * inst->regs_written; i++)
> {
> | for (int c = 0; c < 4; c++)
> | result_live[c] |= BITSET_TEST(
> | live, var_from_reg(alloc, inst->dst, c, i));
> | }
>
> Note that the offset call goes away. The factor of two makes sense
> because you need to check 4 * 2 * regs_written bits in total, since
> you're keeping track of 8 bits per GRF. It would likely make sense
> to
Hmm... what about the case of exec_size == 4 and writing just a float?
I understand in this case we only should mark one word, so the loop
should not be 2*inst->regs_written.
Note that in the original patch that was the case for using offs == 0.
So I guess we should compute if we should use 1 or 2 times
regs_written.
J.A.
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mesa-dev mailing list
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https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 10/95] i965/vec4: handle 32 and 64 bit channels in liveness analysis
On Mon, 2016-08-08 at 16:12 +0200, Juan A. Suarez Romero wrote: > Hmm... what about the case of exec_size == 4 and writing just a > float? > > I understand in this case we only should mark one word, so the loop > should not be 2*inst->regs_written. > > Note that in the original patch that was the case for using offs == > 0. > So I guess we should compute if we should use 1 or 2 times > regs_written. Thinking more carefully, I think it is fine using 2*regs_written/read in this case. So forget about my comment! J.A. signature.asc Description: This is a digitally signed message part ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] glsl: inspect interfaces in contains_foo()
When checking if a type contains doubles, integers, samples, etc. we
check if the current type is a record or array, but not if it is an
interface.
This commit also inspects if the type is an interface.
It fixes
spec/arb_enhanced_layouts/compiler/transform-feedback-layout-qualifiers/xfb_offset/invalid-block-with-double.vert
piglit test.
---
src/compiler/glsl_types.cpp | 11 ++-
src/compiler/glsl_types.h | 16
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index 55e5285..44cd2ac 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -248,7 +248,7 @@ glsl_type::contains_sampler() const
{
if (this->is_array()) {
return this->fields.array->contains_sampler();
- } else if (this->is_record()) {
+ } else if (this->is_record() || this->is_interface()) {
for (unsigned int i = 0; i < this->length; i++) {
if (this->fields.structure[i].type->contains_sampler())
return true;
@@ -265,7 +265,7 @@ glsl_type::contains_integer() const
{
if (this->is_array()) {
return this->fields.array->contains_integer();
- } else if (this->is_record()) {
+ } else if (this->is_record() || this->is_interface()) {
for (unsigned int i = 0; i < this->length; i++) {
if (this->fields.structure[i].type->contains_integer())
return true;
@@ -281,7 +281,7 @@ glsl_type::contains_double() const
{
if (this->is_array()) {
return this->fields.array->contains_double();
- } else if (this->is_record()) {
+ } else if (this->is_record() || this->is_interface()) {
for (unsigned int i = 0; i < this->length; i++) {
if (this->fields.structure[i].type->contains_double())
return true;
@@ -302,6 +302,7 @@ glsl_type::contains_opaque() const {
case GLSL_TYPE_ARRAY:
return fields.array->contains_opaque();
case GLSL_TYPE_STRUCT:
+ case GLSL_TYPE_INTERFACE:
for (unsigned int i = 0; i < length; i++) {
if (fields.structure[i].type->contains_opaque())
return true;
@@ -317,7 +318,7 @@ glsl_type::contains_subroutine() const
{
if (this->is_array()) {
return this->fields.array->contains_subroutine();
- } else if (this->is_record()) {
+ } else if (this->is_record() || this->is_interface()) {
for (unsigned int i = 0; i < this->length; i++) {
if (this->fields.structure[i].type->contains_subroutine())
return true;
@@ -363,7 +364,7 @@ glsl_type::contains_image() const
{
if (this->is_array()) {
return this->fields.array->contains_image();
- } else if (this->is_record()) {
+ } else if (this->is_record() || this->is_interface()) {
for (unsigned int i = 0; i < this->length; i++) {
if (this->fields.structure[i].type->contains_image())
return true;
diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h
index e5b9f3b..f607dd8 100644
--- a/src/compiler/glsl_types.h
+++ b/src/compiler/glsl_types.h
@@ -473,14 +473,14 @@ struct glsl_type {
}
/**
-* Query whether or not type is an integral type, or for struct and array
-* types, contains an integral type.
+* Query whether or not type is an integral type, or for struct, interface
+* and array types, contains an integral type.
*/
bool contains_integer() const;
/**
-* Query whether or not type is a double type, or for struct and array
-* types, contains a double type.
+* Query whether or not type is a double type, or for struct, interface and
+* array types, contains a double type.
*/
bool contains_double() const;
@@ -533,8 +533,8 @@ struct glsl_type {
}
/**
-* Query whether or not type is a sampler, or for struct and array
-* types, contains a sampler.
+* Query whether or not type is a sampler, or for struct, interface and
+* array types, contains a sampler.
*/
bool contains_sampler() const;
@@ -544,8 +544,8 @@ struct glsl_type {
gl_texture_index sampler_index() const;
/**
-* Query whether or not type is an image, or for struct and array
-* types, contains an image.
+* Query whether or not type is an image, or for struct, interface and
+* array types, contains an image.
*/
bool contains_image() const;
--
2.7.4
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[Mesa-dev] [PATCH] glsl: inspect interfaces in contains_foo()
When checking if a type contains doubles, integers, samples, etc. we
check if the current type is a record or array, but not if it is an
interface.
This commit also inspects if the type is an interface.
It fixes
spec/arb_enhanced_layouts/compiler/transform-feedback-layout-qualifiers/xfb_offset/invalid-block-with-double.vert
piglit test.
---
src/compiler/glsl_types.cpp | 11 ++-
src/compiler/glsl_types.h | 16
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index 55e5285..44cd2ac 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -248,7 +248,7 @@ glsl_type::contains_sampler() const
{
if (this->is_array()) {
return this->fields.array->contains_sampler();
- } else if (this->is_record()) {
+ } else if (this->is_record() || this->is_interface()) {
for (unsigned int i = 0; i < this->length; i++) {
if (this->fields.structure[i].type->contains_sampler())
return true;
@@ -265,7 +265,7 @@ glsl_type::contains_integer() const
{
if (this->is_array()) {
return this->fields.array->contains_integer();
- } else if (this->is_record()) {
+ } else if (this->is_record() || this->is_interface()) {
for (unsigned int i = 0; i < this->length; i++) {
if (this->fields.structure[i].type->contains_integer())
return true;
@@ -281,7 +281,7 @@ glsl_type::contains_double() const
{
if (this->is_array()) {
return this->fields.array->contains_double();
- } else if (this->is_record()) {
+ } else if (this->is_record() || this->is_interface()) {
for (unsigned int i = 0; i < this->length; i++) {
if (this->fields.structure[i].type->contains_double())
return true;
@@ -302,6 +302,7 @@ glsl_type::contains_opaque() const {
case GLSL_TYPE_ARRAY:
return fields.array->contains_opaque();
case GLSL_TYPE_STRUCT:
+ case GLSL_TYPE_INTERFACE:
for (unsigned int i = 0; i < length; i++) {
if (fields.structure[i].type->contains_opaque())
return true;
@@ -317,7 +318,7 @@ glsl_type::contains_subroutine() const
{
if (this->is_array()) {
return this->fields.array->contains_subroutine();
- } else if (this->is_record()) {
+ } else if (this->is_record() || this->is_interface()) {
for (unsigned int i = 0; i < this->length; i++) {
if (this->fields.structure[i].type->contains_subroutine())
return true;
@@ -363,7 +364,7 @@ glsl_type::contains_image() const
{
if (this->is_array()) {
return this->fields.array->contains_image();
- } else if (this->is_record()) {
+ } else if (this->is_record() || this->is_interface()) {
for (unsigned int i = 0; i < this->length; i++) {
if (this->fields.structure[i].type->contains_image())
return true;
diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h
index e5b9f3b..f607dd8 100644
--- a/src/compiler/glsl_types.h
+++ b/src/compiler/glsl_types.h
@@ -473,14 +473,14 @@ struct glsl_type {
}
/**
-* Query whether or not type is an integral type, or for struct and array
-* types, contains an integral type.
+* Query whether or not type is an integral type, or for struct, interface
+* and array types, contains an integral type.
*/
bool contains_integer() const;
/**
-* Query whether or not type is a double type, or for struct and array
-* types, contains a double type.
+* Query whether or not type is a double type, or for struct, interface and
+* array types, contains a double type.
*/
bool contains_double() const;
@@ -533,8 +533,8 @@ struct glsl_type {
}
/**
-* Query whether or not type is a sampler, or for struct and array
-* types, contains a sampler.
+* Query whether or not type is a sampler, or for struct, interface and
+* array types, contains a sampler.
*/
bool contains_sampler() const;
@@ -544,8 +544,8 @@ struct glsl_type {
gl_texture_index sampler_index() const;
/**
-* Query whether or not type is an image, or for struct and array
-* types, contains an image.
+* Query whether or not type is an image, or for struct, interface and
+* array types, contains an image.
*/
bool contains_image() const;
--
2.7.4
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[Mesa-dev] [PATCH] glsl: do not show locp information if it is not available
Ignore source file, line number and column in glcpp_error() and
glcpp_warning() if those are not available.
It fixes 4 piglit tests:
spec/glsl-1.10/compiler/version-0.frag: crash pass
spec/glsl-1.10/compiler/version-0.vert: crash pass
spec/glsl-es-3.00/compiler/version-0.frag: crash pass
spec/glsl-es-3.00/compiler/version-0.vert: crash pass
---
src/compiler/glsl/glcpp/pp.c | 41 +++--
1 file changed, 27 insertions(+), 14 deletions(-)
diff --git a/src/compiler/glsl/glcpp/pp.c b/src/compiler/glsl/glcpp/pp.c
index b591279..38f031a 100644
--- a/src/compiler/glsl/glcpp/pp.c
+++ b/src/compiler/glsl/glcpp/pp.c
@@ -32,13 +32,20 @@ glcpp_error (YYLTYPE *locp, glcpp_parser_t *parser, const
char *fmt, ...)
va_list ap;
parser->error = 1;
- ralloc_asprintf_rewrite_tail(&parser->info_log,
-&parser->info_log_length,
-"%u:%u(%u): "
-"preprocessor error: ",
-locp->source,
-locp->first_line,
-locp->first_column);
+
+if (locp)
+ ralloc_asprintf_rewrite_tail(&parser->info_log,
+&parser->info_log_length,
+"%u:%u(%u): "
+"preprocessor error: ",
+locp->source,
+locp->first_line,
+locp->first_column);
+else
+ ralloc_asprintf_rewrite_tail(&parser->info_log,
+&parser->info_log_length,
+"preprocessor error: ");
+
va_start(ap, fmt);
ralloc_vasprintf_rewrite_tail(&parser->info_log,
&parser->info_log_length,
@@ -53,13 +60,19 @@ glcpp_warning (YYLTYPE *locp, glcpp_parser_t *parser, const
char *fmt, ...)
{
va_list ap;
- ralloc_asprintf_rewrite_tail(&parser->info_log,
-&parser->info_log_length,
-"%u:%u(%u): "
-"preprocessor warning: ",
-locp->source,
-locp->first_line,
-locp->first_column);
+if (locp)
+ ralloc_asprintf_rewrite_tail(&parser->info_log,
+&parser->info_log_length,
+"%u:%u(%u): "
+"preprocessor warning: ",
+locp->source,
+locp->first_line,
+locp->first_column);
+else
+ ralloc_asprintf_rewrite_tail(&parser->info_log,
+&parser->info_log_length,
+"preprocesor warning: ");
+
va_start(ap, fmt);
ralloc_vasprintf_rewrite_tail(&parser->info_log,
&parser->info_log_length,
--
2.7.4
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Re: [Mesa-dev] [PATCH] glsl: do not show locp information if it is not available
On Wed, 2016-10-26 at 19:32 +1100, Timothy Arceri wrote: > Please use braces with if when there is on more than a single line in > the then/else blocks. > OK. > Also there seems to be tabs in here please remove them when adding > new > code :) Hmm... all the code in this file is using tabs. But the lines I'm adding do not have tabs. J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] glsl: do not show locp information if it is not available
Ignore source file, line number and column in glcpp_error() and
glcpp_warning() if those are not available.
It fixes 4 piglit tests:
spec/glsl-1.10/compiler/version-0.frag: crash pass
spec/glsl-1.10/compiler/version-0.vert: crash pass
spec/glsl-es-3.00/compiler/version-0.frag: crash pass
spec/glsl-es-3.00/compiler/version-0.vert: crash pass
V2:
- Use brackets (Timothy)
---
src/compiler/glsl/glcpp/pp.c | 43 +--
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/src/compiler/glsl/glcpp/pp.c b/src/compiler/glsl/glcpp/pp.c
index b591279..ab6a214 100644
--- a/src/compiler/glsl/glcpp/pp.c
+++ b/src/compiler/glsl/glcpp/pp.c
@@ -32,13 +32,21 @@ glcpp_error (YYLTYPE *locp, glcpp_parser_t *parser, const
char *fmt, ...)
va_list ap;
parser->error = 1;
- ralloc_asprintf_rewrite_tail(&parser->info_log,
-&parser->info_log_length,
-"%u:%u(%u): "
-"preprocessor error: ",
-locp->source,
-locp->first_line,
-locp->first_column);
+
+if (locp) {
+ ralloc_asprintf_rewrite_tail(&parser->info_log,
+&parser->info_log_length,
+"%u:%u(%u): "
+"preprocessor error: ",
+locp->source,
+locp->first_line,
+locp->first_column);
+} else {
+ ralloc_asprintf_rewrite_tail(&parser->info_log,
+&parser->info_log_length,
+"preprocessor error: ");
+}
+
va_start(ap, fmt);
ralloc_vasprintf_rewrite_tail(&parser->info_log,
&parser->info_log_length,
@@ -53,13 +61,20 @@ glcpp_warning (YYLTYPE *locp, glcpp_parser_t *parser, const
char *fmt, ...)
{
va_list ap;
- ralloc_asprintf_rewrite_tail(&parser->info_log,
-&parser->info_log_length,
-"%u:%u(%u): "
-"preprocessor warning: ",
-locp->source,
-locp->first_line,
-locp->first_column);
+if (locp) {
+ ralloc_asprintf_rewrite_tail(&parser->info_log,
+&parser->info_log_length,
+"%u:%u(%u): "
+"preprocessor warning: ",
+locp->source,
+locp->first_line,
+locp->first_column);
+} else {
+ ralloc_asprintf_rewrite_tail(&parser->info_log,
+&parser->info_log_length,
+"preprocesor warning: ");
+}
+
va_start(ap, fmt);
ralloc_vasprintf_rewrite_tail(&parser->info_log,
&parser->info_log_length,
--
2.7.4
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Re: [Mesa-dev] [PATCH] glsl: do not show locp information if it is not available
On Wed, 2016-10-26 at 13:42 +0200, Juan A. Suarez Romero wrote:
> Ignore source file, line number and column in glcpp_error() and
> glcpp_warning() if those are not available.
>
> It fixes 4 piglit tests:
> spec/glsl-1.10/compiler/version-0.frag: crash pass
> spec/glsl-1.10/compiler/version-0.vert: crash pass
> spec/glsl-es-3.00/compiler/version-0.frag: crash pass
> spec/glsl-es-3.00/compiler/version-0.vert: crash pass
>
> V2:
> - Use brackets (Timothy)
> ---
> src/compiler/glsl/glcpp/pp.c | 43 +-
> -
> 1 file changed, 29 insertions(+), 14 deletions(-)
>
> diff --git a/src/compiler/glsl/glcpp/pp.c
> b/src/compiler/glsl/glcpp/pp.c
> index b591279..ab6a214 100644
> --- a/src/compiler/glsl/glcpp/pp.c
> +++ b/src/compiler/glsl/glcpp/pp.c
> @@ -32,13 +32,21 @@ glcpp_error (YYLTYPE *locp, glcpp_parser_t
> *parser, const char *fmt, ...)
> va_list ap;
>
> parser->error = 1;
> - ralloc_asprintf_rewrite_tail(&parser->info_log,
> - &parser->info_log_length,
> - "%u:%u(%u): "
> - "preprocessor error: ",
> - locp->source,
> - locp->first_line,
> - locp->first_column);
> +
> +if (locp) {
> + ralloc_asprintf_rewrite_tail(&parser->info_log,
> +&parser->info_log_length,
> +"%u:%u(%u): "
> +"preprocessor error: ",
> +locp->source,
> +locp->first_line,
> +locp->first_column);
> +} else {
> + ralloc_asprintf_rewrite_tail(&parser->info_log,
> +&parser->info_log_length,
> +"preprocessor error: ");
> +}
> +
> va_start(ap, fmt);
> ralloc_vasprintf_rewrite_tail(&parser->info_log,
> &parser->info_log_length,
> @@ -53,13 +61,20 @@ glcpp_warning (YYLTYPE *locp, glcpp_parser_t
> *parser, const char *fmt, ...)
> {
> va_list ap;
>
> - ralloc_asprintf_rewrite_tail(&parser->info_log,
> - &parser->info_log_length,
> - "%u:%u(%u): "
> - "preprocessor warning: ",
> - locp->source,
> - locp->first_line,
> - locp->first_column);
> +if (locp) {
> + ralloc_asprintf_rewrite_tail(&parser->info_log,
> +&parser->info_log_length,
> +"%u:%u(%u): "
> +"preprocessor warning: ",
> +locp->source,
> +locp->first_line,
> +locp->first_column);
> +} else {
> + ralloc_asprintf_rewrite_tail(&parser->info_log,
> +&parser->info_log_length,
> +"preprocesor warning: ");
> +}
> +
> va_start(ap, fmt);
> ralloc_vasprintf_rewrite_tail(&parser->info_log,
> &parser->info_log_length,
Timothy, can this be considered as Reviewed-by: you?
Thanks in advance!
J.A.
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Re: [Mesa-dev] [PATCH] i965: use rzalloc instead of calloc in brwNewProgram
On Thu, 2016-11-03 at 11:40 +0200, Tapani Pälli wrote:
> commit cc6aa1d161280f10ded7834d1ec2413bc97589fe changed to using
> rzalloc
> for gl_program creation but one instance for program creation was
> still
> using calloc.
>
> Signed-off-by: Tapani Pälli
> ---
> src/mesa/drivers/dri/i965/brw_program.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_program.c
> b/src/mesa/drivers/dri/i965/brw_program.c
> index 647f138..ffe4c27 100644
> --- a/src/mesa/drivers/dri/i965/brw_program.c
> +++ b/src/mesa/drivers/dri/i965/brw_program.c
> @@ -152,7 +152,7 @@ static struct gl_program *brwNewProgram( struct
> gl_context *ctx,
> rzalloc(NULL, struct gen4_fragment_program);
> prog = &g4_prog->base;
> } else {
> - prog = CALLOC_STRUCT(brw_program);
> + prog = rzalloc(NULL, struct brw_program);
> }
>
> if (prog) {
I had exactly the same patch ready to be submitted :)
Reviewed-by: Juan A. Suarez
J.A.
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[Mesa-dev] [PATCH] i965: allow unsourced enabled VAO
The GL 4.5 spec says:
"If any enabled array’s buffer binding is zero when DrawArrays
or one of the other drawing commands defined in section 10.4 is
called, the result is undefined."
This commits avoids crashing the code, which is not a very good
"undefined result".
This fixes spec/!opengl 3.1/vao-broken-attrib piglit test.
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index ab2fc50..3925b6e 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -421,13 +421,22 @@ copy_array_to_vbo_array(struct brw_context *brw,
uint8_t *dst = intel_upload_space(brw, size, dst_stride,
&buffer->bo, &buffer->offset);
- if (dst_stride == src_stride) {
- memcpy(dst, src, size);
- } else {
- while (count--) {
-memcpy(dst, src, dst_stride);
-src += src_stride;
-dst += dst_stride;
+ /* The GL 4.5 spec says:
+* "If any enabled array’s buffer binding is zero when DrawArrays or
+* one of the other drawing commands defined in section 10.4 is called,
+* the result is undefined."
+*
+* In this case, let's the dst with undefined values
+*/
+ if (src != NULL) {
+ if (dst_stride == src_stride) {
+ memcpy(dst, src, size);
+ } else {
+ while (count--) {
+memcpy(dst, src, dst_stride);
+src += src_stride;
+dst += dst_stride;
+ }
}
}
buffer->stride = dst_stride;
--
2.7.4
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Re: [Mesa-dev] [PATCH] glsl: do not show locp information if it is not available
On Thu, 2016-11-03 at 12:23 -0700, Ian Romanick wrote: > I'm also a little curious how we get to this point with locp being > NULL. > Some commentary about that should at least go in the commit message. So here is the reason. Mesa initializes parser->version as 0. When finalizes parsing the shader, if it didn't set explicitly the version it adds it implicitly. Mesa knows it if parser->version != 0. As this code is added implicitly, the locp in this case is NULL. But the problem with this test is that user defines #version 0. So Mesa doesn't realize version was set, and tries to implicitly adds the version. But version was defined before, so it shows the error that version is redefined. Problem? As said above, with the implicit code locp is NULL, hence the error. After thinking about it, I think this could be fixed if parser->version is initialized to a value that we know user can't set it. In this case, initializing to -1. This would mean changing the parser->version type to int instead of uint. But this is not a problem. So I withdraw this patch and will submit a new one. J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] glcpp: initializes version to -1
Shader can define #version as an integer, including 0.
Initializes version to -1 to know later if shader has defined a #version
or not.
It fixes 4 piglit tests:
spec/glsl-1.10/compiler/version-0.frag: crash pass
spec/glsl-1.10/compiler/version-0.vert: crash pass
spec/glsl-es-3.00/compiler/version-0.frag: crash pass
spec/glsl-es-3.00/compiler/version-0.vert: crash pass
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97420
---
src/compiler/glsl/glcpp/glcpp-parse.y | 8
src/compiler/glsl/glcpp/glcpp.h | 2 +-
src/compiler/glsl/glsl_lexer.ll | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y
b/src/compiler/glsl/glcpp/glcpp-parse.y
index b80ff04..6207a62 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -420,13 +420,13 @@ control_line_success:
_glcpp_parser_skip_stack_pop (parser, & @1);
} NEWLINE
| HASH_TOKEN VERSION_TOKEN integer_constant NEWLINE {
- if (parser->version != 0) {
+ if (parser->version != -1) {
glcpp_error(& @1, parser, "#version must appear on the
first line");
}
_glcpp_parser_handle_version_declaration(parser, $3, NULL,
true);
}
| HASH_TOKEN VERSION_TOKEN integer_constant IDENTIFIER NEWLINE {
- if (parser->version != 0) {
+ if (parser->version != -1) {
glcpp_error(& @1, parser, "#version must appear on the
first line");
}
_glcpp_parser_handle_version_declaration(parser, $3, $4, true);
@@ -1360,7 +1360,7 @@ glcpp_parser_create(glcpp_extension_iterator extensions,
void *state, gl_api api
parser->extensions = extensions;
parser->state = state;
parser->api = api;
- parser->version = 0;
+ parser->version = -1;
parser->has_new_line_number = 0;
parser->new_line_number = 1;
@@ -2293,7 +2293,7 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t
*parser, intmax_t versio
const char *es_identifier,
bool explicitly_set)
{
- if (parser->version != 0)
+ if (parser->version != -1)
return;
parser->version = version;
diff --git a/src/compiler/glsl/glcpp/glcpp.h b/src/compiler/glsl/glcpp/glcpp.h
index bb4ad67..2acac0c 100644
--- a/src/compiler/glsl/glcpp/glcpp.h
+++ b/src/compiler/glsl/glcpp/glcpp.h
@@ -207,7 +207,7 @@ struct glcpp_parser {
glcpp_extension_iterator extensions;
void *state;
gl_api api;
- unsigned version;
+ int version;
bool has_new_line_number;
int new_line_number;
bool has_new_source_number;
diff --git a/src/compiler/glsl/glsl_lexer.ll b/src/compiler/glsl/glsl_lexer.ll
index b473af7..7d1d616 100644
--- a/src/compiler/glsl/glsl_lexer.ll
+++ b/src/compiler/glsl/glsl_lexer.ll
@@ -249,7 +249,7 @@ HASH^{SPC}#{SPC}
yylval->identifier = linear_strdup(mem_ctx,
yytext);
return IDENTIFIER;
}
-[1-9][0-9]*{
+[0-9][0-9]*{
yylval->n = strtol(yytext, NULL, 10);
return INTCONSTANT;
}
--
2.7.4
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Re: [Mesa-dev] [PATCH] glcpp: initializes version to -1
On Fri, 2016-11-04 at 14:09 +, Eric Engestrom wrote:
> On Friday, 2016-11-04 13:22:07 +0100, Juan A. Suarez Romero wrote:
> >
> > Shader can define #version as an integer, including 0.
> >
> > Initializes version to -1 to know later if shader has defined a
> > #version
> > or not.
> >
> > It fixes 4 piglit tests:
> > spec/glsl-1.10/compiler/version-0.frag: crash pass
> > spec/glsl-1.10/compiler/version-0.vert: crash pass
> > spec/glsl-es-3.00/compiler/version-0.frag: crash pass
> > spec/glsl-es-3.00/compiler/version-0.vert: crash pass
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97420
> > ---
> > src/compiler/glsl/glcpp/glcpp-parse.y | 8
> > src/compiler/glsl/glcpp/glcpp.h | 2 +-
> > src/compiler/glsl/glsl_lexer.ll | 2 +-
> > 3 files changed, 6 insertions(+), 6 deletions(-)
> >
> [snip]
> >
> > diff --git a/src/compiler/glsl/glsl_lexer.ll
> > b/src/compiler/glsl/glsl_lexer.ll
> > index b473af7..7d1d616 100644
> > --- a/src/compiler/glsl/glsl_lexer.ll
> > +++ b/src/compiler/glsl/glsl_lexer.ll
> > @@ -249,7 +249,7 @@ HASH^{SPC}#{SPC}
> > yylval->identifier =
> > linear_strdup(mem_ctx, yytext);
> > return IDENTIFIER;
> > }
> > -[1-9][0-9]*{
> > +[0-9][0-9]*{
>
> I'm not familiar with flex, but with regexes I've worked with that
> would
> be equivalent to:
> [0-9]+ {
> :)
>
Yes, right :).
J.A.
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Re: [Mesa-dev] [PATCH] glcpp: initializes version to -1
On Fri, 2016-11-04 at 16:57 +0100, Karol Herbst wrote: > for reference the bug I've created for this: > https://bugs.freedesktop.org/show_bug.cgi?id=97420 > > I'll tag the commit with this bug. J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glcpp: initializes version to -1
On Sat, 2016-11-05 at 10:48 +0100, Karol Herbst wrote: > 2016-11-05 2:50 GMT+01:00 Ian Romanick : > > (Sorry about the top post. Sent from my phone.) > > > > That expression will allow versions like 0130 as valid. If you > just want to > > allow 0, you need a more complex regular expression. I feel like > that's > > just a bandage... what about other bad values like "#version > -130"? Won't > > that have the same problem that 0 currently has? > > > > no, it doesn't. > > I tested the patch with glsl_compiler > > "#version 0130": 0:1(10): error: GLSL 0.88 is not supported. > Supported > versions are: 1.10, 1.20, 1.30, 1.00 ES, and 3.00 ES > > "#version 0": 0:1(10): error: GLSL 0.00 is not supported. Supported > versions are: 1.10, 1.20, 1.30, 1.00 ES, and 3.00 ES > > "#version -130":0:1(10): preprocessor error: syntax error, unexpected > '-', expecting INTEGER or INTEGER_STRING > Correct. It only accepts any positive integer; for negative numbers it gives an error. > but > > "#version 0512": 0:1(10): error: GLSL 3.30 is not supported. > Supported > versions are: 1.10, 1.20, 1.30, 1.00 ES, and 3.00 ES > > so the issue with this would be, that "0512" is parsed as 3.30, which > isn't right either, but the current master version does the same. \o/ > new bug found Good catch! Should this parse mistake filed as a separate bug? J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glcpp: initializes version to -1
On Sat, 2016-11-05 at 10:48 +0100, Karol Herbst wrote: > "#version 0512": 0:1(10): error: GLSL 3.30 is not supported. > Supported > versions are: 1.10, 1.20, 1.30, 1.00 ES, and 3.00 ES > > so the issue with this would be, that "0512" is parsed as 3.30, which > isn't right either, but the current master version does the same. \o/ > new bug found Doing a quick check, not sure if this is a bug... 0512 is interpreted in octal format, which in decimal is 330. Same for 0130, which is 88 in decimal. So unless we want to force all the values to be read as decimal, I woulnd't say it is a bug. J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glcpp: initializes version to -1
On Tue, 2016-11-08 at 14:19 +0100, Karol Herbst wrote: > well I don't care either way, maybe the spec does say anything about > it. I was re-reading GLSL 1.10 spec about #version directive. #version follows the same convention as __VERSION__ For __VERSION___, spec says "will substitute a decimal integer reflecting the version number of the OpenGL shading language" So no clear if we should always read as decimal, or keep current behaviour. J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965/vec4: skip registers already marked as no_spill
Do not evaluate spill costs for registers that were already marked as
no_spill.
---
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 228e04c..5a5be85 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -385,7 +385,7 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool
*no_spill)
*/
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
for (unsigned int i = 0; i < 3; i++) {
- if (inst->src[i].file == VGRF) {
+ if (inst->src[i].file == VGRF && !no_spill[inst->src[i].nr]) {
/* We will only unspill src[i] it it wasn't unspilled for the
* previous instruction, in which case we'll just reuse the scratch
* reg for this instruction.
@@ -399,7 +399,7 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool
*no_spill)
}
}
- if (inst->dst.file == VGRF) {
+ if (inst->dst.file == VGRF && !no_spill[inst->dst.nr]) {
spill_costs[inst->dst.nr] += loop_scale;
if (inst->dst.reladdr || inst->dst.offset % REG_SIZE != 0)
no_spill[inst->dst.nr] = true;
--
2.7.4
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Re: [Mesa-dev] [PATCH] i965/vec4: skip registers already marked as no_spill
On Sun, 2016-11-13 at 23:00 -0800, Kenneth Graunke wrote:
> On Friday, November 11, 2016 9:41:11 AM PST Juan A. Suarez Romero
> wrote:
> >
> > Do not evaluate spill costs for registers that were already marked
> > as
> > no_spill.
> > ---
> > src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
> > b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
> > index 228e04c..5a5be85 100644
> > --- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
> > @@ -385,7 +385,7 @@ vec4_visitor::evaluate_spill_costs(float
> > *spill_costs, bool *no_spill)
> > */
> > foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
> > for (unsigned int i = 0; i < 3; i++) {
> > - if (inst->src[i].file == VGRF) {
> > + if (inst->src[i].file == VGRF && !no_spill[inst-
> > >src[i].nr]) {
> > /* We will only unspill src[i] it it wasn't unspilled
> > for the
> > * previous instruction, in which case we'll just
> > reuse the scratch
> > * reg for this instruction.
> > @@ -399,7 +399,7 @@ vec4_visitor::evaluate_spill_costs(float
> > *spill_costs, bool *no_spill)
> > }
> > }
> >
> > - if (inst->dst.file == VGRF) {
> > + if (inst->dst.file == VGRF && !no_spill[inst->dst.nr]) {
> > spill_costs[inst->dst.nr] += loop_scale;
> > if (inst->dst.reladdr || inst->dst.offset % REG_SIZE !=
> > 0)
> > no_spill[inst->dst.nr] = true;
> >
>
> Hmm, it seems pretty harmless to do this...also, the FS backend
> doesn't
> have these checks either.
>
> I'm guessing you're trying to avoid the overhead of calling
> can_use_scratch_for_source()? It's a bunch of list walking for a
> value
> that ultimately won't matter.
Exactly.
> Cutting that seems reasonable.
>
> Reviewed-by: Kenneth Graunke
Thanks!
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[Mesa-dev] [PATCH 1/5] anv/pipeline: do not discard 'const' modifier
Fixes warning.
---
src/intel/vulkan/genX_pipeline.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index cb164ad..ada7985 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1138,7 +1138,7 @@ emit_3dstate_ps(struct anv_pipeline *pipeline,
bool dual_src_blend = false;
if (wm_prog_data->dual_src_blend) {
for (uint32_t i = 0; i < blend->attachmentCount; i++) {
- VkPipelineColorBlendAttachmentState *bstate = &blend->pAttachments[i];
+ const VkPipelineColorBlendAttachmentState *bstate =
&blend->pAttachments[i];
if (bstate->blendEnable &&
(is_dual_src_blend_factor(bstate->srcColorBlendFactor) ||
is_dual_src_blend_factor(bstate->dstColorBlendFactor) ||
--
2.7.4
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[Mesa-dev] [PATCH 2/5] anv/pipeline: define is_dual_src_blend_factor() for gen <= 8
Fixes defined but not used warning.
---
src/intel/vulkan/genX_pipeline.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index ada7985..991fbf6 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1100,6 +1100,7 @@ emit_3dstate_wm(struct anv_pipeline *pipeline, struct
anv_subpass *subpass,
}
}
+#if GEN_GEN < 8
static bool
is_dual_src_blend_factor(VkBlendFactor factor)
{
@@ -1108,6 +1109,7 @@ is_dual_src_blend_factor(VkBlendFactor factor)
factor == VK_BLEND_FACTOR_SRC1_ALPHA ||
factor == VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA;
}
+#endif
static void
emit_3dstate_ps(struct anv_pipeline *pipeline,
--
2.7.4
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[Mesa-dev] [PATCH 0/5] Several fixes for different warnings
I'm sending several unrelated patches that fix different warnings when building Mesa. Juan A. Suarez Romero (5): anv/pipeline: do not discard 'const' modifier anv/pipeline: define is_dual_src_blend_factor() for gen <= 8 st/va: remove unsed variable ttn: handle GLSL_SAMPLER_DIM_SUBPASS_MS case st/va: declare vlVaBuffer before vlVaContext src/gallium/auxiliary/nir/tgsi_to_nir.c| 1 + src/gallium/state_trackers/va/surface.c| 1 - src/gallium/state_trackers/va/va_private.h | 30 +++--- src/intel/vulkan/genX_pipeline.c | 4 +++- 4 files changed, 19 insertions(+), 17 deletions(-) -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/5] ttn: handle GLSL_SAMPLER_DIM_SUBPASS_MS case
Fixes a warning.
---
src/gallium/auxiliary/nir/tgsi_to_nir.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 3f05acd..e90684f 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -1341,6 +1341,7 @@ ttn_tex(struct ttn_compile *c, nir_alu_dest dest,
nir_ssa_def **src)
instr->coord_components = 3;
break;
case GLSL_SAMPLER_DIM_SUBPASS:
+ case GLSL_SAMPLER_DIM_SUBPASS_MS:
unreachable("invalid sampler_dim");
}
--
2.7.4
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[Mesa-dev] [PATCH 5/5] st/va: declare vlVaBuffer before vlVaContext
And declare coded_buf in vlVaContext as "vlVaBuffer *" instead of
"struct vlVaBuffer *".
This fixes several warnings later about assignment from incompatible
pointer type.
---
src/gallium/state_trackers/va/va_private.h | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/gallium/state_trackers/va/va_private.h
b/src/gallium/state_trackers/va/va_private.h
index c9a6a41..054cfb3 100644
--- a/src/gallium/state_trackers/va/va_private.h
+++ b/src/gallium/state_trackers/va/va_private.h
@@ -220,6 +220,20 @@ typedef struct {
} vlVaSubpicture;
typedef struct {
+ VABufferType type;
+ unsigned int size;
+ unsigned int num_elements;
+ void *data;
+ struct {
+ struct pipe_resource *resource;
+ struct pipe_transfer *transfer;
+ } derived_surface;
+ unsigned int export_refcount;
+ VABufferInfo export_state;
+ unsigned int coded_size;
+} vlVaBuffer;
+
+typedef struct {
struct pipe_video_codec templat, *decoder;
struct pipe_video_buffer *target;
union {
@@ -242,7 +256,7 @@ typedef struct {
} mpeg4;
struct vl_deint_filter *deint;
- struct vlVaBuffer *coded_buf;
+ vlVaBuffer *coded_buf;
int target_id;
} vlVaContext;
@@ -254,20 +268,6 @@ typedef struct {
} vlVaConfig;
typedef struct {
- VABufferType type;
- unsigned int size;
- unsigned int num_elements;
- void *data;
- struct {
- struct pipe_resource *resource;
- struct pipe_transfer *transfer;
- } derived_surface;
- unsigned int export_refcount;
- VABufferInfo export_state;
- unsigned int coded_size;
-} vlVaBuffer;
-
-typedef struct {
struct pipe_video_buffer templat, *buffer;
struct util_dynarray subpics; /* vlVaSubpicture */
VAContextID ctx;
--
2.7.4
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[Mesa-dev] [PATCH 3/5] st/va: remove unsed variable
pbuff is defined but not used. --- src/gallium/state_trackers/va/surface.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/gallium/state_trackers/va/surface.c b/src/gallium/state_trackers/va/surface.c index f8513d9..357e85e 100644 --- a/src/gallium/state_trackers/va/surface.c +++ b/src/gallium/state_trackers/va/surface.c @@ -94,7 +94,6 @@ vlVaSyncSurface(VADriverContextP ctx, VASurfaceID render_target) vlVaDriver *drv; vlVaContext *context; vlVaSurface *surf; - void *pbuff; if (!ctx) return VA_STATUS_ERROR_INVALID_CONTEXT; -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 01/22] spirv: fix typo in spec_constant_decoration_cb()
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 34968a4..c28d425 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -932,7 +932,7 @@ vtn_null_constant(struct vtn_builder *b, const struct
glsl_type *type)
}
static void
-spec_constant_deocoration_cb(struct vtn_builder *b, struct vtn_value *v,
+spec_constant_decoration_cb(struct vtn_builder *b, struct vtn_value *v,
int member, const struct vtn_decoration *dec,
void *data)
{
@@ -954,7 +954,7 @@ static uint32_t
get_specialization(struct vtn_builder *b, struct vtn_value *val,
uint32_t const_value)
{
- vtn_foreach_decoration(b, val, spec_constant_deocoration_cb, &const_value);
+ vtn_foreach_decoration(b, val, spec_constant_decoration_cb, &const_value);
return const_value;
}
--
2.7.4
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[Mesa-dev] [PATCH 00/22] Enable Float64 capability support for Intel's Vulkan driver
Hello,
This patch series implements support for Float64 capability to SPIR-V to NIR
pass and adds the needed bits to enable it in Intel's Vulkan driver. Float64
capability is only enabled in Intel's generations that support
ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit (currently Broadwell and newer),
follow-up patches will be sent once ARB_gpu_shader_fp64 and
ARB_vertex_attrib_64bit support for other generations (Haswell and Ivybridge) is
in master.
We have tested these patches against Vulkan conformance test suite [0]. All the
Float64 tests pass, except the ones that also requires other unsupported
capabilities. The results we got running VulkanCTS on master with and without
these patches are:
| name| master | patch series |
|-++--|
| pass| 76968 |77195 |
| fail|100 | 100 |
| crash | 6 |5 |
| skip| 45990 |45764 |
| timeout | 0 |0 |
| warn| 7 |7 |
| incomplete | 0 |0 |
| dmesg-warn | 0 |0 |
| dmesg-fail | 0 |0 |
| changes | 0 | 227 |
| fixes | 0 |1 |
| regressions | 0 |0 |
| TOTAL | 123071 | 123071 |
If you want to test these patches, you can clone our branch with the following
command:
$ git clone -b spirv-to-nir-rc1 https://github.com/Igalia/mesa.git
Thanks,
J.A.
[0] https://github.com/KhronosGroup/Vulkan-CTS
Juan A. Suarez Romero (2):
anv/pipeline: get map for double input attributes
anv/nir: add support for dvec3/4 consuming two locations
Samuel Iglesias Gonsálvez (20):
spirv: fix typo in spec_constant_decoration_cb()
spirv: add definition of double based data types
spirv: add double support for loading DF constants
spirv: add DF support to vtn_const_ssa_value()
spirv: add DF support to SpvOp*ConstantComposite
spirv: fix SpvOpSpecConstantOp with SpvOpVectorShuffle working with
double-based vecs
spirv: add double support to SpvOpCompositeExtract
spirv: add double support to _vtn_variable_load_store
spirv: add double support to _vtn_block_load_store()
spirv: Enable double floating points when copying variables in
_vtn_variable_copy()
spirv: add support for doubles on OpComposite{Insert,Extract}
spirv/nir: implement DF conversions
spirv/nir: add (un)packDouble2x32() translation
spirv: add support for doubles to OpSpecConstant
isl: fix VA64 support for double and dvecN vertex attributes
nir: Add flag to detect platforms with native float64 support
spirv: Add nir_options to vtn_builder
spirv: enable SpvCapabilityFloat64 only to supported platforms
i965: enable nir_option's native_float64 to supported generations
anv: enable shaderFloat64 feature
src/amd/vulkan/radv_pipeline.c | 6 +-
src/compiler/nir/nir.h | 10 ++
src/compiler/nir/nir_gather_info.c | 6 +-
src/compiler/spirv/nir_spirv.h | 5 +-
src/compiler/spirv/spirv_to_nir.c| 193 ++-
src/compiler/spirv/vtn_alu.c | 37 +++--
src/compiler/spirv/vtn_glsl450.c | 2 +
src/compiler/spirv/vtn_private.h | 4 +-
src/compiler/spirv/vtn_variables.c | 3 +
src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 +
src/intel/isl/isl_format.c | 4 +-
src/intel/isl/isl_format_layout.csv | 3 -
src/intel/vulkan/anv_device.c| 4 +-
src/intel/vulkan/anv_formats.c | 8 +-
src/intel/vulkan/anv_pipeline.c | 6 +-
src/intel/vulkan/genX_pipeline.c | 62 +
src/mesa/drivers/dri/i965/brw_compiler.c | 50 +--
src/mesa/drivers/dri/i965/brw_compiler.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 +-
src/mesa/drivers/dri/i965/brw_nir.c | 18 ++-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 +-
src/mesa/drivers/dri/i965/intel_screen.c | 3 +-
22 files changed, 337 insertions(+), 117 deletions(-)
--
2.7.4
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[Mesa-dev] [PATCH 03/22] spirv: add double support for loading DF constants
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index e5ec868..dadf7fc 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1005,10 +1005,17 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
break;
}
- case SpvOpConstant:
+ case SpvOpConstant: {
assert(glsl_type_is_scalar(val->const_type));
- val->constant->value.u[0] = w[3];
+ int bit_size = glsl_get_bit_size(val->const_type);
+ if (bit_size == 64) {
+ val->constant->value.u[0] = w[3];
+ val->constant->value.u[1] = w[4];
+ } else {
+ val->constant->value.u[0] = w[3];
+ }
break;
+ }
case SpvOpSpecConstant:
assert(glsl_type_is_scalar(val->const_type));
val->constant->value.u[0] = get_specialization(b, val, w[3]);
--
2.7.4
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[Mesa-dev] [PATCH 02/22] spirv: add definition of double based data types
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index c28d425..e5ec868 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -706,9 +706,11 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
val->type->type = (signedness ? glsl_int_type() : glsl_uint_type());
break;
}
- case SpvOpTypeFloat:
- val->type->type = glsl_float_type();
+ case SpvOpTypeFloat: {
+ int bit_size = w[2];
+ val->type->type = bit_size == 64 ? glsl_double_type() :
glsl_float_type();
break;
+ }
case SpvOpTypeVector: {
struct vtn_type *base = vtn_value(b, w[2], vtn_value_type_type)->type;
--
2.7.4
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[Mesa-dev] [PATCH 04/22] spirv: add DF support to vtn_const_ssa_value()
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index dadf7fc..8569bc8 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -98,14 +98,19 @@ vtn_const_ssa_value(struct vtn_builder *b, nir_constant
*constant,
case GLSL_TYPE_UINT:
case GLSL_TYPE_BOOL:
case GLSL_TYPE_FLOAT:
- case GLSL_TYPE_DOUBLE:
+ case GLSL_TYPE_DOUBLE: {
+ int bit_size = glsl_get_bit_size(type);
if (glsl_type_is_vector_or_scalar(type)) {
unsigned num_components = glsl_get_vector_elements(val->type);
nir_load_const_instr *load =
-nir_load_const_instr_create(b->shader, num_components, 32);
+nir_load_const_instr_create(b->shader, num_components, bit_size);
- for (unsigned i = 0; i < num_components; i++)
-load->value.u32[i] = constant->value.u[i];
+ for (unsigned i = 0; i < num_components; i++) {
+if (bit_size == 64)
+ load->value.f64[i] = constant->value.d[i];
+else
+ load->value.u32[i] = constant->value.u[i];
+ }
nir_instr_insert_before_cf_list(&b->impl->body, &load->instr);
val->def = &load->def;
@@ -119,10 +124,14 @@ vtn_const_ssa_value(struct vtn_builder *b, nir_constant
*constant,
struct vtn_ssa_value *col_val = rzalloc(b, struct vtn_ssa_value);
col_val->type = glsl_get_column_type(val->type);
nir_load_const_instr *load =
- nir_load_const_instr_create(b->shader, rows, 32);
+ nir_load_const_instr_create(b->shader, rows, bit_size);
-for (unsigned j = 0; j < rows; j++)
- load->value.u32[j] = constant->value.u[rows * i + j];
+for (unsigned j = 0; j < rows; j++) {
+ if (bit_size == 64)
+ load->value.f64[j] = constant->value.d[rows * i + j];
+ else
+ load->value.u32[j] = constant->value.u[rows * i + j];
+}
nir_instr_insert_before_cf_list(&b->impl->body, &load->instr);
col_val->def = &load->def;
@@ -131,6 +140,7 @@ vtn_const_ssa_value(struct vtn_builder *b, nir_constant
*constant,
}
}
break;
+ }
case GLSL_TYPE_ARRAY: {
unsigned elems = glsl_get_length(val->type);
--
2.7.4
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[Mesa-dev] [PATCH 07/22] spirv: add double support to SpvOpCompositeExtract
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 02dbceb..3bc23d3 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1182,8 +1182,12 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
val->constant = *c;
} else {
unsigned num_components = glsl_get_vector_elements(type);
+ unsigned bit_size = glsl_get_bit_size(type);
for (unsigned i = 0; i < num_components; i++)
- val->constant->value.u[i] = (*c)->value.u[elem + i];
+ if (bit_size == 64)
+ val->constant->value.d[i] = (*c)->value.d[elem + i];
+ else
+ val->constant->value.u[i] = (*c)->value.u[elem + i];
}
} else {
struct vtn_value *insert =
@@ -1193,8 +1197,12 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
*c = insert->constant;
} else {
unsigned num_components = glsl_get_vector_elements(type);
+ unsigned bit_size = glsl_get_bit_size(type);
for (unsigned i = 0; i < num_components; i++)
- (*c)->value.u[elem + i] = insert->constant->value.u[i];
+ if (bit_size == 64)
+ (*c)->value.d[elem + i] = insert->constant->value.d[i];
+ else
+ (*c)->value.u[elem + i] = insert->constant->value.u[i];
}
}
break;
--
2.7.4
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[Mesa-dev] [PATCH 05/22] spirv: add DF support to SpvOp*ConstantComposite
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 8569bc8..9751679 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1042,21 +1042,31 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
case GLSL_TYPE_INT:
case GLSL_TYPE_FLOAT:
case GLSL_TYPE_BOOL:
+ case GLSL_TYPE_DOUBLE: {
+ int bit_size = glsl_get_bit_size(val->const_type);
if (glsl_type_is_matrix(val->const_type)) {
unsigned rows = glsl_get_vector_elements(val->const_type);
assert(glsl_get_matrix_columns(val->const_type) == elem_count);
for (unsigned i = 0; i < elem_count; i++)
- for (unsigned j = 0; j < rows; j++)
- val->constant->value.u[rows * i + j] = elems[i]->value.u[j];
+ for (unsigned j = 0; j < rows; j++) {
+ if (bit_size == 64)
+ val->constant->value.d[rows * i + j] =
elems[i]->value.d[j];
+ else
+ val->constant->value.u[rows * i + j] =
elems[i]->value.u[j];
+ }
} else {
assert(glsl_type_is_vector(val->const_type));
assert(glsl_get_vector_elements(val->const_type) == elem_count);
-for (unsigned i = 0; i < elem_count; i++)
- val->constant->value.u[i] = elems[i]->value.u[0];
+for (unsigned i = 0; i < elem_count; i++) {
+ if (bit_size == 64)
+ val->constant->value.d[i] = elems[i]->value.d[0];
+ else
+ val->constant->value.u[i] = elems[i]->value.u[0];
+}
}
ralloc_free(elems);
break;
-
+ }
case GLSL_TYPE_STRUCT:
case GLSL_TYPE_ARRAY:
ralloc_steal(val->constant, elems);
--
2.7.4
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[Mesa-dev] [PATCH 06/22] spirv: fix SpvOpSpecConstantOp with SpvOpVectorShuffle working with double-based vecs
From: Samuel Iglesias Gonsálvez
We need to pick two 32-bit values per component to perform the right shuffle
operation.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 25 +
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 9751679..02dbceb 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1089,18 +1089,35 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
unsigned len0 = glsl_get_vector_elements(v0->const_type);
unsigned len1 = glsl_get_vector_elements(v1->const_type);
- uint32_t u[8];
+ if (glsl_get_bit_size(v0->const_type) == 64)
+len0 *= 2;
+ if (glsl_get_bit_size(v1->const_type) == 64)
+len1 *= 2;
+
+ /* Allocate space for two dvec4s */
+ uint32_t u[16];
+ assert(len0 + len1 < 16);
for (unsigned i = 0; i < len0; i++)
u[i] = v0->constant->value.u[i];
for (unsigned i = 0; i < len1; i++)
u[len0 + i] = v1->constant->value.u[i];
- for (unsigned i = 0; i < count - 6; i++) {
+ unsigned bit_size = glsl_get_bit_size(val->const_type);
+ for (unsigned i = 0, j = 0; i < count - 6; i++, j++) {
uint32_t comp = w[i + 6];
+/* In case of doubles, we need to pick two 32-bit values,
+ * then we duplicate the component to pick the right values.
+ */
+if (bit_size == 64)
+ comp *= 2;
if (comp == (uint32_t)-1) {
- val->constant->value.u[i] = 0xdeadbeef;
+ val->constant->value.u[j] = 0xdeadbeef;
+ if (bit_size == 64)
+ val->constant->value.u[++j] = 0xdeadbeef;
} else {
- val->constant->value.u[i] = u[comp];
+ val->constant->value.u[j] = u[comp];
+ if (bit_size == 64)
+ val->constant->value.u[++j] = u[comp + 1];
}
}
break;
--
2.7.4
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[Mesa-dev] [PATCH 08/22] spirv: add double support to _vtn_variable_load_store
From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index 14366dc..407f449 100644 --- a/src/compiler/spirv/vtn_variables.c +++ b/src/compiler/spirv/vtn_variables.c @@ -640,6 +640,7 @@ _vtn_variable_load_store(struct vtn_builder *b, bool load, case GLSL_TYPE_INT: case GLSL_TYPE_FLOAT: case GLSL_TYPE_BOOL: + case GLSL_TYPE_DOUBLE: /* At this point, we have a scalar, vector, or matrix so we know that * there cannot be any structure splitting still in the way. By * stopping at the matrix level rather than the vector level, we -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 09/22] spirv: add double support to _vtn_block_load_store()
From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index 407f449..c02698b 100644 --- a/src/compiler/spirv/vtn_variables.c +++ b/src/compiler/spirv/vtn_variables.c @@ -443,6 +443,7 @@ _vtn_block_load_store(struct vtn_builder *b, nir_intrinsic_op op, bool load, case GLSL_TYPE_UINT: case GLSL_TYPE_INT: case GLSL_TYPE_FLOAT: + case GLSL_TYPE_DOUBLE: case GLSL_TYPE_BOOL: /* This is where things get interesting. At this point, we've hit * a vector, a scalar, or a matrix. -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 12/22] spirv/nir: implement DF conversions
From: Samuel Iglesias Gonsálvez
SPIR-V does not have special opcodes for DF conversions. We need to identify
them by checking the bit size of the operand and the result.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 29 ++---
src/compiler/spirv/vtn_alu.c | 37 +++--
src/compiler/spirv/vtn_private.h | 3 ++-
3 files changed, 51 insertions(+), 18 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index a13f72a..81c73da 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1211,12 +1211,21 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
default: {
bool swap;
- nir_op op = vtn_nir_alu_op_for_spirv_opcode(opcode, &swap);
-
- unsigned num_components = glsl_get_vector_elements(val->const_type);
unsigned bit_size =
glsl_get_bit_size(val->const_type);
+ bool is_double_dst = bit_size == 64;
+ bool is_double_src = is_double_dst;
+ /* We assume there is no double conversion here */
+ assert(bit_size != 64 ||
+(opcode != SpvOpConvertFToU && opcode != SpvOpConvertFToS &&
+ opcode != SpvOpConvertSToF && opcode != SpvOpConvertUToF &&
+ opcode != SpvOpFConvert));
+ nir_op op =
+vtn_nir_alu_op_for_spirv_opcode(opcode, &swap,
+is_double_dst, is_double_src);
+
+ unsigned num_components = glsl_get_vector_elements(val->const_type);
nir_const_value src[4];
assert(count <= 7);
for (unsigned i = 0; i < count - 4; i++) {
@@ -1224,16 +1233,22 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
vtn_value(b, w[4 + i], vtn_value_type_constant)->constant;
unsigned j = swap ? 1 - i : i;
-assert(bit_size == 32);
for (unsigned k = 0; k < num_components; k++)
- src[j].u32[k] = c->value.u[k];
+ if (!is_double_src)
+ src[j].u32[k] = c->value.u[k];
+ else
+ src[j].f64[k] = c->value.d[k];
}
nir_const_value res = nir_eval_const_opcode(op, num_components,
bit_size, src);
- for (unsigned k = 0; k < num_components; k++)
-val->constant->value.u[k] = res.u32[k];
+ for (unsigned k = 0; k < num_components; k++) {
+if (!is_double_dst)
+ val->constant->value.u[k] = res.u32[k];
+else
+ val->constant->value.d[k] = res.f64[k];
+ }
break;
} /* default */
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 95ff2b1..e444d3f 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -211,7 +211,8 @@ vtn_handle_matrix_alu(struct vtn_builder *b, SpvOp opcode,
}
nir_op
-vtn_nir_alu_op_for_spirv_opcode(SpvOp opcode, bool *swap)
+vtn_nir_alu_op_for_spirv_opcode(SpvOp opcode, bool *swap,
+bool is_double_dst, bool is_double_src)
{
/* Indicates that the first two arguments should be swapped. This is
* used for implementing greater-than and less-than-or-equal.
@@ -284,16 +285,21 @@ vtn_nir_alu_op_for_spirv_opcode(SpvOp opcode, bool *swap)
case SpvOpFUnordGreaterThanEqual: return nir_op_fge;
/* Conversions: */
- case SpvOpConvertFToU: return nir_op_f2u;
- case SpvOpConvertFToS: return nir_op_f2i;
- case SpvOpConvertSToF: return nir_op_i2f;
- case SpvOpConvertUToF: return nir_op_u2f;
+ case SpvOpConvertFToU: return is_double_src ? nir_op_d2u :
nir_op_f2u;
+ case SpvOpConvertFToS: return is_double_src ? nir_op_d2i :
nir_op_f2i;
+ case SpvOpConvertSToF: return is_double_dst ? nir_op_i2d :
nir_op_i2f;
+ case SpvOpConvertUToF: return is_double_dst ? nir_op_u2d :
nir_op_u2f;
case SpvOpBitcast: return nir_op_imov;
case SpvOpUConvert:
case SpvOpQuantizeToF16: return nir_op_fquantize2f16;
- /* TODO: NIR is 32-bit only; these are no-ops. */
+ /* TODO: int64 is not supported yet. This is a no-op. */
case SpvOpSConvert: return nir_op_imov;
- case SpvOpFConvert: return nir_op_fmov;
+ case SpvOpFConvert:
+ if (is_double_src && !is_double_dst)
+ return nir_op_d2f;
+ if (!is_double_src && is_double_dst)
+ return nir_op_f2d;
+ return nir_op_fmov;
/* Derivatives: */
case SpvOpDPdx: return nir_op_fddx;
@@ -457,7 +463,10 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
case SpvOpFUnordLessThanEqual:
case SpvOpFUnordGreaterThanEqual: {
bool swap;
- nir_op op = vtn_nir_alu_op_for_sp
[Mesa-dev] [PATCH 11/22] spirv: add support for doubles on OpComposite{Insert, Extract}
From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/spirv_to_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 3bc23d3..a13f72a 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -1147,6 +1147,7 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode, case GLSL_TYPE_UINT: case GLSL_TYPE_INT: case GLSL_TYPE_FLOAT: +case GLSL_TYPE_DOUBLE: case GLSL_TYPE_BOOL: /* If we hit this granularity, we're picking off an element */ if (elem < 0) -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 10/22] spirv: Enable double floating points when copying variables in _vtn_variable_copy()
From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index c02698b..8b01da3 100644 --- a/src/compiler/spirv/vtn_variables.c +++ b/src/compiler/spirv/vtn_variables.c @@ -717,6 +717,7 @@ _vtn_variable_copy(struct vtn_builder *b, struct vtn_access_chain *dest, case GLSL_TYPE_UINT: case GLSL_TYPE_INT: case GLSL_TYPE_FLOAT: + case GLSL_TYPE_DOUBLE: case GLSL_TYPE_BOOL: /* At this point, we have a scalar, vector, or matrix so we know that * there cannot be any structure splitting still in the way. By -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 13/22] spirv/nir: add (un)packDouble2x32() translation
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index cb0570d..01df1dd 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -399,11 +399,13 @@ vtn_nir_alu_op_for_spirv_glsl_opcode(enum GLSLstd450
opcode)
case GLSLstd450PackSnorm2x16:return nir_op_pack_snorm_2x16;
case GLSLstd450PackUnorm2x16:return nir_op_pack_unorm_2x16;
case GLSLstd450PackHalf2x16: return nir_op_pack_half_2x16;
+ case GLSLstd450PackDouble2x32: return nir_op_pack_double_2x32;
case GLSLstd450UnpackSnorm4x8: return nir_op_unpack_snorm_4x8;
case GLSLstd450UnpackUnorm4x8: return nir_op_unpack_unorm_4x8;
case GLSLstd450UnpackSnorm2x16: return nir_op_unpack_snorm_2x16;
case GLSLstd450UnpackUnorm2x16: return nir_op_unpack_unorm_2x16;
case GLSLstd450UnpackHalf2x16: return nir_op_unpack_half_2x16;
+ case GLSLstd450UnpackDouble2x32: return nir_op_unpack_double_2x32;
default:
unreachable("No NIR equivalent");
--
2.7.4
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[Mesa-dev] [PATCH 15/22] anv/pipeline: get map for double input attributes
--- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 27217b9..7c26cce 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -476,6 +476,7 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline, ralloc_steal(mem_ctx, nir); prog_data.inputs_read = nir->info->inputs_read; + prog_data.double_inputs_read = nir->info->double_inputs_read; brw_compute_vue_map(&pipeline->device->info, &prog_data.base.vue_map, -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 14/22] spirv: add support for doubles to OpSpecConstant
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/amd/vulkan/radv_pipeline.c| 5 +++-
src/compiler/spirv/nir_spirv.h| 5 +++-
src/compiler/spirv/spirv_to_nir.c | 54 ++-
src/intel/vulkan/anv_pipeline.c | 5 +++-
4 files changed, 60 insertions(+), 9 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 7d7d0c6..ee5d812 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -188,7 +188,10 @@ radv_shader_compile_to_nir(struct radv_device *device,
assert(data + entry.size <= spec_info->pData +
spec_info->dataSize);
spec_entries[i].id =
spec_info->pMapEntries[i].constantID;
- spec_entries[i].data = *(const uint32_t *)data;
+if (spec_info->dataSize == 8)
+ spec_entries[i].data64 = *(const uint64_t
*)data;
+else
+ spec_entries[i].data32 = *(const uint32_t
*)data;
}
}
diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_spirv.h
index 500f2cb..33a2781 100644
--- a/src/compiler/spirv/nir_spirv.h
+++ b/src/compiler/spirv/nir_spirv.h
@@ -38,7 +38,10 @@ extern "C" {
struct nir_spirv_specialization {
uint32_t id;
- uint32_t data;
+ union {
+ uint32_t data32;
+ uint64_t data64;
+ };
};
nir_function *spirv_to_nir(const uint32_t *words, size_t word_count,
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 81c73da..82d81aa 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -31,6 +31,14 @@
#include "nir/nir_constant_expressions.h"
#include "spirv_info.h"
+struct spec_constant_value {
+ bool is_double;
+ union {
+ uint32_t data32;
+ uint64_t data64;
+ };
+};
+
void
_vtn_warn(const char *file, int line, const char *msg, ...)
{
@@ -952,11 +960,14 @@ spec_constant_decoration_cb(struct vtn_builder *b, struct
vtn_value *v,
if (dec->decoration != SpvDecorationSpecId)
return;
- uint32_t *const_value = data;
+ struct spec_constant_value *const_value = data;
for (unsigned i = 0; i < b->num_specializations; i++) {
if (b->specializations[i].id == dec->literals[0]) {
- *const_value = b->specializations[i].data;
+ if (const_value->is_double)
+const_value->data64 = b->specializations[i].data64;
+ else
+const_value->data32 = b->specializations[i].data32;
return;
}
}
@@ -966,8 +977,22 @@ static uint32_t
get_specialization(struct vtn_builder *b, struct vtn_value *val,
uint32_t const_value)
{
- vtn_foreach_decoration(b, val, spec_constant_decoration_cb, &const_value);
- return const_value;
+ struct spec_constant_value data;
+ data.is_double = false;
+ data.data32 = const_value;
+ vtn_foreach_decoration(b, val, spec_constant_decoration_cb, &data);
+ return data.data32;
+}
+
+static uint64_t
+get_specialization64(struct vtn_builder *b, struct vtn_value *val,
+ uint64_t const_value)
+{
+ struct spec_constant_value data;
+ data.is_double = true;
+ data.data64 = const_value;
+ vtn_foreach_decoration(b, val, spec_constant_decoration_cb, &data);
+ return data.data64;
}
static void
@@ -1026,10 +1051,27 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
}
break;
}
- case SpvOpSpecConstant:
+ case SpvOpSpecConstant: {
assert(glsl_type_is_scalar(val->const_type));
- val->constant->value.u[0] = get_specialization(b, val, w[3]);
+ int bit_size = glsl_get_bit_size(val->const_type);
+ if (bit_size == 64) {
+ union {
+double d;
+uint64_t u64;
+struct {
+ uint32_t u1;
+ uint32_t u2;
+};
+ } di;
+ di.u1 = w[3];
+ di.u2 = w[4];
+ di.u64 = get_specialization64(b, val, di.u64);
+ val->constant->value.d[0] = di.d;
+ } else {
+ val->constant->value.u[0] = get_specialization(b, val, w[3]);
+ }
break;
+ }
case SpvOpSpecConstantComposite:
case SpvOpConstantComposite: {
unsigned elem_count = count - 3;
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 9b65e35..27217b9 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -117,7 +117,10 @@ anv_shader_compile_to_nir(struct anv_device *device,
assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
spec_entries[i].id = spec_info->pMapEntries[i].constantID;
- spec_entries[i].data = *(const uint32_t *)data;
+ if (spec_info->dataSize == 8)
+spec_entries[i]
[Mesa-dev] [PATCH 16/22] isl: fix VA64 support for double and dvecN vertex attributes
From: Samuel Iglesias Gonsálvez
We use *64*_PASSTHRU formats to upload vertex attributes of 64 bits
to avoid conversions. From the BDW PRM, Volume 2d, page 586
(VERTEX_ELEMENT_STATE):
"When SourceElementFormat is set to one of the *64*_PASSTHRU
formats, 64-bit components are stored in the URB without any
conversion. In this case, vertex elements must be written as 128
or 256 bits, with VFCOMP_STORE_0 being used to pad the output
as required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
component into the URB, Component 1 must be specified as
VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE)
in order to output a 128-bit vertex element, or Components 1-3 must
be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
to be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
element."
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/isl/isl_format.c | 4 ++--
src/intel/isl/isl_format_layout.csv | 3 ---
src/intel/vulkan/anv_formats.c | 8
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index 98806f4..92b630a 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -97,7 +97,7 @@ static const struct surface_format_info format_info[] = {
SF( x, x, x, x, x, x, Y, x, x,x, R32G32B32A32_SSCALED)
SF( x, x, x, x, x, x, Y, x, x,x, R32G32B32A32_USCALED)
SF( x, x, x, x, x, x, 75, x, x,x, R32G32B32A32_SFIXED)
- SF( x, x, x, x, x, x, x, x, x,x, R64G64_PASSTHRU)
+ SF( x, x, x, x, x, x, 80, x, x,x, R64G64_PASSTHRU)
SF( Y, 50, x, x, x, x, Y, Y, x,x, R32G32B32_FLOAT)
SF( Y, x, x, x, x, x, Y, Y, x,x, R32G32B32_SINT)
SF( Y, x, x, x, x, x, Y, Y, x,x, R32G32B32_UINT)
@@ -131,7 +131,7 @@ static const struct surface_format_info format_info[] = {
SF( x, x, x, x, x, x, Y, x, x,x, R32G32_SSCALED)
SF( x, x, x, x, x, x, Y, x, x,x, R32G32_USCALED)
SF( x, x, x, x, x, x, 75, x, x,x, R32G32_SFIXED)
- SF( x, x, x, x, x, x, x, x, x,x, R64_PASSTHRU)
+ SF( x, x, x, x, x, x, 80, x, x,x, R64_PASSTHRU)
SF( Y, Y, x, Y, Y, Y, Y, x, 60, 90, B8G8R8A8_UNORM)
SF( Y, Y, x, x, Y, Y, x, x, x,x, B8G8R8A8_UNORM_SRGB)
/* smpl filt shad CK RT AB VB SO color ccs_e */
diff --git a/src/intel/isl/isl_format_layout.csv
b/src/intel/isl/isl_format_layout.csv
index f0f31c7..b1e298b 100644
--- a/src/intel/isl/isl_format_layout.csv
+++ b/src/intel/isl/isl_format_layout.csv
@@ -96,7 +96,6 @@ X32_TYPELESS_G8X24_UINT , 64, 1, 1, 1, x32, ui8,
x24, , ,
L32A32_FLOAT, 64, 1, 1, 1, , , , sf32, sf32,
,, linear,
R32G32_UNORM, 64, 1, 1, 1, un32, un32, , , ,
,, linear,
R32G32_SNORM, 64, 1, 1, 1, sn32, sn32, , , ,
,, linear,
-R64_FLOAT , 64, 1, 1, 1, sf64, , , , ,
,, linear,
R16G16B16X16_UNORM , 64, 1, 1, 1, un16, un16, un16, x16, ,
,, linear,
R16G16B16X16_FLOAT , 64, 1, 1, 1, sf16, sf16, sf16, x16, ,
,, linear,
A32X32_FLOAT, 64, 1, 1, 1, , , , sf32, x32,
,, alpha,
@@ -243,8 +242,6 @@ R8G8B8_UNORM, 24, 1, 1, 1, un8, un8,
un8, , ,
R8G8B8_SNORM, 24, 1, 1, 1, sn8, sn8, sn8, , ,
,, linear,
R8G8B8_SSCALED , 24, 1, 1, 1, ss8, ss8, ss8, , ,
,, linear,
R8G8B8_USCALED , 24, 1, 1, 1, us8, us8, us8, , ,
,, linear,
-R64G64B64A64_FLOAT , 256, 1, 1, 1, sf64, sf64, sf64, sf64, ,
,, linear,
-R64G64B64_FLOAT , 196, 1, 1, 1, sf64, sf64, sf64, , ,
,, linear,
BC4_SNORM , 64, 4, 4, 1, sn8, , , , ,
,, linear, rgtc1
BC5_SNORM , 128, 4, 4, 1, sn8, sn8, , , ,
,, linear, rgtc2
R16G16B16_FLOAT , 48, 1, 1, 1, sf16, sf16, sf16, , ,
,, linear,
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 9ef998c..39810d4 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -156,16 +156,16 @@ static const struct anv_format anv_formats[] = {
fmt(VK_FORMAT_R32G32B32A32_SFLOAT, ISL_FORMAT_R32G32B32A32_FLOAT),
fmt(VK_FORMAT_R64_UINT,ISL_FORMAT_R64_PASSTHRU),
fmt(VK_FORMAT_R64_SINT,ISL_FORMAT_R64_PASSTHRU),
- fmt(VK_FORMAT_R64_SFLOAT, ISL_FORMAT_R64_FLOA
[Mesa-dev] [PATCH 17/22] nir: Add flag to detect platforms with native float64 support
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 3e6d168..1679d89 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1777,6 +1777,11 @@ typedef struct nir_shader_compiler_options {
*/
bool native_integers;
+ /**
+* Does the driver support 64-bit floats?
+*/
+ bool native_float64;
+
/* Indicates that the driver only has zero-based vertex id */
bool vertex_id_zero_based;
--
2.7.4
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[Mesa-dev] [PATCH 18/22] spirv: Add nir_options to vtn_builder
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 1 +
src/compiler/spirv/vtn_private.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 82d81aa..70e45c1 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3096,6 +3096,7 @@ spirv_to_nir(const uint32_t *words, size_t word_count,
exec_list_make_empty(&b->functions);
b->entry_point_stage = stage;
b->entry_point_name = entry_point_name;
+ b->nir_options = options;
/* Handle all the preamble instructions */
words = vtn_foreach_instruction(b, words, word_end,
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index 7159f8b..cc841e7 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -344,6 +344,7 @@ struct vtn_decoration {
struct vtn_builder {
nir_builder nb;
+ const nir_shader_compiler_options *nir_options;
nir_shader *shader;
nir_function_impl *impl;
--
2.7.4
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[Mesa-dev] [PATCH 19/22] anv/nir: add support for dvec3/4 consuming two locations
One difference between OpenGL and Vulkan regarding 64-bit vertex
attribute types is that dvec3 and dvec4 consumes just one location in
OpenGL, while in Vulkan it consumes two locations.
Thus, in OpenGL for each dvec3/dvec4 vertex attrib we mark just one bit
in our internal inputs_read bitmap (and also the corresponding bit in
double_inputs_read bitmap) while in Vulkan we mark two consecutive bits
in both bitmaps.
This is handled with a nir option called "dvec3_consumes_two_locations",
which is set to True for Vulkan code. And all the computation regarding
emitting vertices as well as the mapping between attributes and physical
registers use this option to correctly do the work.
---
src/amd/vulkan/radv_pipeline.c | 1 +
src/compiler/nir/nir.h | 5 +++
src/compiler/nir/nir_gather_info.c | 6 +--
src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 +
src/intel/vulkan/anv_device.c| 2 +-
src/intel/vulkan/genX_pipeline.c | 62 +---
src/mesa/drivers/dri/i965/brw_compiler.c | 23 ++-
src/mesa/drivers/dri/i965/brw_compiler.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 +--
src/mesa/drivers/dri/i965/brw_nir.c | 18 +---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 --
src/mesa/drivers/dri/i965/intel_screen.c | 3 +-
12 files changed, 105 insertions(+), 45 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index ee5d812..90d4650 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -59,6 +59,7 @@ static const struct nir_shader_compiler_options nir_options =
{
.lower_unpack_unorm_4x8 = true,
.lower_extract_byte = true,
.lower_extract_word = true,
+ .dvec3_consumes_two_locations = true,
};
VkResult radv_CreateShaderModule(
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 1679d89..0fc8f39 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1794,6 +1794,11 @@ typedef struct nir_shader_compiler_options {
* information must be inferred from the list of input nir_variables.
*/
bool use_interpolated_input_intrinsics;
+
+ /**
+* In Vulkan, a dvec3/dvec4 consumes two locations instead just one.
+*/
+ bool dvec3_consumes_two_locations;
} nir_shader_compiler_options;
typedef struct nir_shader {
diff --git a/src/compiler/nir/nir_gather_info.c
b/src/compiler/nir/nir_gather_info.c
index 07c9949..8c80671 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -96,7 +96,7 @@ mark_whole_variable(nir_shader *shader, nir_variable *var)
const unsigned slots =
var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
-: glsl_count_attribute_slots(type, is_vertex_input);
+: glsl_count_attribute_slots(type, is_vertex_input &&
!shader->options->dvec3_consumes_two_locations);
set_io_mask(shader, var, 0, slots);
}
@@ -168,7 +168,7 @@ try_mask_partial_io(nir_shader *shader, nir_deref_var
*deref)
var->data.mode == nir_var_shader_in)
is_vertex_input = true;
- unsigned offset = get_io_offset(deref, is_vertex_input);
+ unsigned offset = get_io_offset(deref, is_vertex_input &&
!shader->options->dvec3_consumes_two_locations);
if (offset == -1)
return false;
@@ -184,7 +184,7 @@ try_mask_partial_io(nir_shader *shader, nir_deref_var
*deref)
}
/* double element width for double types that takes two slots */
- if (!is_vertex_input &&
+ if ((!is_vertex_input || shader->options->dvec3_consumes_two_locations) &&
glsl_type_is_dual_slot(glsl_without_array(type))) {
elem_width *= 2;
}
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
index 2d86a52..5c5c9ad 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
@@ -50,6 +50,7 @@ static const nir_shader_compiler_options options = {
.vertex_id_zero_based = true,
.lower_extract_byte = true,
.lower_extract_word = true,
+ .dvec3_consumes_two_locations = false,
};
struct nir_shader *
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 2c8ac49..725848f 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -167,7 +167,7 @@ anv_physical_device_init(struct anv_physical_device *device,
brw_process_intel_debug_variable();
- device->compiler = brw_compiler_create(NULL, &device->info);
+ device->compiler = brw_compiler_create(NULL, &device->info, true);
if (device->compiler == NULL) {
result = vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
goto fail;
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index cb164ad..97c40b8 100644
--- a/src/intel/v
[Mesa-dev] [PATCH 20/22] spirv: enable SpvCapabilityFloat64 only to supported platforms
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 70e45c1..ae35e83 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -2560,6 +2560,13 @@ vtn_handle_preamble_instruction(struct vtn_builder *b,
SpvOp opcode,
case SpvCapabilityInputAttachment:
break;
+ case SpvCapabilityFloat64:
+ if (!b->nir_options->native_float64) {
+vtn_warn("Unsupported SPIR-V capability: %s",
+ spirv_capability_to_string(cap));
+ }
+ break;
+
case SpvCapabilityGeometryStreams:
case SpvCapabilityTessellation:
case SpvCapabilityTessellationPointSize:
@@ -2567,7 +2574,6 @@ vtn_handle_preamble_instruction(struct vtn_builder *b,
SpvOp opcode,
case SpvCapabilityVector16:
case SpvCapabilityFloat16Buffer:
case SpvCapabilityFloat16:
- case SpvCapabilityFloat64:
case SpvCapabilityInt64:
case SpvCapabilityInt64Atomics:
case SpvCapabilityAtomicStorage:
--
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[Mesa-dev] [PATCH 21/22] i965: enable nir_option's native_float64 to supported generations
From: Samuel Iglesias Gonsálvez
Currently, gen8+ supports ARB_gpu_shader_fp64 in mesa master.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_compiler.c | 53 +---
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c
b/src/mesa/drivers/dri/i965/brw_compiler.c
index b9eceeb..b88ea7a 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.c
+++ b/src/mesa/drivers/dri/i965/brw_compiler.c
@@ -43,33 +43,36 @@
.use_interpolated_input_intrinsics = true, \
.vertex_id_zero_based = true
-static const struct nir_shader_compiler_options scalar_nir_options = {
+#define COMMON_SCALAR_NIR_OPTIONS \
+ .lower_pack_half_2x16 = true, \
+ .lower_pack_snorm_2x16 = true, \
+ .lower_pack_snorm_4x8 = true, \
+ .lower_pack_unorm_2x16 = true, \
+ .lower_pack_unorm_4x8 = true, \
+ .lower_unpack_half_2x16 = true,\
+ .lower_unpack_snorm_2x16 = true, \
+ .lower_unpack_snorm_4x8 = true,\
+ .lower_unpack_unorm_2x16 = true, \
+ .lower_unpack_unorm_4x8 = true
+
+static const struct nir_shader_compiler_options scalar_nir_options_pre_gen8 = {
COMMON_OPTIONS,
- .lower_pack_half_2x16 = true,
- .lower_pack_snorm_2x16 = true,
- .lower_pack_snorm_4x8 = true,
- .lower_pack_unorm_2x16 = true,
- .lower_pack_unorm_4x8 = true,
- .lower_unpack_half_2x16 = true,
- .lower_unpack_snorm_2x16 = true,
- .lower_unpack_snorm_4x8 = true,
- .lower_unpack_unorm_2x16 = true,
- .lower_unpack_unorm_4x8 = true,
+ COMMON_SCALAR_NIR_OPTIONS,
+ .native_float64 = false,
.dvec3_consumes_two_locations = false,
};
-static const struct nir_shader_compiler_options vulkan_scalar_nir_options = {
+static const struct nir_shader_compiler_options scalar_nir_options_gen8 = {
COMMON_OPTIONS,
- .lower_pack_half_2x16 = true,
- .lower_pack_snorm_2x16 = true,
- .lower_pack_snorm_4x8 = true,
- .lower_pack_unorm_2x16 = true,
- .lower_pack_unorm_4x8 = true,
- .lower_unpack_half_2x16 = true,
- .lower_unpack_snorm_2x16 = true,
- .lower_unpack_snorm_4x8 = true,
- .lower_unpack_unorm_2x16 = true,
- .lower_unpack_unorm_4x8 = true,
+ COMMON_SCALAR_NIR_OPTIONS,
+ .native_float64 = true,
+ .dvec3_consumes_two_locations = false,
+};
+
+static const struct nir_shader_compiler_options vulkan_scalar_nir_options_gen8
= {
+ COMMON_OPTIONS,
+ COMMON_SCALAR_NIR_OPTIONS,
+ .native_float64 = true,
.dvec3_consumes_two_locations = true,
};
@@ -156,8 +159,10 @@ brw_compiler_create(void *mem_ctx, const struct
gen_device_info *devinfo, bool i
compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
if (is_scalar) {
- compiler->glsl_compiler_options[i].NirOptions = is_vulkan ?
&vulkan_scalar_nir_options
- :
&scalar_nir_options;
+ compiler->glsl_compiler_options[i].NirOptions =
+(devinfo->gen >= 8) ? (is_vulkan ? &vulkan_scalar_nir_options_gen8
+ : &scalar_nir_options_gen8)
+: &scalar_nir_options_pre_gen8;
} else {
compiler->glsl_compiler_options[i].NirOptions =
devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
--
2.7.4
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[Mesa-dev] [PATCH 22/22] anv: enable shaderFloat64 feature
From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 725848f..9f53fc9 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -441,7 +441,7 @@ void anv_GetPhysicalDeviceFeatures( .shaderStorageImageWriteWithoutFormat = true, .shaderClipDistance = true, .shaderCullDistance = true, - .shaderFloat64= false, + .shaderFloat64= pdevice->info.gen >= 8, .shaderInt64 = false, .shaderInt16 = false, .alphaToOne = true, -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] Mesa 13.1.0 release plan
On Thu, 2016-12-01 at 21:29 +0100, Marek Olšák wrote: > On Wed, Nov 30, 2016 at 9:23 PM, Emil Velikov om> wrote: > > Hi all, > > > > With holidays not far off, it might be a nice idea to consider the > > branchpoint/release schedule for the next release. > > > > I will be having limited internet access during 20 Dec - 7 Jan, > > thus > > the I'm leaning towards following: > > Jan 13 2017 - Feature freeze/Release candidate 1 > > Jan 20 2017 - Release candidate 2 > > Jan 27 2017 - Release candidate 3 > > Feb 03 2017 - Release candidate 4/final release > > Sounds like a good plan for 17.0. :) +1 J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: allow unsourced enabled VAO
On Thu, 2016-11-03 at 11:02 +0100, Juan A. Suarez Romero wrote: > The GL 4.5 spec says: > "If any enabled array’s buffer binding is zero when DrawArrays > or one of the other drawing commands defined in section 10.4 is > called, the result is undefined." > > This commits avoids crashing the code, which is not a very good > "undefined result". > Gently pinging someone that could review it. J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/5] st/va: remove unsed variable
On Thu, 2016-11-24 at 13:36 +0100, Juan A. Suarez Romero wrote: > pbuff is defined but not used. > --- > src/gallium/state_trackers/va/surface.c | 1 - > 1 file changed, 1 deletion(-) > > Gently ping someone to review it. J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 19/22] anv/nir: add support for dvec3/4 consuming two locations
On Thu, 2016-12-01 at 22:22 -0800, Jason Ekstrand wrote:
> +Ken
>
> On Thu, Dec 1, 2016 at 10:17 PM, Jason Ekstrand > wrote:
> > I'm not sure how I feel about this one. It seems like it would
> > almost be easier to just pick one convention or the other for NIR
> > and adjust one of the drivers accordingly. I don't know that I
> > have a huge preference which convention we choose. I guess the
> > Vulkan convention matches our hardware a bit better. In either
> > case, converting from one to the other should be a simple matter of
> > building a remap table or a creative use of popcount.
> >
As you said in another email, I also think it would be more easy to
just mark 2 bits per dvec3/dvec4 in inputs_read and change the GL
driver accordingly, than the other way around, as it is done in TGSI.
> > On Fri, Nov 25, 2016 at 12:52 AM, Juan A. Suarez Romero > galia.com> wrote:
> > > One difference between OpenGL and Vulkan regarding 64-bit vertex
> > >
> > > attribute types is that dvec3 and dvec4 consumes just one
> > > location in
> > >
> > > OpenGL, while in Vulkan it consumes two locations.
> > >
> > >
> > >
> > > Thus, in OpenGL for each dvec3/dvec4 vertex attrib we mark just
> > > one bit
> > >
> > > in our internal inputs_read bitmap (and also the corresponding
> > > bit in
> > >
> > > double_inputs_read bitmap) while in Vulkan we mark two
> > > consecutive bits
> > >
> > > in both bitmaps.
> > >
> > >
> > >
> > > This is handled with a nir option called
> > > "dvec3_consumes_two_locations",
> > >
> > > which is set to True for Vulkan code. And all the computation
> > > regarding
> > >
> > > emitting vertices as well as the mapping between attributes and
> > > physical
> > >
> > > registers use this option to correctly do the work.
> > >
> > > ---
> > >
> > > src/amd/vulkan/radv_pipeline.c | 1 +
> > >
> > > src/compiler/nir/nir.h | 5 +++
> > >
> > > src/compiler/nir/nir_gather_info.c | 6 +--
> > >
> > > src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 +
> > >
> > > src/intel/vulkan/anv_device.c | 2 +-
> > >
> > > src/intel/vulkan/genX_pipeline.c | 62
> > > +---
> > >
> > > src/mesa/drivers/dri/i965/brw_compiler.c | 23 ++-
> > >
> > > src/mesa/drivers/dri/i965/brw_compiler.h | 2 +-
> > >
> > > src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 +--
> > >
> > > src/mesa/drivers/dri/i965/brw_nir.c | 18 +---
> > >
> > > src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 --
> > >
> > > src/mesa/drivers/dri/i965/intel_screen.c | 3 +-
> > >
> > > 12 files changed, 105 insertions(+), 45 deletions(-)
> > >
> > >
> > >
> > > diff --git a/src/amd/vulkan/radv_pipeline.c
> > > b/src/amd/vulkan/radv_pipeline.c
> > >
> > > index ee5d812..90d4650 100644
> > >
> > > --- a/src/amd/vulkan/radv_pipeline.c
> > >
> > > +++ b/src/amd/vulkan/radv_pipeline.c
> > >
> > > @@ -59,6 +59,7 @@ static const struct nir_shader_compiler_options
> > > nir_options = {
> > >
> > > .lower_unpack_unorm_4x8 = true,
> > >
> > > .lower_extract_byte = true,
> > >
> > > .lower_extract_word = true,
> > >
> > > + .dvec3_consumes_two_locations = true,
> > >
> > > };
> > >
> > >
> > >
> > > VkResult radv_CreateShaderModule(
> > >
> > > diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> > >
> > > index 1679d89..0fc8f39 100644
> > >
> > > --- a/src/compiler/nir/nir.h
> > >
> > > +++ b/src/compiler/nir/nir.h
> > >
> > > @@ -1794,6 +1794,11 @@ typedef struct nir_shader_compiler_options
> > > {
> > >
> > > * information must be inferred from the list of input
> > > nir_variables.
> > >
> > > */
> > >
> > > bool use_interpolated_input_intrinsics;
> > >
> > > +
> > >
> > > + /**
> > >
> > > +
[Mesa-dev] [PATCH v2 00/25] Enable Float64 capability support for Intel's Vulkan driver
This patch series is a second iteration of previous one:
https://lists.freedesktop.org/archives/mesa-dev/2016-November/136507.html
Main changes are the ones suggested by Jason, and also a refactor of the way
inputs_read bitmap is used in NIR.
If you want to test these patches, you can clone our branch with the following
command:
$ git clone -b spirv-to-nir-rc2 https://github.com/Igalia/mesa.github
Thanks,
J.A.
Juan A. Suarez Romero (2):
anv/pipeline: get map for double input attributes
nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input
attributes
Samuel Iglesias Gonsálvez (23):
spirv: fix typo in spec_constant_decoration_cb()
spirv: add definition of double based data types
spirv: add support for loading DF constants
spirv: add DF support to vtn_const_ssa_value()
spirv: add DF support to SpvOp*ConstantComposite
spirv: fix SpvOpSpecConstantOp with SpvOpVectorShuffle working with
double-based vecs
spirv: add double support to SpvOpCompositeExtract
spirv: add double support to _vtn_variable_load_store
spirv: add double support to _vtn_block_load_store()
spirv: Enable double floating points when copying variables in
_vtn_variable_copy()
spirv: add support for doubles on OpComposite{Insert,Extract}
compiler/nir: add glsl_type_is_{float,integer}()
nir: add nir_get_nir_type_for_glsl_type()
nir: add nir_type_conversion_op()
spirv/nir: implement DF conversions
spirv/nir: add (un)packDouble2x32() translation
spirv: add support for doubles to OpSpecConstant
isl: fix VA64 support for double and dvecN vertex attributes
nir: Add flag to detect platforms with native float64 support
spirv: Add nir_options to vtn_builder
spirv: enable SpvCapabilityFloat64 only to supported platforms
i965: enable nir_option's native_float64 to supported generations
anv: enable shaderFloat64 feature
src/amd/vulkan/radv_pipeline.c | 5 +-
src/compiler/glsl/glsl_to_nir.cpp| 28 ++
src/compiler/nir/nir.c | 83
src/compiler/nir/nir.h | 26 +
src/compiler/nir/nir_gather_info.c | 48 +
src/compiler/nir_types.cpp | 15 +++
src/compiler/nir_types.h | 2 +
src/compiler/spirv/nir_spirv.h | 5 +-
src/compiler/spirv/spirv_to_nir.c| 141 ++-
src/compiler/spirv/vtn_alu.c | 29 +++---
src/compiler/spirv/vtn_glsl450.c | 2 +
src/compiler/spirv/vtn_private.h | 4 +-
src/compiler/spirv/vtn_variables.c | 3 +
src/intel/isl/isl_format.c | 4 +-
src/intel/isl/isl_format_layout.csv | 1 -
src/intel/vulkan/anv_device.c| 2 +-
src/intel/vulkan/anv_formats.c | 8 +-
src/intel/vulkan/anv_pipeline.c | 6 +-
src/intel/vulkan/genX_pipeline.c | 63 +++-
src/mesa/drivers/dri/i965/brw_compiler.c | 36 ---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 11 ++-
src/mesa/drivers/dri/i965/brw_fs.cpp | 13 ---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 3 +-
src/mesa/drivers/dri/i965/brw_nir.c | 6 +-
src/mesa/drivers/dri/i965/brw_nir.h | 1 -
src/mesa/drivers/dri/i965/brw_vec4.cpp | 11 +--
26 files changed, 419 insertions(+), 137 deletions(-)
--
2.9.3
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[Mesa-dev] [PATCH v2 01/25] spirv: fix typo in spec_constant_decoration_cb()
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index f60c6e6..76faf27 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -930,7 +930,7 @@ vtn_null_constant(struct vtn_builder *b, const struct
glsl_type *type)
}
static void
-spec_constant_deocoration_cb(struct vtn_builder *b, struct vtn_value *v,
+spec_constant_decoration_cb(struct vtn_builder *b, struct vtn_value *v,
int member, const struct vtn_decoration *dec,
void *data)
{
@@ -952,7 +952,7 @@ static uint32_t
get_specialization(struct vtn_builder *b, struct vtn_value *val,
uint32_t const_value)
{
- vtn_foreach_decoration(b, val, spec_constant_deocoration_cb, &const_value);
+ vtn_foreach_decoration(b, val, spec_constant_decoration_cb, &const_value);
return const_value;
}
--
2.9.3
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[Mesa-dev] [PATCH v2 02/25] spirv: add definition of double based data types
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 76faf27..5b16d50 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -704,9 +704,11 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
val->type->type = (signedness ? glsl_int_type() : glsl_uint_type());
break;
}
- case SpvOpTypeFloat:
- val->type->type = glsl_float_type();
+ case SpvOpTypeFloat: {
+ int bit_size = w[2];
+ val->type->type = bit_size == 64 ? glsl_double_type() :
glsl_float_type();
break;
+ }
case SpvOpTypeVector: {
struct vtn_type *base = vtn_value(b, w[2], vtn_value_type_type)->type;
--
2.9.3
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[Mesa-dev] [PATCH v2 04/25] spirv: add DF support to vtn_const_ssa_value()
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index c162964..3fa1d8e 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -98,11 +98,12 @@ vtn_const_ssa_value(struct vtn_builder *b, nir_constant
*constant,
case GLSL_TYPE_UINT:
case GLSL_TYPE_BOOL:
case GLSL_TYPE_FLOAT:
- case GLSL_TYPE_DOUBLE:
+ case GLSL_TYPE_DOUBLE: {
+ int bit_size = glsl_get_bit_size(type);
if (glsl_type_is_vector_or_scalar(type)) {
unsigned num_components = glsl_get_vector_elements(val->type);
nir_load_const_instr *load =
-nir_load_const_instr_create(b->shader, num_components, 32);
+nir_load_const_instr_create(b->shader, num_components, bit_size);
load->value = constant->values[0];
@@ -118,7 +119,7 @@ vtn_const_ssa_value(struct vtn_builder *b, nir_constant
*constant,
struct vtn_ssa_value *col_val = rzalloc(b, struct vtn_ssa_value);
col_val->type = glsl_get_column_type(val->type);
nir_load_const_instr *load =
- nir_load_const_instr_create(b->shader, rows, 32);
+ nir_load_const_instr_create(b->shader, rows, bit_size);
load->value = constant->values[i];
@@ -129,6 +130,7 @@ vtn_const_ssa_value(struct vtn_builder *b, nir_constant
*constant,
}
}
break;
+ }
case GLSL_TYPE_ARRAY: {
unsigned elems = glsl_get_length(val->type);
--
2.9.3
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[Mesa-dev] [PATCH v2 03/25] spirv: add support for loading DF constants
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 5b16d50..c162964 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1003,10 +1003,17 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
break;
}
- case SpvOpConstant:
+ case SpvOpConstant: {
assert(glsl_type_is_scalar(val->const_type));
- val->constant->values[0].u32[0] = w[3];
+ int bit_size = glsl_get_bit_size(val->const_type);
+ if (bit_size == 64) {
+ val->constant->values->u32[0] = w[3];
+ val->constant->values->u32[1] = w[4];
+ } else {
+ val->constant->values->u32[0] = w[3];
+ }
break;
+ }
case SpvOpSpecConstant:
assert(glsl_type_is_scalar(val->const_type));
val->constant->values[0].u32[0] = get_specialization(b, val, w[3]);
--
2.9.3
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[Mesa-dev] [PATCH v2 07/25] spirv: add double support to SpvOpCompositeExtract
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 5126dc9..60cc988 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1166,8 +1166,12 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
val->constant = *c;
} else {
unsigned num_components = glsl_get_vector_elements(type);
+ unsigned bit_size = glsl_get_bit_size(type);
for (unsigned i = 0; i < num_components; i++)
- val->constant->values[0].u32[i] = (*c)->values[col].u32[elem
+ i];
+ if (bit_size == 64)
+ val->constant->values[0].u64[i] =
(*c)->values[col].u64[elem + i];
+ else
+ val->constant->values[0].u32[i] =
(*c)->values[col].u32[elem + i];
}
} else {
struct vtn_value *insert =
@@ -1177,8 +1181,12 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
*c = insert->constant;
} else {
unsigned num_components = glsl_get_vector_elements(type);
+ unsigned bit_size = glsl_get_bit_size(type);
for (unsigned i = 0; i < num_components; i++)
- (*c)->values[col].u32[elem + i] =
insert->constant->values[0].u32[i];
+ if (bit_size == 64)
+ (*c)->values[col].u64[elem + i] =
insert->constant->values[0].u64[i];
+ else
+ (*c)->values[col].u32[elem + i] =
insert->constant->values[0].u32[i];
}
}
break;
--
2.9.3
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[Mesa-dev] [PATCH v2 08/25] spirv: add double support to _vtn_variable_load_store
From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index be64dd9..d125096 100644 --- a/src/compiler/spirv/vtn_variables.c +++ b/src/compiler/spirv/vtn_variables.c @@ -640,6 +640,7 @@ _vtn_variable_load_store(struct vtn_builder *b, bool load, case GLSL_TYPE_INT: case GLSL_TYPE_FLOAT: case GLSL_TYPE_BOOL: + case GLSL_TYPE_DOUBLE: /* At this point, we have a scalar, vector, or matrix so we know that * there cannot be any structure splitting still in the way. By * stopping at the matrix level rather than the vector level, we -- 2.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 10/25] spirv: Enable double floating points when copying variables in _vtn_variable_copy()
From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index fbfa4e6..bd93083 100644 --- a/src/compiler/spirv/vtn_variables.c +++ b/src/compiler/spirv/vtn_variables.c @@ -717,6 +717,7 @@ _vtn_variable_copy(struct vtn_builder *b, struct vtn_access_chain *dest, case GLSL_TYPE_UINT: case GLSL_TYPE_INT: case GLSL_TYPE_FLOAT: + case GLSL_TYPE_DOUBLE: case GLSL_TYPE_BOOL: /* At this point, we have a scalar, vector, or matrix so we know that * there cannot be any structure splitting still in the way. By -- 2.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 11/25] spirv: add support for doubles on OpComposite{Insert, Extract}
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 60cc988..d8553c0 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1132,6 +1132,7 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
case GLSL_TYPE_UINT:
case GLSL_TYPE_INT:
case GLSL_TYPE_FLOAT:
+case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_BOOL:
/* If we hit this granularity, we're picking off an element */
if (glsl_type_is_matrix(type)) {
--
2.9.3
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[Mesa-dev] [PATCH v2 09/25] spirv: add double support to _vtn_block_load_store()
From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index d125096..fbfa4e6 100644 --- a/src/compiler/spirv/vtn_variables.c +++ b/src/compiler/spirv/vtn_variables.c @@ -443,6 +443,7 @@ _vtn_block_load_store(struct vtn_builder *b, nir_intrinsic_op op, bool load, case GLSL_TYPE_UINT: case GLSL_TYPE_INT: case GLSL_TYPE_FLOAT: + case GLSL_TYPE_DOUBLE: case GLSL_TYPE_BOOL: /* This is where things get interesting. At this point, we've hit * a vector, a scalar, or a matrix. -- 2.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 12/25] compiler/nir: add glsl_type_is_{float, integer}()
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir_types.cpp | 15 +++
src/compiler/nir_types.h | 2 ++
2 files changed, 17 insertions(+)
diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index cc90efd..ea3bcb8 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_types.cpp
@@ -235,6 +235,21 @@ glsl_type_is_numeric(const struct glsl_type *type)
}
bool
+glsl_type_is_integer(const struct glsl_type *type)
+{
+ return (type->base_type == GLSL_TYPE_INT ||
+ type->base_type == GLSL_TYPE_UINT);
+}
+
+bool
+glsl_type_is_float(const struct glsl_type *type)
+{
+ return (type->base_type == GLSL_TYPE_FLOAT ||
+ type->base_type == GLSL_TYPE_DOUBLE);
+}
+
+
+bool
glsl_type_is_boolean(const struct glsl_type *type)
{
return type->is_boolean();
diff --git a/src/compiler/nir_types.h b/src/compiler/nir_types.h
index 9088a06..cf15ffc 100644
--- a/src/compiler/nir_types.h
+++ b/src/compiler/nir_types.h
@@ -114,6 +114,8 @@ bool glsl_type_is_sampler(const struct glsl_type *type);
bool glsl_type_is_image(const struct glsl_type *type);
bool glsl_type_is_dual_slot(const struct glsl_type *type);
bool glsl_type_is_numeric(const struct glsl_type *type);
+bool glsl_type_is_integer(const struct glsl_type *type);
+bool glsl_type_is_float(const struct glsl_type *type);
bool glsl_type_is_boolean(const struct glsl_type *type);
bool glsl_sampler_type_is_shadow(const struct glsl_type *type);
bool glsl_sampler_type_is_array(const struct glsl_type *type);
--
2.9.3
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[Mesa-dev] [PATCH v2 13/25] nir: add nir_get_nir_type_for_glsl_type()
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 544d4ba..9310dab 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -670,6 +670,25 @@ nir_alu_type_get_base_type(nir_alu_type type)
return type & NIR_ALU_TYPE_BASE_TYPE_MASK;
}
+static inline nir_alu_type
+nir_get_nir_type_for_glsl_type(const struct glsl_type *type)
+{
+ unsigned bit_size = glsl_get_bit_size(type);
+ if (glsl_type_is_boolean(type))
+ return (nir_alu_type)(nir_type_bool | bit_size);
+
+ if (glsl_type_is_integer(type)) {
+ if (glsl_get_base_type(type) == GLSL_TYPE_UINT)
+ return (nir_alu_type)(nir_type_uint | bit_size);
+ else
+ return (nir_alu_type)(nir_type_int | bit_size);
+ }
+
+ if (glsl_type_is_float(type))
+ return (nir_alu_type)(nir_type_float | bit_size);
+ unreachable("unknown type");
+}
+
typedef enum {
NIR_OP_IS_COMMUTATIVE = (1 << 0),
NIR_OP_IS_ASSOCIATIVE = (1 << 1),
--
2.9.3
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[Mesa-dev] [PATCH v2 14/25] nir: add nir_type_conversion_op()
From: Samuel Iglesias Gonsálvez
This function returns the nir_op corresponding to the conversion between
the given nir_alu_type arguments.
This function lacks support for integer-based types with bit_size != 32
and for float16 conversion ops.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir.c | 83 ++
src/compiler/nir/nir.h | 2 ++
2 files changed, 85 insertions(+)
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index 2d882f7..3e00452 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -1953,3 +1953,86 @@ nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
unreachable("intrinsic doesn't produce a system value");
}
}
+
+nir_op
+nir_type_conversion_op(nir_alu_type src, nir_alu_type dst)
+{
+ nir_alu_type src_base_type = (nir_alu_type) nir_alu_type_get_base_type(src);
+ nir_alu_type dst_base_type = (nir_alu_type) nir_alu_type_get_base_type(dst);
+ unsigned src_bitsize = nir_alu_type_get_type_size(src);
+ unsigned dst_bitsize = nir_alu_type_get_type_size(dst);
+
+ if (src_base_type == dst_base_type) {
+ if (src_bitsize == dst_bitsize)
+ return (src_base_type == nir_type_float) ? nir_op_fmov : nir_op_imov;
+
+ switch (src_base_type) {
+ case nir_type_bool:
+ case nir_type_uint:
+ case nir_type_int:
+ return nir_op_imov;
+ case nir_type_float:
+ /* TODO: implement support for float16 */
+ assert(src_bitsize == 64 || dst_bitsize == 64);
+ return (src_bitsize == 64) ? nir_op_d2f : nir_op_f2d;
+ default:
+ assert(!"Invalid conversion");
+ };
+ }
+
+ /* Different base type but same bit_size */
+ if (src_bitsize == dst_bitsize) {
+ /* TODO: This does not include specific conversions between
+ * signed or unsigned integer types of bit size different of 32 yet.
+ */
+ assert(src_bitsize == 32);
+ switch (src_base_type) {
+ case nir_type_uint:
+ return (dst_base_type == nir_type_float) ? nir_op_u2f : nir_op_imov;
+ case nir_type_int:
+ return (dst_base_type == nir_type_float) ? nir_op_i2f : nir_op_imov;
+ case nir_type_bool:
+ return (dst_base_type == nir_type_float) ? nir_op_b2f : nir_op_imov;
+ case nir_type_float:
+ return (dst_base_type == nir_type_uint) ? nir_op_f2u :
+(dst_base_type == nir_type_bool) ? nir_op_f2b : nir_op_f2i;
+ default:
+ assert(!"Invalid conversion");
+ };
+ }
+
+ /* Different bit_size and different base type */
+ /* TODO: Implement integer support for types with bit_size != 32 */
+ switch (src_base_type) {
+ case nir_type_uint:
+ assert(dst == nir_type_float64);
+ return nir_op_u2d;
+ case nir_type_int:
+ assert(dst == nir_type_float64);
+ return nir_op_i2d;
+ case nir_type_bool:
+ assert(dst == nir_type_float64);
+ return nir_op_u2d;
+ case nir_type_float:
+ assert(src_bitsize == 32 || src_bitsize == 64);
+ if (src_bitsize != 64) {
+ assert(dst == nir_type_float64);
+ return nir_op_f2d;
+ }
+ assert(dst_bitsize == 32);
+ switch (dst_base_type) {
+ case nir_type_uint:
+ return nir_op_d2u;
+ case nir_type_int:
+ return nir_op_d2i;
+ case nir_type_bool:
+ return nir_op_d2b;
+ case nir_type_float:
+ return nir_op_d2f;
+ default:
+ assert(!"Invalid conversion");
+ };
+ default:
+ assert(!"Invalid conversion");
+ };
+}
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 9310dab..9f3abb7 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -689,6 +689,8 @@ nir_get_nir_type_for_glsl_type(const struct glsl_type *type)
unreachable("unknown type");
}
+nir_op nir_type_conversion_op(nir_alu_type src, nir_alu_type dst);
+
typedef enum {
NIR_OP_IS_COMMUTATIVE = (1 << 0),
NIR_OP_IS_ASSOCIATIVE = (1 << 1),
--
2.9.3
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[Mesa-dev] [PATCH v2 16/25] spirv/nir: add (un)packDouble2x32() translation
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index cb0570d..01df1dd 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -399,11 +399,13 @@ vtn_nir_alu_op_for_spirv_glsl_opcode(enum GLSLstd450
opcode)
case GLSLstd450PackSnorm2x16:return nir_op_pack_snorm_2x16;
case GLSLstd450PackUnorm2x16:return nir_op_pack_unorm_2x16;
case GLSLstd450PackHalf2x16: return nir_op_pack_half_2x16;
+ case GLSLstd450PackDouble2x32: return nir_op_pack_double_2x32;
case GLSLstd450UnpackSnorm4x8: return nir_op_unpack_snorm_4x8;
case GLSLstd450UnpackUnorm4x8: return nir_op_unpack_unorm_4x8;
case GLSLstd450UnpackSnorm2x16: return nir_op_unpack_snorm_2x16;
case GLSLstd450UnpackUnorm2x16: return nir_op_unpack_unorm_2x16;
case GLSLstd450UnpackHalf2x16: return nir_op_unpack_half_2x16;
+ case GLSLstd450UnpackDouble2x32: return nir_op_unpack_double_2x32;
default:
unreachable("No NIR equivalent");
--
2.9.3
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[Mesa-dev] [PATCH v2 15/25] spirv/nir: implement DF conversions
From: Samuel Iglesias Gonsálvez
SPIR-V does not have special opcodes for DF conversions. We need to identify
them by checking the bit size of the operand and the result.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 4 +++-
src/compiler/spirv/vtn_alu.c | 29 ++---
src/compiler/spirv/vtn_private.h | 3 ++-
3 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index d8553c0..2a60b53 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1195,7 +1195,9 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
default: {
bool swap;
- nir_op op = vtn_nir_alu_op_for_spirv_opcode(opcode, &swap);
+ nir_alu_type dst_alu_type =
nir_get_nir_type_for_glsl_type(val->const_type);
+ nir_alu_type src_alu_type = dst_alu_type;
+ nir_op op = vtn_nir_alu_op_for_spirv_opcode(opcode, &swap,
src_alu_type, dst_alu_type);
unsigned num_components = glsl_get_vector_elements(val->const_type);
unsigned bit_size =
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 95ff2b1..55f7f2e 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -211,7 +211,8 @@ vtn_handle_matrix_alu(struct vtn_builder *b, SpvOp opcode,
}
nir_op
-vtn_nir_alu_op_for_spirv_opcode(SpvOp opcode, bool *swap)
+vtn_nir_alu_op_for_spirv_opcode(SpvOp opcode, bool *swap,
+nir_alu_type src, nir_alu_type dst)
{
/* Indicates that the first two arguments should be swapped. This is
* used for implementing greater-than and less-than-or-equal.
@@ -284,16 +285,16 @@ vtn_nir_alu_op_for_spirv_opcode(SpvOp opcode, bool *swap)
case SpvOpFUnordGreaterThanEqual: return nir_op_fge;
/* Conversions: */
- case SpvOpConvertFToU: return nir_op_f2u;
- case SpvOpConvertFToS: return nir_op_f2i;
- case SpvOpConvertSToF: return nir_op_i2f;
- case SpvOpConvertUToF: return nir_op_u2f;
case SpvOpBitcast: return nir_op_imov;
case SpvOpUConvert:
case SpvOpQuantizeToF16: return nir_op_fquantize2f16;
- /* TODO: NIR is 32-bit only; these are no-ops. */
- case SpvOpSConvert: return nir_op_imov;
- case SpvOpFConvert: return nir_op_fmov;
+ case SpvOpConvertFToU:
+ case SpvOpConvertFToS:
+ case SpvOpConvertSToF:
+ case SpvOpConvertUToF:
+ case SpvOpSConvert:
+ case SpvOpFConvert:
+ return nir_type_conversion_op(src, dst);
/* Derivatives: */
case SpvOpDPdx: return nir_op_fddx;
@@ -457,7 +458,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
case SpvOpFUnordLessThanEqual:
case SpvOpFUnordGreaterThanEqual: {
bool swap;
- nir_op op = vtn_nir_alu_op_for_spirv_opcode(opcode, &swap);
+ nir_alu_type src_alu_type =
nir_get_nir_type_for_glsl_type(vtn_src[0]->type);
+ nir_alu_type dst_alu_type = nir_get_nir_type_for_glsl_type(type);
+ nir_op op = vtn_nir_alu_op_for_spirv_opcode(opcode, &swap, src_alu_type,
dst_alu_type);
if (swap) {
nir_ssa_def *tmp = src[0];
@@ -481,7 +484,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
case SpvOpFOrdLessThanEqual:
case SpvOpFOrdGreaterThanEqual: {
bool swap;
- nir_op op = vtn_nir_alu_op_for_spirv_opcode(opcode, &swap);
+ nir_alu_type src_alu_type =
nir_get_nir_type_for_glsl_type(vtn_src[0]->type);
+ nir_alu_type dst_alu_type = nir_get_nir_type_for_glsl_type(type);
+ nir_op op = vtn_nir_alu_op_for_spirv_opcode(opcode, &swap, src_alu_type,
dst_alu_type);
if (swap) {
nir_ssa_def *tmp = src[0];
@@ -500,7 +505,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
default: {
bool swap;
- nir_op op = vtn_nir_alu_op_for_spirv_opcode(opcode, &swap);
+ nir_alu_type src_alu_type =
nir_get_nir_type_for_glsl_type(vtn_src[0]->type);
+ nir_alu_type dst_alu_type = nir_get_nir_type_for_glsl_type(type);
+ nir_op op = vtn_nir_alu_op_for_spirv_opcode(opcode, &swap, src_alu_type,
dst_alu_type);
if (swap) {
nir_ssa_def *tmp = src[0];
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index 47579fe..4b2721e 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -480,7 +480,8 @@ typedef void (*vtn_execution_mode_foreach_cb)(struct
vtn_builder *,
void vtn_foreach_execution_mode(struct vtn_builder *b, struct vtn_value *value,
vtn_execution_mode_foreach_cb cb, void *data);
-nir_op vtn_nir_alu_op_for_spirv_opcode(SpvOp opcode, bool *swap);
+nir_op vtn_nir_alu_op_for_spirv_opcode(SpvOp opcode, bool *swap,
+ nir_alu_type src, nir_alu_type dst);
void vtn_handle_alu(
[Mesa-dev] [PATCH v2 17/25] spirv: add support for doubles to OpSpecConstant
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/amd/vulkan/radv_pipeline.c| 5 +++-
src/compiler/spirv/nir_spirv.h| 5 +++-
src/compiler/spirv/spirv_to_nir.c | 51 +++
src/intel/vulkan/anv_pipeline.c | 5 +++-
4 files changed, 58 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 23ed2d2..6d8299e 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -188,7 +188,10 @@ radv_shader_compile_to_nir(struct radv_device *device,
assert(data + entry.size <= spec_info->pData +
spec_info->dataSize);
spec_entries[i].id =
spec_info->pMapEntries[i].constantID;
- spec_entries[i].data = *(const uint32_t *)data;
+if (spec_info->dataSize == 8)
+ spec_entries[i].data64 = *(const uint64_t
*)data;
+else
+ spec_entries[i].data32 = *(const uint32_t
*)data;
}
}
diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_spirv.h
index 500f2cb..33a2781 100644
--- a/src/compiler/spirv/nir_spirv.h
+++ b/src/compiler/spirv/nir_spirv.h
@@ -38,7 +38,10 @@ extern "C" {
struct nir_spirv_specialization {
uint32_t id;
- uint32_t data;
+ union {
+ uint32_t data32;
+ uint64_t data64;
+ };
};
nir_function *spirv_to_nir(const uint32_t *words, size_t word_count,
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 2a60b53..380fbae 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -31,6 +31,14 @@
#include "nir/nir_constant_expressions.h"
#include "spirv_info.h"
+struct spec_constant_value {
+ bool is_double;
+ union {
+ uint32_t data32;
+ uint64_t data64;
+ };
+};
+
void
_vtn_warn(const char *file, int line, const char *msg, ...)
{
@@ -942,11 +950,14 @@ spec_constant_decoration_cb(struct vtn_builder *b, struct
vtn_value *v,
if (dec->decoration != SpvDecorationSpecId)
return;
- uint32_t *const_value = data;
+ struct spec_constant_value *const_value = data;
for (unsigned i = 0; i < b->num_specializations; i++) {
if (b->specializations[i].id == dec->literals[0]) {
- *const_value = b->specializations[i].data;
+ if (const_value->is_double)
+const_value->data64 = b->specializations[i].data64;
+ else
+const_value->data32 = b->specializations[i].data32;
return;
}
}
@@ -956,8 +967,22 @@ static uint32_t
get_specialization(struct vtn_builder *b, struct vtn_value *val,
uint32_t const_value)
{
- vtn_foreach_decoration(b, val, spec_constant_decoration_cb, &const_value);
- return const_value;
+ struct spec_constant_value data;
+ data.is_double = false;
+ data.data32 = const_value;
+ vtn_foreach_decoration(b, val, spec_constant_decoration_cb, &data);
+ return data.data32;
+}
+
+static uint64_t
+get_specialization64(struct vtn_builder *b, struct vtn_value *val,
+ uint64_t const_value)
+{
+ struct spec_constant_value data;
+ data.is_double = true;
+ data.data64 = const_value;
+ vtn_foreach_decoration(b, val, spec_constant_decoration_cb, &data);
+ return data.data64;
}
static void
@@ -1016,10 +1041,26 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
}
break;
}
- case SpvOpSpecConstant:
+ case SpvOpSpecConstant: {
assert(glsl_type_is_scalar(val->const_type));
val->constant->values[0].u32[0] = get_specialization(b, val, w[3]);
+ int bit_size = glsl_get_bit_size(val->const_type);
+ if (bit_size == 64) {
+ union {
+uint64_t u64;
+struct {
+ uint32_t u1;
+ uint32_t u2;
+};
+ } di;
+ di.u1 = w[3];
+ di.u2 = w[4];
+ val->constant->values[0].u64[0] = get_specialization64(b, val,
di.u64);
+ } else {
+ val->constant->values[0].u32[0] = get_specialization(b, val, w[3]);
+ }
break;
+ }
case SpvOpSpecConstantComposite:
case SpvOpConstantComposite: {
unsigned elem_count = count - 3;
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 9104267..30ac19a 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -117,7 +117,10 @@ anv_shader_compile_to_nir(struct anv_device *device,
assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
spec_entries[i].id = spec_info->pMapEntries[i].constantID;
- spec_entries[i].data = *(const uint32_t *)data;
+ if (spec_info->dataSize == 8)
+spec_entries[i].data64 = *(const uint64_t *)
[Mesa-dev] [PATCH v2 18/25] anv/pipeline: get map for double input attributes
--- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 30ac19a..6a141b6 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -489,6 +489,7 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline, ralloc_steal(mem_ctx, nir); prog_data.inputs_read = nir->info->inputs_read; + prog_data.double_inputs_read = nir->info->double_inputs_read; brw_compute_vue_map(&pipeline->device->info, &prog_data.base.vue_map, -- 2.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 19/25] isl: fix VA64 support for double and dvecN vertex attributes
From: Samuel Iglesias Gonsálvez
We use *64*_PASSTHRU formats to upload vertex attributes of 64 bits
to avoid conversions. From the BDW PRM, Volume 2d, page 586
(VERTEX_ELEMENT_STATE):
"When SourceElementFormat is set to one of the *64*_PASSTHRU
formats, 64-bit components are stored in the URB without any
conversion. In this case, vertex elements must be written as 128
or 256 bits, with VFCOMP_STORE_0 being used to pad the output
as required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
component into the URB, Component 1 must be specified as
VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE)
in order to output a 128-bit vertex element, or Components 1-3 must
be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
to be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
element."
v2 (Jason):
- Don't delete unused formats.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/isl/isl_format.c | 4 ++--
src/intel/isl/isl_format_layout.csv | 1 -
src/intel/vulkan/anv_formats.c | 8
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index 98806f4..92b630a 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -97,7 +97,7 @@ static const struct surface_format_info format_info[] = {
SF( x, x, x, x, x, x, Y, x, x,x, R32G32B32A32_SSCALED)
SF( x, x, x, x, x, x, Y, x, x,x, R32G32B32A32_USCALED)
SF( x, x, x, x, x, x, 75, x, x,x, R32G32B32A32_SFIXED)
- SF( x, x, x, x, x, x, x, x, x,x, R64G64_PASSTHRU)
+ SF( x, x, x, x, x, x, 80, x, x,x, R64G64_PASSTHRU)
SF( Y, 50, x, x, x, x, Y, Y, x,x, R32G32B32_FLOAT)
SF( Y, x, x, x, x, x, Y, Y, x,x, R32G32B32_SINT)
SF( Y, x, x, x, x, x, Y, Y, x,x, R32G32B32_UINT)
@@ -131,7 +131,7 @@ static const struct surface_format_info format_info[] = {
SF( x, x, x, x, x, x, Y, x, x,x, R32G32_SSCALED)
SF( x, x, x, x, x, x, Y, x, x,x, R32G32_USCALED)
SF( x, x, x, x, x, x, 75, x, x,x, R32G32_SFIXED)
- SF( x, x, x, x, x, x, x, x, x,x, R64_PASSTHRU)
+ SF( x, x, x, x, x, x, 80, x, x,x, R64_PASSTHRU)
SF( Y, Y, x, Y, Y, Y, Y, x, 60, 90, B8G8R8A8_UNORM)
SF( Y, Y, x, x, Y, Y, x, x, x,x, B8G8R8A8_UNORM_SRGB)
/* smpl filt shad CK RT AB VB SO color ccs_e */
diff --git a/src/intel/isl/isl_format_layout.csv
b/src/intel/isl/isl_format_layout.csv
index f0f31c7..a177eef 100644
--- a/src/intel/isl/isl_format_layout.csv
+++ b/src/intel/isl/isl_format_layout.csv
@@ -96,7 +96,6 @@ X32_TYPELESS_G8X24_UINT , 64, 1, 1, 1, x32, ui8,
x24, , ,
L32A32_FLOAT, 64, 1, 1, 1, , , , sf32, sf32,
,, linear,
R32G32_UNORM, 64, 1, 1, 1, un32, un32, , , ,
,, linear,
R32G32_SNORM, 64, 1, 1, 1, sn32, sn32, , , ,
,, linear,
-R64_FLOAT , 64, 1, 1, 1, sf64, , , , ,
,, linear,
R16G16B16X16_UNORM , 64, 1, 1, 1, un16, un16, un16, x16, ,
,, linear,
R16G16B16X16_FLOAT , 64, 1, 1, 1, sf16, sf16, sf16, x16, ,
,, linear,
A32X32_FLOAT, 64, 1, 1, 1, , , , sf32, x32,
,, alpha,
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 9ef998c..39810d4 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -156,16 +156,16 @@ static const struct anv_format anv_formats[] = {
fmt(VK_FORMAT_R32G32B32A32_SFLOAT, ISL_FORMAT_R32G32B32A32_FLOAT),
fmt(VK_FORMAT_R64_UINT,ISL_FORMAT_R64_PASSTHRU),
fmt(VK_FORMAT_R64_SINT,ISL_FORMAT_R64_PASSTHRU),
- fmt(VK_FORMAT_R64_SFLOAT, ISL_FORMAT_R64_FLOAT),
+ fmt(VK_FORMAT_R64_SFLOAT, ISL_FORMAT_R64_PASSTHRU),
fmt(VK_FORMAT_R64G64_UINT, ISL_FORMAT_R64G64_PASSTHRU),
fmt(VK_FORMAT_R64G64_SINT, ISL_FORMAT_R64G64_PASSTHRU),
- fmt(VK_FORMAT_R64G64_SFLOAT, ISL_FORMAT_R64G64_FLOAT),
+ fmt(VK_FORMAT_R64G64_SFLOAT, ISL_FORMAT_R64G64_PASSTHRU),
fmt(VK_FORMAT_R64G64B64_UINT, ISL_FORMAT_R64G64B64_PASSTHRU),
fmt(VK_FORMAT_R64G64B64_SINT, ISL_FORMAT_R64G64B64_PASSTHRU),
- fmt(VK_FORMAT_R64G64B64_SFLOAT,ISL_FORMAT_R64G64B64_FLOAT),
+ fmt(VK_FORMAT_R64G64B64_SFLOAT,ISL_FORMAT_R64G64B64_PASSTHRU),
fmt(VK_FORMAT_R64G64B64A64_UINT, ISL_FORMAT_R64G64B64A64_PASSTHRU),
fmt(VK_FORMAT_R64G64B64A64_SINT, ISL_FORMAT_R64G64B64A64_PASSTHRU),
- fmt(VK_FORMAT_R64G64B64A64_SFLOAT,
[Mesa-dev] [PATCH v2 22/25] nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributes
So far, input_reads was a bitmap tracking which vertex input locations
were being used.
In OpenGL, an attribute bigger than a vec4 (like a dvec3 or dvec4)
consumes just one location, any other small attribute. So we mark the
proper bit in inputs_read, and also the same bit in double_inputs_read
if the attribute is a dvec3/dvec4.
But in Vulkan, this is slightly different: a dvec3/dvec4 attribute
consumes two locations, not just one. And hence two bits would be marked
in inputs_read for the same vertex input attribute.
To avoid handling two different situations in NIR, we just choose the
latest one: in OpenGL, when creating NIR from GLSL/IR, any dvec3/dvec4
vertex input attribute is marked with two bits in the inputs_read bitmap
(and also in the double_inputs_read), and following attributes are
adjusted accordingly.
As example, if in our GLSL/IR shader we have three attributes:
layout(location = 0) vec3 attr0;
layout(location = 1) dvec4 attr1;
layout(location = 2) dvec3 attr2;
then in our NIR shader we put attr0 in location 0, attr1 in locations 1
and 2, and attr2 in location 3.
Checking carefully, basically we are using slots rather than locations
in NIR.
When emitting the vertices, we do a inverse map to know the
corresponding location for each slot.
v2 (Jason):
- use two slots from inputs_read for dvec3/dvec4 NIR from GLSL/IR.
---
src/compiler/glsl/glsl_to_nir.cpp| 28 +
src/compiler/nir/nir_gather_info.c | 48 ++---
src/intel/vulkan/genX_pipeline.c | 63 +---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 11 +++--
src/mesa/drivers/dri/i965/brw_fs.cpp | 13 --
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 3 +-
src/mesa/drivers/dri/i965/brw_nir.c | 6 +--
src/mesa/drivers/dri/i965/brw_nir.h | 1 -
src/mesa/drivers/dri/i965/brw_vec4.cpp | 11 +++--
9 files changed, 106 insertions(+), 78 deletions(-)
diff --git a/src/compiler/glsl/glsl_to_nir.cpp
b/src/compiler/glsl/glsl_to_nir.cpp
index 4debc37..0814dad 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -129,6 +129,19 @@ private:
} /* end of anonymous namespace */
+static void
+nir_remap_attributes(nir_shader *shader)
+{
+ nir_foreach_variable(var, &shader->inputs) {
+ var->data.location += _mesa_bitcount_64(shader->info->double_inputs_read
&
+
BITFIELD64_MASK(var->data.location));
+ }
+
+ /* Once the remap is done, reset double_inputs_read, so later it will have
+* which location/slots are doubles */
+ shader->info->double_inputs_read = 0;
+}
+
nir_shader *
glsl_to_nir(const struct gl_shader_program *shader_prog,
gl_shader_stage stage,
@@ -146,6 +159,13 @@ glsl_to_nir(const struct gl_shader_program *shader_prog,
nir_lower_constant_initializers(shader, (nir_variable_mode)~0);
+ /* Remap the locations to slots so those requiring two slots will occupy
+* two locations. For instance, if we have in the IR code a dvec3 attr0 in
+* location 0 and vec4 attr1 in location 1, in NIR attr0 will use
+* locations/slots 0 and 1, and attr1 will use location/slot 2 */
+ if (shader->stage == MESA_SHADER_VERTEX)
+ nir_remap_attributes(shader);
+
shader->info->name = ralloc_asprintf(shader, "GLSL%d", shader_prog->Name);
if (shader_prog->Label)
shader->info->label = ralloc_strdup(shader, shader_prog->Label);
@@ -315,6 +335,14 @@ nir_visitor::visit(ir_variable *ir)
} else {
var->data.mode = nir_var_shader_in;
}
+
+ /* Mark all the locations that require two slots */
+ if (glsl_type_is_dual_slot(glsl_without_array(var->type))) {
+ for (uint i = 0; i < glsl_count_attribute_slots(var->type, true);
i++) {
+uint64_t bitfield = BITFIELD64_BIT(var->data.location + i);
+shader->info->double_inputs_read |= bitfield;
+ }
+ }
break;
case ir_var_shader_out:
diff --git a/src/compiler/nir/nir_gather_info.c
b/src/compiler/nir/nir_gather_info.c
index 07c9949..35a1ce4 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -53,11 +53,6 @@ set_io_mask(nir_shader *shader, nir_variable *var, int
offset, int len)
else
shader->info->inputs_read |= bitfield;
- /* double inputs read is only for vertex inputs */
- if (shader->stage == MESA_SHADER_VERTEX &&
- glsl_type_is_dual_slot(glsl_without_array(var->type)))
-shader->info->double_inputs_read |= bitfield;
-
if (shader->stage == MESA_SHADER_FRAGMENT) {
shader->info->fs.uses_sample_qualifier |= var->data.sample;
}
@@ -83,26 +78,21 @@ static void
mark_whole_variable(nir_shader *shader, nir_variable *var)
{
const struct glsl_type *type = var->type;
- bool is_vertex_input = false;
if (nir_is_per_vertex_io(var, sha
[Mesa-dev] [PATCH v2 20/25] nir: Add flag to detect platforms with native float64 support
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 9f3abb7..c369db3 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1758,6 +1758,11 @@ typedef struct nir_shader_compiler_options {
*/
bool native_integers;
+ /**
+* Does the driver support 64-bit floats?
+*/
+ bool native_float64;
+
/* Indicates that the driver only has zero-based vertex id */
bool vertex_id_zero_based;
--
2.9.3
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[Mesa-dev] [PATCH v2 24/25] i965: enable nir_option's native_float64 to supported generations
From: Samuel Iglesias Gonsálvez
Currently, gen8+ supports ARB_gpu_shader_fp64 in mesa master.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_compiler.c | 36 +---
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c
b/src/mesa/drivers/dri/i965/brw_compiler.c
index 1aa72bc..3dcf2b3 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.c
+++ b/src/mesa/drivers/dri/i965/brw_compiler.c
@@ -43,18 +43,28 @@
.use_interpolated_input_intrinsics = true, \
.vertex_id_zero_based = true
-static const struct nir_shader_compiler_options scalar_nir_options = {
+#define COMMON_SCALAR_NIR_OPTIONS \
+ .lower_pack_half_2x16 = true, \
+ .lower_pack_snorm_2x16 = true, \
+ .lower_pack_snorm_4x8 = true, \
+ .lower_pack_unorm_2x16 = true, \
+ .lower_pack_unorm_4x8 = true, \
+ .lower_unpack_half_2x16 = true,\
+ .lower_unpack_snorm_2x16 = true, \
+ .lower_unpack_snorm_4x8 = true,\
+ .lower_unpack_unorm_2x16 = true, \
+ .lower_unpack_unorm_4x8 = true
+
+static const struct nir_shader_compiler_options scalar_nir_options_pre_gen8 = {
COMMON_OPTIONS,
- .lower_pack_half_2x16 = true,
- .lower_pack_snorm_2x16 = true,
- .lower_pack_snorm_4x8 = true,
- .lower_pack_unorm_2x16 = true,
- .lower_pack_unorm_4x8 = true,
- .lower_unpack_half_2x16 = true,
- .lower_unpack_snorm_2x16 = true,
- .lower_unpack_snorm_4x8 = true,
- .lower_unpack_unorm_2x16 = true,
- .lower_unpack_unorm_4x8 = true,
+ COMMON_SCALAR_NIR_OPTIONS,
+ .native_float64 = false,
+};
+
+static const struct nir_shader_compiler_options scalar_nir_options_gen8 = {
+ COMMON_OPTIONS,
+ COMMON_SCALAR_NIR_OPTIONS,
+ .native_float64 = true,
};
static const struct nir_shader_compiler_options vector_nir_options = {
@@ -138,7 +148,9 @@ brw_compiler_create(void *mem_ctx, const struct
gen_device_info *devinfo)
compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
if (is_scalar) {
- compiler->glsl_compiler_options[i].NirOptions = &scalar_nir_options;
+ compiler->glsl_compiler_options[i].NirOptions =
+(devinfo->gen >= 8) ? &scalar_nir_options_gen8
+: &scalar_nir_options_pre_gen8;
} else {
compiler->glsl_compiler_options[i].NirOptions =
devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
--
2.9.3
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[Mesa-dev] [PATCH v2 25/25] anv: enable shaderFloat64 feature
From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index d594df7..eb2368a 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -479,7 +479,7 @@ void anv_GetPhysicalDeviceFeatures( .shaderStorageImageArrayDynamicIndexing = true, .shaderClipDistance = true, .shaderCullDistance = true, - .shaderFloat64= false, + .shaderFloat64= pdevice->info.gen >= 8, .shaderInt64 = false, .shaderInt16 = false, .shaderResourceMinLod = false, -- 2.9.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 23/25] spirv: enable SpvCapabilityFloat64 only to supported platforms
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 11f6248..f4bf3b4 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -2525,6 +2525,13 @@ vtn_handle_preamble_instruction(struct vtn_builder *b,
SpvOp opcode,
case SpvCapabilityInputAttachment:
break;
+ case SpvCapabilityFloat64:
+ if (!b->nir_options->native_float64) {
+vtn_warn("Unsupported SPIR-V capability: %s",
+ spirv_capability_to_string(cap));
+ }
+ break;
+
case SpvCapabilityGeometryStreams:
case SpvCapabilityTessellation:
case SpvCapabilityTessellationPointSize:
@@ -2532,7 +2539,6 @@ vtn_handle_preamble_instruction(struct vtn_builder *b,
SpvOp opcode,
case SpvCapabilityVector16:
case SpvCapabilityFloat16Buffer:
case SpvCapabilityFloat16:
- case SpvCapabilityFloat64:
case SpvCapabilityInt64:
case SpvCapabilityInt64Atomics:
case SpvCapabilityAtomicStorage:
--
2.9.3
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[Mesa-dev] [PATCH v2 21/25] spirv: Add nir_options to vtn_builder
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 1 +
src/compiler/spirv/vtn_private.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 380fbae..11f6248 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3061,6 +3061,7 @@ spirv_to_nir(const uint32_t *words, size_t word_count,
exec_list_make_empty(&b->functions);
b->entry_point_stage = stage;
b->entry_point_name = entry_point_name;
+ b->nir_options = options;
/* Handle all the preamble instructions */
words = vtn_foreach_instruction(b, words, word_end,
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index 4b2721e..d559e87 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -344,6 +344,7 @@ struct vtn_decoration {
struct vtn_builder {
nir_builder nb;
+ const nir_shader_compiler_options *nir_options;
nir_shader *shader;
nir_function_impl *impl;
--
2.9.3
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[Mesa-dev] [PATCH v2 05/25] spirv: add DF support to SpvOp*ConstantComposite
From: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 3fa1d8e..5303a94 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1032,6 +1032,8 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
case GLSL_TYPE_INT:
case GLSL_TYPE_FLOAT:
case GLSL_TYPE_BOOL:
+ case GLSL_TYPE_DOUBLE: {
+ int bit_size = glsl_get_bit_size(val->const_type);
if (glsl_type_is_matrix(val->const_type)) {
assert(glsl_get_matrix_columns(val->const_type) == elem_count);
for (unsigned i = 0; i < elem_count; i++)
@@ -1039,12 +1041,16 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
} else {
assert(glsl_type_is_vector(val->const_type));
assert(glsl_get_vector_elements(val->const_type) == elem_count);
-for (unsigned i = 0; i < elem_count; i++)
- val->constant->values[0].u32[i] = elems[i]->values[0].u32[0];
+for (unsigned i = 0; i < elem_count; i++) {
+ if (bit_size == 64)
+ val->constant->values[0].u64[i] =
elems[i]->values[0].u64[0];
+ else
+ val->constant->values[0].u32[i] = elems[i]->values[0].u32[0];
+}
}
ralloc_free(elems);
break;
-
+ }
case GLSL_TYPE_STRUCT:
case GLSL_TYPE_ARRAY:
ralloc_steal(val->constant, elems);
--
2.9.3
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[Mesa-dev] [PATCH v2 06/25] spirv: fix SpvOpSpecConstantOp with SpvOpVectorShuffle working with double-based vecs
From: Samuel Iglesias Gonsálvez
We need to pick two 32-bit values per component to perform the right shuffle
operation.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv_to_nir.c | 25 +
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 5303a94..5126dc9 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1073,18 +1073,35 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
unsigned len0 = glsl_get_vector_elements(v0->const_type);
unsigned len1 = glsl_get_vector_elements(v1->const_type);
- uint32_t u[8];
+ if (glsl_get_bit_size(v0->const_type) == 64)
+len0 *= 2;
+ if (glsl_get_bit_size(v1->const_type) == 64)
+len1 *= 2;
+
+ /* Allocate space for two dvec4s */
+ uint32_t u[16];
+ assert(len0 + len1 < 16);
for (unsigned i = 0; i < len0; i++)
u[i] = v0->constant->values[0].u32[i];
for (unsigned i = 0; i < len1; i++)
u[len0 + i] = v1->constant->values[0].u32[i];
- for (unsigned i = 0; i < count - 6; i++) {
+ unsigned bit_size = glsl_get_bit_size(val->const_type);
+ for (unsigned i = 0, j = 0; i < count - 6; i++, j++) {
uint32_t comp = w[i + 6];
+/* In case of doubles, we need to pick two 32-bit values,
+ * then we duplicate the component to pick the right values.
+ */
+if (bit_size == 64)
+ comp *= 2;
if (comp == (uint32_t)-1) {
- val->constant->values[0].u32[i] = 0xdeadbeef;
+ val->constant->values[0].u32[j] = 0xdeadbeef;
+ if (bit_size == 64)
+ val->constant->values[0].u32[++j] = 0xdeadbeef;
} else {
- val->constant->values[0].u32[i] = u[comp];
+ val->constant->values[0].u32[j] = u[comp];
+ if (bit_size == 64)
+ val->constant->values[0].u32[++j] = u[comp + 1];
}
}
break;
--
2.9.3
___
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Re: [Mesa-dev] [PATCH v2 043/103] i965/vec4: handle 32 and 64 bit channels in liveness analysis
On Mon, 2016-12-19 at 13:58 -0800, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > From: "Juan A. Suarez Romero"
> >
> > Our current data flow analysis does not take into account that
> > channels
> > on 64-bit operands are 64-bit. This is a problem when the same
> > register
> > is accessed using both 64-bit and 32-bit channels. This is very
> > common
> > in operations where we need to access 64-bit data in 32-bit chunks,
> > such as the double packing and packing operations.
> >
> > This patch changes the analysis by checking the bits that each
> > source
> > or destination datatype needs. Actually, rather than bits, we use
> > blocks of 32bits, which is the minimum channel size.
> >
> > Because a vgrf can contain a dvec4 (256 bits), we reserve 8
> > 32-bit blocks to map the channels.
> >
> > v2 (Curro):
> > - Simplify code by making the var_from_reg helpers take an extra
> > argument with the register component we want.
> > - Fix a couple of cases where we had to update the code to the
> > new
> > way of representing live variables.
> > ---
> > src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +-
> > src/mesa/drivers/dri/i965/brw_vec4_cse.cpp | 2 +-
> > .../dri/i965/brw_vec4_dead_code_eliminate.cpp | 25 +-
> > ---
> > .../drivers/dri/i965/brw_vec4_live_variables.cpp | 32
> > +++---
> > .../drivers/dri/i965/brw_vec4_live_variables.h | 15 ++
> > 5 files changed, 42 insertions(+), 34 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> > b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> > index 3191eab..34cab04 100644
> > --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> > @@ -1140,7 +1140,7 @@ vec4_visitor::opt_register_coalesce()
> > /* Can't coalesce this GRF if someone else was going to
> > * read it later.
> > */
> > - if (var_range_end(var_from_reg(alloc, dst_reg(inst-
> > >src[0])), 4) > ip)
> > + if (var_range_end(var_from_reg(alloc, dst_reg(inst-
> > >src[0])), 8) > ip)
> > continue;
> >
> > /* We need to check interference with the final destination
> > between this
> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> > b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> > index 1b91db9..bef897a 100644
> > --- a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
> > @@ -246,7 +246,7 @@ vec4_visitor::opt_cse_local(bblock_t *block)
> > * more -- a sure sign they'll fail operands_match().
> > */
> > if (src->file == VGRF) {
> > - if (var_range_end(var_from_reg(alloc,
> > dst_reg(*src)), 4) < ip) {
> > + if (var_range_end(var_from_reg(alloc,
> > dst_reg(*src)), 8) < ip) {
> > entry->remove();
> > ralloc_free(entry);
> > break;
> > diff --git
> > a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
> > b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
> > index 950c6c8..6a80810 100644
> > --- a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
> > @@ -57,12 +57,13 @@ vec4_visitor::dead_code_eliminate()
> > if ((inst->dst.file == VGRF && !inst->has_side_effects())
> > ||
> > (inst->dst.is_null() && inst->writes_flag())){
> > bool result_live[4] = { false };
> > -
> > if (inst->dst.file == VGRF) {
> > - for (unsigned i = 0; i < regs_written(inst); i++) {
> > - for (int c = 0; c < 4; c++)
> > - result_live[c] |= BITSET_TEST(
> > -live, var_from_reg(alloc, offset(inst-
> > >dst, i), c));
> > + for (unsigned i = 0; i < 2 * regs_written(inst);
> > i++) {
>
> One of the issues we discussed in the past about this approach is
> that
> it would overestimate the number of register OWORDs accessed by
> instructions with size_written < REG_SIZE (or size_read(i) <
> REG_SIZE),
> which will be emitted by the SIMD lowering pass. Now that the amount
> of
> data read and written by instructions is represented in byte units
> you
> can avoid this problem by usin
