[Mesa-dev] [PATCH] gallium: Add format modifier aux plane query
Rather than hard-code a list of all the format
modifiers supported by any gallium driver in
the dri state tracker, add a screen proc that
queries the number of auxiliary planes required
for a given modifier+format pair.
Since the only format modifier that requires
auxiliary planes currently is the iris driver's
I915_FORMAT_MOD_Y_TILED_CCS, provide a generic
implementation of this screen proc as a utility
function, and use that in every driver besides
the iris driver, which requires a trivial
customization on top of it.
Signed-off-by: James Jones
---
src/gallium/auxiliary/util/u_screen.c | 35 ++
src/gallium/auxiliary/util/u_screen.h | 7
src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 +
.../drivers/freedreno/freedreno_screen.c | 1 +
src/gallium/drivers/iris/iris_resource.c | 17 +
src/gallium/drivers/lima/lima_screen.c| 1 +
.../drivers/nouveau/nvc0/nvc0_resource.c | 2 ++
src/gallium/drivers/tegra/tegra_screen.c | 12 +++
src/gallium/drivers/v3d/v3d_screen.c | 1 +
src/gallium/drivers/vc4/vc4_screen.c | 1 +
src/gallium/include/pipe/p_screen.h | 15
src/gallium/state_trackers/dri/dri2.c | 36 ---
12 files changed, 107 insertions(+), 22 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_screen.c
b/src/gallium/auxiliary/util/u_screen.c
index 785d1bd3e24..0697d483372 100644
--- a/src/gallium/auxiliary/util/u_screen.c
+++ b/src/gallium/auxiliary/util/u_screen.c
@@ -412,3 +412,38 @@ u_pipe_screen_get_param_defaults(struct pipe_screen
*pscreen,
unreachable("bad PIPE_CAP_*");
}
}
+
+bool
+u_pipe_screen_get_modifier_aux_planes(struct pipe_screen *pscreen,
+ uint64_t modifier,
+ enum pipe_format format,
+ unsigned *num_aux_planes)
+{
+ int num_mods, i;
+ uint64_t *supported_mods;
+
+ pscreen->query_dmabuf_modifiers(pscreen, format, 0, NULL, NULL,
+ &num_mods);
+
+ if (!num_mods)
+ return false;
+
+ supported_mods = malloc(num_mods * sizeof(supported_mods[0]));
+
+ if (!supported_mods)
+ return false;
+
+ pscreen->query_dmabuf_modifiers(pscreen, format, num_mods, supported_mods,
+ NULL, &num_mods);
+
+ for (i = 0; i < num_mods && supported_mods[i] != modifier; i++);
+
+ free(supported_mods);
+
+ if (i == num_mods)
+ return false;
+
+ *num_aux_planes = 0;
+
+ return true;
+}
diff --git a/src/gallium/auxiliary/util/u_screen.h
b/src/gallium/auxiliary/util/u_screen.h
index 3952a11f2ca..0abcfd282b1 100644
--- a/src/gallium/auxiliary/util/u_screen.h
+++ b/src/gallium/auxiliary/util/u_screen.h
@@ -23,6 +23,7 @@
struct pipe_screen;
enum pipe_cap;
+enum pipe_format;
#ifdef __cplusplus
extern "C" {
@@ -32,6 +33,12 @@ int
u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
enum pipe_cap param);
+bool
+u_pipe_screen_get_modifier_aux_planes(struct pipe_screen *pscreen,
+ uint64_t modifier,
+ enum pipe_format format,
+ unsigned *num_aux_planes);
+
#ifdef __cplusplus
};
#endif
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index dcceddc4729..32909a4e5ea 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -1019,6 +1019,7 @@ etna_screen_create(struct etna_device *dev, struct
etna_gpu *gpu,
pscreen->context_create = etna_context_create;
pscreen->is_format_supported = etna_screen_is_format_supported;
pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
+ pscreen->get_modifier_aux_planes = u_pipe_screen_get_modifier_aux_planes;
etna_fence_screen_init(pscreen);
etna_query_screen_init(pscreen);
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c
b/src/gallium/drivers/freedreno/freedreno_screen.c
index 3c0ed69a9cb..5d25df02ebf 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -984,6 +984,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly
*ro)
pscreen->fence_get_fd = fd_fence_get_fd;
pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
+ pscreen->get_modifier_aux_planes =
u_pipe_screen_get_modifier_aux_planes;
if (!screen->supported_modifiers) {
static const uint64_t supported_modifiers[] = {
diff --git a/src/gallium/drivers/iris/iris_resource.c
b/src/gallium/drivers/iris/iris_resource.c
index bdd715df2c9..a3b0e87070f 100644
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -38,6 +38,7 @@
#include "util/u_cpu_detect.h"
#inclu
[Mesa-dev] [PATCH 0/5] nouveau: Improved format modifier support
This series pulls in the proposed DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D() format modifier macro and wires it up in the nouveau nvc0 driver. In doing so, it improves the existing format modifier code to behave more like other format-modifier-capable drivers, and is written in such a way that it should be easier to port to nv50-class and future turing-class drivers as well. Modifiers supporting import/export of compressed surfaces are not included in this series. Once the general approach here is agreed upon, I can send out a follow-on series adding those as well. This series depends on the general gallium/dri cleanup patch: [PATCH] gallium: Add format modifier aux plane query Which was sent out separately. James Jones (5): drm-uapi: Update headers from nouveau/linux-5.6 nouveau: Stash supported sector layout in screen nouveau: Use DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D nouveau: no modifier != the invalid modifier nouveau: Use format modifiers in buffer allocation include/drm-uapi/drm_fourcc.h | 135 +++- src/gallium/drivers/nouveau/nouveau_screen.c | 12 + src/gallium/drivers/nouveau/nouveau_screen.h | 1 + .../drivers/nouveau/nvc0/nvc0_miptree.c | 208 -- .../drivers/nouveau/nvc0/nvc0_resource.c | 41 ++-- .../drivers/nouveau/nvc0/nvc0_resource.h | 5 + 6 files changed, 306 insertions(+), 96 deletions(-) -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/5] nouveau: Use DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D
Replace existing usage of the NVIDIA_16BX2_BLOCK
format modifiers with parameterized use of the
more general macro. Nouveau will now report
support for slightly different modifiers depending
on whether the underlying chip is a tegra GPU or
not, and will potentially report valid format
modifiers for more resource types, but overall
this should be a functional no-op for existing
applications.
Signed-off-by: James Jones
---
.../drivers/nouveau/nvc0/nvc0_miptree.c | 99 ---
.../drivers/nouveau/nvc0/nvc0_resource.c | 37 ---
.../drivers/nouveau/nvc0/nvc0_resource.h | 5 +
3 files changed, 64 insertions(+), 77 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
index c897e4e8b97..20e4c4decb1 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
@@ -37,19 +37,14 @@ nvc0_tex_choose_tile_dims(unsigned nx, unsigned ny,
unsigned nz, bool is_3d)
return nv50_tex_choose_tile_dims_helper(nx, ny, nz, is_3d);
}
-static uint32_t
-nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool compressed)
+uint32_t
+nvc0_choose_tiled_storage_type(enum pipe_format format,
+ unsigned ms,
+ bool compressed)
{
- const unsigned ms = util_logbase2(mt->base.base.nr_samples);
-
uint32_t tile_flags;
- if (unlikely(mt->base.base.bind & PIPE_BIND_CURSOR))
- return 0;
- if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR))
- return 0;
-
- switch (mt->base.base.format) {
+ switch (format) {
case PIPE_FORMAT_Z16_UNORM:
if (compressed)
tile_flags = 0x02 + ms;
@@ -86,7 +81,7 @@ nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool
compressed)
tile_flags = 0xc3;
break;
default:
- switch (util_format_get_blocksizebits(mt->base.base.format)) {
+ switch (util_format_get_blocksizebits(format)) {
case 128:
if (compressed)
tile_flags = 0xf4 + ms * 2;
@@ -136,6 +131,19 @@ nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool
compressed)
return tile_flags;
}
+static uint32_t
+nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool compressed)
+{
+ const unsigned ms = util_logbase2(mt->base.base.nr_samples);
+
+ if (unlikely(mt->base.base.bind & PIPE_BIND_CURSOR))
+ return 0;
+ if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR))
+ return 0;
+
+ return nvc0_choose_tiled_storage_type(mt->base.base.format, ms, compressed);
+}
+
static inline bool
nvc0_miptree_init_ms_mode(struct nv50_miptree *mt)
{
@@ -236,57 +244,32 @@ nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt)
}
}
-static uint64_t nvc0_miptree_get_modifier(struct nv50_miptree *mt)
+static uint64_t
+nvc0_miptree_get_modifier(struct pipe_screen *pscreen, struct nv50_miptree *mt)
{
- union nouveau_bo_config *config = &mt->base.bo->config;
- uint64_t modifier;
+ const union nouveau_bo_config *config = &mt->base.bo->config;
+ const uint32_t uc_kind =
+ nvc0_choose_tiled_storage_type(mt->base.base.format,
+ mt->base.base.nr_samples,
+ false);
if (mt->layout_3d)
return DRM_FORMAT_MOD_INVALID;
+ if (mt->base.base.nr_samples > 1)
+ return DRM_FORMAT_MOD_INVALID;
+ if (config->nvc0.memtype == 0x00)
+ return DRM_FORMAT_MOD_LINEAR;
+ if (NVC0_TILE_MODE_Y(config->nvc0.tile_mode) > 5)
+ return DRM_FORMAT_MOD_INVALID;
+ if (config->nvc0.memtype != uc_kind)
+ return DRM_FORMAT_MOD_INVALID;
- switch (config->nvc0.memtype) {
- case 0x00:
- modifier = DRM_FORMAT_MOD_LINEAR;
- break;
-
- case 0xfe:
- switch (NVC0_TILE_MODE_Y(config->nvc0.tile_mode)) {
- case 0:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB;
- break;
-
- case 1:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB;
- break;
-
- case 2:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB;
- break;
-
- case 3:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB;
- break;
-
- case 4:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB;
- break;
-
- case 5:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB;
- break;
-
- default:
- modifier = DRM_FORMAT_MOD_INVALID;
- break;
- }
- break;
-
- default:
- modifier = DRM_FORMAT_MOD_INVALID;
- break;
- }
-
- return modifier;
+ return DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(
+ 0,
+ nouveau_screen(pscreen)->tegra_sector_layout ? 0 : 1,
+ 0,
+ config->nvc0.memtype,
+ NVC0_TILE_MODE_Y(config->nvc0.tile_mode));
}
static bool
@@ -301,7 +284,7 @@ nvc0_miptree_get_handle(struct pip
[Mesa-dev] [PATCH 4/5] nouveau: no modifier != the invalid modifier
Other drivers fail resource allocation when a list
of modifiers for the resource is provided but none
are supported. This includes cases when the never-
supported DRM_FORMAT_MOD_INVALID modifier is
explicitly passed. To enable matching that
functionality in nouveau, use an empty modifier
list rather than creating a one-entry list
containing only DRM_FORMAT_MOD_INVALID when the
non-modifier resource creation function is used.
This change stops short of failing allocations
when no modifier is specified, because the current
code ignores all modifiers except the linear
modifier when creating resources, so there is not
yet a framework in place to determine which
modifiers are valid for a given resource creation
request, and hence no way to reject only those
which are invalid.
Signed-off-by: James Jones
---
src/gallium/drivers/nouveau/nvc0/nvc0_resource.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
index 18c4dfad23d..c9ee097d269 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
@@ -10,13 +10,11 @@ static struct pipe_resource *
nvc0_resource_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
- const uint64_t modifier = DRM_FORMAT_MOD_INVALID;
-
switch (templ->target) {
case PIPE_BUFFER:
return nouveau_buffer_create(screen, templ);
default:
- return nvc0_miptree_create(screen, templ, &modifier, 1);
+ return nvc0_miptree_create(screen, templ, NULL, 0);
}
}
--
2.17.1
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[Mesa-dev] [PATCH 5/5] nouveau: Use format modifiers in buffer allocation
The nvc0 nouveau backend already claimed to
support format modifiers, but in practice it
ignored them when allocating buffers outside of a
perfunctory check for the linear modifier in the
first element of the format modifier list.
This change deduces the supported modifiers, if
any, for a given miptree creation request,
prioritizes them based on performance and memory
waste properties, compares the requested modifiers
against the prioritized list of supported
modifiers, and overrides the internal layout
calculations based on the layout defined by the
resulting modifier.
Additionally, if modifiers are provided and none
are compatible with the miptree creation request,
the function now fails. This brings the nouveau
behavior in line with other drivers such as i965
and etnaviv.
Signed-off-by: James Jones
---
.../drivers/nouveau/nvc0/nvc0_miptree.c | 111 --
1 file changed, 103 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
index 20e4c4decb1..02c163e3e8a 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
@@ -132,7 +132,7 @@ nvc0_choose_tiled_storage_type(enum pipe_format format,
}
static uint32_t
-nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool compressed)
+nvc0_mt_choose_storage_type(const struct nv50_miptree *mt, bool compressed)
{
const unsigned ms = util_logbase2(mt->base.base.nr_samples);
@@ -196,7 +196,7 @@ nvc0_miptree_init_layout_video(struct nv50_miptree *mt)
}
static void
-nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt)
+nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt, uint64_t modifier)
{
struct pipe_resource *pt = &mt->base.base;
unsigned w, h, d, l;
@@ -213,6 +213,9 @@ nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt)
d = mt->layout_3d ? pt->depth0 : 1;
assert(!mt->ms_mode || !pt->last_level);
+ assert(modifier == DRM_FORMAT_MOD_INVALID ||
+ (!pt->last_level && !mt->layout_3d));
+ assert(modifier != DRM_FORMAT_MOD_LINEAR);
for (l = 0; l <= pt->last_level; ++l) {
struct nv50_miptree_level *lvl = &mt->level[l];
@@ -222,7 +225,10 @@ nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt)
lvl->offset = mt->total_size;
- lvl->tile_mode = nvc0_tex_choose_tile_dims(nbx, nby, d, mt->layout_3d);
+ if (modifier != DRM_FORMAT_MOD_INVALID)
+ lvl->tile_mode = ((uint32_t)modifier & 0xf) << 4;
+ else
+ lvl->tile_mode = nvc0_tex_choose_tile_dims(nbx, nby, d,
mt->layout_3d);
tsx = NVC0_TILE_SIZE_X(lvl->tile_mode); /* x is tile row pitch in bytes
*/
tsy = NVC0_TILE_SIZE_Y(lvl->tile_mode);
@@ -289,6 +295,79 @@ nvc0_miptree_get_handle(struct pipe_screen *pscreen,
return true;
}
+static uint64_t
+nvc0_miptree_select_best_modifier(struct pipe_screen *pscreen,
+ const struct nv50_miptree *mt,
+ const uint64_t *modifiers,
+ unsigned int count)
+{
+ uint64_t prio_supported_mods[] = {
+ DRM_FORMAT_MOD_INVALID,
+ DRM_FORMAT_MOD_INVALID,
+ DRM_FORMAT_MOD_INVALID,
+ DRM_FORMAT_MOD_INVALID,
+ DRM_FORMAT_MOD_INVALID,
+ DRM_FORMAT_MOD_INVALID,
+ DRM_FORMAT_MOD_LINEAR,
+ };
+ const uint32_t uc_kind = nvc0_mt_choose_storage_type(mt, false);
+ int top_mod_slot = ARRAY_SIZE(prio_supported_mods);
+ unsigned int i;
+ int p;
+
+ if (uc_kind != 0u) {
+ const struct pipe_resource *pt = &mt->base.base;
+ const unsigned nbx = util_format_get_nblocksx(pt->format, pt->width0);
+ const unsigned nby = util_format_get_nblocksy(pt->format, pt->height0);
+ const uint32_t lbh_preferred =
+ NVC0_TILE_MODE_Y(nvc0_tex_choose_tile_dims(nbx, nby, 1u, false));
+ uint32_t lbh = lbh_preferred;
+ bool dec_lbh = true;
+ const uint8_t s = nouveau_screen(pscreen)->tegra_sector_layout ? 0 : 1;
+
+ for (i = 0; i <= 5u; i++) {
+ assert(lbh <= 5u);
+ prio_supported_mods[i] =
+DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, s, 0, uc_kind, lbh);
+
+ /*
+ * The preferred block height is the largest block size that doesn't
+ * waste excessive space with unused padding bytes relative to the
+ * height of the image. Construct the priority array such that
+ * the preferred block height is highest priority, followed by
+ * progressively smaller block sizes down to a block height of one,
+ * followed by progressively larger (more wasteful) block sizes up
+ * to 5.
+ */
+ if (lbh == 0u) {
+lbh = lbh_preferred + 1u;
+dec_lbh = false;
+ } else if (dec_lbh) {
+lbh--;
+ } else {
+lbh++;
+ }
+ }
+ }
+
+ assert(prio_supported_mods[ARRAY_SIZE(prio_supported_mod
[Mesa-dev] [PATCH 2/5] nouveau: Stash supported sector layout in screen
Older Tegra GPUs use a different sector bit
swizzling layout than desktop and Xavier GPUs.
Hence their format modifiers must be
differentiated from those of other GPUs. As
a precursor to supporting more expressive
block linear format modifiers, deduce the
sector layout used for a given GPU from its
chipset and stash the layout in the nouveau
screen structure.
Signed-off-by: James Jones
---
src/gallium/drivers/nouveau/nouveau_screen.c | 12
src/gallium/drivers/nouveau/nouveau_screen.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c
b/src/gallium/drivers/nouveau/nouveau_screen.c
index de9cce3812a..f63af6313e4 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.c
+++ b/src/gallium/drivers/nouveau/nouveau_screen.c
@@ -213,6 +213,18 @@ nouveau_screen_init(struct nouveau_screen *screen, struct
nouveau_device *dev)
size = sizeof(nvc0_data);
}
+ switch (dev->chipset) {
+ case 0x0ea: /* TK1, GK20A */
+ case 0x12b: /* TX1, GM20B */
+ case 0x13b: /* TX2, GP10B */
+ screen->tegra_sector_layout = true;
+ break;
+ default:
+ /* Xavier's GPU and everything else */
+ screen->tegra_sector_layout = false;
+ break;
+ }
+
/*
* Set default VRAM domain if not overridden
*/
diff --git a/src/gallium/drivers/nouveau/nouveau_screen.h
b/src/gallium/drivers/nouveau/nouveau_screen.h
index 40464225c75..0abaf4db0f5 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.h
+++ b/src/gallium/drivers/nouveau/nouveau_screen.h
@@ -58,6 +58,7 @@ struct nouveau_screen {
int64_t cpu_gpu_time_delta;
bool hint_buf_keep_sysmem_copy;
+ bool tegra_sector_layout;
unsigned vram_domain;
--
2.17.1
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[Mesa-dev] [PATCH 1/5] drm-uapi: Update headers from nouveau/linux-5.6
Copy latest drm_fourcc.h from nouveau/linux-5.6
XXX - Update this with final commit ID/info
commit: d8a841ff4f4cbb31dd0dfd037399421969837730
Author: James Jones
Date: Tue Aug 6 17:10:10 2019 -0700
drm: Generalized NV Block Linear DRM format mod
Signed-off-by: James Jones
---
include/drm-uapi/drm_fourcc.h | 135 +++---
1 file changed, 126 insertions(+), 9 deletions(-)
diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index 2376d36ea57..56217e2f39e 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -69,7 +69,7 @@ extern "C" {
#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
((__u32)(c) << 16) | ((__u32)(d) << 24))
-#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of
little endian */
+#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of
little endian */
/* Reserve 0 for the invalid format specifier */
#define DRM_FORMAT_INVALID 0
@@ -410,6 +410,17 @@ extern "C" {
#define I915_FORMAT_MOD_Y_TILED_CCSfourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
@@ -497,7 +508,113 @@ extern "C" {
#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
/*
- * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
+ * Generalized Block Linear layout, used by desktop GPUs starting with
NV50/G80,
+ * and Tegra GPUs starting with Tegra K1.
+ *
+ * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
+ * based on the architecture generation. GOBs themselves are then arranged in
+ * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
+ * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
+ * a block depth or height of "4").
+ *
+ * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
+ * in full detail.
+ *
+ * Macro
+ * Bits Param Description
+ * -
-
+ *
+ * 3:0 h log2(height) of each block, in GOBs. Placed here for
+ * compatibility with the existing
+ * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
+ *
+ * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
+ * compatibility with the existing
+ * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
+ *
+ * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
+ * size). Must be zero.
+ *
+ * Note there is no log2(width) parameter. Some portions of the
+ * hardware support a block width of two gobs, but it is
impractical
+ * to use due to lack of support elsewhere, and has no known
+ * benefits.
+ *
+ * 11:9 - Reserved (To support 2D-array textures with variable array
stride
+ * in blocks, specified via log2(tile width in blocks)). Must be
+ * zero.
+ *
+ * 19:12 k Page Kind. This value directly maps to a field in the page
+ * tables of all GPUs >= NV50. It affects the exact layout of bits
+ * in memory and can be derived from the tuple
+ *
+ * (format, GPU model, compression type, samples per pixel)
+ *
+ * Where compression type is defined below. If GPU model were
+ * implied by the format modifier, format, or memory buffer, page
+ * kind would not need to be included in the modifier itself, but
+ * since the modifier should define the layout of the associated
+ * memory buffer independent from any device or other context, it
+ * must be included here.
+ *
+ * 21:20 g GOB Height and Page Kind Generation. The height of a GOB
changed
+ * starting with Fermi GPUs. Additionally, the mapping between
page
+ * kind and bit layout has changed at various points.
+ *
+ * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
+ * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
+ * 2 = Gob Height 8, Turing+ Page Kind mapping
+ * 3 = Reserved for future use.
+ *
+ * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a
further
+ * bit remapping step that o
Re: [Mesa-dev] [PATCH 0/5] nouveau: Improved format modifier support
FYI: GitLab merge requests are the preferred way to send patches these days. --Jason On February 5, 2020 21:52:25 James Jones wrote: This series pulls in the proposed DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D() format modifier macro and wires it up in the nouveau nvc0 driver. In doing so, it improves the existing format modifier code to behave more like other format-modifier-capable drivers, and is written in such a way that it should be easier to port to nv50-class and future turing-class drivers as well. Modifiers supporting import/export of compressed surfaces are not included in this series. Once the general approach here is agreed upon, I can send out a follow-on series adding those as well. This series depends on the general gallium/dri cleanup patch: [PATCH] gallium: Add format modifier aux plane query Which was sent out separately. James Jones (5): drm-uapi: Update headers from nouveau/linux-5.6 nouveau: Stash supported sector layout in screen nouveau: Use DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D nouveau: no modifier != the invalid modifier nouveau: Use format modifiers in buffer allocation include/drm-uapi/drm_fourcc.h | 135 +++- src/gallium/drivers/nouveau/nouveau_screen.c | 12 + src/gallium/drivers/nouveau/nouveau_screen.h | 1 + .../drivers/nouveau/nvc0/nvc0_miptree.c | 208 -- .../drivers/nouveau/nvc0/nvc0_resource.c | 41 ++-- .../drivers/nouveau/nvc0/nvc0_resource.h | 5 + 6 files changed, 306 insertions(+), 96 deletions(-) -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/5] nouveau: Improved format modifier support
Thanks, now available as https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3724 -James On 2/5/20 1:45 PM, Jason Ekstrand wrote: FYI: GitLab merge requests are the preferred way to send patches these days. --Jason On February 5, 2020 21:52:25 James Jones wrote: This series pulls in the proposed DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D() format modifier macro and wires it up in the nouveau nvc0 driver. In doing so, it improves the existing format modifier code to behave more like other format-modifier-capable drivers, and is written in such a way that it should be easier to port to nv50-class and future turing-class drivers as well. Modifiers supporting import/export of compressed surfaces are not included in this series. Once the general approach here is agreed upon, I can send out a follow-on series adding those as well. This series depends on the general gallium/dri cleanup patch: [PATCH] gallium: Add format modifier aux plane query Which was sent out separately. James Jones (5): drm-uapi: Update headers from nouveau/linux-5.6 nouveau: Stash supported sector layout in screen nouveau: Use DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D nouveau: no modifier != the invalid modifier nouveau: Use format modifiers in buffer allocation include/drm-uapi/drm_fourcc.h | 135 +++- src/gallium/drivers/nouveau/nouveau_screen.c | 12 + src/gallium/drivers/nouveau/nouveau_screen.h | 1 + .../drivers/nouveau/nvc0/nvc0_miptree.c | 208 -- .../drivers/nouveau/nvc0/nvc0_resource.c | 41 ++-- .../drivers/nouveau/nvc0/nvc0_resource.h | 5 + 6 files changed, 306 insertions(+), 96 deletions(-) -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
