Replace existing usage of the NVIDIA_16BX2_BLOCK
format modifiers with parameterized use of the
more general macro. Nouveau will now report
support for slightly different modifiers depending
on whether the underlying chip is a tegra GPU or
not, and will potentially report valid format
modifiers for more resource types, but overall
this should be a functional no-op for existing
applications.
Signed-off-by: James Jones <jajo...@nvidia.com>
---
.../drivers/nouveau/nvc0/nvc0_miptree.c | 99 ++++++++-----------
.../drivers/nouveau/nvc0/nvc0_resource.c | 37 ++++---
.../drivers/nouveau/nvc0/nvc0_resource.h | 5 +
3 files changed, 64 insertions(+), 77 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
index c897e4e8b97..20e4c4decb1 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_miptree.c
@@ -37,19 +37,14 @@ nvc0_tex_choose_tile_dims(unsigned nx, unsigned ny,
unsigned nz, bool is_3d)
return nv50_tex_choose_tile_dims_helper(nx, ny, nz, is_3d);
}
-static uint32_t
-nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool compressed)
+uint32_t
+nvc0_choose_tiled_storage_type(enum pipe_format format,
+ unsigned ms,
+ bool compressed)
{
- const unsigned ms = util_logbase2(mt->base.base.nr_samples);
-
uint32_t tile_flags;
- if (unlikely(mt->base.base.bind & PIPE_BIND_CURSOR))
- return 0;
- if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR))
- return 0;
-
- switch (mt->base.base.format) {
+ switch (format) {
case PIPE_FORMAT_Z16_UNORM:
if (compressed)
tile_flags = 0x02 + ms;
@@ -86,7 +81,7 @@ nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool
compressed)
tile_flags = 0xc3;
break;
default:
- switch (util_format_get_blocksizebits(mt->base.base.format)) {
+ switch (util_format_get_blocksizebits(format)) {
case 128:
if (compressed)
tile_flags = 0xf4 + ms * 2;
@@ -136,6 +131,19 @@ nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool
compressed)
return tile_flags;
}
+static uint32_t
+nvc0_mt_choose_storage_type(struct nv50_miptree *mt, bool compressed)
+{
+ const unsigned ms = util_logbase2(mt->base.base.nr_samples);
+
+ if (unlikely(mt->base.base.bind & PIPE_BIND_CURSOR))
+ return 0;
+ if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR))
+ return 0;
+
+ return nvc0_choose_tiled_storage_type(mt->base.base.format, ms, compressed);
+}
+
static inline bool
nvc0_miptree_init_ms_mode(struct nv50_miptree *mt)
{
@@ -236,57 +244,32 @@ nvc0_miptree_init_layout_tiled(struct nv50_miptree *mt)
}
}
-static uint64_t nvc0_miptree_get_modifier(struct nv50_miptree *mt)
+static uint64_t
+nvc0_miptree_get_modifier(struct pipe_screen *pscreen, struct nv50_miptree *mt)
{
- union nouveau_bo_config *config = &mt->base.bo->config;
- uint64_t modifier;
+ const union nouveau_bo_config *config = &mt->base.bo->config;
+ const uint32_t uc_kind =
+ nvc0_choose_tiled_storage_type(mt->base.base.format,
+ mt->base.base.nr_samples,
+ false);
if (mt->layout_3d)
return DRM_FORMAT_MOD_INVALID;
+ if (mt->base.base.nr_samples > 1)
+ return DRM_FORMAT_MOD_INVALID;
+ if (config->nvc0.memtype == 0x00)
+ return DRM_FORMAT_MOD_LINEAR;
+ if (NVC0_TILE_MODE_Y(config->nvc0.tile_mode) > 5)
+ return DRM_FORMAT_MOD_INVALID;
+ if (config->nvc0.memtype != uc_kind)
+ return DRM_FORMAT_MOD_INVALID;
- switch (config->nvc0.memtype) {
- case 0x00:
- modifier = DRM_FORMAT_MOD_LINEAR;
- break;
-
- case 0xfe:
- switch (NVC0_TILE_MODE_Y(config->nvc0.tile_mode)) {
- case 0:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB;
- break;
-
- case 1:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB;
- break;
-
- case 2:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB;
- break;
-
- case 3:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB;
- break;
-
- case 4:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB;
- break;
-
- case 5:
- modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB;
- break;
-
- default:
- modifier = DRM_FORMAT_MOD_INVALID;
- break;
- }
- break;
-
- default:
- modifier = DRM_FORMAT_MOD_INVALID;
- break;
- }
-
- return modifier;
+ return DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(
+ 0,
+ nouveau_screen(pscreen)->tegra_sector_layout ? 0 : 1,
+ 0,
+ config->nvc0.memtype,
+ NVC0_TILE_MODE_Y(config->nvc0.tile_mode));
}
static bool
@@ -301,7 +284,7 @@ nvc0_miptree_get_handle(struct pipe_screen *pscreen,
if (!ret)
return ret;
- whandle->modifier = nvc0_miptree_get_modifier(mt);
+ whandle->modifier = nvc0_miptree_get_modifier(pscreen, mt);
return true;
}
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
index ab7bc69022c..18c4dfad23d 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.c
@@ -39,35 +39,34 @@ nvc0_query_dmabuf_modifiers(struct pipe_screen *screen,
uint64_t *modifiers, unsigned int *external_only,
int *count)
{
- static const uint64_t supported_modifiers[] = {
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB,
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB,
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB,
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB,
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB,
- DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB,
- };
+ const int s = nouveau_screen(screen)->tegra_sector_layout ? 0 : 1;
+ const uint32_t uc_kind =
+ nvc0_choose_tiled_storage_type(format, 0, false);
+ const uint32_t num_uc = uc_kind ? 6 : 0; /* max block height = 32 GOBs */
+ const int num_supported = num_uc + 1; /* LINEAR is always supported */
int i, num = 0;
- if (max > ARRAY_SIZE(supported_modifiers))
- max = ARRAY_SIZE(supported_modifiers);
+ if (max > num_supported)
+ max = num_supported;
if (!max) {
- max = ARRAY_SIZE(supported_modifiers);
+ max = num_supported;
external_only = NULL;
modifiers = NULL;
}
- for (i = 0; i < max; i++) {
- if (modifiers)
- modifiers[num] = supported_modifiers[i];
+#define NVC0_ADD_MOD(m) do { \
+ if (modifiers) modifiers[num] = m; \
+ if (external_only) external_only[num] = 0; \
+ num++; \
+} while (0)
- if (external_only)
- external_only[num] = 0;
+ for (i = 0; i < max && i < num_uc; i++)
+ NVC0_ADD_MOD(DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, s, 0, uc_kind,
+ 5 - i));
- num++;
- }
+ if (i < max)
+ NVC0_ADD_MOD(DRM_FORMAT_MOD_LINEAR);
*count = num;
}
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h
b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h
index 78a1d79261e..a51c43179fb 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_resource.h
@@ -33,6 +33,11 @@ nvc0_screen_init_resource_functions(struct pipe_screen
*pscreen);
/* Internal functions:
*/
+uint32_t
+nvc0_choose_tiled_storage_type(enum pipe_format format,
+ unsigned ms,
+ bool compressed);
+
struct pipe_resource *
nvc0_miptree_create(struct pipe_screen *pscreen,
const struct pipe_resource *tmp,
--
2.17.1
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