[llvm-branch-commits] [llvm] SelectionDAG: Avoid using MachineFunction::getMMI (PR #99696)
https://github.com/rnk approved this pull request. https://github.com/llvm/llvm-project/pull/99696 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] CodeGen: Remove UsesMSVCFloatingPoint from MachineModuleInfo (PR #100368)
https://github.com/rnk approved this pull request. I think @jyknight touched this last, and I may have advised him to simply use MMI to store this, since historically it has been used as a side channel for passing information along the code generation pipeline. It's good to avoid that, but it was what we were doing at the time. :) I think the reason the existing scan was done as part of SDISel is that it is a scan over the IR, and ISel is the point at which we walk the IR to build the mostly-standalone MIR representation. Moving this scan to AsmPrinting is a bit distasteful, but it works and is less code. You could also make a cache-locality argument that walking the IR again during AsmPrinting is slow, but that's pretty weak. Scanning the IR for FP types is obviously a gross approximation of `_fltused`. If we want to try to implement this properly, maybe we could scan all MachineInstrs during AsmPrinting for usage of vector or x87 FP operands. We can leave that out of scope, though. In conclusion, we should land this as is, but I wanted to share some context. https://github.com/llvm/llvm-project/pull/100368 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] CodeGen: Remove UsesMSVCFloatingPoint from MachineModuleInfo (PR #100368)
@@ -975,6 +976,28 @@ static void emitNonLazyStubs(MachineModuleInfo *MMI,
MCStreamer &OutStreamer) {
}
}
+/// True if this module is being built for windows/msvc, and uses floating
+/// point. This is used to emit an undefined reference to _fltused.
rnk wrote:
Please add a FIXME or TODO about computing this from MIR instead of the IR, and
include some context about how this is used in Windows kernel or driver
contexts to find and prevent code from modifying non-GPR registers.
https://github.com/llvm/llvm-project/pull/100368
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[llvm-branch-commits] [llvm] CodeGen: Move current call site out of MachineModuleInfo (PR #100369)
https://github.com/rnk approved this pull request. lgtm https://github.com/llvm/llvm-project/pull/100369 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang codegen] Fix MS ABI detection of user-provided constructors. (#90151) (PR #90639)
rnk wrote: I should point out that it is an ABI break, but it aligns with MSVC, and the benefit of the fix outweighs the cost, so we should merge it. https://github.com/llvm/llvm-project/pull/90639 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang codegen] Fix MS ABI detection of user-provided constructors. (#90151) (PR #90639)
https://github.com/rnk approved this pull request. There's the approve button https://github.com/llvm/llvm-project/pull/90639 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 988a533 - [Win64] Ensure all stack frames are 8 byte aligned
Author: Reid Kleckner
Date: 2021-01-25T10:39:27-08:00
New Revision: 988a5334ed40ee65c91bf30be93631b092316390
URL:
https://github.com/llvm/llvm-project/commit/988a5334ed40ee65c91bf30be93631b092316390
DIFF:
https://github.com/llvm/llvm-project/commit/988a5334ed40ee65c91bf30be93631b092316390.diff
LOG: [Win64] Ensure all stack frames are 8 byte aligned
The unwind info format requires that all adjustments are 8 byte aligned,
and the bottom three bits are masked out. Most Win64 calling conventions
have 32 bytes of shadow stack space for spilling parameters, and I
believe that constructing these fixed stack objects had the side effect
of ensuring an alignment of 8. However, the Intel regcall convention
does not have this shadow space, so when using that convention, it was
possible to make a 4 byte stack frame, which was impossible to describe
with unwind info.
Fixes pr48867
Added:
llvm/test/CodeGen/X86/win64_regcall.ll
Modified:
llvm/lib/Target/X86/X86FrameLowering.cpp
llvm/lib/Target/X86/X86FrameLowering.h
Removed:
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp
b/llvm/lib/Target/X86/X86FrameLowering.cpp
index 8339f512158d..866f11364004 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -3516,13 +3516,21 @@ void
X86FrameLowering::processFunctionBeforeFrameFinalized(
// emitPrologue if it gets called and emits CFI.
MF.setHasWinCFI(false);
+ // If we are using Windows x64 CFI, ensure that the stack is always 8 byte
+ // aligned. The format doesn't support misaligned stack adjustments.
+ if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI())
+MF.getFrameInfo().ensureMaxAlignment(Align(SlotSize));
+
// If this function isn't doing Win64-style C++ EH, we don't need to do
// anything.
- const Function &F = MF.getFunction();
- if (!STI.is64Bit() || !MF.hasEHFunclets() ||
- classifyEHPersonality(F.getPersonalityFn()) != EHPersonality::MSVC_CXX)
-return;
+ if (STI.is64Bit() && MF.hasEHFunclets() &&
+ classifyEHPersonality(MF.getFunction().getPersonalityFn()) ==
+ EHPersonality::MSVC_CXX) {
+adjustFrameForMsvcCxxEh(MF);
+ }
+}
+void X86FrameLowering::adjustFrameForMsvcCxxEh(MachineFunction &MF) const {
// Win64 C++ EH needs to allocate the UnwindHelp object at some fixed offset
// relative to RSP after the prologue. Find the offset of the last fixed
// object, so that we can allocate a slot immediately following it. If there
diff --git a/llvm/lib/Target/X86/X86FrameLowering.h
b/llvm/lib/Target/X86/X86FrameLowering.h
index f77a4843bba4..26e80811af2e 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.h
+++ b/llvm/lib/Target/X86/X86FrameLowering.h
@@ -224,6 +224,8 @@ class X86FrameLowering : public TargetFrameLowering {
const DebugLoc &DL, uint64_t Offset,
uint64_t Align) const;
+ void adjustFrameForMsvcCxxEh(MachineFunction &MF) const;
+
/// Aligns the stack pointer by ANDing it with -MaxAlign.
void BuildStackAlignAND(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
diff --git a/llvm/test/CodeGen/X86/win64_regcall.ll
b/llvm/test/CodeGen/X86/win64_regcall.ll
new file mode 100644
index ..4cd051928f36
--- /dev/null
+++ b/llvm/test/CodeGen/X86/win64_regcall.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=x86_64-windows-msvc | FileCheck %s
+
+define dso_local x86_regcallcc void @ensure_align() local_unnamed_addr #0 {
+entry:
+ %b = alloca i32, align 4
+ call void asm sideeffect "nopl $0", "=*m,~{dirflag},~{fpsr},~{flags}"(i32*
nonnull %b)
+ ret void
+}
+
+; CHECK-LABEL: ensure_align: # @ensure_align
+; CHECK: .seh_stackalloc 8
+; CHECK: .seh_endprologue
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[llvm-branch-commits] [cfe-branch] r245387 - Merge r244266 to the 3.7 release branch
Author: rnk
Date: Tue Aug 18 18:16:47 2015
New Revision: 245387
URL: http://llvm.org/viewvc/llvm-project?rev=245387&view=rev
Log:
Merge r244266 to the 3.7 release branch
It's actually probably a no-op, since the 3.7 branch will not generate
available externally vtables.
Modified:
cfe/branches/release_37/ (props changed)
cfe/branches/release_37/lib/CodeGen/ItaniumCXXABI.cpp
cfe/branches/release_37/test/CodeGenCXX/dllimport-rtti.cpp
Propchange: cfe/branches/release_37/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug 18 18:16:47 2015
@@ -1,4 +1,4 @@
/cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:242244,242285,242293,242297,242313,242382,242422,242499,242574,242600,242660,242662,242667,242678,242766,242854,242905,242973,243018,243048,243085,243098,243101,243105,243133,243144,243153,243196,243206,243277,243280,243285,243289,243343,243417,243463,243538,243594,243642-243644,243851,243945-243950,243964,244000,244193,244468,244502,244719,244794,245041,245259
+/cfe/trunk:242244,242285,242293,242297,242313,242382,242422,242499,242574,242600,242660,242662,242667,242678,242766,242854,242905,242973,243018,243048,243085,243098,243101,243105,243133,243144,243153,243196,243206,243277,243280,243285,243289,243343,243417,243463,243538,243594,243642-243644,243851,243945-243950,243964,244000,244193,244266,244468,244502,244719,244794,245041,245259
/cfe/trunk/test:170344
/cfe/trunk/test/SemaTemplate:126920
Modified: cfe/branches/release_37/lib/CodeGen/ItaniumCXXABI.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_37/lib/CodeGen/ItaniumCXXABI.cpp?rev=245387&r1=245386&r2=245387&view=diff
==
--- cfe/branches/release_37/lib/CodeGen/ItaniumCXXABI.cpp (original)
+++ cfe/branches/release_37/lib/CodeGen/ItaniumCXXABI.cpp Tue Aug 18 18:16:47
2015
@@ -2420,10 +2420,13 @@ static bool ShouldUseExternalRTTIDescrip
// FIXME: this may need to be reconsidered if the key function
// changes.
+// N.B. We must always emit the RTTI data ourselves if there exists a key
+// function.
+bool IsDLLImport = RD->hasAttr();
if (CGM.getVTables().isVTableExternal(RD))
- return true;
+ return IsDLLImport ? false : true;
-if (RD->hasAttr())
+if (IsDLLImport)
return true;
}
@@ -2653,8 +2656,15 @@ static llvm::GlobalVariable::LinkageType
const CXXRecordDecl *RD = cast(Record->getDecl());
if (RD->hasAttr())
return llvm::GlobalValue::WeakODRLinkage;
- if (RD->isDynamicClass())
-return CGM.getVTableLinkage(RD);
+ if (RD->isDynamicClass()) {
+llvm::GlobalValue::LinkageTypes LT = CGM.getVTableLinkage(RD);
+// MinGW won't export the RTTI information when there is a key
function.
+// Make sure we emit our own copy instead of attempting to dllimport
it.
+if (RD->hasAttr() &&
+llvm::GlobalValue::isAvailableExternallyLinkage(LT))
+ LT = llvm::GlobalValue::LinkOnceODRLinkage;
+return LT;
+ }
}
return llvm::GlobalValue::LinkOnceODRLinkage;
Modified: cfe/branches/release_37/test/CodeGenCXX/dllimport-rtti.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_37/test/CodeGenCXX/dllimport-rtti.cpp?rev=245387&r1=245386&r2=245387&view=diff
==
--- cfe/branches/release_37/test/CodeGenCXX/dllimport-rtti.cpp (original)
+++ cfe/branches/release_37/test/CodeGenCXX/dllimport-rtti.cpp Tue Aug 18
18:16:47 2015
@@ -15,3 +15,8 @@ struct __declspec(dllimport) S {
struct U : S {
} u;
+
+struct __declspec(dllimport) V {
+ virtual void f();
+} v;
+// GNU-DAG: @_ZTV1V = external dllimport
___
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[llvm-branch-commits] [cfe-branch] r245388 - Merge r244488 to the 3.7 release branch
Author: rnk
Date: Tue Aug 18 18:18:57 2015
New Revision: 245388
URL: http://llvm.org/viewvc/llvm-project?rev=245388&view=rev
Log:
Merge r244488 to the 3.7 release branch
It avoids doing key function optimizations when the key function is
dllimported.
Fixed PR24409.
Modified:
cfe/branches/release_37/ (props changed)
cfe/branches/release_37/lib/AST/RecordLayoutBuilder.cpp
cfe/branches/release_37/test/CodeGenCXX/dllimport-rtti.cpp
Propchange: cfe/branches/release_37/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug 18 18:18:57 2015
@@ -1,4 +1,4 @@
/cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:242244,242285,242293,242297,242313,242382,242422,242499,242574,242600,242660,242662,242667,242678,242766,242854,242905,242973,243018,243048,243085,243098,243101,243105,243133,243144,243153,243196,243206,243277,243280,243285,243289,243343,243417,243463,243538,243594,243642-243644,243851,243945-243950,243964,244000,244193,244266,244468,244502,244719,244794,245041,245259
+/cfe/trunk:242244,242285,242293,242297,242313,242382,242422,242499,242574,242600,242660,242662,242667,242678,242766,242854,242905,242973,243018,243048,243085,243098,243101,243105,243133,243144,243153,243196,243206,243277,243280,243285,243289,243343,243417,243463,243538,243594,243642-243644,243851,243945-243950,243964,244000,244193,244266,244468,244488,244502,244719,244794,245041,245259
/cfe/trunk/test:170344
/cfe/trunk/test/SemaTemplate:126920
Modified: cfe/branches/release_37/lib/AST/RecordLayoutBuilder.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_37/lib/AST/RecordLayoutBuilder.cpp?rev=245388&r1=245387&r2=245388&view=diff
==
--- cfe/branches/release_37/lib/AST/RecordLayoutBuilder.cpp (original)
+++ cfe/branches/release_37/lib/AST/RecordLayoutBuilder.cpp Tue Aug 18 18:18:57
2015
@@ -2014,6 +2014,12 @@ static const CXXMethodDecl *computeKeyFu
continue;
}
+// If the key function is dllimport but the class isn't, then the class has
+// no key function. The DLL that exports the key function won't export the
+// vtable in this case.
+if (MD->hasAttr() && !RD->hasAttr())
+ return nullptr;
+
// We found it.
return MD;
}
Modified: cfe/branches/release_37/test/CodeGenCXX/dllimport-rtti.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_37/test/CodeGenCXX/dllimport-rtti.cpp?rev=245388&r1=245387&r2=245388&view=diff
==
--- cfe/branches/release_37/test/CodeGenCXX/dllimport-rtti.cpp (original)
+++ cfe/branches/release_37/test/CodeGenCXX/dllimport-rtti.cpp Tue Aug 18
18:18:57 2015
@@ -20,3 +20,11 @@ struct __declspec(dllimport) V {
virtual void f();
} v;
// GNU-DAG: @_ZTV1V = external dllimport
+
+struct W {
+ __declspec(dllimport) virtual void f();
+ virtual void g();
+} w;
+// GNU-DAG: @_ZTV1W = linkonce_odr
+// GNU-DAG: @_ZTS1W = linkonce_odr
+// GNU-DAG: @_ZTI1W = linkonce_odr
___
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[llvm-branch-commits] [cfe-branch] r246036 - Add note about SEH to clang 3.7 notes
Author: rnk Date: Wed Aug 26 10:41:07 2015 New Revision: 246036 URL: http://llvm.org/viewvc/llvm-project?rev=246036&view=rev Log: Add note about SEH to clang 3.7 notes Modified: cfe/branches/release_37/docs/ReleaseNotes.rst Modified: cfe/branches/release_37/docs/ReleaseNotes.rst URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_37/docs/ReleaseNotes.rst?rev=246036&r1=246035&r2=246036&view=diff == --- cfe/branches/release_37/docs/ReleaseNotes.rst (original) +++ cfe/branches/release_37/docs/ReleaseNotes.rst Wed Aug 26 10:41:07 2015 @@ -42,6 +42,10 @@ Major New Features extension is also enabled when compiling CUDA code, but its use should be viewed as an implementation detail that is subject to change. +- On Windows targets, some uses of the ``__try``, ``__except``, and + ``__finally`` language constructs are supported in Clang 3.7. MSVC-compatible + C++ exceptions are not yet supported, however. + - Clang 3.7 fully supports OpenMP 3.1 and reported to work on many platforms, including x86, x86-64 and Power. Also, pragma ``omp simd`` from OpenMP 4.0 is supported as well. See below for details. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm-branch] r247191 - Merge r242372 to 3.7 so that it goes out in 3.7.1
Author: rnk
Date: Wed Sep 9 16:03:25 2015
New Revision: 247191
URL: http://llvm.org/viewvc/llvm-project?rev=247191&view=rev
Log:
Merge r242372 to 3.7 so that it goes out in 3.7.1
It restores the signature of LLVMBuildLandingPad in the C API back to what it
was in 3.6 and earlier.
The 3.7.0 release should have had this but it did not.
Modified:
llvm/branches/release_37/ (props changed)
llvm/branches/release_37/bindings/go/llvm/ir.go
llvm/branches/release_37/bindings/ocaml/llvm/llvm_ocaml.c
llvm/branches/release_37/include/llvm-c/Core.h
llvm/branches/release_37/lib/IR/Core.cpp
Propchange: llvm/branches/release_37/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Sep 9 16:03:25 2015
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243891,243898,243927,243932,243934,243984,243986,243999,244058,244123,244232,244332,244418,28,244554,244644,244659,244676,244789,244889,245064,245105,245119,245256,245355,245365,245369,245394-245395,245530,245535,245902
+/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242372,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243891,243898,243927,243932,243934,243984,243986,243999,244058,244123,244232,244332,244418,28,244554,244644,244659,244676,244789,244889,245064,245105,245119,245256,245355,245365,245369,245394-245395,245530,245535,245902
Modified: llvm/branches/release_37/bindings/go/llvm/ir.go
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/bindings/go/llvm/ir.go?rev=247191&r1=247190&r2=247191&view=diff
==
--- llvm/branches/release_37/bindings/go/llvm/ir.go (original)
+++ llvm/branches/release_37/bindings/go/llvm/ir.go Wed Sep 9 16:03:25 2015
@@ -1728,7 +1728,7 @@ func (b Builder) CreatePtrDiff(lhs, rhs
func (b Builder) CreateLandingPad(t Type, personality Value, nclauses int,
name string) (l Value) {
cname := C.CString(name)
defer C.free(unsafe.Pointer(cname))
- l.C = C.LLVMBuildLandingPad(b.C, t.C, C.unsigned(nclauses), cname)
+ l.C = C.LLVMBuildLandingPad(b.C, t.C, nil, C.unsigned(nclauses), cname)
return l
}
Modified: llvm/branches/release_37/bindings/ocaml/llvm/llvm_ocaml.c
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/bindings/ocaml/llvm/llvm_ocaml.c?rev=247191&r1=247190&r2=247191&view=diff
==
--- llvm/branches/release_37/bindings/ocaml/llvm/llvm_ocaml.c (original)
+++ llvm/branches/release_37/bindings/ocaml/llvm/llvm_ocaml.c Wed Sep 9
16:03:25 2015
@@ -1745,7 +1745,7 @@ CAMLprim LLVMValueRef llvm_build_invoke_
CAMLprim LLVMValueRef llvm_build_landingpad(LLVMTypeRef Ty, LLVMValueRef
PersFn,
value NumClauses, value Name,
value B) {
-return LLVMBuildLandingPad(Builder_val(B), Ty, Int_val(NumClauses),
+return LLVMBuildLandingPad(Builder_val(B), Ty, PersFn, Int_val(NumClauses),
String_val(Name));
}
Modified: llvm/branches/release_37/include/llvm-c/Core.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/include/llvm-c/Core.h?rev=247191&r1=247190&r2=247191&view=diff
==
--- llvm/branches/release_37/include/llvm-c/Core.h (original)
+++ llvm/branches/release_37/include/llvm-c/Core.h Wed Sep 9 16:03:25 2015
@@ -2675,7 +2675,8 @@ LLVMValueRef LLVMBuildInvoke(LLVMBuilder
LLVMBasicBlockRef Then, LLVMBasicBlockRef Catch,
const char *Name);
LLVMValueRef LLVMBuildLandingPad(LLVMBuilderRef B, LLVMTypeRef Ty,
- unsigned NumClauses, const char *Name);
+ LLVMValueRef PersFn, unsigned NumClauses,
+ const char *Name);
LLVMValueRef LLVMBuildResume(LLVMBuilderRef B, LLVMValueRef Exn);
LLVMValueRef LLVMBuildUnreachable(LLVMBuilderRef);
Modified: llvm/branches/release_37/lib/IR/Core.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/IR/Core.cpp?rev=247191&r1=247190&r2=247191&view=diff
==
--- llvm/bra
[llvm-branch-commits] [cfe-branch] r253250 - Merge r251567:
Author: rnk
Date: Mon Nov 16 15:05:53 2015
New Revision: 253250
URL: http://llvm.org/viewvc/llvm-project?rev=253250&view=rev
Log:
Merge r251567:
Fix the calling convention of Mingw64 long double values
GCC uses the x87DoubleExtended model for long doubles, and passes them
indirectly by address through function calls.
Also replace the existing mingw-long-double assembly emitting test with
an IR-level test.
Modified:
cfe/branches/release_37/ (props changed)
cfe/branches/release_37/lib/Basic/Targets.cpp
cfe/branches/release_37/lib/CodeGen/TargetInfo.cpp
Propchange: cfe/branches/release_37/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Nov 16 15:05:53 2015
@@ -1,4 +1,4 @@
/cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:242244,242285,242293,242297,242313,242382,242422,242499,242574,242600,242660,242662,242667,242678,242766,242854,242905,242973,243018,243048,243085,243098,243101,243105,243133,243144,243153,243196,243206,243277,243280,243285,243289,243343,243417,243463,243538,243594,243642-243644,243851,243945-243950,243964,244000,244193,244266,244468,244488,244502,244719,244794,244902,245041,245259,245560
+/cfe/trunk:242244,242285,242293,242297,242313,242382,242422,242499,242574,242600,242660,242662,242667,242678,242766,242854,242905,242973,243018,243048,243085,243098,243101,243105,243133,243144,243153,243196,243206,243277,243280,243285,243289,243343,243417,243463,243538,243594,243642-243644,243851,243945-243950,243964,244000,244193,244266,244468,244488,244502,244719,244794,244902,245041,245259,245560,251567
/cfe/trunk/test:170344
/cfe/trunk/test/SemaTemplate:126920
Modified: cfe/branches/release_37/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_37/lib/Basic/Targets.cpp?rev=253250&r1=253249&r2=253250&view=diff
==
--- cfe/branches/release_37/lib/Basic/Targets.cpp (original)
+++ cfe/branches/release_37/lib/Basic/Targets.cpp Mon Nov 16 15:05:53 2015
@@ -3968,7 +3968,13 @@ public:
class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
public:
MinGWX86_64TargetInfo(const llvm::Triple &Triple)
- : WindowsX86_64TargetInfo(Triple) {}
+ : WindowsX86_64TargetInfo(Triple) {
+// Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
+// with x86 FP ops. Weird.
+LongDoubleWidth = LongDoubleAlign = 128;
+LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
+ }
+
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
Modified: cfe/branches/release_37/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_37/lib/CodeGen/TargetInfo.cpp?rev=253250&r1=253249&r2=253250&view=diff
==
--- cfe/branches/release_37/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/branches/release_37/lib/CodeGen/TargetInfo.cpp Mon Nov 16 15:05:53 2015
@@ -1552,12 +1552,10 @@ public:
/// WinX86_64ABIInfo - The Windows X86_64 ABI information.
class WinX86_64ABIInfo : public ABIInfo {
-
- ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs,
- bool IsReturnType) const;
-
public:
- WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
+ WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
+ : ABIInfo(CGT),
+IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
void computeInfo(CGFunctionInfo &FI) const override;
@@ -1574,6 +1572,12 @@ public:
// FIXME: Assumes vectorcall is in use.
return isX86VectorCallAggregateSmallEnough(NumMembers);
}
+
+private:
+ ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs,
+ bool IsReturnType) const;
+
+ bool IsMingw64;
};
class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
@@ -3059,7 +3063,7 @@ ABIArgInfo WinX86_64ABIInfo::classify(Qu
TypeInfo Info = getContext().getTypeInfo(Ty);
uint64_t Width = Info.Width;
- unsigned Align = getContext().toCharUnitsFromBits(Info.Align).getQuantity();
+ CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
const RecordType *RT = Ty->getAs();
if (RT) {
@@ -3070,7 +3074,6 @@ ABIArgInfo WinX86_64ABIInfo::classify(Qu
if (RT->getDecl()->hasFlexibleArrayMember())
return ABIArgInfo::getIndirect(0, /*ByVal=*/false);
-
}
// vectorcall adds the concept of a homogenous vector aggregate, similar to
@@ -3112,6 +3115,14 @@ ABIArgInfo WinX86_64ABIInfo::classify(Qu
if (BT && BT->getKind() == BuiltinType::Bool)
return ABIArgInfo::getExtend();
+ // Mingw64 GCC uses the old 80 bit extended precision floating point unit. It
+ // passes them indirectly through memory.
+ if (IsMingw64 && BT && BT->getKind() == BuiltinType::Lon
[llvm-branch-commits] [cfe-branch] r253252 - Fix r253250 build break, getIndirect appears to take bytes instead of CharUnits in 3.7.0
Author: rnk
Date: Mon Nov 16 15:15:26 2015
New Revision: 253252
URL: http://llvm.org/viewvc/llvm-project?rev=253252&view=rev
Log:
Fix r253250 build break, getIndirect appears to take bytes instead of CharUnits
in 3.7.0
Modified:
cfe/branches/release_37/lib/CodeGen/TargetInfo.cpp
Modified: cfe/branches/release_37/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_37/lib/CodeGen/TargetInfo.cpp?rev=253252&r1=253251&r2=253252&view=diff
==
--- cfe/branches/release_37/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/branches/release_37/lib/CodeGen/TargetInfo.cpp Mon Nov 16 15:15:26 2015
@@ -3063,7 +3063,7 @@ ABIArgInfo WinX86_64ABIInfo::classify(Qu
TypeInfo Info = getContext().getTypeInfo(Ty);
uint64_t Width = Info.Width;
- CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);
+ unsigned Align = getContext().toCharUnitsFromBits(Info.Align).getQuantity();
const RecordType *RT = Ty->getAs();
if (RT) {
___
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[llvm-branch-commits] [cfe-branch] r253380 - Merge part of r246985, which disables this assertion
Author: rnk
Date: Tue Nov 17 15:37:58 2015
New Revision: 253380
URL: http://llvm.org/viewvc/llvm-project?rev=253380&view=rev
Log:
Merge part of r246985, which disables this assertion
Modified:
cfe/branches/release_37/lib/CodeGen/CGCall.cpp
cfe/branches/release_37/test/CodeGen/libcalls-fno-builtin.c
Modified: cfe/branches/release_37/lib/CodeGen/CGCall.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_37/lib/CodeGen/CGCall.cpp?rev=253380&r1=253379&r2=253380&view=diff
==
--- cfe/branches/release_37/lib/CodeGen/CGCall.cpp (original)
+++ cfe/branches/release_37/lib/CodeGen/CGCall.cpp Tue Nov 17 15:37:58 2015
@@ -1279,12 +1279,7 @@ CodeGenTypes::GetFunctionType(const CGFu
}
break;
- case ABIArgInfo::Indirect: {
-assert(!retAI.getIndirectAlign() && "Align unused on indirect return.");
-resultType = llvm::Type::getVoidTy(getLLVMContext());
-break;
- }
-
+ case ABIArgInfo::Indirect:
case ABIArgInfo::Ignore:
resultType = llvm::Type::getVoidTy(getLLVMContext());
break;
Modified: cfe/branches/release_37/test/CodeGen/libcalls-fno-builtin.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_37/test/CodeGen/libcalls-fno-builtin.c?rev=253380&r1=253379&r2=253380&view=diff
==
--- cfe/branches/release_37/test/CodeGen/libcalls-fno-builtin.c (original)
+++ cfe/branches/release_37/test/CodeGen/libcalls-fno-builtin.c Tue Nov 17
15:37:58 2015
@@ -1,4 +1,5 @@
// RUN: %clang_cc1 -S -O3 -fno-builtin -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-w64-mingw32 -S -O3 -fno-builtin -o - %s |
FileCheck %s
// rdar://10551066
typedef __SIZE_TYPE__ size_t;
___
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[llvm-branch-commits] [llvm-branch] r324007 - Merging r323155:
Author: rnk Date: Thu Feb 1 13:28:26 2018 New Revision: 324007 URL: http://llvm.org/viewvc/llvm-project?rev=324007&view=rev Log: Merging r323155: r323155 | chandlerc | 2018-01-22 14:05:25 -0800 (Mon, 22 Jan 2018) | 133 lines Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre.. Summary: First, we need to explain the core of the vulnerability. Note that this is a very incomplete description, please see the Project Zero blog post for details: https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html The basis for branch target injection is to direct speculative execution of the processor to some "gadget" of executable code by poisoning the prediction of indirect branches with the address of that gadget. The gadget in turn contains an operation that provides a side channel for reading data. Most commonly, this will look like a load of secret data followed by a branch on the loaded value and then a load of some predictable cache line. The attacker then uses timing of the processors cache to determine which direction the branch took *in the speculative execution*, and in turn what one bit of the loaded value was. Due to the nature of these timing side channels and the branch predictor on Intel processors, this allows an attacker to leak data only accessible to a privileged domain (like the kernel) back into an unprivileged domain. The goal is simple: avoid generating code which contains an indirect branch that could have its prediction poisoned by an attacker. In many cases, the compiler can simply use directed conditional branches and a small search tree. LLVM already has support for lowering switches in this way and the first step of this patch is to disable jump-table lowering of switches and introduce a pass to rewrite explicit indirectbr sequences into a switch over integers. However, there is no fully general alternative to indirect calls. We introduce a new construct we call a "retpoline" to implement indirect calls in a non-speculatable way. It can be thought of loosely as a trampoline for indirect calls which uses the RET instruction on x86. Further, we arrange for a specific call->ret sequence which ensures the processor predicts the return to go to a controlled, known location. The retpoline then "smashes" the return address pushed onto the stack by the call with the desired target of the original indirect call. The result is a predicted return to the next instruction after a call (which can be used to trap speculative execution within an infinite loop) and an actual indirect branch to an arbitrary address. On 64-bit x86 ABIs, this is especially easily done in the compiler by using a guaranteed scratch register to pass the target into this device. For 32-bit ABIs there isn't a guaranteed scratch register and so several different retpoline variants are introduced to use a scratch register if one is available in the calling convention and to otherwise use direct stack push/pop sequences to pass the target address. This "retpoline" mitigation is fully described in the following blog post: https://support.google.com/faqs/answer/7625886 We also support a target feature that disables emission of the retpoline thunk by the compiler to allow for custom thunks if users want them. These are particularly useful in environments like kernels that routinely do hot-patching on boot and want to hot-patch their thunk to different code sequences. They can write this custom thunk and use `-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this case, on x86-64 thu thunk names must be: ``` __llvm_external_retpoline_r11 ``` or on 32-bit: ``` __llvm_external_retpoline_eax __llvm_external_retpoline_ecx __llvm_external_retpoline_edx __llvm_external_retpoline_push ``` And the target of the retpoline is passed in the named register, or in the case of the `push` suffix on the top of the stack via a `pushl` instruction. There is one other important source of indirect branches in x86 ELF binaries: the PLT. These patches also include support for LLD to generate PLT entries that perform a retpoline-style indirection. The only other indirect branches remaining that we are aware of are from precompiled runtimes (such as crt0.o and similar). The ones we have found are not really attackable, and so we have not focused on them here, but eventually these runtimes should also be replicated for retpoline-ed configurations for completeness. For kernels or other freestanding or fully static executables, the compiler switch `-mretpoline` is sufficient to fully mitigate this particular attack. For dynamic executables, you must compile *all* libraries with `-mretpoline` and additionally link the dynamic executable and all sh
[llvm-branch-commits] [llvm-branch] r324009 - Merging r323915:
Author: rnk
Date: Thu Feb 1 13:31:35 2018
New Revision: 324009
URL: http://llvm.org/viewvc/llvm-project?rev=324009&view=rev
Log:
Merging r323915:
r323915 | chandlerc | 2018-01-31 12:56:37 -0800 (Wed, 31 Jan 2018) | 17 lines
[x86] Make the retpoline thunk insertion a machine function pass.
Summary:
This removes the need for a machine module pass using some deeply
questionable hacks. This should address PR36123 which is a case where in
full LTO the memory usage of a machine module pass actually ended up
being significant.
We should revert this on trunk as soon as we understand and fix the
memory usage issue, but we should include this in any backports of
retpolines themselves.
Reviewers: echristo, MatzeB
Subscribers: sanjoy, mcrosier, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D42726
Modified:
llvm/branches/release_50/ (props changed)
llvm/branches/release_50/lib/Target/X86/X86.h
llvm/branches/release_50/lib/Target/X86/X86RetpolineThunks.cpp
llvm/branches/release_50/test/CodeGen/X86/O0-pipeline.ll
Propchange: llvm/branches/release_50/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Feb 1 13:31:35 2018
@@ -1,2 +1,2 @@
-/llvm/trunk:313366,323155
+/llvm/trunk:313366,323155,323915
/llvm/trunk:155241,308483-308484,308503,308808,308813,308847,308891,308906,308950,308963,308978,308986,309044,309071,309113,309120,309122,309140,309227,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495,309555,309561,309594,309614,309651,309744,309758,309849,309928,309930,309945,310066,310071,310190,310240-310242,310250,310253,310262,310267,310481,310492,310498,310510,310534,310552,310604,310712,310779,310784,310796,310842,310906,310926,310939,310979,310988,310990-310991,311061,311068,311071,311087,311229,311258,311263,311387,311429,311554,311565,311572,311623,311835,312022,312285,313334:312337
Modified: llvm/branches/release_50/lib/Target/X86/X86.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/X86/X86.h?rev=324009&r1=324008&r2=324009&view=diff
==
--- llvm/branches/release_50/lib/Target/X86/X86.h (original)
+++ llvm/branches/release_50/lib/Target/X86/X86.h Thu Feb 1 13:31:35 2018
@@ -100,7 +100,7 @@ void initializeFixupBWInstPassPass(PassR
FunctionPass *createX86EvexToVexInsts();
/// This pass creates the thunks for the retpoline feature.
-ModulePass *createX86RetpolineThunksPass();
+FunctionPass *createX86RetpolineThunksPass();
InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
X86Subtarget &,
Modified: llvm/branches/release_50/lib/Target/X86/X86RetpolineThunks.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/X86/X86RetpolineThunks.cpp?rev=324009&r1=324008&r2=324009&view=diff
==
--- llvm/branches/release_50/lib/Target/X86/X86RetpolineThunks.cpp (original)
+++ llvm/branches/release_50/lib/Target/X86/X86RetpolineThunks.cpp Thu Feb 1
13:31:35 2018
@@ -38,18 +38,27 @@ using namespace llvm;
#define DEBUG_TYPE "x86-retpoline-thunks"
+static const char ThunkNamePrefix[] = "__llvm_retpoline_";
+static const char R11ThunkName[]= "__llvm_retpoline_r11";
+static const char EAXThunkName[]= "__llvm_retpoline_eax";
+static const char ECXThunkName[]= "__llvm_retpoline_ecx";
+static const char EDXThunkName[]= "__llvm_retpoline_edx";
+static const char PushThunkName[] = "__llvm_retpoline_push";
+
namespace {
-class X86RetpolineThunks : public ModulePass {
+class X86RetpolineThunks : public MachineFunctionPass {
public:
static char ID;
- X86RetpolineThunks() : ModulePass(ID) {}
+ X86RetpolineThunks() : MachineFunctionPass(ID) {}
StringRef getPassName() const override { return "X86 Retpoline Thunks"; }
- bool runOnModule(Module &M) override;
+ bool doInitialization(Module &M) override;
+ bool runOnMachineFunction(MachineFunction &F) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
+MachineFunctionPass::getAnalysisUsage(AU);
AU.addRequired();
AU.addPreserved();
}
@@ -61,51 +70,74 @@ private:
const X86Subtarget *STI;
const X86InstrInfo *TII;
- Function *createThunkFunction(Module &M, StringRef Name);
+ bool InsertedThunks;
+
+ void createThunkFunction(Module &M, StringRef Name);
void insertRegReturnAddrClobber(MachineBasicBlock &MBB, unsigned Reg);
void insert32BitPushReturnAddrClobber(MachineBasicBlock &MBB);
- void createThunk(Module &M, StringRef NameSuffix,
- Optional Reg = None);
+ void populateThunk(Mac
[llvm-branch-commits] [cfe-branch] r324012 - Merging r323155:
Author: rnk Date: Thu Feb 1 13:46:03 2018 New Revision: 324012 URL: http://llvm.org/viewvc/llvm-project?rev=324012&view=rev Log: Merging r323155: r323155 | chandlerc | 2018-01-22 14:05:25 -0800 (Mon, 22 Jan 2018) | 133 lines Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre.. Summary: First, we need to explain the core of the vulnerability. Note that this is a very incomplete description, please see the Project Zero blog post for details: https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html The basis for branch target injection is to direct speculative execution of the processor to some "gadget" of executable code by poisoning the prediction of indirect branches with the address of that gadget. The gadget in turn contains an operation that provides a side channel for reading data. Most commonly, this will look like a load of secret data followed by a branch on the loaded value and then a load of some predictable cache line. The attacker then uses timing of the processors cache to determine which direction the branch took *in the speculative execution*, and in turn what one bit of the loaded value was. Due to the nature of these timing side channels and the branch predictor on Intel processors, this allows an attacker to leak data only accessible to a privileged domain (like the kernel) back into an unprivileged domain. The goal is simple: avoid generating code which contains an indirect branch that could have its prediction poisoned by an attacker. In many cases, the compiler can simply use directed conditional branches and a small search tree. LLVM already has support for lowering switches in this way and the first step of this patch is to disable jump-table lowering of switches and introduce a pass to rewrite explicit indirectbr sequences into a switch over integers. However, there is no fully general alternative to indirect calls. We introduce a new construct we call a "retpoline" to implement indirect calls in a non-speculatable way. It can be thought of loosely as a trampoline for indirect calls which uses the RET instruction on x86. Further, we arrange for a specific call->ret sequence which ensures the processor predicts the return to go to a controlled, known location. The retpoline then "smashes" the return address pushed onto the stack by the call with the desired target of the original indirect call. The result is a predicted return to the next instruction after a call (which can be used to trap speculative execution within an infinite loop) and an actual indirect branch to an arbitrary address. On 64-bit x86 ABIs, this is especially easily done in the compiler by using a guaranteed scratch register to pass the target into this device. For 32-bit ABIs there isn't a guaranteed scratch register and so several different retpoline variants are introduced to use a scratch register if one is available in the calling convention and to otherwise use direct stack push/pop sequences to pass the target address. This "retpoline" mitigation is fully described in the following blog post: https://support.google.com/faqs/answer/7625886 We also support a target feature that disables emission of the retpoline thunk by the compiler to allow for custom thunks if users want them. These are particularly useful in environments like kernels that routinely do hot-patching on boot and want to hot-patch their thunk to different code sequences. They can write this custom thunk and use `-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this case, on x86-64 thu thunk names must be: ``` __llvm_external_retpoline_r11 ``` or on 32-bit: ``` __llvm_external_retpoline_eax __llvm_external_retpoline_ecx __llvm_external_retpoline_edx __llvm_external_retpoline_push ``` And the target of the retpoline is passed in the named register, or in the case of the `push` suffix on the top of the stack via a `pushl` instruction. There is one other important source of indirect branches in x86 ELF binaries: the PLT. These patches also include support for LLD to generate PLT entries that perform a retpoline-style indirection. The only other indirect branches remaining that we are aware of are from precompiled runtimes (such as crt0.o and similar). The ones we have found are not really attackable, and so we have not focused on them here, but eventually these runtimes should also be replicated for retpoline-ed configurations for completeness. For kernels or other freestanding or fully static executables, the compiler switch `-mretpoline` is sufficient to fully mitigate this particular attack. For dynamic executables, you must compile *all* libraries with `-mretpoline` and additionally link the dynamic executable and all sh
[llvm-branch-commits] [lld] r324025 - Merging r323155 in LLD, with modifications to handle int3 fill
Author: rnk Date: Thu Feb 1 14:37:22 2018 New Revision: 324025 URL: http://llvm.org/viewvc/llvm-project?rev=324025&view=rev Log: Merging r323155 in LLD, with modifications to handle int3 fill Original commit message: r323155 | chandlerc | 2018-01-22 14:05:25 -0800 (Mon, 22 Jan 2018) | 133 lines Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre.. Summary: First, we need to explain the core of the vulnerability. Note that this is a very incomplete description, please see the Project Zero blog post for details: https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html The basis for branch target injection is to direct speculative execution of the processor to some "gadget" of executable code by poisoning the prediction of indirect branches with the address of that gadget. The gadget in turn contains an operation that provides a side channel for reading data. Most commonly, this will look like a load of secret data followed by a branch on the loaded value and then a load of some predictable cache line. The attacker then uses timing of the processors cache to determine which direction the branch took *in the speculative execution*, and in turn what one bit of the loaded value was. Due to the nature of these timing side channels and the branch predictor on Intel processors, this allows an attacker to leak data only accessible to a privileged domain (like the kernel) back into an unprivileged domain. The goal is simple: avoid generating code which contains an indirect branch that could have its prediction poisoned by an attacker. In many cases, the compiler can simply use directed conditional branches and a small search tree. LLVM already has support for lowering switches in this way and the first step of this patch is to disable jump-table lowering of switches and introduce a pass to rewrite explicit indirectbr sequences into a switch over integers. However, there is no fully general alternative to indirect calls. We introduce a new construct we call a "retpoline" to implement indirect calls in a non-speculatable way. It can be thought of loosely as a trampoline for indirect calls which uses the RET instruction on x86. Further, we arrange for a specific call->ret sequence which ensures the processor predicts the return to go to a controlled, known location. The retpoline then "smashes" the return address pushed onto the stack by the call with the desired target of the original indirect call. The result is a predicted return to the next instruction after a call (which can be used to trap speculative execution within an infinite loop) and an actual indirect branch to an arbitrary address. On 64-bit x86 ABIs, this is especially easily done in the compiler by using a guaranteed scratch register to pass the target into this device. For 32-bit ABIs there isn't a guaranteed scratch register and so several different retpoline variants are introduced to use a scratch register if one is available in the calling convention and to otherwise use direct stack push/pop sequences to pass the target address. This "retpoline" mitigation is fully described in the following blog post: https://support.google.com/faqs/answer/7625886 We also support a target feature that disables emission of the retpoline thunk by the compiler to allow for custom thunks if users want them. These are particularly useful in environments like kernels that routinely do hot-patching on boot and want to hot-patch their thunk to different code sequences. They can write this custom thunk and use `-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this case, on x86-64 thu thunk names must be: ``` __llvm_external_retpoline_r11 ``` or on 32-bit: ``` __llvm_external_retpoline_eax __llvm_external_retpoline_ecx __llvm_external_retpoline_edx __llvm_external_retpoline_push ``` And the target of the retpoline is passed in the named register, or in the case of the `push` suffix on the top of the stack via a `pushl` instruction. There is one other important source of indirect branches in x86 ELF binaries: the PLT. These patches also include support for LLD to generate PLT entries that perform a retpoline-style indirection. The only other indirect branches remaining that we are aware of are from precompiled runtimes (such as crt0.o and similar). The ones we have found are not really attackable, and so we have not focused on them here, but eventually these runtimes should also be replicated for retpoline-ed configurations for completeness. For kernels or other freestanding or fully static executables, the compiler switch `-mretpoline` is sufficient to fully mitigate this particular attack. For dynamic executables, you must compile *all* libraries wi
[llvm-branch-commits] [lld] r324026 - Merging r323288:
Author: rnk
Date: Thu Feb 1 14:39:52 2018
New Revision: 324026
URL: http://llvm.org/viewvc/llvm-project?rev=324026&view=rev
Log:
Merging r323288:
r323288 | ruiu | 2018-01-23 16:26:57 -0800 (Tue, 23 Jan 2018) | 3 lines
Fix retpoline PLT header size for i386.
Differential Revision: https://reviews.llvm.org/D42397
Modified:
lld/branches/release_50/ (props changed)
lld/branches/release_50/ELF/Arch/X86.cpp
lld/branches/release_50/test/ELF/i386-retpoline-nopic.s
Propchange: lld/branches/release_50/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Feb 1 14:39:52 2018
@@ -1 +1 @@
-/lld/trunk:308492,308728,308935,308998,309002,310526,310989,310992,312706,313741,323155
+/lld/trunk:308492,308728,308935,308998,309002,310526,310989,310992,312706,313741,323155,323288
Modified: lld/branches/release_50/ELF/Arch/X86.cpp
URL:
http://llvm.org/viewvc/llvm-project/lld/branches/release_50/ELF/Arch/X86.cpp?rev=324026&r1=324025&r2=324026&view=diff
==
--- lld/branches/release_50/ELF/Arch/X86.cpp (original)
+++ lld/branches/release_50/ELF/Arch/X86.cpp Thu Feb 1 14:39:52 2018
@@ -438,7 +438,7 @@ void RetpolinePic::writePlt(uint8_t *Buf
}
RetpolineNoPic::RetpolineNoPic() {
- PltHeaderSize = 64;
+ PltHeaderSize = 48;
PltEntrySize = 32;
}
@@ -464,10 +464,6 @@ void RetpolineNoPic::writePltHeader(uint
0x59,// 2d: pop %ecx
0xc3,// 2e: ret
0xcc,// 2f: int3
- 0xcc, 0xcc, 0xcc, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc,
- 0xcc, 0xcc, 0xcc, 0xcc,
};
memcpy(Buf, PltData, sizeof(PltData));
assert(sizeof(PltData) == TargetInfo::PltHeaderSize);
Modified: lld/branches/release_50/test/ELF/i386-retpoline-nopic.s
URL:
http://llvm.org/viewvc/llvm-project/lld/branches/release_50/test/ELF/i386-retpoline-nopic.s?rev=324026&r1=324025&r2=324026&view=diff
==
--- lld/branches/release_50/test/ELF/i386-retpoline-nopic.s (original)
+++ lld/branches/release_50/test/ELF/i386-retpoline-nopic.s Thu Feb 1 14:39:52
2018
@@ -30,50 +30,34 @@
// CHECK-NEXT: 1103d: 59 popl%ecx
// CHECK-NEXT: 1103e: c3 retl
// CHECK-NEXT: 1103f: cc int3
-// CHECK-NEXT: 11040: cc int3
-// CHECK-NEXT: 11041: cc int3
-// CHECK-NEXT: 11042: cc int3
-// CHECK-NEXT: 11043: cc int3
-// CHECK-NEXT: 11044: cc int3
-// CHECK-NEXT: 11045: cc int3
-// CHECK-NEXT: 11046: cc int3
-// CHECK-NEXT: 11047: cc int3
-// CHECK-NEXT: 11048: cc int3
-// CHECK-NEXT: 11049: cc int3
-// CHECK-NEXT: 1104a: cc int3
-// CHECK-NEXT: 1104b: cc int3
-// CHECK-NEXT: 1104c: cc int3
-// CHECK-NEXT: 1104d: cc int3
-// CHECK-NEXT: 1104e: cc int3
-// CHECK-NEXT: 1104f: cc int3
-// CHECK-NEXT: 11050: 50 pushl %eax
-// CHECK-NEXT: 11051: a1 0c 20 01 00 movl73740, %eax
-// CHECK-NEXT: 11056: e8 d5 ff ff ff calll -43 <.plt+0x20>
-// CHECK-NEXT: 1105b: e9 c1 ff ff ff jmp -63 <.plt+0x11>
-// CHECK-NEXT: 11060: 68 00 00 00 00 pushl $0
-// CHECK-NEXT: 11065: e9 a6 ff ff ff jmp -90 <.plt>
-// CHECK-NEXT: 1106a: cc int3
-// CHECK-NEXT: 1106b: cc int3
-// CHECK-NEXT: 1106c: cc int3
-// CHECK-NEXT: 1106d: cc int3
-// CHECK-NEXT: 1106e: cc int3
-// CHECK-NEXT: 1106f: cc int3
-// CHECK-NEXT: 11070: 50 pushl %eax
-// CHECK-NEXT: 11071: a1 10 20 01 00 movl73744, %eax
-// CHECK-NEXT: 11076: e8 b5 ff ff ff calll -75 <.plt+0x20>
-// CHECK-NEXT: 1107b: e9 a1 ff ff ff jmp -95 <.plt+0x11>
-// CHECK-NEXT: 11080: 68 08 00 00 00 pushl $8
-// CHECK-NEXT: 11085: e9 86 ff ff ff jmp -122 <.plt>
-// CHECK-NEXT: 1108a: cc int3
-// CHECK-NEXT: 1108b: cc int3
-// CHECK-NEXT: 1108c: cc int3
-// CHECK-NEXT: 1108d: cc int3
-// CHECK-NEXT: 1108e: cc int3
-// CHECK-NEXT: 1108f: cc int3
+// CHECK-NEXT: 11040: 50 pushl %eax
+// CHECK-NEXT: 11041: a1 0c 20 01 00 movl73740, %eax
+// CHECK-NEXT: 11046: e8 e5 ff ff ff calll -27 <.plt+0x20>
+// CHECK-NEXT: 1104b: e9 d1 ff ff ff jmp -47 <.plt+0x11>
+// CHECK-NEXT: 11050: 68 00 00 00 00 pushl $0
+// CHECK-NEXT: 11055: e9 b6 ff ff ff jmp -74 <.plt>
+// CHECK-NEXT: 1105a: cc int3
+// CHECK-NEXT: 1105b: cc i
[llvm-branch-commits] [llvm-branch] r325082 - Merging r324449:
Author: rnk
Date: Tue Feb 13 16:18:17 2018
New Revision: 325082
URL: http://llvm.org/viewvc/llvm-project?rev=325082&view=rev
Log:
Merging r324449:
r324449 | chandlerc | 2018-02-06 22:16:24 -0800 (Tue, 06 Feb 2018) | 15 lines
[x86/retpoline] Make the external thunk names exactly match the names
that happened to end up in GCC.
This is really unfortunate, as the names don't have much rhyme or reason
to them. Originally in the discussions it seemed fine to rely on aliases
to map different names to whatever external thunk code developers wished
to use but there are practical problems with that in the kernel it turns
out. And since we're discovering this practical problems late and since
GCC has already shipped a release with one set of names, we are forced,
yet again, to blindly match what is there.
Somewhat rushing this patch out for the Linux kernel folks to test and
so we can get it patched into our releases.
Differential Revision: https://reviews.llvm.org/D42998
Modified:
llvm/branches/release_60/ (props changed)
llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_60/test/CodeGen/X86/retpoline-external.ll
Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 13 16:18:17 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324422,324746,324772
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324422,324449,324746,324772
Modified: llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp?rev=325082&r1=325081&r2=325082&view=diff
==
--- llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp Tue Feb 13
16:18:17 2018
@@ -27094,28 +27094,57 @@ static unsigned getOpcodeForRetpoline(un
static const char *getRetpolineSymbol(const X86Subtarget &Subtarget,
unsigned Reg) {
+ if (Subtarget.useRetpolineExternalThunk()) {
+// When using an external thunk for retpolines, we pick names that match
the
+// names GCC happens to use as well. This helps simplify the implementation
+// of the thunks for kernels where they have no easy ability to create
+// aliases and are doing non-trivial configuration of the thunk's body. For
+// example, the Linux kernel will do boot-time hot patching of the thunk
+// bodies and cannot easily export aliases of these to loaded modules.
+//
+// Note that at any point in the future, we may need to change the
semantics
+// of how we implement retpolines and at that time will likely change the
+// name of the called thunk. Essentially, there is no hard guarantee that
+// LLVM will generate calls to specific thunks, we merely make a
best-effort
+// attempt to help out kernels and other systems where duplicating the
+// thunks is costly.
+switch (Reg) {
+case 0:
+ assert(!Subtarget.is64Bit() && "R11 should always be available on x64");
+ return "__x86_indirect_thunk";
+case X86::EAX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_eax";
+case X86::ECX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_ecx";
+case X86::EDX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_edx";
+case X86::R11:
+ assert(Subtarget.is64Bit() && "Should not be using a 64-bit thunk!");
+ return "__x86_indirect_thunk_r11";
+}
[llvm-branch-commits] [llvm-branch] r325083 - Merging r324645:
Author: rnk
Date: Tue Feb 13 16:19:26 2018
New Revision: 325083
URL: http://llvm.org/viewvc/llvm-project?rev=325083&view=rev
Log:
Merging r324645:
r324645 | dwmw2 | 2018-02-08 12:06:05 -0800 (Thu, 08 Feb 2018) | 5 lines
[X86] Support 'V' register operand modifier
This allows the register name to be printed without the leading '%'.
This can be used for emitting calls to the retpoline thunks from inline
asm.
Added:
llvm/branches/release_60/test/CodeGen/X86/inline-asm-modifier-V.ll
- copied unchanged from r324645,
llvm/trunk/test/CodeGen/X86/inline-asm-modifier-V.ll
Modified:
llvm/branches/release_60/ (props changed)
llvm/branches/release_60/lib/Target/X86/X86AsmPrinter.cpp
Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 13 16:19:26 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324422,324449,324746,324772
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324422,324449,324645,324746,324772
Modified: llvm/branches/release_60/lib/Target/X86/X86AsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86AsmPrinter.cpp?rev=325083&r1=325082&r2=325083&view=diff
==
--- llvm/branches/release_60/lib/Target/X86/X86AsmPrinter.cpp (original)
+++ llvm/branches/release_60/lib/Target/X86/X86AsmPrinter.cpp Tue Feb 13
16:19:26 2018
@@ -370,6 +370,8 @@ static void printIntelMemReference(X86As
static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO,
char Mode, raw_ostream &O) {
unsigned Reg = MO.getReg();
+ bool EmitPercent = true;
+
switch (Mode) {
default: return true; // Unknown mode.
case 'b': // Print QImode register
@@ -384,6 +386,9 @@ static bool printAsmMRegister(X86AsmPrin
case 'k': // Print SImode register
Reg = getX86SubSuperRegister(Reg, 32);
break;
+ case 'V':
+EmitPercent = false;
+LLVM_FALLTHROUGH;
case 'q':
// Print 64-bit register names if 64-bit integer registers are available.
// Otherwise, print 32-bit register names.
@@ -391,7 +396,10 @@ static bool printAsmMRegister(X86AsmPrin
break;
}
- O << '%' << X86ATTInstPrinter::getRegisterName(Reg);
+ if (EmitPercent)
+O << '%';
+
+ O << X86ATTInstPrinter::getRegisterName(Reg);
return false;
}
@@ -464,6 +472,7 @@ bool X86AsmPrinter::PrintAsmOperand(cons
case 'w': // Print HImode register
case 'k': // Print SImode register
case 'q': // Print DImode register
+case 'V': // Print native register without '%'
if (MO.isReg())
return printAsmMRegister(*this, MO, ExtraCode[0], O);
printOperand(*this, MI, OpNo, O);
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm-branch] r325084 - Merging r325049:
Author: rnk
Date: Tue Feb 13 16:22:20 2018
New Revision: 325084
URL: http://llvm.org/viewvc/llvm-project?rev=325084&view=rev
Log:
Merging r325049:
r325049 | rnk | 2018-02-13 12:47:49 -0800 (Tue, 13 Feb 2018) | 17 lines
[X86] Use EDI for retpoline when no scratch regs are left
Summary:
Instead of solving the hard problem of how to pass the callee to the indirect
jump thunk without a register, just use a CSR. At a call boundary, there's
nothing stopping us from using a CSR to hold the callee as long as we save and
restore it in the prologue.
Also, add tests for this mregparm=3 case. I wrote execution tests for
__llvm_retpoline_push, but they never got committed as lit tests, either
because I never rewrote them or because they got lost in merge conflicts.
Reviewers: chandlerc, dwmw2
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D43214
Added:
llvm/branches/release_60/test/CodeGen/X86/retpoline-regparm.ll
- copied unchanged from r325049,
llvm/trunk/test/CodeGen/X86/retpoline-regparm.ll
Modified:
llvm/branches/release_60/ (props changed)
llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_60/lib/Target/X86/X86RetpolineThunks.cpp
llvm/branches/release_60/test/CodeGen/X86/retpoline.ll
Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 13 16:22:20 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324422,324449,324645,324746,324772
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324422,324449,324645,324746,324772,325049
Modified: llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp?rev=325084&r1=325083&r2=325084&view=diff
==
--- llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_60/lib/Target/X86/X86ISelLowering.cpp Tue Feb 13
16:22:20 2018
@@ -27109,9 +27109,6 @@ static const char *getRetpolineSymbol(co
// attempt to help out kernels and other systems where duplicating the
// thunks is costly.
switch (Reg) {
-case 0:
- assert(!Subtarget.is64Bit() && "R11 should always be available on x64");
- return "__x86_indirect_thunk";
case X86::EAX:
assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
return "__x86_indirect_thunk_eax";
@@ -27121,6 +27118,9 @@ static const char *getRetpolineSymbol(co
case X86::EDX:
assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
return "__x86_indirect_thunk_edx";
+case X86::EDI:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_edi";
case X86::R11:
assert(Subtarget.is64Bit() && "Should not be using a 64-bit thunk!");
return "__x86_indirect_thunk_r11";
@@ -27130,9 +27130,6 @@ static const char *getRetpolineSymbol(co
// When targeting an internal COMDAT thunk use an LLVM-specific name.
switch (Reg) {
- case 0:
-assert(!Subtarget.is64Bit() && "R11 should always be available on x64");
-return "__llvm_retpoline_push";
case X86::EAX:
assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
return "__llvm_retpoline_eax";
@@ -27142,6 +27139,9 @@ static const char *getRetpolineSymbol(co
case X86::EDX:
assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
return "__llvm_retpoline_edx";
+ case X86::EDI:
+assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+return "__llvm_retpoline_edi";
[llvm-branch-commits] [llvm-branch] r325086 - Merging r325085:
Author: rnk
Date: Tue Feb 13 16:26:04 2018
New Revision: 325086
URL: http://llvm.org/viewvc/llvm-project?rev=325086&view=rev
Log:
Merging r325085:
r325085 | rnk | 2018-02-13 16:24:29 -0800 (Tue, 13 Feb 2018) | 3 lines
[X86] Remove dead code from retpoline thunk generation
Follow-up to r325049
Modified:
llvm/branches/release_60/ (props changed)
llvm/branches/release_60/lib/Target/X86/X86RetpolineThunks.cpp
Propchange: llvm/branches/release_60/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 13 16:26:04 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324422,324449,324645,324746,324772,325049
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,33,322272,322313,322372,322473,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324422,324449,324645,324746,324772,325049,325085
Modified: llvm/branches/release_60/lib/Target/X86/X86RetpolineThunks.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86RetpolineThunks.cpp?rev=325086&r1=325085&r2=325086&view=diff
==
--- llvm/branches/release_60/lib/Target/X86/X86RetpolineThunks.cpp (original)
+++ llvm/branches/release_60/lib/Target/X86/X86RetpolineThunks.cpp Tue Feb 13
16:26:04 2018
@@ -74,7 +74,6 @@ private:
void createThunkFunction(Module &M, StringRef Name);
void insertRegReturnAddrClobber(MachineBasicBlock &MBB, unsigned Reg);
- void insert32BitPushReturnAddrClobber(MachineBasicBlock &MBB);
void populateThunk(MachineFunction &MF, Optional Reg = None);
};
@@ -225,31 +224,6 @@ void X86RetpolineThunks::insertRegReturn
.addReg(Reg);
}
-void X86RetpolineThunks::insert32BitPushReturnAddrClobber(
-MachineBasicBlock &MBB) {
- // The instruction sequence we use to replace the return address without
- // a scratch register is somewhat complicated:
- // # Clear capture_spec from return address.
- // addl $4, %esp
- // # Top of stack words are: Callee, RA. Exchange Callee and RA.
- // pushl 4(%esp) # Push callee
- // pushl 4(%esp) # Push RA
- // popl 8(%esp) # Pop RA to final RA
- // popl (%esp)# Pop callee to next top of stack
- // retl # Ret to callee
- BuildMI(&MBB, DebugLoc(), TII->get(X86::ADD32ri), X86::ESP)
- .addReg(X86::ESP)
- .addImm(4);
- addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::PUSH32rmm)), X86::ESP,
- false, 4);
- addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::PUSH32rmm)), X86::ESP,
- false, 4);
- addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::POP32rmm)), X86::ESP,
- false, 8);
- addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::POP32rmm)), X86::ESP,
- false, 0);
-}
-
void X86RetpolineThunks::populateThunk(MachineFunction &MF,
Optional Reg) {
// Set MF properties. We never use vregs...
___
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[llvm-branch-commits] [llvm-branch] r325089 - Merging r324645:
Author: rnk
Date: Tue Feb 13 16:33:00 2018
New Revision: 325089
URL: http://llvm.org/viewvc/llvm-project?rev=325089&view=rev
Log:
Merging r324645:
r324645 | dwmw2 | 2018-02-08 12:06:05 -0800 (Thu, 08 Feb 2018) | 5 lines
[X86] Support 'V' register operand modifier
This allows the register name to be printed without the leading '%'.
This can be used for emitting calls to the retpoline thunks from inline
asm.
Added:
llvm/branches/release_50/test/CodeGen/X86/inline-asm-modifier-V.ll
- copied unchanged from r324645,
llvm/trunk/test/CodeGen/X86/inline-asm-modifier-V.ll
Modified:
llvm/branches/release_50/ (props changed)
llvm/branches/release_50/lib/Target/X86/X86AsmPrinter.cpp
Propchange: llvm/branches/release_50/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 13 16:33:00 2018
@@ -1,2 +1,2 @@
-/llvm/trunk:313366,323155,323915,324449
+/llvm/trunk:313366,323155,323915,324449,324645
/llvm/trunk:155241,308483-308484,308503,308808,308813,308847,308891,308906,308950,308963,308978,308986,309044,309071,309113,309120,309122,309140,309227,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495,309555,309561,309594,309614,309651,309744,309758,309849,309928,309930,309945,310066,310071,310190,310240-310242,310250,310253,310262,310267,310481,310492,310498,310510,310534,310552,310604,310712,310779,310784,310796,310842,310906,310926,310939,310979,310988,310990-310991,311061,311068,311071,311087,311229,311258,311263,311387,311429,311554,311565,311572,311623,311835,312022,312285,313334:312337
Modified: llvm/branches/release_50/lib/Target/X86/X86AsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/X86/X86AsmPrinter.cpp?rev=325089&r1=325088&r2=325089&view=diff
==
--- llvm/branches/release_50/lib/Target/X86/X86AsmPrinter.cpp (original)
+++ llvm/branches/release_50/lib/Target/X86/X86AsmPrinter.cpp Tue Feb 13
16:33:00 2018
@@ -344,6 +344,8 @@ static void printIntelMemReference(X86As
static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO,
char Mode, raw_ostream &O) {
unsigned Reg = MO.getReg();
+ bool EmitPercent = true;
+
switch (Mode) {
default: return true; // Unknown mode.
case 'b': // Print QImode register
@@ -358,6 +360,9 @@ static bool printAsmMRegister(X86AsmPrin
case 'k': // Print SImode register
Reg = getX86SubSuperRegister(Reg, 32);
break;
+ case 'V':
+EmitPercent = false;
+LLVM_FALLTHROUGH;
case 'q':
// Print 64-bit register names if 64-bit integer registers are available.
// Otherwise, print 32-bit register names.
@@ -365,7 +370,10 @@ static bool printAsmMRegister(X86AsmPrin
break;
}
- O << '%' << X86ATTInstPrinter::getRegisterName(Reg);
+ if (EmitPercent)
+O << '%';
+
+ O << X86ATTInstPrinter::getRegisterName(Reg);
return false;
}
@@ -438,6 +446,7 @@ bool X86AsmPrinter::PrintAsmOperand(cons
case 'w': // Print HImode register
case 'k': // Print SImode register
case 'q': // Print DImode register
+case 'V': // Print native register without '%'
if (MO.isReg())
return printAsmMRegister(*this, MO, ExtraCode[0], O);
printOperand(*this, MI, OpNo, O);
___
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[llvm-branch-commits] [llvm-branch] r325088 - Merging r324449:
Author: rnk
Date: Tue Feb 13 16:32:26 2018
New Revision: 325088
URL: http://llvm.org/viewvc/llvm-project?rev=325088&view=rev
Log:
Merging r324449:
r324449 | chandlerc | 2018-02-06 22:16:24 -0800 (Tue, 06 Feb 2018) | 15 lines
[x86/retpoline] Make the external thunk names exactly match the names
that happened to end up in GCC.
This is really unfortunate, as the names don't have much rhyme or reason
to them. Originally in the discussions it seemed fine to rely on aliases
to map different names to whatever external thunk code developers wished
to use but there are practical problems with that in the kernel it turns
out. And since we're discovering this practical problems late and since
GCC has already shipped a release with one set of names, we are forced,
yet again, to blindly match what is there.
Somewhat rushing this patch out for the Linux kernel folks to test and
so we can get it patched into our releases.
Differential Revision: https://reviews.llvm.org/D42998
Modified:
llvm/branches/release_50/ (props changed)
llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_50/test/CodeGen/X86/retpoline-external.ll
Propchange: llvm/branches/release_50/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 13 16:32:26 2018
@@ -1,2 +1,2 @@
-/llvm/trunk:313366,323155,323915
+/llvm/trunk:313366,323155,323915,324449
/llvm/trunk:155241,308483-308484,308503,308808,308813,308847,308891,308906,308950,308963,308978,308986,309044,309071,309113,309120,309122,309140,309227,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495,309555,309561,309594,309614,309651,309744,309758,309849,309928,309930,309945,310066,310071,310190,310240-310242,310250,310253,310262,310267,310481,310492,310498,310510,310534,310552,310604,310712,310779,310784,310796,310842,310906,310926,310939,310979,310988,310990-310991,311061,311068,311071,311087,311229,311258,311263,311387,311429,311554,311565,311572,311623,311835,312022,312285,313334:312337
Modified: llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp?rev=325088&r1=325087&r2=325088&view=diff
==
--- llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp Tue Feb 13
16:32:26 2018
@@ -26250,28 +26250,57 @@ static unsigned getOpcodeForRetpoline(un
static const char *getRetpolineSymbol(const X86Subtarget &Subtarget,
unsigned Reg) {
+ if (Subtarget.useRetpolineExternalThunk()) {
+// When using an external thunk for retpolines, we pick names that match
the
+// names GCC happens to use as well. This helps simplify the implementation
+// of the thunks for kernels where they have no easy ability to create
+// aliases and are doing non-trivial configuration of the thunk's body. For
+// example, the Linux kernel will do boot-time hot patching of the thunk
+// bodies and cannot easily export aliases of these to loaded modules.
+//
+// Note that at any point in the future, we may need to change the
semantics
+// of how we implement retpolines and at that time will likely change the
+// name of the called thunk. Essentially, there is no hard guarantee that
+// LLVM will generate calls to specific thunks, we merely make a
best-effort
+// attempt to help out kernels and other systems where duplicating the
+// thunks is costly.
+switch (Reg) {
+case 0:
+ assert(!Subtarget.is64Bit() && "R11 should always be available on x64");
+ return "__x86_indirect_thunk";
+case X86::EAX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_eax";
+case X86::ECX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_ecx";
+case X86::EDX:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_edx";
+case X86::R11:
+ assert(Subtarget.is64Bit() && "Should not be using a 64-bit thunk!");
+ return "__x86_indirect_thunk_r11";
+}
+llvm_unreachable("unexpected reg for retpoline");
+ }
+
+ // When targeting an internal COMDAT thunk use an LLVM-specific name.
switch (Reg) {
case 0:
assert(!Subtarget.is64Bit() && "R11 should always be available on x64");
-return Subtarget.useRetpolineExternalThunk()
- ? "__llvm_external_retpoline_push"
- : "__llvm_retpoline_push";
+return "__llvm_retpoline_push";
case X86::E
[llvm-branch-commits] [llvm-branch] r325090 - Merging r325049:
Author: rnk
Date: Tue Feb 13 16:34:13 2018
New Revision: 325090
URL: http://llvm.org/viewvc/llvm-project?rev=325090&view=rev
Log:
Merging r325049:
r325049 | rnk | 2018-02-13 12:47:49 -0800 (Tue, 13 Feb 2018) | 17 lines
[X86] Use EDI for retpoline when no scratch regs are left
Summary:
Instead of solving the hard problem of how to pass the callee to the indirect
jump thunk without a register, just use a CSR. At a call boundary, there's
nothing stopping us from using a CSR to hold the callee as long as we save and
restore it in the prologue.
Also, add tests for this mregparm=3 case. I wrote execution tests for
__llvm_retpoline_push, but they never got committed as lit tests, either
because I never rewrote them or because they got lost in merge conflicts.
Reviewers: chandlerc, dwmw2
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D43214
Added:
llvm/branches/release_50/test/CodeGen/X86/retpoline-regparm.ll
- copied unchanged from r325049,
llvm/trunk/test/CodeGen/X86/retpoline-regparm.ll
Modified:
llvm/branches/release_50/ (props changed)
llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_50/lib/Target/X86/X86RetpolineThunks.cpp
llvm/branches/release_50/test/CodeGen/X86/retpoline.ll
Propchange: llvm/branches/release_50/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 13 16:34:13 2018
@@ -1,2 +1,2 @@
-/llvm/trunk:313366,323155,323915,324449,324645
+/llvm/trunk:313366,323155,323915,324449,324645,325049
/llvm/trunk:155241,308483-308484,308503,308808,308813,308847,308891,308906,308950,308963,308978,308986,309044,309071,309113,309120,309122,309140,309227,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495,309555,309561,309594,309614,309651,309744,309758,309849,309928,309930,309945,310066,310071,310190,310240-310242,310250,310253,310262,310267,310481,310492,310498,310510,310534,310552,310604,310712,310779,310784,310796,310842,310906,310926,310939,310979,310988,310990-310991,311061,311068,311071,311087,311229,311258,311263,311387,311429,311554,311565,311572,311623,311835,312022,312285,313334:312337
Modified: llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp?rev=325090&r1=325089&r2=325090&view=diff
==
--- llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_50/lib/Target/X86/X86ISelLowering.cpp Tue Feb 13
16:34:13 2018
@@ -26265,9 +26265,6 @@ static const char *getRetpolineSymbol(co
// attempt to help out kernels and other systems where duplicating the
// thunks is costly.
switch (Reg) {
-case 0:
- assert(!Subtarget.is64Bit() && "R11 should always be available on x64");
- return "__x86_indirect_thunk";
case X86::EAX:
assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
return "__x86_indirect_thunk_eax";
@@ -26277,6 +26274,9 @@ static const char *getRetpolineSymbol(co
case X86::EDX:
assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
return "__x86_indirect_thunk_edx";
+case X86::EDI:
+ assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+ return "__x86_indirect_thunk_edi";
case X86::R11:
assert(Subtarget.is64Bit() && "Should not be using a 64-bit thunk!");
return "__x86_indirect_thunk_r11";
@@ -26286,9 +26286,6 @@ static const char *getRetpolineSymbol(co
// When targeting an internal COMDAT thunk use an LLVM-specific name.
switch (Reg) {
- case 0:
-assert(!Subtarget.is64Bit() && "R11 should always be available on x64");
-return "__llvm_retpoline_push";
case X86::EAX:
assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
return "__llvm_retpoline_eax";
@@ -26298,6 +26295,9 @@ static const char *getRetpolineSymbol(co
case X86::EDX:
assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
return "__llvm_retpoline_edx";
+ case X86::EDI:
+assert(!Subtarget.is64Bit() && "Should not be using a 32-bit thunk!");
+return "__llvm_retpoline_edi";
case X86::R11:
assert(Subtarget.is64Bit() && "Should not be using a 64-bit thunk!");
return "__llvm_retpoline_r11";
@@ -26319,15 +26319,13 @@ X86TargetLowering::EmitLoweredRetpoline(
// just use R11, but we scan for uses anyway to ensure we don't generate
// incorrect code. On 32-bit, we use one of EAX, ECX, or EDX that isn't
// already a register use operand to the call to hold the callee. If none
- // are avai
[llvm-branch-commits] [llvm-branch] r325091 - Merging r325085:
Author: rnk
Date: Tue Feb 13 16:34:35 2018
New Revision: 325091
URL: http://llvm.org/viewvc/llvm-project?rev=325091&view=rev
Log:
Merging r325085:
r325085 | rnk | 2018-02-13 16:24:29 -0800 (Tue, 13 Feb 2018) | 3 lines
[X86] Remove dead code from retpoline thunk generation
Follow-up to r325049
Modified:
llvm/branches/release_50/ (props changed)
llvm/branches/release_50/lib/Target/X86/X86RetpolineThunks.cpp
Propchange: llvm/branches/release_50/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 13 16:34:35 2018
@@ -1,2 +1,2 @@
-/llvm/trunk:313366,323155,323915,324449,324645,325049
+/llvm/trunk:313366,323155,323915,324449,324645,325049,325085
/llvm/trunk:155241,308483-308484,308503,308808,308813,308847,308891,308906,308950,308963,308978,308986,309044,309071,309113,309120,309122,309140,309227,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495,309555,309561,309594,309614,309651,309744,309758,309849,309928,309930,309945,310066,310071,310190,310240-310242,310250,310253,310262,310267,310481,310492,310498,310510,310534,310552,310604,310712,310779,310784,310796,310842,310906,310926,310939,310979,310988,310990-310991,311061,311068,311071,311087,311229,311258,311263,311387,311429,311554,311565,311572,311623,311835,312022,312285,313334:312337
Modified: llvm/branches/release_50/lib/Target/X86/X86RetpolineThunks.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/X86/X86RetpolineThunks.cpp?rev=325091&r1=325090&r2=325091&view=diff
==
--- llvm/branches/release_50/lib/Target/X86/X86RetpolineThunks.cpp (original)
+++ llvm/branches/release_50/lib/Target/X86/X86RetpolineThunks.cpp Tue Feb 13
16:34:35 2018
@@ -74,7 +74,6 @@ private:
void createThunkFunction(Module &M, StringRef Name);
void insertRegReturnAddrClobber(MachineBasicBlock &MBB, unsigned Reg);
- void insert32BitPushReturnAddrClobber(MachineBasicBlock &MBB);
void populateThunk(MachineFunction &MF, Optional Reg = None);
};
@@ -225,31 +224,6 @@ void X86RetpolineThunks::insertRegReturn
.addReg(Reg);
}
-void X86RetpolineThunks::insert32BitPushReturnAddrClobber(
-MachineBasicBlock &MBB) {
- // The instruction sequence we use to replace the return address without
- // a scratch register is somewhat complicated:
- // # Clear capture_spec from return address.
- // addl $4, %esp
- // # Top of stack words are: Callee, RA. Exchange Callee and RA.
- // pushl 4(%esp) # Push callee
- // pushl 4(%esp) # Push RA
- // popl 8(%esp) # Pop RA to final RA
- // popl (%esp)# Pop callee to next top of stack
- // retl # Ret to callee
- BuildMI(&MBB, DebugLoc(), TII->get(X86::ADD32ri), X86::ESP)
- .addReg(X86::ESP)
- .addImm(4);
- addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::PUSH32rmm)), X86::ESP,
- false, 4);
- addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::PUSH32rmm)), X86::ESP,
- false, 4);
- addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::POP32rmm)), X86::ESP,
- false, 8);
- addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(X86::POP32rmm)), X86::ESP,
- false, 0);
-}
-
void X86RetpolineThunks::populateThunk(MachineFunction &MF,
Optional Reg) {
// Set MF properties. We never use vregs...
___
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[llvm-branch-commits] [lld] 6529d7c - [PDB] Defer relocating .debug$S until commit time and parallelize it
Author: Reid Kleckner
Date: 2021-01-12T17:46:29-08:00
New Revision: 6529d7c5a45b1b9588e512013b02f891d71bc134
URL:
https://github.com/llvm/llvm-project/commit/6529d7c5a45b1b9588e512013b02f891d71bc134
DIFF:
https://github.com/llvm/llvm-project/commit/6529d7c5a45b1b9588e512013b02f891d71bc134.diff
LOG: [PDB] Defer relocating .debug$S until commit time and parallelize it
This is a pretty classic optimization. Instead of processing symbol
records and copying them to temporary storage, do a first pass to
measure how large the module symbol stream will be, and then copy the
data into place in the PDB file. This requires defering relocation until
much later, which accounts for most of the complexity in this patch.
This patch avoids copying the contents of all live .debug$S sections
into heap memory, which is worth about 20% of private memory usage when
making PDBs. However, this is not an unmitigated performance win,
because it can be faster to read dense, temporary, heap data than it is
to iterate symbol records in object file backed memory a second time.
Results on release chrome.dll:
peak mem: 5164.89MB -> 4072.19MB (-1,092.7MB, -21.2%)
wall-j1: 0m30.844s -> 0m32.094s (slightly slower)
wall-j3: 0m20.968s -> 0m20.312s (slightly faster)
wall-j8: 0m19.062s -> 0m17.672s (meaningfully faster)
I gathered similar numbers for a debug, component build of content.dll
in Chrome, and the performance impact of this change was in the noise.
The memory usage reduction was visible and similar.
Because of the new parallelism in the PDB commit phase, more cores makes
the new approach faster. I'm assuming that most C++ developer machines
these days are at least quad core, so I think this is a win.
Differential Revision: https://reviews.llvm.org/D94267
Added:
Modified:
lld/COFF/Chunks.cpp
lld/COFF/Chunks.h
lld/COFF/PDB.cpp
llvm/include/llvm/DebugInfo/PDB/Native/DbiModuleDescriptorBuilder.h
llvm/lib/DebugInfo/PDB/Native/DbiModuleDescriptorBuilder.cpp
llvm/lib/DebugInfo/PDB/Native/DbiStreamBuilder.cpp
Removed:
diff --git a/lld/COFF/Chunks.cpp b/lld/COFF/Chunks.cpp
index e04ceed505c2..f2cdc24b7bf1 100644
--- a/lld/COFF/Chunks.cpp
+++ b/lld/COFF/Chunks.cpp
@@ -369,47 +369,88 @@ void SectionChunk::writeTo(uint8_t *buf) const {
continue;
}
-uint8_t *off = buf + rel.VirtualAddress;
+applyRelocation(buf + rel.VirtualAddress, rel);
+ }
+}
-auto *sym =
-dyn_cast_or_null(file->getSymbol(rel.SymbolTableIndex));
+void SectionChunk::applyRelocation(uint8_t *off,
+ const coff_relocation &rel) const {
+ auto *sym = dyn_cast_or_null(file->getSymbol(rel.SymbolTableIndex));
-// Get the output section of the symbol for this relocation. The output
-// section is needed to compute SECREL and SECTION relocations used in
debug
-// info.
-Chunk *c = sym ? sym->getChunk() : nullptr;
-OutputSection *os = c ? c->getOutputSection() : nullptr;
-
-// Skip the relocation if it refers to a discarded section, and diagnose it
-// as an error if appropriate. If a symbol was discarded early, it may be
-// null. If it was discarded late, the output section will be null, unless
-// it was an absolute or synthetic symbol.
-if (!sym ||
-(!os && !isa(sym) && !isa(sym))) {
- maybeReportRelocationToDiscarded(this, sym, rel);
- continue;
-}
+ // Get the output section of the symbol for this relocation. The output
+ // section is needed to compute SECREL and SECTION relocations used in debug
+ // info.
+ Chunk *c = sym ? sym->getChunk() : nullptr;
+ OutputSection *os = c ? c->getOutputSection() : nullptr;
-uint64_t s = sym->getRVA();
+ // Skip the relocation if it refers to a discarded section, and diagnose it
+ // as an error if appropriate. If a symbol was discarded early, it may be
+ // null. If it was discarded late, the output section will be null, unless
+ // it was an absolute or synthetic symbol.
+ if (!sym ||
+ (!os && !isa(sym) && !isa(sym))) {
+maybeReportRelocationToDiscarded(this, sym, rel);
+return;
+ }
-// Compute the RVA of the relocation for relative relocations.
-uint64_t p = rva + rel.VirtualAddress;
-switch (config->machine) {
-case AMD64:
- applyRelX64(off, rel.Type, os, s, p);
- break;
-case I386:
- applyRelX86(off, rel.Type, os, s, p);
- break;
-case ARMNT:
- applyRelARM(off, rel.Type, os, s, p);
- break;
-case ARM64:
- applyRelARM64(off, rel.Type, os, s, p);
+ uint64_t s = sym->getRVA();
+
+ // Compute the RVA of the relocation for relative relocations.
+ uint64_t p = rva + rel.VirtualAddress;
+ switch (config->machine) {
+ case AMD64:
+applyRelX64(off, rel.Type, os, s, p);
+break;
+ case I386:
+applyRelX86(off, rel.Type, os, s, p);
+break;
+ case ARMNT:
+applyR
[llvm-branch-commits] [libcxx] 4f24d0d - Fix libc++ clang-cl build, swap attribute order
Author: Reid Kleckner
Date: 2021-01-15T11:44:13-08:00
New Revision: 4f24d0dd5386cc0ff61be23062b89855da87094b
URL:
https://github.com/llvm/llvm-project/commit/4f24d0dd5386cc0ff61be23062b89855da87094b
DIFF:
https://github.com/llvm/llvm-project/commit/4f24d0dd5386cc0ff61be23062b89855da87094b.diff
LOG: Fix libc++ clang-cl build, swap attribute order
Clang insists that __attribute__ attributes precede __declspec
attributes. This is a longstanding known issue:
https://llvm.org/pr24559. Re-order the visibility and deprecation macros
to fix the build.
Differential Revision: https://reviews.llvm.org/D94788
Added:
Modified:
libcxx/include/__locale
libcxx/src/locale.cpp
Removed:
diff --git a/libcxx/include/__locale b/libcxx/include/__locale
index 4e9e0c08acf0..7b7331d74a01 100644
--- a/libcxx/include/__locale
+++ b/libcxx/include/__locale
@@ -1078,7 +1078,7 @@ protected:
// template <> class codecvt // deprecated in C++20
template <>
-class _LIBCPP_TYPE_VIS _LIBCPP_DEPRECATED_IN_CXX20 codecvt
+class _LIBCPP_DEPRECATED_IN_CXX20 _LIBCPP_TYPE_VIS codecvt
: public locale::facet,
public codecvt_base
{
@@ -1254,7 +1254,7 @@ protected:
// template <> class codecvt // deprecated in C++20
template <>
-class _LIBCPP_TYPE_VIS _LIBCPP_DEPRECATED_IN_CXX20 codecvt
+class _LIBCPP_DEPRECATED_IN_CXX20 _LIBCPP_TYPE_VIS codecvt
: public locale::facet,
public codecvt_base
{
@@ -1453,8 +1453,8 @@ _LIBCPP_SUPPRESS_DEPRECATED_POP
_LIBCPP_EXTERN_TEMPLATE(class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS
codecvt_byname)
_LIBCPP_EXTERN_TEMPLATE(class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS
codecvt_byname)
-_LIBCPP_EXTERN_TEMPLATE(class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS
_LIBCPP_DEPRECATED_IN_CXX20 codecvt_byname) //
deprecated in C++20
-_LIBCPP_EXTERN_TEMPLATE(class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS
_LIBCPP_DEPRECATED_IN_CXX20 codecvt_byname) //
deprecated in C++20
+_LIBCPP_EXTERN_TEMPLATE(class _LIBCPP_DEPRECATED_IN_CXX20
_LIBCPP_EXTERN_TEMPLATE_TYPE_VIS codecvt_byname) //
deprecated in C++20
+_LIBCPP_EXTERN_TEMPLATE(class _LIBCPP_DEPRECATED_IN_CXX20
_LIBCPP_EXTERN_TEMPLATE_TYPE_VIS codecvt_byname) //
deprecated in C++20
#ifndef _LIBCPP_NO_HAS_CHAR8_T
_LIBCPP_EXTERN_TEMPLATE(class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS
codecvt_byname) // C++20
_LIBCPP_EXTERN_TEMPLATE(class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS
codecvt_byname) // C++20
diff --git a/libcxx/src/locale.cpp b/libcxx/src/locale.cpp
index 42bac3c371cd..f109389f68f3 100644
--- a/libcxx/src/locale.cpp
+++ b/libcxx/src/locale.cpp
@@ -6334,8 +6334,8 @@ template class _LIBCPP_CLASS_TEMPLATE_INSTANTIATION_VIS
messages_byname
template class _LIBCPP_CLASS_TEMPLATE_INSTANTIATION_VIS codecvt_byname;
template class _LIBCPP_CLASS_TEMPLATE_INSTANTIATION_VIS
codecvt_byname;
-template class _LIBCPP_CLASS_TEMPLATE_INSTANTIATION_VIS
_LIBCPP_DEPRECATED_IN_CXX20 codecvt_byname;
-template class _LIBCPP_CLASS_TEMPLATE_INSTANTIATION_VIS
_LIBCPP_DEPRECATED_IN_CXX20 codecvt_byname;
+template class _LIBCPP_DEPRECATED_IN_CXX20
_LIBCPP_CLASS_TEMPLATE_INSTANTIATION_VIS codecvt_byname;
+template class _LIBCPP_DEPRECATED_IN_CXX20
_LIBCPP_CLASS_TEMPLATE_INSTANTIATION_VIS codecvt_byname;
#ifndef _LIBCPP_NO_HAS_CHAR8_T
template class _LIBCPP_CLASS_TEMPLATE_INSTANTIATION_VIS
codecvt_byname;
template class _LIBCPP_CLASS_TEMPLATE_INSTANTIATION_VIS
codecvt_byname;
___
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[llvm-branch-commits] [llvm] 64db296 - Revert "[BasicAA] Handle recursive queries more efficiently"
Author: Reid Kleckner
Date: 2021-01-15T12:29:57-08:00
New Revision: 64db296e5a8c9fdc2f7feb4afb60d59c140a78aa
URL:
https://github.com/llvm/llvm-project/commit/64db296e5a8c9fdc2f7feb4afb60d59c140a78aa
DIFF:
https://github.com/llvm/llvm-project/commit/64db296e5a8c9fdc2f7feb4afb60d59c140a78aa.diff
LOG: Revert "[BasicAA] Handle recursive queries more efficiently"
This reverts commit a3904cc77f181cff7355357688edfc392a236f5d.
It causes the compiler to crash while building Harfbuzz for ARM in
Chromium, reduced reproducer forthcoming:
https://crbug.com/1167305
Added:
Modified:
llvm/include/llvm/Analysis/BasicAliasAnalysis.h
llvm/lib/Analysis/BasicAliasAnalysis.cpp
llvm/lib/Analysis/GlobalsModRef.cpp
Removed:
diff --git a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
index b95365d0481f..635c35585f81 100644
--- a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
+++ b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
@@ -240,17 +240,18 @@ class BasicAAResult : public AAResultBase {
AliasResult aliasPHI(const PHINode *PN, LocationSize PNSize,
const AAMDNodes &PNAAInfo, const Value *V2,
LocationSize V2Size, const AAMDNodes &V2AAInfo,
- AAQueryInfo &AAQI);
+ const Value *UnderV2, AAQueryInfo &AAQI);
AliasResult aliasSelect(const SelectInst *SI, LocationSize SISize,
const AAMDNodes &SIAAInfo, const Value *V2,
LocationSize V2Size, const AAMDNodes &V2AAInfo,
- AAQueryInfo &AAQI);
+ const Value *UnderV2, AAQueryInfo &AAQI);
AliasResult aliasCheck(const Value *V1, LocationSize V1Size,
const AAMDNodes &V1AATag, const Value *V2,
LocationSize V2Size, const AAMDNodes &V2AATag,
- AAQueryInfo &AAQI);
+ AAQueryInfo &AAQI, const Value *O1 = nullptr,
+ const Value *O2 = nullptr);
AliasResult aliasCheckRecursive(const Value *V1, LocationSize V1Size,
const AAMDNodes &V1AATag, const Value *V2,
diff --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp
b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
index 29fd58e6e5d7..313a85ccc4de 100644
--- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp
+++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
@@ -798,8 +798,26 @@ AliasResult BasicAAResult::alias(const MemoryLocation
&LocA,
AAQueryInfo &AAQI) {
assert(notDifferentParent(LocA.Ptr, LocB.Ptr) &&
"BasicAliasAnalysis doesn't support interprocedural queries.");
- return aliasCheck(LocA.Ptr, LocA.Size, LocA.AATags, LocB.Ptr, LocB.Size,
-LocB.AATags, AAQI);
+
+ // If we have a directly cached entry for these locations, we have recursed
+ // through this once, so just return the cached results. Notably, when this
+ // happens, we don't clear the cache.
+ AAQueryInfo::LocPair Locs(LocA, LocB);
+ if (Locs.first.Ptr > Locs.second.Ptr)
+std::swap(Locs.first, Locs.second);
+ auto CacheIt = AAQI.AliasCache.find(Locs);
+ if (CacheIt != AAQI.AliasCache.end()) {
+// This code exists to skip a second BasicAA call while recursing into
+// BestAA. Don't make use of assumptions here.
+const auto &Entry = CacheIt->second;
+return Entry.isDefinitive() ? Entry.Result : MayAlias;
+ }
+
+ AliasResult Alias = aliasCheck(LocA.Ptr, LocA.Size, LocA.AATags, LocB.Ptr,
+ LocB.Size, LocB.AATags, AAQI);
+
+ assert(VisitedPhiBBs.empty());
+ return Alias;
}
/// Checks to see if the specified callsite can clobber the specified memory
@@ -1112,17 +1130,16 @@ AliasResult BasicAAResult::aliasGEP(
if (isGEPBaseAtNegativeOffset(GEP2, DecompGEP2, DecompGEP1, V1Size))
return NoAlias;
// Do the base pointers alias?
-AliasResult BaseAlias = getBestAAResults().alias(
-MemoryLocation::getBeforeOrAfter(UnderlyingV1),
-MemoryLocation::getBeforeOrAfter(UnderlyingV2), AAQI);
+AliasResult BaseAlias = aliasCheck(
+UnderlyingV1, LocationSize::beforeOrAfterPointer(), AAMDNodes(),
+UnderlyingV2, LocationSize::beforeOrAfterPointer(), AAMDNodes(), AAQI);
// For GEPs with identical offsets, we can preserve the size and AAInfo
// when performing the alias check on the underlying objects.
if (BaseAlias == MayAlias && DecompGEP1.Offset == DecompGEP2.Offset &&
DecompGEP1.VarIndices == DecompGEP2.VarIndices) {
- AliasResult PreciseBaseAlias = getBestAAResults().alias(
- MemoryLocation(UnderlyingV1, V1Size, V1AAInfo),
- MemoryLocation(UnderlyingV2, V2Size, V2AAInfo), AAQI);
+ AliasResult PreciseBaseAlias = aliasCheck(
+ UnderlyingV1, V1Size, V
[llvm-branch-commits] [clang] 6f69f2e - Consider ASan messages interesting for creduce
Author: Reid Kleckner Date: 2021-01-19T11:15:02-08:00 New Revision: 6f69f2ed61ae805df496fc86ef22e7685573d556 URL: https://github.com/llvm/llvm-project/commit/6f69f2ed61ae805df496fc86ef22e7685573d556 DIFF: https://github.com/llvm/llvm-project/commit/6f69f2ed61ae805df496fc86ef22e7685573d556.diff LOG: Consider ASan messages interesting for creduce Helped me reduce llvm.org/pr48582 Added: Modified: clang/utils/creduce-clang-crash.py Removed: diff --git a/clang/utils/creduce-clang-crash.py b/clang/utils/creduce-clang-crash.py index cdc639c6f854..51f4d9d333bc 100755 --- a/clang/utils/creduce-clang-crash.py +++ b/clang/utils/creduce-clang-crash.py @@ -134,7 +134,8 @@ def read_expected_output(self): r"UNREACHABLE executed at .+?!", r"LLVM IR generation of declaration '.+'", r"Generating code for declaration '.+'", - r"\*\*\* Bad machine code: .+ \*\*\*"] + r"\*\*\* Bad machine code: .+ \*\*\*", + r"ERROR: .*Sanitizer: [^ ]+ "] for msg_re in regexes: match = re.search(msg_re, crash_output) if match: ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] e678656 - Add bounds checking assertions to APValue, NFC
Author: Reid Kleckner
Date: 2021-01-19T11:15:02-08:00
New Revision: e678656625a3e2b6a5f2849f4a6f7612ceeaed07
URL:
https://github.com/llvm/llvm-project/commit/e678656625a3e2b6a5f2849f4a6f7612ceeaed07
DIFF:
https://github.com/llvm/llvm-project/commit/e678656625a3e2b6a5f2849f4a6f7612ceeaed07.diff
LOG: Add bounds checking assertions to APValue, NFC
These checks help find llvm.org/pr48582 without ASan
Added:
Modified:
clang/include/clang/AST/APValue.h
Removed:
diff --git a/clang/include/clang/AST/APValue.h
b/clang/include/clang/AST/APValue.h
index f9b189926c76..5f4ac02f53c9 100644
--- a/clang/include/clang/AST/APValue.h
+++ b/clang/include/clang/AST/APValue.h
@@ -537,10 +537,12 @@ class APValue {
}
APValue &getStructBase(unsigned i) {
assert(isStruct() && "Invalid accessor");
+assert(i < getStructNumBases() && "base class index OOB");
return ((StructData *)(char *)&Data)->Elts[i];
}
APValue &getStructField(unsigned i) {
assert(isStruct() && "Invalid accessor");
+assert(i < getStructNumFields() && "field index OOB");
return ((StructData *)(char *)&Data)->Elts[getStructNumBases() + i];
}
const APValue &getStructBase(unsigned i) const {
___
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[llvm-branch-commits] [lld] 69e0bc7 - [COFF] Use range for on relocations, NFC
Author: Reid Kleckner
Date: 2021-01-20T11:01:33-08:00
New Revision: 69e0bc77a5d74a5f0e57ad3e7a22ce4fba210b85
URL:
https://github.com/llvm/llvm-project/commit/69e0bc77a5d74a5f0e57ad3e7a22ce4fba210b85
DIFF:
https://github.com/llvm/llvm-project/commit/69e0bc77a5d74a5f0e57ad3e7a22ce4fba210b85.diff
LOG: [COFF] Use range for on relocations, NFC
Added:
Modified:
lld/COFF/Chunks.cpp
Removed:
diff --git a/lld/COFF/Chunks.cpp b/lld/COFF/Chunks.cpp
index e04ceed505c2..9d60bc746c96 100644
--- a/lld/COFF/Chunks.cpp
+++ b/lld/COFF/Chunks.cpp
@@ -357,9 +357,7 @@ void SectionChunk::writeTo(uint8_t *buf) const {
// Apply relocations.
size_t inputSize = getSize();
- for (size_t i = 0, e = relocsSize; i < e; i++) {
-const coff_relocation &rel = relocsData[i];
-
+ for (const coff_relocation &rel : getRelocs()) {
// Check for an invalid relocation offset. This check isn't perfect,
because
// we don't have the relocation size, which is only known after checking
the
// machine and relocation type. As a result, a relocation may overwrite the
@@ -451,8 +449,7 @@ static uint8_t getBaserelType(const coff_relocation &rel) {
// fixed by the loader if load-time relocation is needed.
// Only called when base relocation is enabled.
void SectionChunk::getBaserels(std::vector *res) {
- for (size_t i = 0, e = relocsSize; i < e; i++) {
-const coff_relocation &rel = relocsData[i];
+ for (const coff_relocation &rel : getRelocs()) {
uint8_t ty = getBaserelType(rel);
if (ty == IMAGE_REL_BASED_ABSOLUTE)
continue;
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[llvm-branch-commits] [lld] 9e708ac - [COFF] Fix relocation offsets in pdb-file-statics test input
Author: Reid Kleckner Date: 2021-01-20T11:45:30-08:00 New Revision: 9e708ac6b9929e9baa2017ff62f2353e6621a105 URL: https://github.com/llvm/llvm-project/commit/9e708ac6b9929e9baa2017ff62f2353e6621a105 DIFF: https://github.com/llvm/llvm-project/commit/9e708ac6b9929e9baa2017ff62f2353e6621a105.diff LOG: [COFF] Fix relocation offsets in pdb-file-statics test input The relocation offsets were incorrect. I fixed them with llvm-readobj -codeview -codeview-subsection-bytes, which has a helpful printout of the relocations that apply to a given symbol record with their offsets. With this, I was able to update the relocation offsets in the yaml to fix the line table and the S_DEFRANGE_REGISTER records. There is still some remaining inconsistency in yaml2obj and obj2yaml when round tripping MSVC objects, but that isn't a blocker for relanding D94267. Added: Modified: lld/test/COFF/Inputs/pdb-file-statics-a.yaml Removed: diff --git a/lld/test/COFF/Inputs/pdb-file-statics-a.yaml b/lld/test/COFF/Inputs/pdb-file-statics-a.yaml index 27e2ee160724..8ece65403460 100644 --- a/lld/test/COFF/Inputs/pdb-file-statics-a.yaml +++ b/lld/test/COFF/Inputs/pdb-file-statics-a.yaml @@ -1591,16 +1591,16 @@ sections: - VirtualAddress: 154 SymbolName: main Type:IMAGE_REL_AMD64_SECTION - - VirtualAddress: 229 + - VirtualAddress: 222 SymbolName: main Type:IMAGE_REL_AMD64_SECREL - - VirtualAddress: 233 + - VirtualAddress: 226 SymbolName: main Type:IMAGE_REL_AMD64_SECTION - - VirtualAddress: 336 + - VirtualAddress: 328 SymbolName: main Type:IMAGE_REL_AMD64_SECREL - - VirtualAddress: 340 + - VirtualAddress: 332 SymbolName: main Type:IMAGE_REL_AMD64_SECTION - Name:.xdata ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 1a9bd5b - Reland "[PDB] Defer relocating .debug$S until commit time and parallelize it"
Author: Reid Kleckner
Date: 2021-01-20T11:53:43-08:00
New Revision: 1a9bd5b81328adf0dd5a8b4f3ad5949463e66da3
URL:
https://github.com/llvm/llvm-project/commit/1a9bd5b81328adf0dd5a8b4f3ad5949463e66da3
DIFF:
https://github.com/llvm/llvm-project/commit/1a9bd5b81328adf0dd5a8b4f3ad5949463e66da3.diff
LOG: Reland "[PDB] Defer relocating .debug$S until commit time and parallelize
it"
This reverts commit 5b7aef6eb4b2930971029b984cb2360f7682e5a5 and relands
6529d7c5a45b1b9588e512013b02f891d71bc134.
The ASan error was debugged and determined to be the fault of an invalid
object file input in our test suite, which was fixed by my last change.
LLD's project policy is that it assumes input objects are valid, so I
have added a comment about this assumption to the relocation bounds
check.
Added:
Modified:
lld/COFF/Chunks.cpp
lld/COFF/Chunks.h
lld/COFF/PDB.cpp
llvm/include/llvm/DebugInfo/PDB/Native/DbiModuleDescriptorBuilder.h
llvm/lib/DebugInfo/PDB/Native/DbiModuleDescriptorBuilder.cpp
llvm/lib/DebugInfo/PDB/Native/DbiStreamBuilder.cpp
Removed:
diff --git a/lld/COFF/Chunks.cpp b/lld/COFF/Chunks.cpp
index 9d60bc746c96..14d0a5ad716c 100644
--- a/lld/COFF/Chunks.cpp
+++ b/lld/COFF/Chunks.cpp
@@ -367,47 +367,89 @@ void SectionChunk::writeTo(uint8_t *buf) const {
continue;
}
-uint8_t *off = buf + rel.VirtualAddress;
+applyRelocation(buf + rel.VirtualAddress, rel);
+ }
+}
-auto *sym =
-dyn_cast_or_null(file->getSymbol(rel.SymbolTableIndex));
+void SectionChunk::applyRelocation(uint8_t *off,
+ const coff_relocation &rel) const {
+ auto *sym = dyn_cast_or_null(file->getSymbol(rel.SymbolTableIndex));
-// Get the output section of the symbol for this relocation. The output
-// section is needed to compute SECREL and SECTION relocations used in
debug
-// info.
-Chunk *c = sym ? sym->getChunk() : nullptr;
-OutputSection *os = c ? c->getOutputSection() : nullptr;
-
-// Skip the relocation if it refers to a discarded section, and diagnose it
-// as an error if appropriate. If a symbol was discarded early, it may be
-// null. If it was discarded late, the output section will be null, unless
-// it was an absolute or synthetic symbol.
-if (!sym ||
-(!os && !isa(sym) && !isa(sym))) {
- maybeReportRelocationToDiscarded(this, sym, rel);
- continue;
-}
+ // Get the output section of the symbol for this relocation. The output
+ // section is needed to compute SECREL and SECTION relocations used in debug
+ // info.
+ Chunk *c = sym ? sym->getChunk() : nullptr;
+ OutputSection *os = c ? c->getOutputSection() : nullptr;
-uint64_t s = sym->getRVA();
+ // Skip the relocation if it refers to a discarded section, and diagnose it
+ // as an error if appropriate. If a symbol was discarded early, it may be
+ // null. If it was discarded late, the output section will be null, unless
+ // it was an absolute or synthetic symbol.
+ if (!sym ||
+ (!os && !isa(sym) && !isa(sym))) {
+maybeReportRelocationToDiscarded(this, sym, rel);
+return;
+ }
-// Compute the RVA of the relocation for relative relocations.
-uint64_t p = rva + rel.VirtualAddress;
-switch (config->machine) {
-case AMD64:
- applyRelX64(off, rel.Type, os, s, p);
- break;
-case I386:
- applyRelX86(off, rel.Type, os, s, p);
- break;
-case ARMNT:
- applyRelARM(off, rel.Type, os, s, p);
- break;
-case ARM64:
- applyRelARM64(off, rel.Type, os, s, p);
+ uint64_t s = sym->getRVA();
+
+ // Compute the RVA of the relocation for relative relocations.
+ uint64_t p = rva + rel.VirtualAddress;
+ switch (config->machine) {
+ case AMD64:
+applyRelX64(off, rel.Type, os, s, p);
+break;
+ case I386:
+applyRelX86(off, rel.Type, os, s, p);
+break;
+ case ARMNT:
+applyRelARM(off, rel.Type, os, s, p);
+break;
+ case ARM64:
+applyRelARM64(off, rel.Type, os, s, p);
+break;
+ default:
+llvm_unreachable("unknown machine type");
+ }
+}
+
+// Defend against unsorted relocations. This may be overly conservative.
+void SectionChunk::sortRelocations() {
+ auto cmpByVa = [](const coff_relocation &l, const coff_relocation &r) {
+return l.VirtualAddress < r.VirtualAddress;
+ };
+ if (llvm::is_sorted(getRelocs(), cmpByVa))
+return;
+ warn("some relocations in " + file->getName() + " are not sorted");
+ MutableArrayRef newRelocs(
+ bAlloc.Allocate(relocsSize), relocsSize);
+ memcpy(newRelocs.data(), relocsData, relocsSize * sizeof(coff_relocation));
+ llvm::sort(newRelocs, cmpByVa);
+ setRelocs(newRelocs);
+}
+
+// Similar to writeTo, but suitable for relocating a subsection of the overall
+// section.
+void SectionChunk::writeAndRelocateSubsection(ArrayRef sec,
+
[llvm-branch-commits] [llvm] f4bcbdf - Suppress GCC Wdangling-else warning on gtest macros
Author: Reid Kleckner
Date: 2021-01-05T17:32:56-08:00
New Revision: f4bcbdf9cea16bf91ba342268f681de45e15733c
URL:
https://github.com/llvm/llvm-project/commit/f4bcbdf9cea16bf91ba342268f681de45e15733c
DIFF:
https://github.com/llvm/llvm-project/commit/f4bcbdf9cea16bf91ba342268f681de45e15733c.diff
LOG: Suppress GCC Wdangling-else warning on gtest macros
See https://github.com/google/googletest/issues/1119
Added:
Modified:
llvm/unittests/Support/CrashRecoveryTest.cpp
Removed:
diff --git a/llvm/unittests/Support/CrashRecoveryTest.cpp
b/llvm/unittests/Support/CrashRecoveryTest.cpp
index 864b852cf2d2..c38fa0b4cb25 100644
--- a/llvm/unittests/Support/CrashRecoveryTest.cpp
+++ b/llvm/unittests/Support/CrashRecoveryTest.cpp
@@ -109,8 +109,9 @@ TEST(CrashRecoveryTest, LimitedStackTrace) {
std::string Str = RawStream.str();
// FIXME: Handle "Depth" parameter in PrintStackTrace() function
// to print stack trace upto a specified Depth.
- if (!Triple(sys::getProcessTriple()).isOSWindows())
+ if (!Triple(sys::getProcessTriple()).isOSWindows()) {
EXPECT_EQ(std::string::npos, Str.find("#1"));
+ }
}
#ifdef _WIN32
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[llvm-branch-commits] [llvm] 08e5e91 - [X86] Remove [ER]SP from all CSR lists
Author: Reid Kleckner
Date: 2021-01-06T09:50:46-08:00
New Revision: 08e5e91e45af96e564f3c19be7ed4cb00bac3034
URL:
https://github.com/llvm/llvm-project/commit/08e5e91e45af96e564f3c19be7ed4cb00bac3034
DIFF:
https://github.com/llvm/llvm-project/commit/08e5e91e45af96e564f3c19be7ed4cb00bac3034.diff
LOG: [X86] Remove [ER]SP from all CSR lists
The CSR lists control which registers are spilled and reloaded in the
prologue and epilogue. The stack pointer is managed explicitly, and
should never be pushed or popped. Remove it from these lists. This
affected regcall and preserves all / most.
Differential Revision: https://reviews.llvm.org/D94118
Added:
Modified:
llvm/lib/Target/X86/X86CallingConv.td
llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
llvm/test/CodeGen/X86/dynamic-regmask.ll
llvm/test/CodeGen/X86/ipra-reg-usage.ll
Removed:
diff --git a/llvm/lib/Target/X86/X86CallingConv.td
b/llvm/lib/Target/X86/X86CallingConv.td
index 9e414ceeb781..3735fab818ce 100644
--- a/llvm/lib/Target/X86/X86CallingConv.td
+++ b/llvm/lib/Target/X86/X86CallingConv.td
@@ -1102,7 +1102,7 @@ def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub
CSR_64_TLS_Darwin, RBP)
// All GPRs - except r11
def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
- R8, R9, R10, RSP)>;
+ R8, R9, R10)>;
// All registers - except r11
def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
@@ -1160,17 +1160,16 @@ def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add
RBX, RSI, R14, R15,
def CSR_64_HHVM : CalleeSavedRegs<(add R12)>;
// Register calling convention preserves few GPR and XMM8-15
-def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP, ESP)>;
+def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE,
(sequence "XMM%u", 4, 7))>;
def CSR_Win32_CFGuard_Check_NoSSE : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE,
ECX)>;
def CSR_Win32_CFGuard_Check : CalleeSavedRegs<(add CSR_32_RegCall, ECX)>;
-def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP,
+def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP,
(sequence "R%u", 10, 15))>;
def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE,
(sequence "XMM%u", 8, 15))>;
-def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP,
+def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP,
(sequence "R%u", 12, 15))>;
def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE,
(sequence "XMM%u", 8, 15))>;
-
diff --git a/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
b/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
index 799747b2aba6..ffe5ffb64af1 100644
--- a/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
+++ b/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
@@ -283,8 +283,7 @@ declare i32 @test_argv32i1helper(<32 x i1> %x0, <32 x i1>
%x1, <32 x i1> %x2)
define dso_local x86_regcallcc i32 @test_argv32i1(<32 x i1> %x0, <32 x i1>
%x1, <32 x i1> %x2) {
; X32-LABEL: test_argv32i1:
; X32: # %bb.0: # %entry
-; X32-NEXT:pushl %esp
-; X32-NEXT:subl $72, %esp
+; X32-NEXT:subl $76, %esp
; X32-NEXT:vmovups %xmm7, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; X32-NEXT:vmovups %xmm6, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; X32-NEXT:vmovups %xmm5, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
@@ -303,8 +302,7 @@ define dso_local x86_regcallcc i32 @test_argv32i1(<32 x i1>
%x0, <32 x i1> %x1,
; X32-NEXT:vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm5 # 16-byte Reload
; X32-NEXT:vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm6 # 16-byte Reload
; X32-NEXT:vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm7 # 16-byte Reload
-; X32-NEXT:addl $72, %esp
-; X32-NEXT:popl %esp
+; X32-NEXT:addl $76, %esp
; X32-NEXT:vzeroupper
; X32-NEXT:retl
;
@@ -316,10 +314,8 @@ define dso_local x86_regcallcc i32 @test_argv32i1(<32 x
i1> %x0, <32 x i1> %x1,
; WIN64-NEXT:.seh_pushreg %r11
; WIN64-NEXT:pushq %r10
; WIN64-NEXT:.seh_pushreg %r10
-; WIN64-NEXT:pushq %rsp
-; WIN64-NEXT:.seh_pushreg %rsp
-; WIN64-NEXT:subq $152, %rsp
-; WIN64-NEXT:.seh_stackalloc 152
+; WIN64-NEXT:subq $128, %rsp
+; WIN64-NEXT:.seh_stackalloc 128
; WIN64-NEXT:leaq {{[0-9]+}}(%rsp), %rbp
; WIN64-NEXT:.seh_setframe %rbp, 128
; WIN64-NEXT:.seh_endprologue
@@ -339,8 +335,7 @@ define dso_
[llvm-branch-commits] [clang] ad55d5c - Simplify vectorcall argument classification of HVAs, NFC
Author: Reid Kleckner
Date: 2021-01-07T11:14:18-08:00
New Revision: ad55d5c3f32f6598f8ac30b68f4961d82cdb1fed
URL:
https://github.com/llvm/llvm-project/commit/ad55d5c3f32f6598f8ac30b68f4961d82cdb1fed
DIFF:
https://github.com/llvm/llvm-project/commit/ad55d5c3f32f6598f8ac30b68f4961d82cdb1fed.diff
LOG: Simplify vectorcall argument classification of HVAs, NFC
This reduces the number of `WinX86_64ABIInfo::classify` call sites from
3 to 1. The call sites were similar, but passed different values for
FreeSSERegs. Use variables instead of `if`s to manage that argument.
Added:
Modified:
clang/lib/CodeGen/TargetInfo.cpp
Removed:
diff --git a/clang/lib/CodeGen/TargetInfo.cpp
b/clang/lib/CodeGen/TargetInfo.cpp
index c6d8942208e8..d36c7344e284 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -1089,11 +1089,6 @@ struct CCState {
unsigned FreeSSERegs = 0;
};
-enum {
- // Vectorcall only allows the first 6 parameters to be passed in registers.
- VectorcallMaxParamNumAsReg = 6
-};
-
/// X86_32ABIInfo - The X86-32 ABI information.
class X86_32ABIInfo : public SwiftABIInfo {
enum Class {
@@ -2405,10 +2400,8 @@ class WinX86_64ABIInfo : public SwiftABIInfo {
private:
ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
bool IsVectorCall, bool IsRegCall) const;
- ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
- const ABIArgInfo ¤t) const;
- void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
- bool IsVectorCall, bool IsRegCall) const;
+ ABIArgInfo reclassifyHvaArgForVectorCall(QualType Ty, unsigned &FreeSSERegs,
+ const ABIArgInfo ¤t) const;
X86AVXABILevel AVXLevel;
@@ -4163,10 +4156,8 @@ Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF,
Address VAListAddr,
/*allowHigherAlign*/ false);
}
-ABIArgInfo
-WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
-const ABIArgInfo ¤t) const {
- // Assumes vectorCall calling convention.
+ABIArgInfo WinX86_64ABIInfo::reclassifyHvaArgForVectorCall(
+QualType Ty, unsigned &FreeSSERegs, const ABIArgInfo ¤t) const {
const Type *Base = nullptr;
uint64_t NumElts = 0;
@@ -4299,31 +4290,6 @@ ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty,
unsigned &FreeSSERegs,
return ABIArgInfo::getDirect();
}
-void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
- unsigned FreeSSERegs,
- bool IsVectorCall,
- bool IsRegCall) const {
- unsigned Count = 0;
- for (auto &I : FI.arguments()) {
-// Vectorcall in x64 only permits the first 6 arguments to be passed
-// as XMM/YMM registers.
-if (Count < VectorcallMaxParamNumAsReg)
- I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
-else {
- // Since these cannot be passed in registers, pretend no registers
- // are left.
- unsigned ZeroSSERegsAvail = 0;
- I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
-IsVectorCall, IsRegCall);
-}
-++Count;
- }
-
- for (auto &I : FI.arguments()) {
-I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
- }
-}
-
void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
const unsigned CC = FI.getCallingConvention();
bool IsVectorCall = CC == llvm::CallingConv::X86_VectorCall;
@@ -4358,13 +4324,25 @@ void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI)
const {
FreeSSERegs = 16;
}
+ unsigned ArgNum = 0;
+ unsigned ZeroSSERegs = 0;
+ for (auto &I : FI.arguments()) {
+// Vectorcall in x64 only permits the first 6 arguments to be passed as
+// XMM/YMM registers. After the sixth argument, pretend no vector
+// registers are left.
+unsigned *MaybeFreeSSERegs =
+(IsVectorCall && ArgNum >= 6) ? &ZeroSSERegs : &FreeSSERegs;
+I.info =
+classify(I.type, *MaybeFreeSSERegs, false, IsVectorCall, IsRegCall);
+++ArgNum;
+ }
+
if (IsVectorCall) {
-computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
- } else {
+// For vectorcall, assign aggregate HVAs to any free vector registers in a
+// second pass.
for (auto &I : FI.arguments())
- I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
+ I.info = reclassifyHvaArgForVectorCall(I.type, FreeSSERegs, I.info);
}
-
}
Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
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[llvm-branch-commits] [llvm] 5464baa - Fix minor build issue (NFC)
Author: David Stuttard
Date: 2021-01-11T11:24:09-08:00
New Revision: 5464baaae8c19997c5b0b76930d2b5ee13f68dfa
URL:
https://github.com/llvm/llvm-project/commit/5464baaae8c19997c5b0b76930d2b5ee13f68dfa
DIFF:
https://github.com/llvm/llvm-project/commit/5464baaae8c19997c5b0b76930d2b5ee13f68dfa.diff
LOG: Fix minor build issue (NFC)
Change [x86] Fix tile register spill issue was causing problems for our build
using gcc-5.4.1
The problem was caused by this line:
for (const MachineInstr &MI : make_range(MIS.begin(), MI))
where MI was previously defined as a MachineBasicBlock iterator.
Differential Revision: https://reviews.llvm.org/D94415
Added:
Modified:
llvm/lib/CodeGen/InlineSpiller.cpp
Removed:
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp
b/llvm/lib/CodeGen/InlineSpiller.cpp
index 81ab9e5ab738..236a70904690 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -1553,12 +1553,12 @@ void HoistSpillHelper::hoistAllSpills() {
for (auto const &Insert : SpillsToIns) {
MachineBasicBlock *BB = Insert.first;
Register LiveReg = Insert.second;
- MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, *BB);
- MachineInstrSpan MIS(MI, BB);
- TII.storeRegToStackSlot(*BB, MI, LiveReg, false, Slot,
+ MachineBasicBlock::iterator MII = IPA.getLastInsertPointIter(OrigLI,
*BB);
+ MachineInstrSpan MIS(MII, BB);
+ TII.storeRegToStackSlot(*BB, MII, LiveReg, false, Slot,
MRI.getRegClass(LiveReg), &TRI);
- LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
- for (const MachineInstr &MI : make_range(MIS.begin(), MI))
+ LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII);
+ for (const MachineInstr &MI : make_range(MIS.begin(), MII))
getVDefInterval(MI, LIS);
++NumSpills;
}
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[llvm-branch-commits] [llvm] 55fc64b - [Hexagon] Tweak _MSC_VER workaround version
Author: Reid Kleckner
Date: 2020-12-14T11:26:36-08:00
New Revision: 55fc64bce08a30f1bf7f7ebf83df776a40700fbe
URL:
https://github.com/llvm/llvm-project/commit/55fc64bce08a30f1bf7f7ebf83df776a40700fbe
DIFF:
https://github.com/llvm/llvm-project/commit/55fc64bce08a30f1bf7f7ebf83df776a40700fbe.diff
LOG: [Hexagon] Tweak _MSC_VER workaround version
My bot runs VS 2019, but it could not compile this code.
Message:
[55/2465] Building CXX object
lib\Target\Hexagon\CMakeFiles\LLVMHexagonCodeGen.dir\HexagonVectorCombine.cpp.obj
FAILED:
lib/Target/Hexagon/CMakeFiles/LLVMHexagonCodeGen.dir/HexagonVectorCombine.cpp.obj
...
C:\Program Files (x86)\Microsoft Visual
Studio\2019\Professional\VC\Tools\MSVC\14.23.28105\include\map(71): error
C2976: 'std::map': too few template arguments
C:\Program Files (x86)\Microsoft Visual
Studio\2019\Professional\VC\Tools\MSVC\14.23.28105\include\map(71): note: see
declaration of 'std::map'
The version in the path, 14.23, corresponds to _MSC_VER 1923, so raise
the version floor to 1924.
I have not tested with versions between 1924 and 1928 (latest), but the
latest works with the variadic version.
Added:
Modified:
llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
Removed:
diff --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
index 4c0c202be4be..2d90e37349e5 100644
--- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
@@ -292,7 +292,7 @@ template <> StoreInst *isCandidate(Instruction
*In) {
return getIfUnordered(dyn_cast(In));
}
-#if !defined(_MSC_VER) || _MSC_VER >= 1920
+#if !defined(_MSC_VER) || _MSC_VER >= 1924
// VS2017 has trouble compiling this:
// error C2976: 'std::map': too few template arguments
template
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[llvm-branch-commits] [clang] d2ed9d6 - Revert "ADT: Migrate users of AlignedCharArrayUnion to std::aligned_union_t, NFC"
Author: Reid Kleckner
Date: 2020-12-14T17:04:06-08:00
New Revision: d2ed9d6b7ec6ae837aac0b2d2920c1e34b89d00b
URL:
https://github.com/llvm/llvm-project/commit/d2ed9d6b7ec6ae837aac0b2d2920c1e34b89d00b
DIFF:
https://github.com/llvm/llvm-project/commit/d2ed9d6b7ec6ae837aac0b2d2920c1e34b89d00b.diff
LOG: Revert "ADT: Migrate users of AlignedCharArrayUnion to
std::aligned_union_t, NFC"
We determined that the MSVC implementation of std::aligned* isn't suited
to our needs. It doesn't support 16 byte alignment or higher, and it
doesn't really guarantee 8 byte alignment. See
https://github.com/microsoft/STL/issues/1533
Also reverts "ADT: Change AlignedCharArrayUnion to an alias of
std::aligned_union_t, NFC"
Also reverts "ADT: Remove AlignedCharArrayUnion, NFC" to bring back
AlignedCharArrayUnion.
This reverts commit 4d8bf870a82765eb0d4fe53c82f796b957c05954.
This reverts commit d10f9863a5ac1cb681af07719650c44b48f289ce.
This reverts commit 4b5dc150b9862271720b3d56a3e723a55dd81838.
Added:
llvm/include/llvm/Support/AlignOf.h
llvm/unittests/Support/AlignOfTest.cpp
Modified:
clang/include/clang/AST/APValue.h
clang/include/clang/AST/ASTContext.h
clang/include/clang/AST/ASTTypeTraits.h
clang/include/clang/AST/ParentMapContext.h
clang/include/clang/Frontend/PrecompiledPreamble.h
clang/include/clang/Sema/Overload.h
clang/lib/DirectoryWatcher/linux/DirectoryWatcher-linux.cpp
clang/lib/DirectoryWatcher/windows/DirectoryWatcher-windows.cpp
clang/lib/Lex/PPDirectives.cpp
llvm/include/llvm/ADT/DenseMap.h
llvm/include/llvm/ADT/IntervalMap.h
llvm/include/llvm/CodeGen/DIE.h
llvm/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/include/llvm/Support/Error.h
llvm/include/llvm/Support/ErrorOr.h
llvm/include/llvm/Support/JSON.h
llvm/include/llvm/Support/TrailingObjects.h
llvm/include/llvm/Support/YAMLTraits.h
llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
llvm/unittests/Support/CMakeLists.txt
Removed:
diff --git a/clang/include/clang/AST/APValue.h
b/clang/include/clang/AST/APValue.h
index d6a33c13b0961..eded34808ad7e 100644
--- a/clang/include/clang/AST/APValue.h
+++ b/clang/include/clang/AST/APValue.h
@@ -20,7 +20,7 @@
#include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/PointerIntPair.h"
#include "llvm/ADT/PointerUnion.h"
-#include
+#include "llvm/Support/AlignOf.h"
namespace clang {
class AddrLabelExpr;
@@ -286,10 +286,9 @@ class APValue {
struct MemberPointerData;
// We ensure elsewhere that Data is big enough for LV and MemberPointerData.
- typedef std::aligned_union_t<1, void *, APSInt, APFloat, ComplexAPSInt,
- ComplexAPFloat, Vec, Arr, StructData, UnionData,
- AddrLabelDiffData>
- DataType;
+ typedef llvm::AlignedCharArrayUnion DataType;
static const size_t DataSize = sizeof(DataType);
DataType Data;
diff --git a/clang/include/clang/AST/ASTContext.h
b/clang/include/clang/AST/ASTContext.h
index 0a635875207d1..71f824b69bc85 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -57,6 +57,7 @@
#include "llvm/ADT/TinyPtrVector.h"
#include "llvm/ADT/Triple.h"
#include "llvm/ADT/iterator_range.h"
+#include "llvm/Support/AlignOf.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
diff --git a/clang/include/clang/AST/ASTTypeTraits.h
b/clang/include/clang/AST/ASTTypeTraits.h
index ea3da8d90c5b9..8791e41b9ac3c 100644
--- a/clang/include/clang/AST/ASTTypeTraits.h
+++ b/clang/include/clang/AST/ASTTypeTraits.h
@@ -22,7 +22,7 @@
#include "clang/AST/TypeLoc.h"
#include "clang/Basic/LLVM.h"
#include "llvm/ADT/DenseMapInfo.h"
-#include
+#include "llvm/Support/AlignOf.h"
namespace llvm {
@@ -456,8 +456,9 @@ class DynTypedNode {
/// \c QualTypes, \c NestedNameSpecifierLocs, \c TypeLocs,
/// \c TemplateArguments and \c TemplateArgumentLocs on the other hand do not
/// have storage or unique pointers and thus need to be stored by value.
- std::aligned_union_t<1, const void *, TemplateArgument, TemplateArgumentLoc,
- NestedNameSpecifierLoc, QualType, TypeLoc>
+ llvm::AlignedCharArrayUnion
Storage;
};
diff --git a/clang/include/clang/AST/ParentMapContext.h
b/clang/include/clang/AST/ParentMapContext.h
index a15790605a3d5..a0412380a864e 100644
--- a/clang/include/clang/AST/ParentMapContext.h
+++ b/clang/include/clang/AST/ParentMapContext.h
@@ -89,7 +89,7 @@ class TraversalKindScope {
/// Container for either a single DynTypedNode or for an ArrayRef to
/// DynTypedNode. For use with ParentMap.
class DynTypedNodeList {
- std::aligned_union_t<1, DynTypedNode, ArrayRef> Storage;
+ llvm::AlignedCharArrayUnion> Storage;
bool IsSingleNode;
public:
diff --git a/clang/include/clang/Frontend/PrecompiledPr
[llvm-branch-commits] [llvm] b0b5d38 - Document that AlignedCharArrayUnion exists to work around an MSVC bug
Author: Reid Kleckner
Date: 2020-12-15T16:01:55-08:00
New Revision: b0b5d389635a54c5aeb490b1b067f3a38e038235
URL:
https://github.com/llvm/llvm-project/commit/b0b5d389635a54c5aeb490b1b067f3a38e038235
DIFF:
https://github.com/llvm/llvm-project/commit/b0b5d389635a54c5aeb490b1b067f3a38e038235.diff
LOG: Document that AlignedCharArrayUnion exists to work around an MSVC bug
Differential Revision: https://reviews.llvm.org/D93355
Added:
Modified:
llvm/include/llvm/Support/AlignOf.h
Removed:
diff --git a/llvm/include/llvm/Support/AlignOf.h
b/llvm/include/llvm/Support/AlignOf.h
index f9dcde4d4ff1..f586d7f182aa 100644
--- a/llvm/include/llvm/Support/AlignOf.h
+++ b/llvm/include/llvm/Support/AlignOf.h
@@ -20,9 +20,10 @@ namespace llvm {
/// A suitably aligned and sized character array member which can hold elements
/// of any type.
///
-/// These types may be arrays, structs, or any other types. This exposes a
-/// `buffer` member which can be used as suitable storage for a placement new
of
-/// any of these types.
+/// This template is equivalent to std::aligned_union_t<1, ...>, but we cannot
+/// use it due to a bug in the MSVC x86 compiler:
+/// https://github.com/microsoft/STL/issues/1533
+/// Using `alignas` here works around the bug.
template struct AlignedCharArrayUnion {
using AlignedUnion = std::aligned_union_t<1, T, Ts...>;
alignas(alignof(AlignedUnion)) char buffer[sizeof(AlignedUnion)];
___
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[llvm-branch-commits] [llvm] 15ca545 - Fix XCore test on Windows, the register order is reversed, for reasons unknown
Author: Reid Kleckner Date: 2020-12-16T13:33:24-08:00 New Revision: 15ca54525d6c2927b2a51b871a9e343c7ce1c2ea URL: https://github.com/llvm/llvm-project/commit/15ca54525d6c2927b2a51b871a9e343c7ce1c2ea DIFF: https://github.com/llvm/llvm-project/commit/15ca54525d6c2927b2a51b871a9e343c7ce1c2ea.diff LOG: Fix XCore test on Windows, the register order is reversed, for reasons unknown Added: Modified: llvm/test/CodeGen/XCore/threads.ll Removed: diff --git a/llvm/test/CodeGen/XCore/threads.ll b/llvm/test/CodeGen/XCore/threads.ll index 0c25314295d7..b4b54e50904d 100644 --- a/llvm/test/CodeGen/XCore/threads.ll +++ b/llvm/test/CodeGen/XCore/threads.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=xcore < %s | FileCheck %s -; RUN: llc -march=xcore -O=0 < %s | FileCheck %s -check-prefix=PHINODE +; RUN: llc -mtriple=xcore-unknown-unknown < %s | FileCheck %s +; RUN: llc -mtriple=xcore-unknown-unknown -O=0 < %s | FileCheck %s -check-prefix=PHINODE declare i8 addrspace(1)* @llvm.xcore.getst.p1i8.p1i8(i8 addrspace(1)* %r) declare void @llvm.xcore.msync.p1i8(i8 addrspace(1)* %r) ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] b7905e8 - Fix split-debug.c test on Windows
Author: Reid Kleckner
Date: 2020-12-16T13:48:57-08:00
New Revision: b7905e81fc3d7b045a5346442ce92ee87bdb7b21
URL:
https://github.com/llvm/llvm-project/commit/b7905e81fc3d7b045a5346442ce92ee87bdb7b21
DIFF:
https://github.com/llvm/llvm-project/commit/b7905e81fc3d7b045a5346442ce92ee87bdb7b21.diff
LOG: Fix split-debug.c test on Windows
Added:
Modified:
clang/test/Driver/split-debug.c
Removed:
diff --git a/clang/test/Driver/split-debug.c b/clang/test/Driver/split-debug.c
index 7d3fcf078c56..de1258dcb13c 100644
--- a/clang/test/Driver/split-debug.c
+++ b/clang/test/Driver/split-debug.c
@@ -59,8 +59,8 @@
/// Invoke objcopy if not using the integrated assembler.
// RUN: %clang -### -c -target x86_64-unknown-linux-gnu -fno-integrated-as
-gsplit-dwarf -g %s 2>&1 | FileCheck %s --check-prefix=OBJCOPY
-// OBJCOPY: objcopy" "--extract-dwo"
-// OBJCOPY-NEXT: objcopy" "--strip-dwo"
+// OBJCOPY: objcopy{{(.exe)?}}" "--extract-dwo"
+// OBJCOPY-NEXT: objcopy{{(.exe)?}}" "--strip-dwo"
/// ... but not for assembly output.
// RUN: %clang -### -S -target x86_64-unknown-linux-gnu -fno-integrated-as
-gsplit-dwarf -g %s 2>&1 | FileCheck %s --check-prefix=NOOBJCOPY
___
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[llvm-branch-commits] [llvm] 0985a8b - Fix left shift overflow UB in PPC backend on LLP64 platforms
Author: Reid Kleckner
Date: 2020-12-19T17:46:09-08:00
New Revision: 0985a8bfea46272561d2a261b10f308a5841f18a
URL:
https://github.com/llvm/llvm-project/commit/0985a8bfea46272561d2a261b10f308a5841f18a
DIFF:
https://github.com/llvm/llvm-project/commit/0985a8bfea46272561d2a261b10f308a5841f18a.diff
LOG: Fix left shift overflow UB in PPC backend on LLP64 platforms
Added:
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 3d9a54305cc6..18e35f5a0850 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -9189,7 +9189,7 @@ static SDValue getCanonicalConstSplat(uint64_t Val,
unsigned SplatSize, EVT VT,
EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
// For a splat with all ones, turn it to vspltisb 0xFF to canonicalize.
- if (Val == ((1LU << (SplatSize * 8)) - 1)) {
+ if (Val == ((1LLU << (SplatSize * 8)) - 1)) {
SplatSize = 1;
Val = 0xFF;
}
___
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[llvm-branch-commits] [llvm] 64802d4 - Make check-clang depend on the LLVM split-file utility
Author: Reid Kleckner
Date: 2020-11-23T12:21:44-08:00
New Revision: 64802d48d51d651bd2e4567b2f228f8795569542
URL:
https://github.com/llvm/llvm-project/commit/64802d48d51d651bd2e4567b2f228f8795569542
DIFF:
https://github.com/llvm/llvm-project/commit/64802d48d51d651bd2e4567b2f228f8795569542.diff
LOG: Make check-clang depend on the LLVM split-file utility
Fixes a recently added test that has this dependency. IMO this utility
is generally useful, so we should go ahead and take the new dependency.
Added:
Modified:
clang/test/CMakeLists.txt
llvm/utils/gn/secondary/clang/test/BUILD.gn
Removed:
diff --git a/clang/test/CMakeLists.txt b/clang/test/CMakeLists.txt
index 4e9a1840fec3..2aff029cfbf1 100644
--- a/clang/test/CMakeLists.txt
+++ b/clang/test/CMakeLists.txt
@@ -124,6 +124,7 @@ if( NOT CLANG_BUILT_STANDALONE )
llvm-readobj
llvm-symbolizer
opt
+split-file
yaml2obj
)
diff --git a/llvm/utils/gn/secondary/clang/test/BUILD.gn
b/llvm/utils/gn/secondary/clang/test/BUILD.gn
index 8f436ac10586..70f28c8b5812 100644
--- a/llvm/utils/gn/secondary/clang/test/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/test/BUILD.gn
@@ -164,6 +164,7 @@ group("test") {
"//llvm/tools/llvm-readobj:symlinks",
"//llvm/tools/llvm-symbolizer:symlinks",
"//llvm/tools/opt",
+"//llvm/tools/split-file",
"//llvm/utils/FileCheck",
"//llvm/utils/count",
"//llvm/utils/llvm-lit",
___
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[llvm-branch-commits] [clang] 09ba206 - Fix compilation issue reported by MSVC user on cfe-dev
Author: Reid Kleckner
Date: 2020-11-24T17:31:25-08:00
New Revision: 09ba2063dc9339957b999c08d3810a3cec2b745b
URL:
https://github.com/llvm/llvm-project/commit/09ba2063dc9339957b999c08d3810a3cec2b745b
DIFF:
https://github.com/llvm/llvm-project/commit/09ba2063dc9339957b999c08d3810a3cec2b745b.diff
LOG: Fix compilation issue reported by MSVC user on cfe-dev
MSVC seems to think this `friend class TrailingObjects;` declaration is
declaring a TrailingObjects class instead of naming the injected base
class. Remove `class` so it does the right thing.
Added:
Modified:
clang/include/clang/AST/ExprCXX.h
Removed:
diff --git a/clang/include/clang/AST/ExprCXX.h
b/clang/include/clang/AST/ExprCXX.h
index d4e0eb83bcc3..2f89b43267b6 100644
--- a/clang/include/clang/AST/ExprCXX.h
+++ b/clang/include/clang/AST/ExprCXX.h
@@ -4864,7 +4864,7 @@ class BuiltinBitCastExpr final
private llvm::TrailingObjects {
friend class ASTStmtReader;
friend class CastExpr;
- friend class TrailingObjects;
+ friend TrailingObjects;
SourceLocation KWLoc;
SourceLocation RParenLoc;
___
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[llvm-branch-commits] [clang] 3bd0672 - [MS] Fix double evaluation of MSVC builtin arguments
Author: Reid Kleckner
Date: 2020-11-25T11:55:01-08:00
New Revision: 3bd06727267184223464f11d4e2470048ac40cb1
URL:
https://github.com/llvm/llvm-project/commit/3bd06727267184223464f11d4e2470048ac40cb1
DIFF:
https://github.com/llvm/llvm-project/commit/3bd06727267184223464f11d4e2470048ac40cb1.diff
LOG: [MS] Fix double evaluation of MSVC builtin arguments
This code got quite twisted because we consider some MSVC builtins to be
target agnostic, and some to be target specific. Target specific
intrinsics have a pattern of doing up-front argument evaluation, while
general intrinsics do not evaluate their arguments up front. As we tried
to share codepaths between the target-specific and target-agnostic
handling, we ended up doing double evaluation.
Instead, have each target handle MSVC intrinsics consistently before up
front argument evaluation. This requires passing less data around and is
more consistent with target independent intrinsic handling.
See D50979 for past examples of this bug. I noticed this while looking
into adding some more intrinsics.
Differential Revision: https://reviews.llvm.org/D92061
Added:
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/CodeGen/CodeGenFunction.h
clang/test/CodeGen/ms-intrinsics.c
Removed:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index e98ec3e35e37..b2bfc3c84322 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -1011,16 +1011,342 @@ enum class CodeGenFunction::MSVCIntrin {
__fastfail,
};
+static Optional
+translateArmToMsvcIntrin(unsigned BuiltinID) {
+ using MSVCIntrin = CodeGenFunction::MSVCIntrin;
+ switch (BuiltinID) {
+ default:
+return None;
+ case ARM::BI_BitScanForward:
+ case ARM::BI_BitScanForward64:
+return MSVCIntrin::_BitScanForward;
+ case ARM::BI_BitScanReverse:
+ case ARM::BI_BitScanReverse64:
+return MSVCIntrin::_BitScanReverse;
+ case ARM::BI_InterlockedAnd64:
+return MSVCIntrin::_InterlockedAnd;
+ case ARM::BI_InterlockedExchange64:
+return MSVCIntrin::_InterlockedExchange;
+ case ARM::BI_InterlockedExchangeAdd64:
+return MSVCIntrin::_InterlockedExchangeAdd;
+ case ARM::BI_InterlockedExchangeSub64:
+return MSVCIntrin::_InterlockedExchangeSub;
+ case ARM::BI_InterlockedOr64:
+return MSVCIntrin::_InterlockedOr;
+ case ARM::BI_InterlockedXor64:
+return MSVCIntrin::_InterlockedXor;
+ case ARM::BI_InterlockedDecrement64:
+return MSVCIntrin::_InterlockedDecrement;
+ case ARM::BI_InterlockedIncrement64:
+return MSVCIntrin::_InterlockedIncrement;
+ case ARM::BI_InterlockedExchangeAdd8_acq:
+ case ARM::BI_InterlockedExchangeAdd16_acq:
+ case ARM::BI_InterlockedExchangeAdd_acq:
+ case ARM::BI_InterlockedExchangeAdd64_acq:
+return MSVCIntrin::_InterlockedExchangeAdd_acq;
+ case ARM::BI_InterlockedExchangeAdd8_rel:
+ case ARM::BI_InterlockedExchangeAdd16_rel:
+ case ARM::BI_InterlockedExchangeAdd_rel:
+ case ARM::BI_InterlockedExchangeAdd64_rel:
+return MSVCIntrin::_InterlockedExchangeAdd_rel;
+ case ARM::BI_InterlockedExchangeAdd8_nf:
+ case ARM::BI_InterlockedExchangeAdd16_nf:
+ case ARM::BI_InterlockedExchangeAdd_nf:
+ case ARM::BI_InterlockedExchangeAdd64_nf:
+return MSVCIntrin::_InterlockedExchangeAdd_nf;
+ case ARM::BI_InterlockedExchange8_acq:
+ case ARM::BI_InterlockedExchange16_acq:
+ case ARM::BI_InterlockedExchange_acq:
+ case ARM::BI_InterlockedExchange64_acq:
+return MSVCIntrin::_InterlockedExchange_acq;
+ case ARM::BI_InterlockedExchange8_rel:
+ case ARM::BI_InterlockedExchange16_rel:
+ case ARM::BI_InterlockedExchange_rel:
+ case ARM::BI_InterlockedExchange64_rel:
+return MSVCIntrin::_InterlockedExchange_rel;
+ case ARM::BI_InterlockedExchange8_nf:
+ case ARM::BI_InterlockedExchange16_nf:
+ case ARM::BI_InterlockedExchange_nf:
+ case ARM::BI_InterlockedExchange64_nf:
+return MSVCIntrin::_InterlockedExchange_nf;
+ case ARM::BI_InterlockedCompareExchange8_acq:
+ case ARM::BI_InterlockedCompareExchange16_acq:
+ case ARM::BI_InterlockedCompareExchange_acq:
+ case ARM::BI_InterlockedCompareExchange64_acq:
+return MSVCIntrin::_InterlockedCompareExchange_acq;
+ case ARM::BI_InterlockedCompareExchange8_rel:
+ case ARM::BI_InterlockedCompareExchange16_rel:
+ case ARM::BI_InterlockedCompareExchange_rel:
+ case ARM::BI_InterlockedCompareExchange64_rel:
+return MSVCIntrin::_InterlockedCompareExchange_rel;
+ case ARM::BI_InterlockedCompareExchange8_nf:
+ case ARM::BI_InterlockedCompareExchange16_nf:
+ case ARM::BI_InterlockedCompareExchange_nf:
+ case ARM::BI_InterlockedCompareExchange64_nf:
+return MSVCIntrin::_InterlockedCompareExchange_nf;
+ case ARM::BI_InterlockedOr8_acq:
+ case ARM::BI_InterlockedOr16_acq:
+ case ARM::BI_InterlockedOr_acq:
+ case ARM::BI_InterlockedOr64_acq:
+return MSVCIntrin::_InterlockedOr_acq;
+ case AR
[llvm-branch-commits] [clang] 1e843a9 - [MS] Add more 128bit cmpxchg intrinsics for AArch64
Author: Reid Kleckner
Date: 2020-11-25T12:07:28-08:00
New Revision: 1e843a987d847da48aaf41801b79cfb364937e8f
URL:
https://github.com/llvm/llvm-project/commit/1e843a987d847da48aaf41801b79cfb364937e8f
DIFF:
https://github.com/llvm/llvm-project/commit/1e843a987d847da48aaf41801b79cfb364937e8f.diff
LOG: [MS] Add more 128bit cmpxchg intrinsics for AArch64
The MSVC STL for requires this on ARM64.
Requested in https://llvm.org/pr47099
Depends on D92061
Differential Revision: https://reviews.llvm.org/D92062
Added:
Modified:
clang/include/clang/Basic/BuiltinsAArch64.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Headers/intrin.h
clang/test/CodeGen/ms-intrinsics.c
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def
b/clang/include/clang/Basic/BuiltinsAArch64.def
index f07c567053de..c684105908de 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -153,6 +153,11 @@ TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_acq,
"LLiLLiD*LLiLLi", "nh",
TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_nf, "LLiLLiD*LLiLLi",
"nh", "intrin.h", ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_rel, "LLiLLiD*LLiLLi",
"nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128,"UcLLiD*LLiLLiLLi*",
"nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128_acq,"UcLLiD*LLiLLiLLi*",
"nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128_nf ,"UcLLiD*LLiLLiLLi*",
"nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128_rel,"UcLLiD*LLiLLiLLi*",
"nh", "intrin.h", ALL_MS_LANGUAGES, "")
+
TARGET_HEADER_BUILTIN(_InterlockedOr8_acq, "ccD*c", "nh", "intrin.h",
ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_InterlockedOr8_nf, "ccD*c", "nh", "intrin.h",
ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_InterlockedOr8_rel, "ccD*c", "nh", "intrin.h",
ALL_MS_LANGUAGES, "")
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index b2bfc3c84322..828d66f83de9 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -304,6 +304,10 @@ Value *EmitAtomicCmpXchgForMSIntrin(CodeGenFunction &CGF,
const CallExpr *E,
AtomicOrdering::Monotonic :
SuccessOrdering;
+ // The atomic instruction is marked volatile for consistency with MSVC. This
+ // blocks the few atomics optimizations that LLVM has. If we want to optimize
+ // _Interlocked* operations in the future, we will have to remove the
volatile
+ // marker.
auto *Result = CGF.Builder.CreateAtomicCmpXchg(
Destination, Comparand, Exchange,
SuccessOrdering, FailureOrdering);
@@ -311,6 +315,68 @@ Value *EmitAtomicCmpXchgForMSIntrin(CodeGenFunction &CGF,
const CallExpr *E,
return CGF.Builder.CreateExtractValue(Result, 0);
}
+// 64-bit Microsoft platforms support 128 bit cmpxchg operations. They are
+// prototyped like this:
+//
+// unsigned char _InterlockedCompareExchange128...(
+// __int64 volatile * _Destination,
+// __int64 _ExchangeHigh,
+// __int64 _ExchangeLow,
+// __int64 * _ComparandResult);
+static Value *EmitAtomicCmpXchg128ForMSIntrin(CodeGenFunction &CGF,
+ const CallExpr *E,
+ AtomicOrdering SuccessOrdering) {
+ assert(E->getNumArgs() == 4);
+ llvm::Value *Destination = CGF.EmitScalarExpr(E->getArg(0));
+ llvm::Value *ExchangeHigh = CGF.EmitScalarExpr(E->getArg(1));
+ llvm::Value *ExchangeLow = CGF.EmitScalarExpr(E->getArg(2));
+ llvm::Value *ComparandPtr = CGF.EmitScalarExpr(E->getArg(3));
+
+ assert(Destination->getType()->isPointerTy());
+ assert(!ExchangeHigh->getType()->isPointerTy());
+ assert(!ExchangeLow->getType()->isPointerTy());
+ assert(ComparandPtr->getType()->isPointerTy());
+
+ // For Release ordering, the failure ordering should be Monotonic.
+ auto FailureOrdering = SuccessOrdering == AtomicOrdering::Release
+ ? AtomicOrdering::Monotonic
+ : SuccessOrdering;
+
+ // Convert to i128 pointers and values.
+ llvm::Type *Int128Ty = llvm::IntegerType::get(CGF.getLLVMContext(), 128);
+ llvm::Type *Int128PtrTy = Int128Ty->getPointerTo();
+ Destination = CGF.Builder.CreateBitCast(Destination, Int128PtrTy);
+ Address ComparandResult(CGF.Builder.CreateBitCast(ComparandPtr, Int128PtrTy),
+ CGF.getContext().toCharUnitsFromBits(128));
+
+ // (((i128)hi) << 64) | ((i128)lo)
+ ExchangeHigh = CGF.Builder.CreateZExt(ExchangeHigh, Int128Ty);
+ ExchangeLow = CGF.Builder.CreateZExt(ExchangeLow, Int128Ty);
+ ExchangeHigh =
+ CGF.Bu
[llvm-branch-commits] [compiler-rt] b534bea - Revert builtins fp16 support: tests do not pass on Mac
Author: Reid Kleckner
Date: 2020-11-25T16:12:49-08:00
New Revision: b534beabeed3ba1777cd0ff9ce552d077e496726
URL:
https://github.com/llvm/llvm-project/commit/b534beabeed3ba1777cd0ff9ce552d077e496726
DIFF:
https://github.com/llvm/llvm-project/commit/b534beabeed3ba1777cd0ff9ce552d077e496726.diff
LOG: Revert builtins fp16 support: tests do not pass on Mac
Revert "[compiler-rt] [builtins] Support conversion between fp16 and fp128" &
dependency
Revert "[compiler-rt] [builtins] Use _Float16 on extendhfsf2, truncdfhf2
__truncsfhf2 if available"
This reverts commit 7a948298813c913841a36ed0b460db0856fe7082.
This reverts commit 1fb91fcf9cfe849c7e9996597c491306e34e7abc.
Added:
Modified:
compiler-rt/cmake/builtin-config-ix.cmake
compiler-rt/lib/builtins/CMakeLists.txt
compiler-rt/lib/builtins/extendhfsf2.c
compiler-rt/lib/builtins/fp_extend.h
compiler-rt/lib/builtins/fp_trunc.h
compiler-rt/lib/builtins/truncdfhf2.c
compiler-rt/lib/builtins/truncsfhf2.c
compiler-rt/test/builtins/CMakeLists.txt
compiler-rt/test/builtins/Unit/extendhfsf2_test.c
compiler-rt/test/builtins/Unit/fp_test.h
compiler-rt/test/builtins/Unit/truncdfhf2_test.c
compiler-rt/test/builtins/Unit/truncsfhf2_test.c
Removed:
compiler-rt/lib/builtins/extendhftf2.c
compiler-rt/lib/builtins/trunctfhf2.c
compiler-rt/test/builtins/Unit/extendhftf2_test.c
compiler-rt/test/builtins/Unit/trunctfhf2_test.c
diff --git a/compiler-rt/cmake/builtin-config-ix.cmake
b/compiler-rt/cmake/builtin-config-ix.cmake
index 8c6243a832cc..16d82b127878 100644
--- a/compiler-rt/cmake/builtin-config-ix.cmake
+++ b/compiler-rt/cmake/builtin-config-ix.cmake
@@ -22,13 +22,6 @@ int foo(int x, int y) {
}
")
-builtin_check_c_compiler_source(COMPILER_RT_HAS_FLOAT16
-"
-_Float16 foo(_Float16 x) {
- return x;
-}
-"
-)
set(ARM64 aarch64)
set(ARM32 arm armhf armv6m armv7m armv7em armv7 armv7s armv7k)
diff --git a/compiler-rt/lib/builtins/CMakeLists.txt
b/compiler-rt/lib/builtins/CMakeLists.txt
index 8b70c1e82781..3c29bba612e1 100644
--- a/compiler-rt/lib/builtins/CMakeLists.txt
+++ b/compiler-rt/lib/builtins/CMakeLists.txt
@@ -179,7 +179,6 @@ set(GENERIC_TF_SOURCES
divtc3.c
divtf3.c
extenddftf2.c
- extendhftf2.c
extendsftf2.c
fixtfdi.c
fixtfsi.c
@@ -198,7 +197,6 @@ set(GENERIC_TF_SOURCES
powitf2.c
subtf3.c
trunctfdf2.c
- trunctfhf2.c
trunctfsf2.c
)
@@ -630,8 +628,6 @@ if (APPLE)
else ()
set(BUILTIN_CFLAGS "")
- append_list_if(COMPILER_RT_HAS_FLOAT16 -DCOMPILER_RT_HAS_FLOAT16
BUILTIN_CFLAGS)
-
append_list_if(COMPILER_RT_HAS_STD_C11_FLAG -std=c11 BUILTIN_CFLAGS)
# These flags would normally be added to CMAKE_C_FLAGS by the llvm
diff --git a/compiler-rt/lib/builtins/extendhfsf2.c
b/compiler-rt/lib/builtins/extendhfsf2.c
index 0159ab09d3eb..7c1a76eb5851 100644
--- a/compiler-rt/lib/builtins/extendhfsf2.c
+++ b/compiler-rt/lib/builtins/extendhfsf2.c
@@ -12,15 +12,15 @@
// Use a forwarding definition and noinline to implement a poor man's alias,
// as there isn't a good cross-platform way of defining one.
-COMPILER_RT_ABI NOINLINE float __extendhfsf2(src_t a) {
+COMPILER_RT_ABI NOINLINE float __extendhfsf2(uint16_t a) {
return __extendXfYf2__(a);
}
-COMPILER_RT_ABI float __gnu_h2f_ieee(src_t a) { return __extendhfsf2(a); }
+COMPILER_RT_ABI float __gnu_h2f_ieee(uint16_t a) { return __extendhfsf2(a); }
#if defined(__ARM_EABI__)
#if defined(COMPILER_RT_ARMHF_TARGET)
-AEABI_RTABI float __aeabi_h2f(src_t a) { return __extendhfsf2(a); }
+AEABI_RTABI float __aeabi_h2f(uint16_t a) { return __extendhfsf2(a); }
#else
COMPILER_RT_ALIAS(__extendhfsf2, __aeabi_h2f)
#endif
diff --git a/compiler-rt/lib/builtins/extendhftf2.c
b/compiler-rt/lib/builtins/extendhftf2.c
deleted file mode 100644
index aefe9737d34f..
--- a/compiler-rt/lib/builtins/extendhftf2.c
+++ /dev/null
@@ -1,23 +0,0 @@
-//===-- lib/extendhftf2.c - half -> quad conversion ---*- C
-*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is dual licensed under the MIT and the University of Illinois Open
-// Source Licenses. See LICENSE.TXT for details.
-//
-//===--===//
-
-#define QUAD_PRECISION
-#include "fp_lib.h"
-
-#if defined(CRT_HAS_128BIT) && defined(CRT_LDBL_128BIT) &&
\
-defined(COMPILER_RT_HAS_FLOAT16)
-#define SRC_HALF
-#define DST_QUAD
-#include "fp_extend_impl.inc"
-
-COMPILER_RT_ABI long double __extendhftf2(_Float16 a) {
- return __extendXfYf2__(a);
-}
-
-#endif
diff --git a/compiler-rt/lib/builtins/fp_extend.h
b/compiler-rt/lib/builtins/fp_extend.h
index aad4436730dd..fb512672e35e 100644
--- a/compiler-rt/lib/builtins/fp_extend.h
+++ b/compiler-rt/lib/builtins/fp_extend.h
@@ -40,11 +40,7 @@ static __inline int src_rep_t_clz(src_rep_t a
[llvm-branch-commits] [clang] 43b5b48 - Fix GCC 5.3 compile error in ASTImporter code
Author: Reid Kleckner
Date: 2020-11-30T16:29:29-08:00
New Revision: 43b5b485a203f190ee4d5d3cab19c44ca865d316
URL:
https://github.com/llvm/llvm-project/commit/43b5b485a203f190ee4d5d3cab19c44ca865d316
DIFF:
https://github.com/llvm/llvm-project/commit/43b5b485a203f190ee4d5d3cab19c44ca865d316.diff
LOG: Fix GCC 5.3 compile error in ASTImporter code
Try to simplify this code a different way: use less Expected, more
outparams.
Added:
Modified:
clang/lib/AST/ASTImporter.cpp
Removed:
diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp
index 1b014314996b..7a1415b658b8 100644
--- a/clang/lib/AST/ASTImporter.cpp
+++ b/clang/lib/AST/ASTImporter.cpp
@@ -202,6 +202,9 @@ namespace clang {
return *MaybeVal;
}
+ExplicitSpecifier importExplicitSpecifier(Error &Err,
+ ExplicitSpecifier ESpec);
+
// Wrapper for an overload set.
template struct CallOverloadedCreateFun {
template decltype(auto) operator()(Args &&... args) {
@@ -3153,6 +3156,14 @@ bool
ASTNodeImporter::hasAutoReturnTypeDeclaredInside(FunctionDecl *D) {
return false;
}
+ExplicitSpecifier
+ASTNodeImporter::importExplicitSpecifier(Error &Err, ExplicitSpecifier ESpec) {
+ Expr *ExplicitExpr = ESpec.getExpr();
+ if (ExplicitExpr)
+ExplicitExpr = importChecked(Err, ESpec.getExpr());
+ return ExplicitSpecifier(ExplicitExpr, ESpec.getKind());
+}
+
ExpectedDecl ASTNodeImporter::VisitFunctionDecl(FunctionDecl *D) {
SmallVector Redecls = getCanonicalForwardRedeclChain(D);
@@ -3329,34 +3340,17 @@ ExpectedDecl
ASTNodeImporter::VisitFunctionDecl(FunctionDecl *D) {
return ToPOrErr.takeError();
}
- // Common code to import an explicit specifier of
diff erent kind of functions.
- auto ImportExplicitExpr = [this, &Err](auto *Fun) -> ExpectedExpr {
-Expr *ExplicitExpr = nullptr;
-if (Fun->getExplicitSpecifier().getExpr()) {
- ExplicitExpr = importChecked(Err, Fun->getExplicitSpecifier().getExpr());
- if (Err)
-return std::move(Err);
-}
-return ExplicitExpr;
- };
-
// Create the imported function.
FunctionDecl *ToFunction = nullptr;
if (auto *FromConstructor = dyn_cast(D)) {
-Expr *ExplicitExpr = nullptr;
-if (FromConstructor->getExplicitSpecifier().getExpr()) {
- auto Imp = import(FromConstructor->getExplicitSpecifier().getExpr());
- if (!Imp)
-return Imp.takeError();
- ExplicitExpr = *Imp;
-}
+ExplicitSpecifier ESpec =
+importExplicitSpecifier(Err, FromConstructor->getExplicitSpecifier());
+if (Err)
+ return std::move(Err);
if (GetImportedOrCreateDecl(
ToFunction, D, Importer.getToContext(), cast(DC),
-ToInnerLocStart, NameInfo, T, TInfo,
-ExplicitSpecifier(
-ExplicitExpr,
-FromConstructor->getExplicitSpecifier().getKind()),
-D->isInlineSpecified(), D->isImplicit(), D->getConstexprKind(),
+ToInnerLocStart, NameInfo, T, TInfo, ESpec, D->isInlineSpecified(),
+D->isImplicit(), D->getConstexprKind(),
InheritedConstructor(), // FIXME: Properly import inherited
// constructor info
TrailingRequiresClause))
@@ -3381,14 +3375,13 @@ ExpectedDecl
ASTNodeImporter::VisitFunctionDecl(FunctionDecl *D) {
ToDtor->setOperatorDelete(ToOperatorDelete, ToThisArg);
} else if (CXXConversionDecl *FromConversion =
dyn_cast(D)) {
-ExpectedExpr ExplicitExpr = ImportExplicitExpr(FromConversion);
-if (!ExplicitExpr)
- return ExplicitExpr.takeError();
+ExplicitSpecifier ESpec =
+importExplicitSpecifier(Err, FromConversion->getExplicitSpecifier());
+if (Err)
+ return std::move(Err);
if (GetImportedOrCreateDecl(
ToFunction, D, Importer.getToContext(), cast(DC),
-ToInnerLocStart, NameInfo, T, TInfo, D->isInlineSpecified(),
-ExplicitSpecifier(*ExplicitExpr,
-
FromConversion->getExplicitSpecifier().getKind()),
+ToInnerLocStart, NameInfo, T, TInfo, D->isInlineSpecified(), ESpec,
D->getConstexprKind(), SourceLocation(), TrailingRequiresClause))
return ToFunction;
} else if (auto *Method = dyn_cast(D)) {
@@ -3399,13 +3392,12 @@ ExpectedDecl
ASTNodeImporter::VisitFunctionDecl(FunctionDecl *D) {
SourceLocation(), TrailingRequiresClause))
return ToFunction;
} else if (auto *Guide = dyn_cast(D)) {
-ExpectedExpr ExplicitExpr = ImportExplicitExpr(Guide);
-if (!ExplicitExpr)
- return ExplicitExpr.takeError();
+ExplicitSpecifier ESpec =
+importExplicitSpecifier(Err, Guide->getExplicitSpecifier());
+if (Err)
+ return std::move(Err);
if (GetImportedOrCreateDecl(
-ToFunction,
[llvm-branch-commits] [compiler-rt] b5af578 - [WinASan] Improve exception reporting accuracy
Author: Reid Kleckner
Date: 2020-11-30T16:39:22-08:00
New Revision: b5af5787b367198f8b87626431cb3f66fef460c1
URL:
https://github.com/llvm/llvm-project/commit/b5af5787b367198f8b87626431cb3f66fef460c1
DIFF:
https://github.com/llvm/llvm-project/commit/b5af5787b367198f8b87626431cb3f66fef460c1.diff
LOG: [WinASan] Improve exception reporting accuracy
Previously, ASan would produce reports like this:
ERROR: AddressSanitizer: breakpoint on unknown address 0x (pc
0x7fffdd7c5e86 ...)
This is unhelpful, because the developer may think this is a null
pointer dereference, and not a breakpoint exception on some PC.
The cause was that SignalContext::GetAddress would read the
ExceptionInformation array to retreive an address for any kind of
exception. That data is only available for access violation exceptions.
This changes it to be conditional on the exception type, and to use the
PC otherwise.
I added a variety of tests for common exception types:
- int div zero
- breakpoint
- ud2a / illegal instruction
- SSE misalignment
I also tightened up IsMemoryAccess and GetWriteFlag to check the
ExceptionCode rather than looking at ExceptionInformation[1] directly.
Differential Revision: https://reviews.llvm.org/D92344
Added:
compiler-rt/test/asan/TestCases/Windows/breakpoint.cpp
compiler-rt/test/asan/TestCases/Windows/illegal_instruction.cpp
compiler-rt/test/asan/TestCases/Windows/integer_divide_by_zero.cpp
compiler-rt/test/asan/TestCases/Windows/sse_misalignment.cpp
Modified:
compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
Removed:
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
b/compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
index 85ac2633bde1..281854aff261 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_win.cpp
@@ -956,22 +956,27 @@ void SignalContext::InitPcSpBp() {
uptr SignalContext::GetAddress() const {
EXCEPTION_RECORD *exception_record = (EXCEPTION_RECORD *)siginfo;
- return exception_record->ExceptionInformation[1];
+ if (exception_record->ExceptionCode == EXCEPTION_ACCESS_VIOLATION)
+return exception_record->ExceptionInformation[1];
+ return (uptr)exception_record->ExceptionAddress;
}
bool SignalContext::IsMemoryAccess() const {
- return GetWriteFlag() != SignalContext::UNKNOWN;
+ return ((EXCEPTION_RECORD *)siginfo)->ExceptionCode ==
+ EXCEPTION_ACCESS_VIOLATION;
}
-bool SignalContext::IsTrueFaultingAddress() const {
- // FIXME: Provide real implementation for this. See Linux and Mac variants.
- return IsMemoryAccess();
-}
+bool SignalContext::IsTrueFaultingAddress() const { return true; }
SignalContext::WriteFlag SignalContext::GetWriteFlag() const {
EXCEPTION_RECORD *exception_record = (EXCEPTION_RECORD *)siginfo;
+
+ // The write flag is only available for access violation exceptions.
+ if (exception_record->ExceptionCode != EXCEPTION_ACCESS_VIOLATION)
+return SignalContext::UNKNOWN;
+
// The contents of this array are documented at
- //
https://msdn.microsoft.com/en-us/library/windows/desktop/aa363082(v=vs.85).aspx
+ //
https://docs.microsoft.com/en-us/windows/win32/api/winnt/ns-winnt-exception_record
// The first element indicates read as 0, write as 1, or execute as 8. The
// second element is the faulting address.
switch (exception_record->ExceptionInformation[0]) {
diff --git a/compiler-rt/test/asan/TestCases/Windows/breakpoint.cpp
b/compiler-rt/test/asan/TestCases/Windows/breakpoint.cpp
new file mode 100644
index ..1c9e8c4a9af9
--- /dev/null
+++ b/compiler-rt/test/asan/TestCases/Windows/breakpoint.cpp
@@ -0,0 +1,18 @@
+// RUN: %clang_cl_asan -Od %s -Fe%t
+// RUN: %env_asan_opts=handle_sigill=1 not %run %t 2>&1 | FileCheck %s
+
+// Test the error output from a breakpoint. Assertion-like macros often end in
+// int3 on Windows.
+
+#include
+
+int main() {
+ puts("before breakpoint");
+ fflush(stdout);
+ __debugbreak();
+ return 0;
+}
+// CHECK: before breakpoint
+// CHECK: ERROR: AddressSanitizer: breakpoint on unknown address [[ADDR:0x[^
]*]]
+// CHECK-SAME: (pc [[ADDR]] {{.*}})
+// CHECK-NEXT: #0 {{.*}} in main {{.*}}breakpoint.cpp:{{.*}}
diff --git a/compiler-rt/test/asan/TestCases/Windows/illegal_instruction.cpp
b/compiler-rt/test/asan/TestCases/Windows/illegal_instruction.cpp
new file mode 100644
index ..2b6b05cfc833
--- /dev/null
+++ b/compiler-rt/test/asan/TestCases/Windows/illegal_instruction.cpp
@@ -0,0 +1,17 @@
+// RUN: %clang_cl_asan -Od %s -Fe%t
+// RUN: %env_asan_opts=handle_sigill=1 not %run %t 2>&1 | FileCheck %s
+
+// Test the error output from an illegal instruction.
+
+#include
+
+int main() {
+ puts("before ud2a");
+ fflush(stdout);
+ __builtin_trap();
+ return 0;
+}
+// CHECK: before ud2a
+// CHECK: ERROR: AddressSanitizer: illegal-instruction on unknown address
[[
[llvm-branch-commits] [llvm] 91e66bf - Revert "Use std::is_trivially_copyable", breaks MSVC build
Author: Reid Kleckner
Date: 2020-12-02T14:30:46-08:00
New Revision: 91e66bfd321ff3e932a9f9706b22fcf455a4a686
URL:
https://github.com/llvm/llvm-project/commit/91e66bfd321ff3e932a9f9706b22fcf455a4a686
DIFF:
https://github.com/llvm/llvm-project/commit/91e66bfd321ff3e932a9f9706b22fcf455a4a686.diff
LOG: Revert "Use std::is_trivially_copyable", breaks MSVC build
Revert "Delete llvm::is_trivially_copyable and CMake variable
HAVE_STD_IS_TRIVIALLY_COPYABLE"
This reverts commit 4d4bd40b578d77b8c5bc349ded405fb58c333c78.
This reverts commit 557b00e0afb2dc1776f50948094ca8cc62d97be4.
Added:
Modified:
llvm/cmake/config-ix.cmake
llvm/docs/ProgrammersManual.rst
llvm/include/llvm/ADT/DenseMap.h
llvm/include/llvm/ADT/Optional.h
llvm/include/llvm/ADT/PointerIntPair.h
llvm/include/llvm/ADT/STLExtras.h
llvm/include/llvm/Config/config.h.cmake
llvm/include/llvm/DebugInfo/CodeView/TypeHashing.h
llvm/include/llvm/Support/type_traits.h
llvm/tools/llvm-diff/DifferenceEngine.cpp
llvm/unittests/ADT/ArrayRefTest.cpp
llvm/unittests/ADT/ImmutableListTest.cpp
llvm/unittests/ADT/OptionalTest.cpp
llvm/unittests/ADT/PointerIntPairTest.cpp
llvm/unittests/ADT/StringRefTest.cpp
llvm/unittests/Analysis/BlockFrequencyInfoTest.cpp
llvm/unittests/Bitstream/BitstreamReaderTest.cpp
llvm/unittests/CodeGen/MachineInstrTest.cpp
llvm/unittests/CodeGen/TypeTraitsTest.cpp
llvm/unittests/IR/CFGBuilder.cpp
llvm/unittests/Support/ScaledNumberTest.cpp
llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
Removed:
diff --git a/llvm/cmake/config-ix.cmake b/llvm/cmake/config-ix.cmake
index b4c54da01912..818fafbce148 100644
--- a/llvm/cmake/config-ix.cmake
+++ b/llvm/cmake/config-ix.cmake
@@ -351,6 +351,15 @@ else()
unset(HAVE_FFI_CALL CACHE)
endif( LLVM_ENABLE_FFI )
+# Whether we can use std::is_trivially_copyable to verify
llvm::is_trivially_copyable.
+CHECK_CXX_SOURCE_COMPILES("
+#include
+struct T { int val; };
+static_assert(std::is_trivially_copyable::value, \"ok\");
+int main() { return 0;}
+" HAVE_STD_IS_TRIVIALLY_COPYABLE)
+
+
# Define LLVM_HAS_ATOMICS if gcc or MSVC atomic builtins are supported.
include(CheckAtomic)
diff --git a/llvm/docs/ProgrammersManual.rst b/llvm/docs/ProgrammersManual.rst
index e303a7a18eba..d9925d69d9f6 100644
--- a/llvm/docs/ProgrammersManual.rst
+++ b/llvm/docs/ProgrammersManual.rst
@@ -1530,7 +1530,7 @@ SmallVector has grown a few other minor advantages over
std::vector, causing
#. std::vector is exception-safe, and some implementations have pessimizations
that copy elements when SmallVector would move them.
-#. SmallVector understands ``std::is_trivially_copyable`` and uses
realloc aggressively.
+#. SmallVector understands ``llvm::is_trivially_copyable`` and uses
realloc aggressively.
#. Many LLVM APIs take a SmallVectorImpl as an out parameter (see the note
below).
diff --git a/llvm/include/llvm/ADT/DenseMap.h
b/llvm/include/llvm/ADT/DenseMap.h
index 7f7a4593ae36..42e4fc84175c 100644
--- a/llvm/include/llvm/ADT/DenseMap.h
+++ b/llvm/include/llvm/ADT/DenseMap.h
@@ -426,8 +426,8 @@ class DenseMapBase : public DebugEpochBase {
setNumEntries(other.getNumEntries());
setNumTombstones(other.getNumTombstones());
-if (std::is_trivially_copyable::value &&
-std::is_trivially_copyable::value)
+if (is_trivially_copyable::value &&
+is_trivially_copyable::value)
memcpy(reinterpret_cast(getBuckets()), other.getBuckets(),
getNumBuckets() * sizeof(BucketT));
else
diff --git a/llvm/include/llvm/ADT/Optional.h
b/llvm/include/llvm/ADT/Optional.h
index 5fff0acca816..be32178cb185 100644
--- a/llvm/include/llvm/ADT/Optional.h
+++ b/llvm/include/llvm/ADT/Optional.h
@@ -17,10 +17,10 @@
#include "llvm/ADT/None.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/type_traits.h"
#include
#include
#include
-#include
#include
namespace llvm {
@@ -32,7 +32,7 @@ namespace optional_detail {
struct in_place_t {};
/// Storage for any type.
-template ::value>
+template ::value>
class OptionalStorage {
union {
char empty;
diff --git a/llvm/include/llvm/ADT/PointerIntPair.h
b/llvm/include/llvm/ADT/PointerIntPair.h
index 600fcebff3ea..cb8b202c48b7 100644
--- a/llvm/include/llvm/ADT/PointerIntPair.h
+++ b/llvm/include/llvm/ADT/PointerIntPair.h
@@ -15,6 +15,7 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/PointerLikeTypeTraits.h"
+#include "llvm/Support/type_traits.h"
#include
#include
#include
@@ -126,6 +127,19 @@ class PointerIntPair {
}
};
+// Specialize is_trivially_copyable to avoid limitation of
llvm::is_trivially_copyable
+// when compiled with gcc 4.9.
+template
+struct is_trivially_copyable> : std::true_type {
+#ifdef HAVE_STD_IS_TRIVIALLY_COPYABLE
+ static_assert(std::is_trivially_copyable>:
[llvm-branch-commits] [llvm] e61a6a2 - Bump MSVC required version to 19.14
Author: Reid Kleckner Date: 2020-12-03T10:09:18-08:00 New Revision: e61a6a229a992d291da81ab96299669e8d28d6ad URL: https://github.com/llvm/llvm-project/commit/e61a6a229a992d291da81ab96299669e8d28d6ad DIFF: https://github.com/llvm/llvm-project/commit/e61a6a229a992d291da81ab96299669e8d28d6ad.diff LOG: Bump MSVC required version to 19.14 LLVM passes overaligned objects by value, which MSVC 19.1 didn't support on x86_32. MSVC added this support somewhere between 19.1 and 19.14, but godbolt doesn't have 19.11, 19.12, or 19.13 so I can't test before 19.14: https://gcc.godbolt.org/z/75YoEz Even if users are using the Visual Studio 2017 series of Visual C++ toolchains, they should've already updated to 19.14 or newer at this point, or they wouldn't be able to build LLVM. This just raises the CMake required minimum version so the build fails earlier. Differential Revision: https://reviews.llvm.org/D92515 Added: Modified: llvm/cmake/modules/CheckCompilerVersion.cmake Removed: diff --git a/llvm/cmake/modules/CheckCompilerVersion.cmake b/llvm/cmake/modules/CheckCompilerVersion.cmake index e54507798b69..375a5265f774 100644 --- a/llvm/cmake/modules/CheckCompilerVersion.cmake +++ b/llvm/cmake/modules/CheckCompilerVersion.cmake @@ -12,9 +12,9 @@ set(APPLECLANG_MIN 6.0) set(APPLECLANG_SOFT_ERROR 6.0) # https://en.wikipedia.org/wiki/Microsoft_Visual_C#Internal_version_numbering -# _MSC_VER == 1910 MSVC++ 14.1 (Visual Studio 2017 version 15.0) -set(MSVC_MIN 19.1) -set(MSVC_SOFT_ERROR 19.1) +# _MSC_VER == 1914 MSVC++ 14.14 (Visual Studio 2017 version 15.4) +set(MSVC_MIN 19.14) +set(MSVC_SOFT_ERROR 19.14) # Map the above GCC versions to dates: https://gcc.gnu.org/develop.html#timeline set(GCC_MIN_DATE 20150422) ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] d7098ff - De-templatify EmitCallArgs argument type checking, NFCI
Author: Reid Kleckner
Date: 2020-12-09T11:08:00-08:00
New Revision: d7098ff29c58dd08ede8314818b7de7fd2fea4cc
URL:
https://github.com/llvm/llvm-project/commit/d7098ff29c58dd08ede8314818b7de7fd2fea4cc
DIFF:
https://github.com/llvm/llvm-project/commit/d7098ff29c58dd08ede8314818b7de7fd2fea4cc.diff
LOG: De-templatify EmitCallArgs argument type checking, NFCI
This template exists to abstract over FunctionPrototype and
ObjCMethodDecl, which have similar APIs for storing parameter types. In
place of a template, use a PointerUnion with two cases to handle this.
Hopefully this improves readability, since the type of the prototype is
easier to discover. This allows me to sink this code, which is mostly
assertions, out of the header file and into the cpp file. I can also
simplify the overloaded methods for computing isGenericMethod, and get
rid of the second EmitCallArgs overload.
Differential Revision: https://reviews.llvm.org/D92883
Added:
Modified:
clang/lib/CodeGen/CGCall.cpp
clang/lib/CodeGen/CGExprCXX.cpp
clang/lib/CodeGen/CodeGenFunction.h
Removed:
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 2b9bfb6a6c88..83903af55ab3 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -3818,13 +3818,79 @@ void CodeGenFunction::EmitNonNullArgCheck(RValue RV,
QualType ArgType,
EmitCheck(std::make_pair(Cond, CheckKind), Handler, StaticData, None);
}
+#ifndef NDEBUG
+// Determine whether the given argument is an Objective-C method
+// that may have type parameters in its signature.
+static bool isObjCMethodWithTypeParams(const ObjCMethodDecl *method) {
+ const DeclContext *dc = method->getDeclContext();
+ if (const ObjCInterfaceDecl *classDecl = dyn_cast(dc)) {
+return classDecl->getTypeParamListAsWritten();
+ }
+
+ if (const ObjCCategoryDecl *catDecl = dyn_cast(dc)) {
+return catDecl->getTypeParamList();
+ }
+
+ return false;
+}
+#endif
+
+/// EmitCallArgs - Emit call arguments for a function.
void CodeGenFunction::EmitCallArgs(
-CallArgList &Args, ArrayRef ArgTypes,
+CallArgList &Args, PrototypeWrapper Prototype,
llvm::iterator_range ArgRange,
AbstractCallee AC, unsigned ParamsToSkip, EvaluationOrder Order) {
+ SmallVector ArgTypes;
+
+ assert((ParamsToSkip == 0 || Prototype.P) &&
+ "Can't skip parameters if type info is not provided");
+
+ // First, use the argument types that the type info knows about
+ bool IsVariadic = false;
+ if (Prototype.P) {
+const auto *MD = Prototype.P.dyn_cast();
+if (MD) {
+ IsVariadic = MD->isVariadic();
+ ArgTypes.assign(MD->param_type_begin() + ParamsToSkip,
+ MD->param_type_end());
+} else {
+ const auto *FPT = Prototype.P.get();
+ IsVariadic = FPT->isVariadic();
+ ArgTypes.assign(FPT->param_type_begin() + ParamsToSkip,
+ FPT->param_type_end());
+}
+
+#ifndef NDEBUG
+// Check that the prototyped types match the argument expression types.
+bool isGenericMethod = MD && isObjCMethodWithTypeParams(MD);
+CallExpr::const_arg_iterator Arg = ArgRange.begin();
+for (QualType Ty : ArgTypes) {
+ assert(Arg != ArgRange.end() && "Running over edge of argument list!");
+ assert(
+ (isGenericMethod || Ty->isVariablyModifiedType() ||
+ Ty.getNonReferenceType()->isObjCRetainableType() ||
+ getContext()
+ .getCanonicalType(Ty.getNonReferenceType())
+ .getTypePtr() ==
+ getContext().getCanonicalType((*Arg)->getType()).getTypePtr())
&&
+ "type mismatch in call argument!");
+ ++Arg;
+}
+
+// Either we've emitted all the call args, or we have a call to variadic
+// function.
+assert((Arg == ArgRange.end() || IsVariadic) &&
+ "Extra arguments in non-variadic function!");
+#endif
+ }
+
+ // If we still have any arguments, emit them using the type of the argument.
+ for (auto *A : llvm::make_range(std::next(ArgRange.begin(), ArgTypes.size()),
+ ArgRange.end()))
+ArgTypes.push_back(IsVariadic ? getVarArgType(A) : A->getType());
assert((int)ArgTypes.size() == (ArgRange.end() - ArgRange.begin()));
- // We *have* to evaluate arguments from right to left in the MS C++ ABI,
+ // We must evaluate arguments from right to left in the MS C++ ABI,
// because arguments are destroyed left to right in the callee. As a special
// case, there are certain language constructs that require left-to-right
// evaluation, and in those cases we consider the evaluation order
requirement
diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp
index c8b059fd7db0..e1907a6f0680 100644
--- a/clang/lib/CodeGen/CGExprCXX.cpp
+++ b/clang/lib/CodeGen/CGExprCXX.cpp
@@ -1329,7 +1329,7 @@ RValue CodeGenFunction::EmitBuil
[llvm-branch-commits] [clang] df28221 - Don't setup inalloca for swiftcc on i686-windows-msvc
Author: Reid Kleckner
Date: 2020-12-09T11:08:48-08:00
New Revision: df282215d497e15104ae9e182e083cdfa0bae3c2
URL:
https://github.com/llvm/llvm-project/commit/df282215d497e15104ae9e182e083cdfa0bae3c2
DIFF:
https://github.com/llvm/llvm-project/commit/df282215d497e15104ae9e182e083cdfa0bae3c2.diff
LOG: Don't setup inalloca for swiftcc on i686-windows-msvc
Swiftcall does it's own target-independent argument type classification,
since it is not designed to be ABI compatible with anything local on the
target that isn't LLVM-based. This means it never uses inalloca.
However, we have duplicate logic for checking for inalloca parameters
that runs before call argument setup. This logic needs to know ahead of
time if inalloca will be used later, and we can't move the
CGFunctionInfo calculation earlier.
This change gets the calling convention from either the
FunctionProtoType or ObjCMethodDecl, checks if it is swift, and if so
skips the stackbase setup.
Depends on D92883.
Differential Revision: https://reviews.llvm.org/D92944
Added:
clang/test/CodeGenCXX/windows-x86-swiftcall.cpp
Modified:
clang/lib/CodeGen/CGCall.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 83903af55ab3..5db34b693bf3 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -198,7 +198,8 @@
CodeGenTypes::arrangeFreeFunctionType(CanQual FTP) {
FTP);
}
-static CallingConv getCallingConventionForDecl(const Decl *D, bool IsWindows) {
+static CallingConv getCallingConventionForDecl(const ObjCMethodDecl *D,
+ bool IsWindows) {
// Set the appropriate calling convention for the Function.
if (D->hasAttr())
return CC_X86StdCall;
@@ -3818,6 +3819,24 @@ void CodeGenFunction::EmitNonNullArgCheck(RValue RV,
QualType ArgType,
EmitCheck(std::make_pair(Cond, CheckKind), Handler, StaticData, None);
}
+// Check if the call is going to use the inalloca convention. This needs to
+// agree with CGFunctionInfo::usesInAlloca. The CGFunctionInfo is arranged
+// later, so we can't check it directly.
+static bool hasInAllocaArgs(CodeGenModule &CGM, CallingConv ExplicitCC,
+ArrayRef ArgTypes) {
+ // The Swift calling convention doesn't go through the target-specific
+ // argument classification, so it never uses inalloca.
+ // TODO: Consider limiting inalloca use to only calling conventions supported
+ // by MSVC.
+ if (ExplicitCC == CC_Swift)
+return false;
+ if (!CGM.getTarget().getCXXABI().isMicrosoft())
+return false;
+ return llvm::any_of(ArgTypes, [&](QualType Ty) {
+return isInAllocaArgument(CGM.getCXXABI(), Ty);
+ });
+}
+
#ifndef NDEBUG
// Determine whether the given argument is an Objective-C method
// that may have type parameters in its signature.
@@ -3845,17 +3864,27 @@ void CodeGenFunction::EmitCallArgs(
assert((ParamsToSkip == 0 || Prototype.P) &&
"Can't skip parameters if type info is not provided");
- // First, use the argument types that the type info knows about
+ // This variable only captures *explicitly* written conventions, not those
+ // applied by default via command line flags or target defaults, such as
+ // thiscall, aapcs, stdcall via -mrtd, etc. Computing that correctly would
+ // require knowing if this is a C++ instance method or being able to see
+ // unprototyped FunctionTypes.
+ CallingConv ExplicitCC = CC_C;
+
+ // First, if a prototype was provided, use those argument types.
bool IsVariadic = false;
if (Prototype.P) {
const auto *MD = Prototype.P.dyn_cast();
if (MD) {
IsVariadic = MD->isVariadic();
+ ExplicitCC = getCallingConventionForDecl(
+ MD, CGM.getTarget().getTriple().isOSWindows());
ArgTypes.assign(MD->param_type_begin() + ParamsToSkip,
MD->param_type_end());
} else {
const auto *FPT = Prototype.P.get();
IsVariadic = FPT->isVariadic();
+ ExplicitCC = FPT->getExtInfo().getCC();
ArgTypes.assign(FPT->param_type_begin() + ParamsToSkip,
FPT->param_type_end());
}
@@ -3923,15 +3952,10 @@ void CodeGenFunction::EmitCallArgs(
};
// Insert a stack save if we're going to need any inalloca args.
- bool HasInAllocaArgs = false;
- if (CGM.getTarget().getCXXABI().isMicrosoft()) {
-for (ArrayRef::iterator I = ArgTypes.begin(), E = ArgTypes.end();
- I != E && !HasInAllocaArgs; ++I)
- HasInAllocaArgs = isInAllocaArgument(CGM.getCXXABI(), *I);
-if (HasInAllocaArgs) {
- assert(getTarget().getTriple().getArch() == llvm::Triple::x86);
- Args.allocateArgumentMemory(*this);
-}
+ if (hasInAllocaArgs(CGM, ExplicitCC, ArgTypes)) {
+assert(getTarget().getTriple().getArch() == llvm::Triple::x86 &&
+ "inalloca only supported on x8
[llvm-branch-commits] [lld] c8466a5 - Avoid a possible one-byte OOB read off of .drectve sections
Author: Reid Kleckner
Date: 2020-12-09T13:32:28-08:00
New Revision: c8466a57310a0f10563e4a5a511e8c6386599cfe
URL:
https://github.com/llvm/llvm-project/commit/c8466a57310a0f10563e4a5a511e8c6386599cfe
DIFF:
https://github.com/llvm/llvm-project/commit/c8466a57310a0f10563e4a5a511e8c6386599cfe.diff
LOG: Avoid a possible one-byte OOB read off of .drectve sections
Pointed out by Ryan Prichard
Added:
Modified:
lld/COFF/DriverUtils.cpp
Removed:
diff --git a/lld/COFF/DriverUtils.cpp b/lld/COFF/DriverUtils.cpp
index f289e66dc6d5..19964428050b 100644
--- a/lld/COFF/DriverUtils.cpp
+++ b/lld/COFF/DriverUtils.cpp
@@ -883,8 +883,10 @@ ParsedDirectives ArgParser::parseDirectives(StringRef s) {
tok.startswith_lower("-include:"))
result.includes.push_back(tok.substr(strlen("/include:")));
else {
- // Save non-null-terminated strings to make proper C strings.
- bool HasNul = tok.data()[tok.size()] == '\0';
+ // Copy substrings that are not valid C strings. The tokenizer may have
+ // already copied quoted arguments for us, so those do not need to be
+ // copied again.
+ bool HasNul = tok.end() != s.end() && tok.data()[tok.size()] == '\0';
rest.push_back(HasNul ? tok.data() : saver.save(tok).data());
}
}
___
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[llvm-branch-commits] [llvm-branch] r339698 - Merging r339636:
Author: rnk Date: Tue Aug 14 10:35:35 2018 New Revision: 339698 URL: http://llvm.org/viewvc/llvm-project?rev=339698&view=rev Log: Merging r339636: r339636 | rnk | 2018-08-13 18:24:35 -0700 (Mon, 13 Aug 2018) | 17 lines [BasicAA] Don't assume tail calls with byval don't alias allocas Summary: Calls marked 'tail' cannot read or write allocas from the current frame because the current frame might be destroyed by the time they run. However, a tail call may use an alloca with byval. Calling with byval copies the contents of the alloca into argument registers or stack slots, so there is no lifetime issue. Tail calls never modify allocas, so we can return just ModRefInfo::Ref. Fixes PR38466, a longstanding bug. Reviewers: hfinkel, nlewycky, gbiv, george.burgess.iv Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D50679 Added: llvm/branches/release_70/test/Analysis/BasicAA/tail-byval.ll - copied unchanged from r339636, llvm/trunk/test/Analysis/BasicAA/tail-byval.ll llvm/branches/release_70/test/Transforms/DeadStoreElimination/tail-byval.ll - copied unchanged from r339636, llvm/trunk/test/Transforms/DeadStoreElimination/tail-byval.ll Modified: llvm/branches/release_70/ (props changed) llvm/branches/release_70/lib/Analysis/BasicAliasAnalysis.cpp Propchange: llvm/branches/release_70/ -- --- svn:mergeinfo (original) +++ svn:mergeinfo Tue Aug 14 10:35:35 2018 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338902,338915,338968,339073,339179,339184,339190,339225,339316,339319,339411,339492,339600 +/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338902,338915,338968,339073,339179,339184,339190,339225,339316,339319,339411,339492,339600,339636 Modified: llvm/branches/release_70/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Analysis/BasicAliasAnalysis.cpp?rev=339698&r1=339697&r2=339698&view=diff == --- llvm/branches/release_70/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/branches/release_70/lib/Analysis/BasicAliasAnalysis.cpp Tue Aug 14 10:35:35 2018 @@ -801,14 +801,15 @@ ModRefInfo BasicAAResult::getModRefInfo( const Value *Object = GetUnderlyingObject(Loc.Ptr, DL); - // If this is a tail call and Loc.Ptr points to a stack location, we know that - // the tail call cannot access or modify the local stack. - // We cannot exclude byval arguments here; these belong to the caller of - // the current function not to the current function, and a tail callee - // may reference them. + // Calls marked 'tail' cannot read or write allocas from the current frame + // because the current frame might be destroyed by the time they run. However, + // a tail call may use an alloca with byval. Calling with byval copies the + // contents of the alloca into argument registers or stack slots, so there is + // no lifetime issue. if (isa(Object)) if (const CallInst *CI = dyn_cast(CS.getInstruction())) - if (CI->isTailCall()) + if (CI->isTailCall() && + !CI->getAttributes().hasAttrSomewhere(Attribute::ByVal)) return ModRefInfo::NoModRef; // If the pointer is to a locally allocated object that does not escape, ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [cfe-branch] r340087 - Merging r340079:
Author: rnk
Date: Fri Aug 17 14:25:51 2018
New Revision: 340087
URL: http://llvm.org/viewvc/llvm-project?rev=340087&view=rev
Log:
Merging r340079:
r340079 | rnk | 2018-08-17 13:59:27 -0700 (Fri, 17 Aug 2018) | 20 lines
[MS] Mangle a hash of the main file path into anonymous namespaces
Summary:
This is needed to avoid conflicts in mangled names for codeview types in
anonymous namespaces. In CodeView, types refer to each other typically
through forward declarations, which contain mangled names. These names
have to be unique, otherwise the debugger will look up the mangled name
and find the wrong definition.
Furthermore, ThinLTO will deduplicate the types, and debug info
verification can fail when the types have the wrong sizes. This is
PR38608.
Fixes PR38609.
Reviewers: majnemer, inglorion, hans
Subscribers: mehdi_amini, aprantl, JDevlieghere, dexonsmith, cfe-commits
Differential Revision: https://reviews.llvm.org/D50877
Modified:
cfe/branches/release_70/ (props changed)
cfe/branches/release_70/lib/AST/MicrosoftMangle.cpp
cfe/branches/release_70/test/CodeGenCXX/cfi-cross-dso.cpp
cfe/branches/release_70/test/CodeGenCXX/cfi-icall.cpp
cfe/branches/release_70/test/CodeGenCXX/debug-info-thunk.cpp
cfe/branches/release_70/test/CodeGenCXX/dllexport.cpp
cfe/branches/release_70/test/CodeGenCXX/mangle-ms.cpp
cfe/branches/release_70/test/CodeGenCXX/microsoft-abi-structors.cpp
cfe/branches/release_70/test/CodeGenCXX/microsoft-abi-throw.cpp
cfe/branches/release_70/test/CodeGenCXX/microsoft-abi-thunks.cpp
cfe/branches/release_70/test/CodeGenCXX/microsoft-abi-vftables.cpp
cfe/branches/release_70/test/CodeGenCXX/microsoft-abi-virtual-member-pointers.cpp
cfe/branches/release_70/test/CodeGenCXX/msabi-swiftcall-cc.cpp
cfe/branches/release_70/test/CodeGenCXX/pragma-init_seg.cpp
cfe/branches/release_70/test/CodeGenCXX/type-metadata.cpp
Propchange: cfe/branches/release_70/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Aug 17 14:25:51 2018
@@ -1,4 +1,4 @@
/cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:338552-338553,338602,338627,338749,338934,338942,339074,339128,339170,339210,339264,339281,339317,339428,339494,339597,339603
+/cfe/trunk:338552-338553,338602,338627,338749,338934,338942,339074,339128,339170,339210,339264,339281,339317,339428,339494,339597,339603,340079
/cfe/trunk/test:170344
/cfe/trunk/test/SemaTemplate:126920
Modified: cfe/branches/release_70/lib/AST/MicrosoftMangle.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_70/lib/AST/MicrosoftMangle.cpp?rev=340087&r1=340086&r2=340087&view=diff
==
--- cfe/branches/release_70/lib/AST/MicrosoftMangle.cpp (original)
+++ cfe/branches/release_70/lib/AST/MicrosoftMangle.cpp Fri Aug 17 14:25:51 2018
@@ -29,6 +29,7 @@
#include "clang/Basic/TargetInfo.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/Support/JamCRC.h"
+#include "llvm/Support/xxhash.h"
#include "llvm/Support/MD5.h"
#include "llvm/Support/MathExtras.h"
@@ -127,10 +128,10 @@ class MicrosoftMangleContextImpl : publi
llvm::DenseMap LambdaIds;
llvm::DenseMap SEHFilterIds;
llvm::DenseMap SEHFinallyIds;
+ SmallString<16> AnonymousNamespaceHash;
public:
- MicrosoftMangleContextImpl(ASTContext &Context, DiagnosticsEngine &Diags)
- : MicrosoftMangleContext(Context, Diags) {}
+ MicrosoftMangleContextImpl(ASTContext &Context, DiagnosticsEngine &Diags);
bool shouldMangleCXXName(const NamedDecl *D) override;
bool shouldMangleStringLiteral(const StringLiteral *SL) override;
void mangleCXXName(const NamedDecl *D, raw_ostream &Out) override;
@@ -238,6 +239,12 @@ public:
return Result.first->second;
}
+ /// Return a character sequence that is (somewhat) unique to the TU suitable
+ /// for mangling anonymous namespaces.
+ StringRef getAnonymousNamespaceHash() const {
+return AnonymousNamespaceHash;
+ }
+
private:
void mangleInitFiniStub(const VarDecl *D, char CharCode, raw_ostream &Out);
};
@@ -371,6 +378,34 @@ private:
};
}
+MicrosoftMangleContextImpl::MicrosoftMangleContextImpl(ASTContext &Context,
+ DiagnosticsEngine
&Diags)
+: MicrosoftMangleContext(Context, Diags) {
+ // To mangle anonymous namespaces, hash the path to the main source file. The
+ // path should be whatever (probably relative) path was passed on the command
+ // line. The goal is for the compiler to produce the same output regardless
of
+ // working directory, so use the uncanonicalized relative path.
+ //
+ // It's important to make the mangled names unique because, when CodeView
+ // debug info is in use, the debugger uses mangl
[llvm-branch-commits] [cfe-branch] r340103 - Merging r340101:
Author: rnk
Date: Fri Aug 17 15:18:56 2018
New Revision: 340103
URL: http://llvm.org/viewvc/llvm-project?rev=340103&view=rev
Log:
Merging r340101:
r340101 | rnk | 2018-08-17 15:11:31 -0700 (Fri, 17 Aug 2018) | 14 lines
Don't warn on returning the address of a label from a statement expression
Summary:
There isn't anything inherently wrong with returning a label from a
statement expression. In practice, the Linux kernel uses this pattern to
materialize PCs.
Fixes PR38569
Reviewers: niravd, rsmith, nickdesaulniers
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D50805
Modified:
cfe/branches/release_70/ (props changed)
cfe/branches/release_70/lib/Sema/SemaInit.cpp
cfe/branches/release_70/test/Sema/statements.c
Propchange: cfe/branches/release_70/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Aug 17 15:18:56 2018
@@ -1,4 +1,4 @@
/cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:338552-338553,338602,338627,338749,338934,338942,339074,339128,339170,339210,339264,339281,339317,339428,339494,339597,339603,340079
+/cfe/trunk:338552-338553,338602,338627,338749,338934,338942,339074,339128,339170,339210,339264,339281,339317,339428,339494,339597,339603,340079,340101
/cfe/trunk/test:170344
/cfe/trunk/test/SemaTemplate:126920
Modified: cfe/branches/release_70/lib/Sema/SemaInit.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_70/lib/Sema/SemaInit.cpp?rev=340103&r1=340102&r2=340103&view=diff
==
--- cfe/branches/release_70/lib/Sema/SemaInit.cpp (original)
+++ cfe/branches/release_70/lib/Sema/SemaInit.cpp Fri Aug 17 15:18:56 2018
@@ -6942,6 +6942,10 @@ void Sema::checkInitializerLifetime(cons
} else if (isa(L)) {
Diag(DiagLoc, diag::err_ret_local_block) << DiagRange;
} else if (isa(L)) {
+// Don't warn when returning a label from a statement expression.
+// Leaving the scope doesn't end its lifetime.
+if (LK == LK_StmtExprResult)
+ return false;
Diag(DiagLoc, diag::warn_ret_addr_label) << DiagRange;
} else {
Diag(DiagLoc, diag::warn_ret_local_temp_addr_ref)
Modified: cfe/branches/release_70/test/Sema/statements.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_70/test/Sema/statements.c?rev=340103&r1=340102&r2=340103&view=diff
==
--- cfe/branches/release_70/test/Sema/statements.c (original)
+++ cfe/branches/release_70/test/Sema/statements.c Fri Aug 17 15:18:56 2018
@@ -34,6 +34,15 @@ bar:
return &&bar; // expected-warning {{returning address of label, which is
local}}
}
+// PR38569: Don't warn when returning a label from a statement expression.
+void test10_logpc(void*);
+void test10a() {
+ test10_logpc(({
+my_pc:
+ &&my_pc;
+ }));
+}
+
// PR6034
void test11(int bit) {
switch (bit)
___
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[llvm-branch-commits] [llvm-branch] r353220 - Merging rr353218:
Author: rnk
Date: Tue Feb 5 13:25:23 2019
New Revision: 353220
URL: http://llvm.org/viewvc/llvm-project?rev=353220&view=rev
Log:
Merging rr353218:
r353218 | rnk | 2019-02-05 13:14:09 -0800 (Tue, 05 Feb 2019) | 19 lines
[MC] Don't error on numberless .file directives on MachO
Summary:
Before r349976, MC ignored such directives when producing an object file
and asserted when re-producing textual assembly output. I turned this
assertion into a hard error in both cases in r349976, but this makes it
unnecessarily difficult to write a single assembly file that supports
both MachO and other object formats that support .file. A user reported
this as PR40578, and we decided to go back to ignoring the directive.
Fixes PR40578
Reviewers: mstorsjo
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57772
Removed:
llvm/branches/release_80/test/MC/MachO/file-single.s
Modified:
llvm/branches/release_80/ (props changed)
llvm/branches/release_80/lib/MC/MCParser/AsmParser.cpp
llvm/branches/release_80/test/MC/MachO/file.s
Propchange: llvm/branches/release_80/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 5 13:25:23 2019
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,351325,351344-351345,351349,351351,351370,351381,351421,351426,351436,351475,351485,351753-351754,351910,351930,351932,352034,352204,352246,352374,352555,352770,352889,352945,353082
+/llvm/trunk:155241,351325,351344-351345,351349,351351,351370,351381,351421,351426,351436,351475,351485,351753-351754,351910,351930,351932,352034,352204,352246,352374,352555,352770,352889,352945,353082,353218
Modified: llvm/branches/release_80/lib/MC/MCParser/AsmParser.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_80/lib/MC/MCParser/AsmParser.cpp?rev=353220&r1=353219&r2=353220&view=diff
==
--- llvm/branches/release_80/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/branches/release_80/lib/MC/MCParser/AsmParser.cpp Tue Feb 5 13:25:23
2019
@@ -3364,10 +3364,11 @@ bool AsmParser::parseDirectiveFile(SMLoc
}
if (FileNumber == -1) {
-if (!getContext().getAsmInfo()->hasSingleParameterDotFile())
- return Error(DirectiveLoc,
- "target does not support '.file' without a number");
-getStreamer().EmitFileDirective(Filename);
+// Ignore the directive if there is no number and the target doesn't
support
+// numberless .file directives. This allows some portability of assembler
+// between different object file formats.
+if (getContext().getAsmInfo()->hasSingleParameterDotFile())
+ getStreamer().EmitFileDirective(Filename);
} else {
// In case there is a -g option as well as debug info from directive .file,
// we turn off the -g option, directly use the existing debug info instead.
Removed: llvm/branches/release_80/test/MC/MachO/file-single.s
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_80/test/MC/MachO/file-single.s?rev=353219&view=auto
==
--- llvm/branches/release_80/test/MC/MachO/file-single.s (original)
+++ llvm/branches/release_80/test/MC/MachO/file-single.s (removed)
@@ -1,8 +0,0 @@
-// RUN: not llvm-mc -triple i386-apple-darwin9 %s -o /dev/null 2>&1 |
FileCheck %s
-
-// Previously this crashed MC.
-
-// CHECK: error: target does not support '.file' without a number
-
-.file "dir/foo"
-nop
Modified: llvm/branches/release_80/test/MC/MachO/file.s
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_80/test/MC/MachO/file.s?rev=353220&r1=353219&r2=353220&view=diff
==
--- llvm/branches/release_80/test/MC/MachO/file.s (original)
+++ llvm/branches/release_80/test/MC/MachO/file.s Tue Feb 5 13:25:23 2019
@@ -1,5 +1,8 @@
// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - |
llvm-readobj -s -section-data | FileCheck %s
+// This number-less file directive is ignored on MachO.
+.file "bar/baz.s"
+
.file 1 "dir/foo"
nop
___
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[llvm-branch-commits] [cfe-branch] r364483 - Merging r359809:
Author: rnk
Date: Wed Jun 26 14:59:19 2019
New Revision: 364483
URL: http://llvm.org/viewvc/llvm-project?rev=364483&view=rev
Log:
Merging r359809:
r359809 | rnk | 2019-05-02 10:45:54 -0700 (Thu, 02 May 2019) | 27 lines
Use primary template parameter names for variable template debug info
Summary:
Fixes PR41677
Consider:
template constexpr bool is_same_v = false;
template constexpr bool is_same_v = true;
template constexpr bool is_same_v;
Before this change, when emitting debug info for the
`is_same_v` global variable, clang would crash because it
would try to use the template parameter list from the partial
specialization to give parameter names to template arguments. This
doesn't work in general, since a partial specialization can have fewer
arguments than the primary template. Therefore, always use the primary
template. Hypothetically we could try to use the parameter names from
the partial specialization when possible, but it's not clear this really
helps debugging in practice.
Reviewers: JDevlieghere, aprantl, ormris, dblaikie
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D61408
Added:
cfe/branches/release_80/test/CodeGenCXX/debug-info-var-template-partial.cpp
- copied, changed from r359809,
cfe/trunk/test/CodeGenCXX/debug-info-var-template-partial.cpp
Modified:
cfe/branches/release_80/ (props changed)
cfe/branches/release_80/lib/CodeGen/CGDebugInfo.cpp
cfe/branches/release_80/test/CodeGenCXX/debug-info-template-member.cpp
Propchange: cfe/branches/release_80/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jun 26 14:59:19 2019
@@ -1,4 +1,4 @@
/cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:351334,351340,351344,351360,351457,351459,351531,351579-351580,352040,352079,352099,352102,352105,352119,352156,352221-35,352229,352307,352323,352463,352539,352610,352672,352822,353142,353393,353402,353411,353431,353493,353495,353656,353943,353976,354035,354074,354147,354351,354721,354723,354937,354968,355489,355491,355743
+/cfe/trunk:351334,351340,351344,351360,351457,351459,351531,351579-351580,352040,352079,352099,352102,352105,352119,352156,352221-35,352229,352307,352323,352463,352539,352610,352672,352822,353142,353393,353402,353411,353431,353493,353495,353656,353943,353976,354035,354074,354147,354351,354721,354723,354937,354968,355489,355491,355743,359809
/cfe/trunk/test:170344
/cfe/trunk/test/SemaTemplate:126920
Modified: cfe/branches/release_80/lib/CodeGen/CGDebugInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_80/lib/CodeGen/CGDebugInfo.cpp?rev=364483&r1=364482&r2=364483&view=diff
==
--- cfe/branches/release_80/lib/CodeGen/CGDebugInfo.cpp (original)
+++ cfe/branches/release_80/lib/CodeGen/CGDebugInfo.cpp Wed Jun 26 14:59:19 2019
@@ -1817,32 +1817,24 @@ CGDebugInfo::CollectFunctionTemplatePara
}
llvm::DINodeArray CGDebugInfo::CollectVarTemplateParams(const VarDecl *VL,
-llvm::DIFile *Unit) {
- if (auto *TS = dyn_cast(VL)) {
-auto T = TS->getSpecializedTemplateOrPartial();
-auto TA = TS->getTemplateArgs().asArray();
-// Collect parameters for a partial specialization
-if (T.is()) {
- const TemplateParameterList *TList =
-T.get()
-->getTemplateParameters();
- return CollectTemplateParams(TList, TA, Unit);
-}
-
-// Collect parameters for an explicit specialization
-if (T.is()) {
- const TemplateParameterList *TList = T.get()
-->getTemplateParameters();
- return CollectTemplateParams(TList, TA, Unit);
-}
- }
- return llvm::DINodeArray();
+llvm::DIFile *Unit) {
+ // Always get the full list of parameters, not just the ones from the
+ // specialization. A partial specialization may have fewer parameters than
+ // there are arguments.
+ auto *TS = dyn_cast(VL);
+ if (!TS)
+return llvm::DINodeArray();
+ VarTemplateDecl *T = TS->getSpecializedTemplate();
+ const TemplateParameterList *TList = T->getTemplateParameters();
+ auto TA = TS->getTemplateArgs().asArray();
+ return CollectTemplateParams(TList, TA, Unit);
}
llvm::DINodeArray CGDebugInfo::CollectCXXTemplateParams(
const ClassTemplateSpecializationDecl *TSpecial, llvm::DIFile *Unit) {
- // Always get the full list of parameters, not just the ones from
- // the specialization.
+ // Always get the full list of parameters, not just the ones from the
+ // specialization. A partial specialization may have fewer parameters than
+ // there are arguments.
TemplateParameterList *TPList =
TSpecial->getSpecializedTemplate()->getTemplateParameters();
const TemplateArgum
[llvm-branch-commits] [llvm] a4b77f5 - [codeview] Workaround for PR43479, don't re-emit instr labels
Author: Reid Kleckner
Date: 2019-10-28T16:22:29-07:00
New Revision: a4b77f5ffb167fb2d41ec5c14f8ace6d4f5832bf
URL:
https://github.com/llvm/llvm-project/commit/a4b77f5ffb167fb2d41ec5c14f8ace6d4f5832bf
DIFF:
https://github.com/llvm/llvm-project/commit/a4b77f5ffb167fb2d41ec5c14f8ace6d4f5832bf.diff
LOG: [codeview] Workaround for PR43479, don't re-emit instr labels
Summary:
In the long run we should come up with another mechanism for marking
call instructions as heap allocation sites, and remove this workaround.
For now, we've had two bug reports about this, so let's apply this
workaround. SLH (the other client of instruction labels) probably has
the same bug, but the solution there is more likely to be to mark the
call instruction as not duplicatable, which doesn't work for debug info.
Reviewers: akhuang
Subscribers: aprantl, hiraditya, aganea, chandlerc, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69068
llvm-svn: 375137
(cherry picked from commit fc69ad09882ccfbedc2d06afc971d59eb6a24ee0)
Added:
llvm/test/CodeGen/X86/taildup-heapallocsite.ll
Modified:
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Removed:
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 54f6cc2d5571..21b1fb8f8675 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -1052,9 +1052,13 @@ void AsmPrinter::EmitFunctionBody() {
++NumInstsInFunction;
}
- // If there is a pre-instruction symbol, emit a label for it here.
+ // If there is a pre-instruction symbol, emit a label for it here. If the
+ // instruction was duplicated and the label has already been emitted,
+ // don't re-emit the same label.
+ // FIXME: Consider strengthening that to an assertion.
if (MCSymbol *S = MI.getPreInstrSymbol())
-OutStreamer->EmitLabel(S);
+if (S->isUndefined())
+ OutStreamer->EmitLabel(S);
if (ShouldPrintDebugScopes) {
for (const HandlerInfo &HI : Handlers) {
@@ -1107,9 +,13 @@ void AsmPrinter::EmitFunctionBody() {
break;
}
- // If there is a post-instruction symbol, emit a label for it here.
+ // If there is a post-instruction symbol, emit a label for it here. If
+ // the instruction was duplicated and the label has already been emitted,
+ // don't re-emit the same label.
+ // FIXME: Consider strengthening that to an assertion.
if (MCSymbol *S = MI.getPostInstrSymbol())
-OutStreamer->EmitLabel(S);
+if (S->isUndefined())
+ OutStreamer->EmitLabel(S);
if (ShouldPrintDebugScopes) {
for (const HandlerInfo &HI : Handlers) {
diff --git a/llvm/test/CodeGen/X86/taildup-heapallocsite.ll
b/llvm/test/CodeGen/X86/taildup-heapallocsite.ll
new file mode 100644
index ..378efe2deec2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/taildup-heapallocsite.ll
@@ -0,0 +1,81 @@
+; RUN: llc < %s -tail-dup-placement-threshold=4 | FileCheck %s
+
+; Based on test case from PR43695:
+; __declspec(allocator) void *alloc(unsigned int size);
+; void f2();
+; void f1(unsigned int *size_ptr) {
+; void *hg = alloc(size_ptr ? *size_ptr : 1UL);
+; f2();
+; }
+
+; In this case, block placement duplicates the heap allocation site. For now,
+; LLVM drops the labels from one call site. Eventually, we should track both.
+
+; ModuleID = 't.cpp'
+source_filename = "t.cpp"
+target datalayout =
"e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-windows-msvc19.22.27905"
+
+define dso_local void @taildupit(i32* readonly %size_ptr) !dbg !8 {
+entry:
+ call void @llvm.dbg.value(metadata i32* %size_ptr, metadata !14, metadata
!DIExpression()), !dbg !17
+ %tobool = icmp eq i32* %size_ptr, null, !dbg !18
+ br i1 %tobool, label %cond.end, label %cond.true, !dbg !18
+
+cond.true:; preds = %entry
+ %0 = load i32, i32* %size_ptr, align 4, !dbg !18, !tbaa !19
+ br label %cond.end, !dbg !18
+
+cond.end: ; preds = %entry, %cond.true
+ %cond = phi i32 [ %0, %cond.true ], [ 1, %entry ], !dbg !18
+ %call = tail call i8* @alloc(i32 %cond), !dbg !18, !heapallocsite !2
+ call void @llvm.dbg.value(metadata i8* %call, metadata !15, metadata
!DIExpression()), !dbg !17
+ tail call void @f2(), !dbg !23
+ ret void, !dbg !24
+}
+
+; CHECK-LABEL: taildupit: # @taildupit
+; CHECK: testq
+; CHECK: je
+; CHECK: .Lheapallocsite0:
+; CHECK: callq alloc
+; CHECK: .Lheapallocsite1:
+; CHECK: jmp f2 # TAILCALL
+; CHECK-NOT: Lheapallocsite
+; CHECK: callq alloc
+; CHECK-NOT: Lheapallocsite
+; CHECK: jmp f2 # TAILCALL
+
+declare dso_local i8* @alloc(i32)
+
+declare dso_local void @f2()
+
+declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+!ll
[llvm-branch-commits] [clang] 2d75b24 - [MS] Fix constexpr data member pointer conversions
Author: Reid Kleckner
Date: 2019-10-30T11:20:31-07:00
New Revision: 2d75b245668a49815935687b9a70beddbc68f66c
URL:
https://github.com/llvm/llvm-project/commit/2d75b245668a49815935687b9a70beddbc68f66c
DIFF:
https://github.com/llvm/llvm-project/commit/2d75b245668a49815935687b9a70beddbc68f66c.diff
LOG: [MS] Fix constexpr data member pointer conversions
Constexpr data member conversions work by starting with the class that
originally introduced the field, and converting from there to the type
that the user desires. Before this change, Clang was using the
inheritance model from the final destination class type instead of the
model from the class that originally introduced the field. To fix this,
find the relevant FieldDecl and take its parent class instead of using
the member pointer type the user provided.
Indirect field decls require some special handling to find the parent
class.
Fixes PR43803
(cherry picked from commit 07ee46d613d7c1862878d7c7d1208a7b3e37459d)
Added:
Modified:
clang/lib/CodeGen/MicrosoftCXXABI.cpp
clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp
Removed:
diff --git a/clang/lib/CodeGen/MicrosoftCXXABI.cpp
b/clang/lib/CodeGen/MicrosoftCXXABI.cpp
index ca06ad3f042b..e02c9ae0b8f2 100644
--- a/clang/lib/CodeGen/MicrosoftCXXABI.cpp
+++ b/clang/lib/CodeGen/MicrosoftCXXABI.cpp
@@ -617,6 +617,9 @@ class MicrosoftCXXABI : public CGCXXABI {
llvm::Function *EmitVirtualMemPtrThunk(const CXXMethodDecl *MD,
const MethodVFTableLocation &ML);
+ llvm::Constant *EmitMemberDataPointer(const CXXRecordDecl *RD,
+CharUnits offset);
+
public:
llvm::Type *ConvertMemberPointerType(const MemberPointerType *MPT) override;
@@ -2700,7 +2703,11 @@ MicrosoftCXXABI::EmitFullMemberPointer(llvm::Constant
*FirstField,
llvm::Constant *
MicrosoftCXXABI::EmitMemberDataPointer(const MemberPointerType *MPT,
CharUnits offset) {
- const CXXRecordDecl *RD = MPT->getMostRecentCXXRecordDecl();
+ return EmitMemberDataPointer(MPT->getMostRecentCXXRecordDecl(), offset);
+}
+
+llvm::Constant *MicrosoftCXXABI::EmitMemberDataPointer(const CXXRecordDecl *RD,
+ CharUnits offset) {
if (RD->getMSInheritanceModel() ==
MSInheritanceAttr::Keyword_virtual_inheritance)
offset -= getContext().getOffsetOfBaseWithVBPtr(RD);
@@ -2724,8 +2731,17 @@ llvm::Constant *MicrosoftCXXABI::EmitMemberPointer(const
APValue &MP,
if (const CXXMethodDecl *MD = dyn_cast(MPD)) {
C = EmitMemberFunctionPointer(MD);
} else {
+// For a pointer to data member, start off with the offset of the field in
+// the class in which it was declared, and convert from there if necessary.
+// For indirect field decls, get the outermost anonymous field and use the
+// parent class.
CharUnits FieldOffset = Ctx.toCharUnitsFromBits(Ctx.getFieldOffset(MPD));
-C = EmitMemberDataPointer(DstTy, FieldOffset);
+const FieldDecl *FD = dyn_cast(MPD);
+if (!FD)
+ FD = cast(*cast(MPD)->chain_begin());
+const CXXRecordDecl *RD = cast(FD->getParent());
+RD = RD->getMostRecentNonInjectedDecl();
+C = EmitMemberDataPointer(RD, FieldOffset);
}
if (!MemberPointerPath.empty()) {
diff --git a/clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp
b/clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp
index cb3b41bbb4f1..4202f847a034 100644
--- a/clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp
+++ b/clang/test/CodeGenCXX/microsoft-abi-member-pointers.cpp
@@ -121,6 +121,33 @@ void VirtualInheritanceFnPtrCall() {
}
} // namespace pr37399
+namespace pr43803 {
+// This case is interesting because it exercises conversion between member
+// pointer types when emitting constants.
+
+struct B;
+struct C { int B::*option; };
+extern const C table[3];
+struct A {
+ int x, y;
+ // Test the indirect case.
+ struct {
+int z;
+ };
+};
+struct B : A {};
+const C table[] = {
+{&B::x},
+{&B::y},
+{&B::z},
+};
+
+// CHECK: @"?table@pr43803@@3QBUC@1@B" = dso_local constant [3 x
%"struct.pr43803::C"]
+// CHECK-SAME: [%"struct.pr43803::C" { { i32, i32, i32 } zeroinitializer, [4 x
i8] undef },
+// CHECK-SAME: %"struct.pr43803::C" { { i32, i32, i32 } { i32 4, i32 0, i32 0
}, [4 x i8] undef },
+// CHECK-SAME: %"struct.pr43803::C" { { i32, i32, i32 } { i32 8, i32 0, i32 0
}, [4 x i8] undef }]
+}
+
struct PR26313_Y;
typedef void (PR26313_Y::*PR26313_FUNC)();
struct PR26313_X {
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[llvm-branch-commits] [llvm] 9a9b649 - [WinEH] Allocate space in funclets stack to save XMM CSRs
Author: Pengfei Wang
Date: 2019-11-05T12:52:54-08:00
New Revision: 9a9b6492a66c3f83e58f5b4e451797b6baf7f3ea
URL:
https://github.com/llvm/llvm-project/commit/9a9b6492a66c3f83e58f5b4e451797b6baf7f3ea
DIFF:
https://github.com/llvm/llvm-project/commit/9a9b6492a66c3f83e58f5b4e451797b6baf7f3ea.diff
LOG: [WinEH] Allocate space in funclets stack to save XMM CSRs
Summary:
This is an alternate approach to D63396
Currently funclets reuse the same stack slots that are used in the
parent function for saving callee-saved xmm registers. If the parent
function modifies a callee-saved xmm register before an excpetion is
thrown, the catch handler will overwrite the original saved value.
This patch allocates space in funclets stack for saving callee-saved xmm
registers and uses RSP instead RBP to access memory.
Signed-off-by: Pengfei Wang
Reviewers: rnk, RKSimon, craig.topper, annita.zhang, LuoYuanke, andrew.w.kaylor
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D66596
Signed-off-by: Pengfei Wang
llvm-svn: 370005
(cherry picked from commit 564fb58a32a808c34d809820d00e2f23c0307a71)
Added:
llvm/test/CodeGen/X86/win64-funclet-savexmm.ll
Modified:
llvm/lib/Target/X86/X86FrameLowering.cpp
llvm/lib/Target/X86/X86FrameLowering.h
llvm/lib/Target/X86/X86MachineFunctionInfo.h
llvm/lib/Target/X86/X86RegisterInfo.cpp
llvm/test/CodeGen/X86/avx512-intel-ocl.ll
llvm/test/CodeGen/X86/catchpad-realign-savexmm.ll
llvm/test/CodeGen/X86/x86-interrupt_cc.ll
Removed:
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp
b/llvm/lib/Target/X86/X86FrameLowering.cpp
index e310fe069117..854156b2bc8e 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -1396,9 +1396,13 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
int FI;
if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
if (X86::FR64RegClass.contains(Reg)) {
+ int Offset;
unsigned IgnoredFrameReg;
- int Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg);
- Offset += SEHFrameOffset;
+ if (IsWin64Prologue && IsFunclet)
+Offset = getWin64EHFrameIndexRef(MF, FI, IgnoredFrameReg);
+ else
+Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg) +
+ SEHFrameOffset;
HasWinCFI = true;
assert(!NeedsWinFPO && "SEH_SaveXMM incompatible with FPO data");
@@ -1554,9 +1558,13 @@ X86FrameLowering::getPSPSlotOffsetFromSP(const
MachineFunction &MF) const {
unsigned
X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
+ const X86MachineFunctionInfo *X86FI = MF.getInfo();
// This is the size of the pushed CSRs.
- unsigned CSSize =
- MF.getInfo()->getCalleeSavedFrameSize();
+ unsigned CSSize = X86FI->getCalleeSavedFrameSize();
+ // This is the size of callee saved XMMs.
+ const auto& WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
+ unsigned XMMSize = WinEHXMMSlotInfo.size() *
+ TRI->getSpillSize(X86::VR128RegClass);
// This is the amount of stack a funclet needs to allocate.
unsigned UsedSize;
EHPersonality Personality =
@@ -1576,7 +1584,7 @@ X86FrameLowering::getWinEHFuncletFrameSize(const
MachineFunction &MF) const {
unsigned FrameSizeMinusRBP = alignTo(CSSize + UsedSize, getStackAlignment());
// Subtract out the size of the callee saved registers. This is how much
stack
// each funclet will allocate.
- return FrameSizeMinusRBP - CSSize;
+ return FrameSizeMinusRBP + XMMSize - CSSize;
}
static bool isTailCallOpcode(unsigned Opc) {
@@ -1850,6 +1858,20 @@ int X86FrameLowering::getFrameIndexReference(const
MachineFunction &MF, int FI,
return Offset + FPDelta;
}
+int X86FrameLowering::getWin64EHFrameIndexRef(const MachineFunction &MF,
+ int FI, unsigned &FrameReg)
const {
+ const MachineFrameInfo &MFI = MF.getFrameInfo();
+ const X86MachineFunctionInfo *X86FI = MF.getInfo();
+ const auto& WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
+ const auto it = WinEHXMMSlotInfo.find(FI);
+
+ if (it == WinEHXMMSlotInfo.end())
+return getFrameIndexReference(MF, FI, FrameReg);
+
+ FrameReg = TRI->getStackRegister();
+ return alignTo(MFI.getMaxCallFrameSize(), getStackAlignment()) + it->second;
+}
+
int X86FrameLowering::getFrameIndexReferenceSP(const MachineFunction &MF,
int FI, unsigned &FrameReg,
int Adjustment) const {
@@ -1948,6 +1970,8 @@ bool X86FrameLowering::assignCalleeSavedSpillSlots(
X86MachineFunctionInfo *X86FI = MF.getInfo();
unsigned CalleeSavedFrameSize = 0;
+ unsigned XMMCalleeSavedFrameSize = 0;
+ auto &WinEHXMMSlotInfo = X86FI->getWinEHXMMSlo
[llvm-branch-commits] [llvm] c23212a - [IR] Keep a double break between functions when printing a module
Author: Reid Kleckner
Date: 2020-01-27T15:34:05-08:00
New Revision: c23212a438f6ff20bf1d98e5ca23c5cd28591ce3
URL:
https://github.com/llvm/llvm-project/commit/c23212a438f6ff20bf1d98e5ca23c5cd28591ce3
DIFF:
https://github.com/llvm/llvm-project/commit/c23212a438f6ff20bf1d98e5ca23c5cd28591ce3.diff
LOG: [IR] Keep a double break between functions when printing a module
This behavior appears to have changed unintentionally in
b0e979724f2679e4e6f5b824144ea89289bd6d56.
Instead of printing the leading newline in printFunction, print it when
printing a module. This ensures that `OS << *Func` starts printing
immediately on the current line, but whole modules are printed nicely.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D73505
(cherry picked from commit 9521c18438a9f09663f3dc68aa7581371c0653c9)
Added:
Modified:
llvm/lib/IR/AsmWriter.cpp
llvm/test/Feature/undefined.ll
Removed:
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
index acf0e4afef27..1f978d136049 100644
--- a/llvm/lib/IR/AsmWriter.cpp
+++ b/llvm/lib/IR/AsmWriter.cpp
@@ -2651,8 +2651,10 @@ void AssemblyWriter::printModule(const Module *M) {
printUseLists(nullptr);
// Output all of the functions.
- for (const Function &F : *M)
+ for (const Function &F : *M) {
+Out << '\n';
printFunction(&F);
+ }
assert(UseListOrders.empty() && "All use-lists should have been consumed");
// Output all attribute groups.
diff --git a/llvm/test/Feature/undefined.ll b/llvm/test/Feature/undefined.ll
index e63ce41f681b..e01ed4c0f9c4 100644
--- a/llvm/test/Feature/undefined.ll
+++ b/llvm/test/Feature/undefined.ll
@@ -1,6 +1,7 @@
; RUN: llvm-as < %s | llvm-dis > %t1.ll
; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
; RUN:
diff %t1.ll %t2.ll
+; RUN: FileCheck %s < %t1.ll
@X = global i32 undef ; [#uses=0]
@@ -15,3 +16,15 @@ define i32 @test2() {
ret i32 %X
}
+
+; Check that there is a newline between functions.
+
+; CHECK: @X = global
+; CHECK-EMPTY:
+; CHECK: declare i32 @atoi(i8*)
+; CHECK-EMPTY:
+; CHECK: define i32 @test() {
+; CHECK: {{^[}]}}
+; CHECK-EMPTY:
+; CHECK: define i32 @test2() {
+; CHECK: {{^[}]}}
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[llvm-branch-commits] [clang] release/20.x: [Clang][MicrosoftMangle] Implement mangling for ConstantMatrixType (#134930) (PR #138017)
@@ -3552,7 +3552,22 @@ void MicrosoftCXXNameMangler::mangleType(const
DependentSizedExtVectorType *T,
void MicrosoftCXXNameMangler::mangleType(const ConstantMatrixType *T,
Qualifiers quals, SourceRange Range) {
- Error(Range.getBegin(), "matrix type") << Range;
+ QualType EltTy = T->getElementType();
+ const BuiltinType *ET = EltTy->getAs();
rnk wrote:
You should also backport ccdd55c518277d749eff878ffcb5ca3de55c2a60 or manually
delete this unused variable to keep the release branch CI green.
https://github.com/llvm/llvm-project/pull/138017
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[llvm-branch-commits] [clang] release/20.x: [Clang][MicrosoftMangle] Implement mangling for ConstantMatrixType (#134930) (PR #138017)
https://github.com/rnk approved this pull request. Let's cherry pick it. https://github.com/llvm/llvm-project/pull/138017 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [Clang][MicrosoftMangle] Implement mangling for ConstantMatrixType (#134930) (PR #138017)
https://github.com/rnk edited https://github.com/llvm/llvm-project/pull/138017 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [KeyInstr][Clang] Add Clang option -g[no-]key-instructions (PR #134627)
@@ -0,0 +1,2 @@ +if not config.has_key_instructions: +config.unsupported = True rnk wrote: > (RIP your future tree conflicts). Yeah... 😢 I went looking for clang/test/DebugInfo, but that did not exist. Our existing debug info IRgen tests are split by language into CodeGen/CodeGenCXX/CodeGenObj, which is not great organization. I think clang/test/DebugInfo/KeyInstrs would be a good final home for these tests, and organizing the existing tests can be future (never?) work. https://github.com/llvm/llvm-project/pull/134627 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [KeyInstr][Clang] Add Clang option -g[no-]key-instructions (PR #134627)
@@ -4767,6 +4767,13 @@ renderDebugOptions(const ToolChain &TC, const Driver &D,
const llvm::Triple &T,
CmdArgs.push_back("-gembed-source");
}
+ if (Args.hasFlag(options::OPT_gkey_instructions,
+ options::OPT_gno_key_instructions, false)) {
+CmdArgs.push_back("-gkey-instructions");
rnk wrote:
I was going to say "we avoid setting mllvm flags in the Driver" because LLVM
option parsing handles duplicate options as an error conflict, rather than
"last one wins silently", but I found lots of prior art contradicting that
position, so I think you're in the clear:
```
$ git grep mllvm ../clang/lib/Driver/ | wc -l
100
```
https://github.com/llvm/llvm-project/pull/134627
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