[llvm-branch-commits] [flang] 49f55d1 - Revert "[Flang] Add partial support for lowering procedure pointer assignment. (#70461)"
Author: Muhammad Omair Javaid
Date: 2023-11-23T12:30:40+05:00
New Revision: 49f55d107548a340992eaec1b9767c0f8fc443cd
URL:
https://github.com/llvm/llvm-project/commit/49f55d107548a340992eaec1b9767c0f8fc443cd
DIFF:
https://github.com/llvm/llvm-project/commit/49f55d107548a340992eaec1b9767c0f8fc443cd.diff
LOG: Revert "[Flang] Add partial support for lowering procedure pointer
assignment. (#70461)"
This reverts commit e07fec10ac208c2868a24c5c0be88e45778b297e.
This change appears to have broken following buildbots:
https://lab.llvm.org/buildbot/#/builders/176
https://lab.llvm.org/buildbot/#/builders/179
https://lab.llvm.org/buildbot/#/builders/184
https://lab.llvm.org/buildbot/#/builders/197
https://lab.llvm.org/buildbot/#/builders/198
All bots fails in testsuite where following tests seems broken:
(eg: https://lab.llvm.org/buildbot/#/builders/176/builds/7131)
test-suite::gfortran-regression-compile-regression__proc_ptr_46_f90.test
test-suite::gfortran-regression-compile-regression__proc_ptr_37_f90.test
Added:
Modified:
flang/include/flang/Lower/BoxAnalyzer.h
flang/include/flang/Lower/CallInterface.h
flang/include/flang/Lower/ConvertProcedureDesignator.h
flang/include/flang/Optimizer/Builder/FIRBuilder.h
flang/include/flang/Optimizer/Builder/HLFIRTools.h
flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h
flang/lib/Lower/Bridge.cpp
flang/lib/Lower/CallInterface.cpp
flang/lib/Lower/ConvertCall.cpp
flang/lib/Lower/ConvertExpr.cpp
flang/lib/Lower/ConvertExprToHLFIR.cpp
flang/lib/Lower/ConvertProcedureDesignator.cpp
flang/lib/Lower/ConvertType.cpp
flang/lib/Lower/ConvertVariable.cpp
flang/lib/Optimizer/Builder/FIRBuilder.cpp
flang/lib/Optimizer/Builder/HLFIRTools.cpp
Removed:
flang/test/Lower/HLFIR/procedure-pointer.f90
diff --git a/flang/include/flang/Lower/BoxAnalyzer.h
b/flang/include/flang/Lower/BoxAnalyzer.h
index 3b8e2455ff273be..52cded8b219d835 100644
--- a/flang/include/flang/Lower/BoxAnalyzer.h
+++ b/flang/include/flang/Lower/BoxAnalyzer.h
@@ -382,8 +382,6 @@ class BoxAnalyzer : public
fir::details::matcher {
/// Run the analysis on `sym`.
void analyze(const Fortran::semantics::Symbol &sym) {
-if (Fortran::semantics::IsProcedurePointer(sym))
- return;
if (symIsArray(sym)) {
bool isConstant = !isAssumedSize(sym);
llvm::SmallVector lbounds;
diff --git a/flang/include/flang/Lower/CallInterface.h
b/flang/include/flang/Lower/CallInterface.h
index c7dca4f8f1348e0..579bdcfd8988792 100644
--- a/flang/include/flang/Lower/CallInterface.h
+++ b/flang/include/flang/Lower/CallInterface.h
@@ -111,8 +111,7 @@ class CallInterface {
CharBoxValueAttribute, // BoxChar with VALUE
// Passing a character procedure as a
// tuple.
-CharProcTuple,
-BoxProcRef
+CharProcTuple
};
/// Different properties of an entity that can be passed/returned.
/// One-to-One mapping with PassEntityBy but for
@@ -125,8 +124,7 @@ class CallInterface {
CharProcTuple,
Box,
MutableBox,
-Value,
-BoxProcRef
+Value
};
using FortranEntity = typename PassedEntityTypes::FortranEntity;
diff --git a/flang/include/flang/Lower/ConvertProcedureDesignator.h
b/flang/include/flang/Lower/ConvertProcedureDesignator.h
index ae772c52e425bc1..86a757a9aadf4f4 100644
--- a/flang/include/flang/Lower/ConvertProcedureDesignator.h
+++ b/flang/include/flang/Lower/ConvertProcedureDesignator.h
@@ -19,8 +19,6 @@
namespace mlir {
class Location;
-class Value;
-class Type;
}
namespace fir {
class ExtendedValue;
@@ -31,9 +29,6 @@ class EntityWithAttributes;
namespace Fortran::evaluate {
struct ProcedureDesignator;
}
-namespace Fortran::semantics {
-class Symbol;
-}
namespace Fortran::lower {
class AbstractConverter;
@@ -55,10 +50,5 @@ hlfir::EntityWithAttributes
convertProcedureDesignatorToHLFIR(
const Fortran::evaluate::ProcedureDesignator &proc,
Fortran::lower::SymMap &symMap, Fortran::lower::StatementContext &stmtCtx);
-/// Generate initialization for procedure pointer to procedure target.
-mlir::Value
-convertProcedureDesignatorInitialTarget(Fortran::lower::AbstractConverter &,
-mlir::Location,
-const Fortran::semantics::Symbol &sym);
} // namespace Fortran::lower
#endif // FORTRAN_LOWER_CONVERT_PROCEDURE_DESIGNATOR_H
diff --git a/flang/include/flang/Optimizer/Builder/FIRBuilder.h
b/flang/include/flang/Optimizer/Builder/FIRBuilder.h
index b5b2c99810b15bb..0b36186d68a4614 100644
--- a/flang/include/flang/Optimizer/Builder/FIRBuilder.h
+++ b/flang/include/flang/Optimizer/Builder/FIRBuilder.h
@@ -677,10 +677,6 @@ mlir::Value genCPtrOrCFunptrValue(fir::FirOpBuilder
&builder,
/// to keep all the lower bound and explicit parameter information.
fir::BoxValue createBoxValue(fir::FirOpBuilder &b
[llvm-branch-commits] [lldb] b45020c - [LLDB] Remove leftovers and typos from RegisterInfos_arm64_sve.h
Author: Muhammad Omair Javaid
Date: 2021-01-25T20:48:15+05:00
New Revision: b45020cf63f6f3a1de0f8d2b8be3c527f6cbdfd5
URL:
https://github.com/llvm/llvm-project/commit/b45020cf63f6f3a1de0f8d2b8be3c527f6cbdfd5
DIFF:
https://github.com/llvm/llvm-project/commit/b45020cf63f6f3a1de0f8d2b8be3c527f6cbdfd5.diff
LOG: [LLDB] Remove leftovers and typos from RegisterInfos_arm64_sve.h
This patch removes a couple of left-overs and a typo from
RegisterInfos_arm64_sve.h and RegisterInfoPOSIX_arm64.h.
Added:
Modified:
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
Removed:
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
index 1cbed5acb41c..2929f2009dd9 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -85,7 +85,7 @@ class RegisterInfoPOSIX_arm64
size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
- uint32_t ConfigureVectorRegisterInfos(uint32_t mode);
+ uint32_t ConfigureVectorRegisterInfos(uint32_t sve_vq);
bool VectorSizeIsValid(uint32_t vq) {
if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax)
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
index ea43ef8fe457..9551db7e8ebf 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
@@ -9,9 +9,6 @@
#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT
enum {
- sve_fpsr = fpu_fpsr,
- sve_fpcr = fpu_fpcr,
-
sve_vg = exc_far,
sve_z0,
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[llvm-branch-commits] [lldb] 2fd4d92 - [LLDB] Define AUXV_AT_HWCAP2 in AuxVector.h
Author: Muhammad Omair Javaid
Date: 2021-01-25T20:48:16+05:00
New Revision: 2fd4d923a826c9563d587e1dafefe41b461ef3b8
URL:
https://github.com/llvm/llvm-project/commit/2fd4d923a826c9563d587e1dafefe41b461ef3b8
DIFF:
https://github.com/llvm/llvm-project/commit/2fd4d923a826c9563d587e1dafefe41b461ef3b8.diff
LOG: [LLDB] Define AUXV_AT_HWCAP2 in AuxVector.h
This patch defines AUXV_AT_HWCAP2 for accessing Aux extensions.
Added:
Modified:
lldb/source/Plugins/Process/Utility/AuxVector.cpp
lldb/source/Plugins/Process/Utility/AuxVector.h
Removed:
diff --git a/lldb/source/Plugins/Process/Utility/AuxVector.cpp
b/lldb/source/Plugins/Process/Utility/AuxVector.cpp
index 685d9d0824f6..c4f45f759a33 100644
--- a/lldb/source/Plugins/Process/Utility/AuxVector.cpp
+++ b/lldb/source/Plugins/Process/Utility/AuxVector.cpp
@@ -82,6 +82,7 @@ const char *AuxVector::GetEntryName(EntryType type) const {
case ENTRY_NAME(AUXV_AT_SECURE); break;
case ENTRY_NAME(AUXV_AT_BASE_PLATFORM); break;
case ENTRY_NAME(AUXV_AT_RANDOM); break;
+case ENTRY_NAME(AUXV_AT_HWCAP2); break;
case ENTRY_NAME(AUXV_AT_EXECFN); break;
case ENTRY_NAME(AUXV_AT_SYSINFO);break;
case ENTRY_NAME(AUXV_AT_SYSINFO_EHDR); break;
diff --git a/lldb/source/Plugins/Process/Utility/AuxVector.h
b/lldb/source/Plugins/Process/Utility/AuxVector.h
index c8c8b1249413..07a0010e198f 100644
--- a/lldb/source/Plugins/Process/Utility/AuxVector.h
+++ b/lldb/source/Plugins/Process/Utility/AuxVector.h
@@ -50,6 +50,7 @@ class AuxVector {
AUXV_AT_SECURE = 23,///< Boolean, was exec setuid-like?
AUXV_AT_BASE_PLATFORM = 24, ///< String identifying real platforms.
AUXV_AT_RANDOM = 25,///< Address of 16 random bytes.
+AUXV_AT_HWCAP2 = 26,///< Extension of AT_HWCAP.
AUXV_AT_EXECFN = 31,///< Filename of executable.
AUXV_AT_SYSINFO = 32, ///< Pointer to the global system page used for
system
/// calls and other nice things.
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[llvm-branch-commits] [lldb] e9a3fac - [LLDB] Skip TestPlatformProcessConnect on arm/aarch64 buildbot
Author: Muhammad Omair Javaid Date: 2021-01-25T20:48:16+05:00 New Revision: e9a3fac76cf199d902a746c2b2fc308dfe0ade26 URL: https://github.com/llvm/llvm-project/commit/e9a3fac76cf199d902a746c2b2fc308dfe0ade26 DIFF: https://github.com/llvm/llvm-project/commit/e9a3fac76cf199d902a746c2b2fc308dfe0ade26.diff LOG: [LLDB] Skip TestPlatformProcessConnect on arm/aarch64 buildbot TestPlatformProcessConnect is randomly failing on LLDB Arm/AArch64 buildbot. I am disabling it temporarily untill problem is fixed. Added: Modified: lldb/test/API/tools/lldb-server/platform-process-connect/TestPlatformProcessConnect.py Removed: diff --git a/lldb/test/API/tools/lldb-server/platform-process-connect/TestPlatformProcessConnect.py b/lldb/test/API/tools/lldb-server/platform-process-connect/TestPlatformProcessConnect.py index 8ddab260b494..74b5f2e16eeb 100644 --- a/lldb/test/API/tools/lldb-server/platform-process-connect/TestPlatformProcessConnect.py +++ b/lldb/test/API/tools/lldb-server/platform-process-connect/TestPlatformProcessConnect.py @@ -12,6 +12,7 @@ class TestPlatformProcessConnect(gdbremote_testcase.GdbRemoteTestCaseBase): @expectedFailureAll(hostoslist=["windows"], triple='.*-android') @skipIfWindows # lldb-server does not terminate correctly @skipIfDarwin # lldb-server not found correctly +@skipIf(oslist=["linux"], archs=["arm", "aarch64"]) # Fails randomly def test_platform_process_connect(self): self.build() ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 9413df3 - [llvm][Release notes] Add AArch64 SVE, PAC and LLDB prebuilt binary
Author: Muhammad Omair Javaid Date: 2021-08-03T20:20:07+05:00 New Revision: 9413df3891f43eb25a9aeb3483a3157e4eeb803a URL: https://github.com/llvm/llvm-project/commit/9413df3891f43eb25a9aeb3483a3157e4eeb803a DIFF: https://github.com/llvm/llvm-project/commit/9413df3891f43eb25a9aeb3483a3157e4eeb803a.diff LOG: [llvm][Release notes] Add AArch64 SVE, PAC and LLDB prebuilt binary This patch updates LLVM release notes to add a announcement about AArch64 SVE, PAC and LLDB prebuilt binary. Added: Modified: llvm/docs/ReleaseNotes.rst Removed: diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 73c0450485d0..9f0befb33249 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -243,6 +243,12 @@ Changes to the LLVM tools Changes to LLDB - +* LLDB executable is now included in pre-built LLVM binaries. + +* LLDB now includes full featured support for AArch64 SVE register access. + +* LLDB now supports AArch64 Pointer Authentication, allowing stack unwind with signed return address. + * LLDB now supports debugging programs on AArch64 Linux that use memory tagging (MTE). * Added ``memory tag read`` and ``memory tag write`` commands. * The ``memory region`` command will note when a region has memory tagging enabled. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] f1342c7 - [LLDB] AArch64 SVE restore SVE registers after expression
Author: Muhammad Omair Javaid
Date: 2021-09-12T04:36:04+05:00
New Revision: f1342c749ac0511f0940f0bb98eb6b523e8214bb
URL:
https://github.com/llvm/llvm-project/commit/f1342c749ac0511f0940f0bb98eb6b523e8214bb
DIFF:
https://github.com/llvm/llvm-project/commit/f1342c749ac0511f0940f0bb98eb6b523e8214bb.diff
LOG: [LLDB] AArch64 SVE restore SVE registers after expression
This patch fixes register save/restore on expression call to also include SVE
registers.
This will fix expression calls like:
re re p1
p
re re p1
In above example register P1 should remain the same before and after the
expression evaluation.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D108739
Added:
Modified:
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/main.c
Removed:
diff --git
a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
index 34a520edb6937..23693e4484a7d 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -46,8 +46,6 @@
#define HWCAP_PACA (1 << 30)
#define HWCAP2_MTE (1 << 18)
-#define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize())
-
using namespace lldb;
using namespace lldb_private;
using namespace lldb_private::process_linux;
@@ -452,45 +450,80 @@ Status NativeRegisterContextLinux_arm64::WriteRegister(
Status NativeRegisterContextLinux_arm64::ReadAllRegisterValues(
lldb::DataBufferSP &data_sp) {
- Status error;
+ // AArch64 register data must contain GPRs, either FPR or SVE registers
+ // and optional MTE register. Pointer Authentication (PAC) registers are
+ // read-only and will be skiped.
- data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
+ // In order to create register data checkpoint we first read all register
+ // values if not done already and calculate total size of register set data.
+ // We store all register values in data_sp by copying full PTrace data that
+ // corresponds to register sets enabled by current register context.
+ Status error;
+ uint32_t reg_data_byte_size = GetGPRBufferSize();
error = ReadGPR();
if (error.Fail())
return error;
- error = ReadFPR();
+ // If SVE is enabled we need not copy FPR separately.
+ if (GetRegisterInfo().IsSVEEnabled()) {
+reg_data_byte_size += GetSVEBufferSize();
+error = ReadAllSVE();
+ } else {
+reg_data_byte_size += GetFPRSize();
+error = ReadFPR();
+ }
if (error.Fail())
return error;
+ if (GetRegisterInfo().IsMTEEnabled()) {
+reg_data_byte_size += GetMTEControlSize();
+error = ReadMTEControl();
+if (error.Fail())
+ return error;
+ }
+
+ data_sp.reset(new DataBufferHeap(reg_data_byte_size, 0));
uint8_t *dst = data_sp->GetBytes();
- ::memcpy(dst, GetGPRBuffer(), GetGPRSize());
- dst += GetGPRSize();
- ::memcpy(dst, GetFPRBuffer(), GetFPRSize());
+
+ ::memcpy(dst, GetGPRBuffer(), GetGPRBufferSize());
+ dst += GetGPRBufferSize();
+
+ if (GetRegisterInfo().IsSVEEnabled()) {
+::memcpy(dst, GetSVEBuffer(), GetSVEBufferSize());
+dst += GetSVEBufferSize();
+ } else {
+::memcpy(dst, GetFPRBuffer(), GetFPRSize());
+dst += GetFPRSize();
+ }
+
+ if (GetRegisterInfo().IsMTEEnabled())
+::memcpy(dst, GetMTEControl(), GetMTEControlSize());
return error;
}
Status NativeRegisterContextLinux_arm64::WriteAllRegisterValues(
const lldb::DataBufferSP &data_sp) {
- Status error;
+ // AArch64 register data must contain GPRs, either FPR or SVE registers
+ // and optional MTE register. Pointer Authentication (PAC) registers are
+ // read-only and will be skiped.
+
+ // We store all register values in data_sp by copying full PTrace data that
+ // corresponds to register sets enabled by current register context. In order
+ // to restore from register data checkpoint we will first restore GPRs, based
+ // on size of remaining register data either SVE or FPRs should be restored
+ // next. SVE is not enabled if we have register data size less than or equal
+ // to size of GPR + FPR + MTE.
+ Status error;
if (!data_sp) {
error.SetErrorStringWithFormat(
-"NativeRegisterContextLinux_x86_64::%s invalid data_sp provided",
+"NativeRegisterContextLinux_arm64::%s invalid data_sp provided",
__FUNCTION__);
return error;
}
- if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) {
-error.SetErrorStringWith
[llvm-branch-commits] [clang] 0024f66 - [clang-cl] Bump default -fms-compatibility-version to 19.20
Author: Muhammad Omair Javaid
Date: 2022-02-11T09:23:05+05:00
New Revision: 0024f665446068af7dc24162f432c89f4e91b2a7
URL:
https://github.com/llvm/llvm-project/commit/0024f665446068af7dc24162f432c89f4e91b2a7
DIFF:
https://github.com/llvm/llvm-project/commit/0024f665446068af7dc24162f432c89f4e91b2a7.diff
LOG: [clang-cl] Bump default -fms-compatibility-version to 19.20
clang-cl MSVC required version is 19.20 now. Update the default
-fms-compatibility-version to 19.20.
Differential Revision: https://reviews.llvm.org/D114639
Added:
Modified:
clang/lib/Driver/ToolChains/MSVC.cpp
clang/test/Driver/cl-options.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/MSVC.cpp
b/clang/lib/Driver/ToolChains/MSVC.cpp
index 18cef288f018a..9f4751167ac12 100644
--- a/clang/lib/Driver/ToolChains/MSVC.cpp
+++ b/clang/lib/Driver/ToolChains/MSVC.cpp
@@ -1393,8 +1393,8 @@ VersionTuple MSVCToolChain::computeMSVCVersion(const
Driver *D,
if (MSVT.empty() &&
Args.hasFlag(options::OPT_fms_extensions, options::OPT_fno_ms_extensions,
IsWindowsMSVC)) {
-// -fms-compatibility-version=19.14 is default, aka 2017, 15.7
-MSVT = VersionTuple(19, 14);
+// -fms-compatibility-version=19.20 is default, aka 2019, 16.x
+MSVT = VersionTuple(19, 20);
}
return MSVT;
}
diff --git a/clang/test/Driver/cl-options.c b/clang/test/Driver/cl-options.c
index 733e733de738e..8d240e6e6e5c6 100644
--- a/clang/test/Driver/cl-options.c
+++ b/clang/test/Driver/cl-options.c
@@ -757,7 +757,7 @@
// Validate that the default triple is used when run an empty tools dir is
specified
// RUN: %clang_cl -vctoolsdir "" -### -- %s 2>&1 | FileCheck %s --check-prefix
VCTOOLSDIR
-// VCTOOLSDIR: "-triple" "{{[a-zA-Z0-9_-]*}}-pc-windows-msvc19.14.0"
+// VCTOOLSDIR: "-triple" "{{[a-zA-Z0-9_-]*}}-pc-windows-msvc19.20.0"
// Validate that built-in include paths are based on the supplied path
// RUN: %clang_cl --target=aarch64-pc-windows-msvc -vctoolsdir "/fake"
-winsdkdir "/foo" -winsdkversion 10.0.12345.0 -### -- %s 2>&1 | FileCheck %s
--check-prefix FAKEDIR
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[llvm-branch-commits] [llvm] 4c33252 - Set LLVM_FORCE_USE_OLD_TOOLCHAIN to disable VS2019 checks
Author: Muhammad Omair Javaid Date: 2022-02-11T09:23:05+05:00 New Revision: 4c33252b7d9ad1b52c7faa66fafeb816ab53f964 URL: https://github.com/llvm/llvm-project/commit/4c33252b7d9ad1b52c7faa66fafeb816ab53f964 DIFF: https://github.com/llvm/llvm-project/commit/4c33252b7d9ad1b52c7faa66fafeb816ab53f964.diff LOG: Set LLVM_FORCE_USE_OLD_TOOLCHAIN to disable VS2019 checks VS2019 version 1920 in now the default and get tested in llvm/include/llvm/Support/Compiler.h. This patch propagates LLVM_FORCE_USE_OLD_TOOLCHAIN macro to disable testing for VS2019. Differential Revision: https://reviews.llvm.org/D114639 Added: Modified: llvm/include/llvm/Config/llvm-config.h.cmake llvm/include/llvm/Support/Compiler.h Removed: diff --git a/llvm/include/llvm/Config/llvm-config.h.cmake b/llvm/include/llvm/Config/llvm-config.h.cmake index 839a1c7c1984f..e8a8c20c7c7ad 100644 --- a/llvm/include/llvm/Config/llvm-config.h.cmake +++ b/llvm/include/llvm/Config/llvm-config.h.cmake @@ -109,4 +109,7 @@ /* Define if building LLVM with BUILD_SHARED_LIBS */ #cmakedefine LLVM_BUILD_SHARED_LIBS +/* Define if building LLVM with LLVM_FORCE_USE_OLD_TOOLCHAIN_LIBS */ +#cmakedefine LLVM_FORCE_USE_OLD_TOOLCHAIN $(LLVM_FORCE_USE_OLD_TOOLCHAIN) + #endif diff --git a/llvm/include/llvm/Support/Compiler.h b/llvm/include/llvm/Support/Compiler.h index f3317049524f3..80b2dfaec4273 100644 --- a/llvm/include/llvm/Support/Compiler.h +++ b/llvm/include/llvm/Support/Compiler.h @@ -90,9 +90,11 @@ #define LLVM_MSC_PREREQ(version) (_MSC_VER >= (version)) // We require at least VS 2019. +#if !defined(LLVM_FORCE_USE_OLD_TOOLCHAIN) #if !LLVM_MSC_PREREQ(1920) #error LLVM requires at least VS 2019. #endif +#endif #else #define LLVM_MSC_PREREQ(version) 0 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] 4fd7766 - [LLDB] Add per-thread register infos shared pointer in gdb-remote
Author: Muhammad Omair Javaid
Date: 2021-01-15T16:11:17+05:00
New Revision: 4fd77668b2cc215f0605fe20bb989b90b29f4346
URL:
https://github.com/llvm/llvm-project/commit/4fd77668b2cc215f0605fe20bb989b90b29f4346
DIFF:
https://github.com/llvm/llvm-project/commit/4fd77668b2cc215f0605fe20bb989b90b29f4346.diff
LOG: [LLDB] Add per-thread register infos shared pointer in gdb-remote
In gdb-remote process we have register infos defind as a refernce object of
GDBRemoteDynamicRegisterInfo class. In past register infos have remained
constant througout the life time of a process.
This has changed after AArch64 SVE support where register infos will have
per-thread configuration. SVE registers will have per-thread size and can
be updated while running. This patch aims to build up for that support by
changing GDBRemoteDynamicRegisterInfo reference to a shared pointer deinfed
per-thread.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D82857
Added:
Modified:
lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.h
lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
lldb/source/Plugins/Process/gdb-remote/ThreadGDBRemote.cpp
lldb/source/Plugins/Process/gdb-remote/ThreadGDBRemote.h
Removed:
diff --git a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
index 71e9b5ea4b2a..411db05da462 100644
--- a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
+++ b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
@@ -650,6 +650,8 @@ void DynamicRegisterInfo::Finalize(const ArchSpec &arch) {
}
}
+bool DynamicRegisterInfo::IsReconfigurable() { return m_is_reconfigurable; }
+
size_t DynamicRegisterInfo::GetNumRegisters() const { return m_regs.size(); }
size_t DynamicRegisterInfo::GetNumRegisterSets() const { return m_sets.size();
}
diff --git a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.h
b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.h
index d5e6f90832bf..0938b472c4ce 100644
--- a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.h
+++ b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.h
@@ -17,6 +17,10 @@
#include "lldb/lldb-private.h"
class DynamicRegisterInfo {
+protected:
+ DynamicRegisterInfo(DynamicRegisterInfo &) = default;
+ DynamicRegisterInfo &operator=(DynamicRegisterInfo &) = default;
+
public:
DynamicRegisterInfo() = default;
@@ -25,9 +29,6 @@ class DynamicRegisterInfo {
virtual ~DynamicRegisterInfo() = default;
- DynamicRegisterInfo(DynamicRegisterInfo &) = delete;
- void operator=(DynamicRegisterInfo &) = delete;
-
DynamicRegisterInfo(DynamicRegisterInfo &&info);
DynamicRegisterInfo &operator=(DynamicRegisterInfo &&info);
@@ -63,6 +64,8 @@ class DynamicRegisterInfo {
void Clear();
+ bool IsReconfigurable();
+
protected:
// Classes that inherit from DynamicRegisterInfo can see and modify these
typedef std::vector reg_collection;
@@ -89,5 +92,6 @@ class DynamicRegisterInfo {
size_t m_reg_data_byte_size = 0u; // The number of bytes required to store
// all registers
bool m_finalized = false;
+ bool m_is_reconfigurable = false;
};
#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_DYNAMICREGISTERINFO_H
diff --git
a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
index 1f31b45d0fa9..19bcac5dc4b7 100644
--- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
+++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
@@ -31,19 +31,20 @@ using namespace lldb_private::process_gdb_remote;
// GDBRemoteRegisterContext constructor
GDBRemoteRegisterContext::GDBRemoteRegisterContext(
ThreadGDBRemote &thread, uint32_t concrete_frame_idx,
-GDBRemoteDynamicRegisterInfo ®_info, bool read_all_at_once,
+GDBRemoteDynamicRegisterInfoSP reg_info_sp, bool read_all_at_once,
bool write_all_at_once)
-: RegisterContext(thread, concrete_frame_idx), m_reg_info(reg_info),
- m_reg_valid(), m_reg_data(), m_read_all_at_once(read_all_at_once),
+: RegisterContext(thread, concrete_frame_idx),
+ m_reg_info_sp(std::move(reg_info_sp)), m_reg_valid(), m_reg_data(),
+ m_read_all_at_once(read_all_at_once),
m_write_all_at_once(write_all_at_once) {
// Resize our vector of bools to contain one bool for every register. We will
// use these boolean values to know when a register value is valid in
// m_reg_data.
- m_reg_valid.resize(reg_info.GetNumRegister
[llvm-branch-commits] [lldb] b9993fc - DynamicRegisterInfo calculate offsets in separate function
Author: Muhammad Omair Javaid
Date: 2021-01-15T16:21:18+05:00
New Revision: b9993fcbf53aa28ca2e7696a1855affeb558b51c
URL:
https://github.com/llvm/llvm-project/commit/b9993fcbf53aa28ca2e7696a1855affeb558b51c
DIFF:
https://github.com/llvm/llvm-project/commit/b9993fcbf53aa28ca2e7696a1855affeb558b51c.diff
LOG: DynamicRegisterInfo calculate offsets in separate function
This patch pull offset calculation logic out of DynamicRegisterInfo::Finalize
into a separate function. We are going to call this function whenever we
update SVE register sizes.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D94008
Added:
Modified:
lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.h
Removed:
diff --git a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
index 411db05da462..8b85c7805f5b 100644
--- a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
+++ b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
@@ -442,28 +442,6 @@ void DynamicRegisterInfo::Finalize(const ArchSpec &arch) {
m_sets[set].registers = m_set_reg_nums[set].data();
}
- // We are going to create a map between remote (eRegisterKindProcessPlugin)
- // and local (eRegisterKindLLDB) register numbers. This map will give us
- // remote register numbers in increasing order for offset calculation.
- std::map remote_to_local_regnum_map;
- for (const auto ® : m_regs)
-remote_to_local_regnum_map[reg.kinds[eRegisterKindProcessPlugin]] =
-reg.kinds[eRegisterKindLLDB];
-
- // At this stage we manually calculate g/G packet offsets of all primary
- // registers, only if target XML or qRegisterInfo packet did not send
- // an offset explicitly.
- uint32_t reg_offset = 0;
- for (auto const ®num_pair : remote_to_local_regnum_map) {
-if (m_regs[regnum_pair.second].byte_offset == LLDB_INVALID_INDEX32 &&
-m_regs[regnum_pair.second].value_regs == nullptr) {
- m_regs[regnum_pair.second].byte_offset = reg_offset;
-
- reg_offset = m_regs[regnum_pair.second].byte_offset +
- m_regs[regnum_pair.second].byte_size;
-}
- }
-
// sort and unique all value registers and make sure each is terminated with
// LLDB_INVALID_REGNUM
@@ -485,24 +463,10 @@ void DynamicRegisterInfo::Finalize(const ArchSpec &arch) {
// Now update all value_regs with each register info as needed
const size_t num_regs = m_regs.size();
for (size_t i = 0; i < num_regs; ++i) {
-if (m_value_regs_map.find(i) != m_value_regs_map.end()) {
+if (m_value_regs_map.find(i) != m_value_regs_map.end())
m_regs[i].value_regs = m_value_regs_map[i].data();
- // Assign a valid offset to all pseudo registers if not assigned by stub.
- // Pseudo registers with value_regs list populated will share same offset
- // as that of their corresponding primary register in value_regs list.
- if (m_regs[i].byte_offset == LLDB_INVALID_INDEX32) {
-uint32_t value_regnum = m_regs[i].value_regs[0];
-if (value_regnum != LLDB_INVALID_INDEX32)
- m_regs[i].byte_offset =
- GetRegisterInfoAtIndex(remote_to_local_regnum_map[value_regnum])
- ->byte_offset;
- }
-} else
+else
m_regs[i].value_regs = nullptr;
-
-reg_offset = m_regs[i].byte_offset + m_regs[i].byte_size;
-if (m_reg_data_byte_size < reg_offset)
- m_reg_data_byte_size = reg_offset;
}
// Expand all invalidation dependencies
@@ -648,6 +612,55 @@ void DynamicRegisterInfo::Finalize(const ArchSpec &arch) {
break;
}
}
+
+ // At this stage call ConfigureOffsets to calculate register offsets for
+ // targets supporting dynamic offset calculation. It also calculates
+ // total byte size of register data.
+ ConfigureOffsets();
+}
+
+void DynamicRegisterInfo::ConfigureOffsets() {
+ // We are going to create a map between remote (eRegisterKindProcessPlugin)
+ // and local (eRegisterKindLLDB) register numbers. This map will give us
+ // remote register numbers in increasing order for offset calculation.
+ std::map remote_to_local_regnum_map;
+ for (const auto ® : m_regs)
+remote_to_local_regnum_map[reg.kinds[eRegisterKindProcessPlugin]] =
+reg.kinds[eRegisterKindLLDB];
+
+ // At this stage we manually calculate g/G packet offsets of all primary
+ // registers, only if target XML or qRegisterInfo packet did not send
+ // an offset explicitly.
+ uint32_t reg_offset = 0;
+ for (auto const ®num_pair : remote_to_local_regnum_map) {
+if (m_regs[regnum_pair.second].byte_offset == LLDB_INVALID_INDEX32 &&
+m_regs[regnum_pair.second].value_regs == nullptr) {
+ m_regs[regnum_pair.second].byte_offset = reg_offset;
+
+ reg_offset = m_regs[regnum_pair.second].byte_off
[llvm-branch-commits] [lldb] e448ad7 - [LLDB] Add support to resize SVE registers at run-time
Author: Muhammad Omair Javaid
Date: 2021-01-19T15:01:32+05:00
New Revision: e448ad787e16119f8db8cc6999896e678a0356ac
URL:
https://github.com/llvm/llvm-project/commit/e448ad787e16119f8db8cc6999896e678a0356ac
DIFF:
https://github.com/llvm/llvm-project/commit/e448ad787e16119f8db8cc6999896e678a0356ac.diff
LOG: [LLDB] Add support to resize SVE registers at run-time
This patch builds on previously submitted SVE patches regarding expedited
register set and per thread register infos. (D82853 D82855 and D82857)
We need to resize SVE register based on value received in expedited list.
Also we need to resize SVE registers when we write vg register using
register write vg command. The resize will result in a updated offset
for all of fpr and sve register set. This offset will be configured
in native register context by RegisterInfoInterface and will also be
be updated on client side in GDBRemoteRegisterContext.
A follow up patch will provide a API test to verify this change.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D82863
Added:
Modified:
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.h
lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
Removed:
diff --git
a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
index 6b2dd25ba44d..c34afe65d47a 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -299,14 +299,31 @@ Status NativeRegisterContextLinux_arm64::WriteRegister(
if (m_sve_state == SVEState::Disabled || m_sve_state == SVEState::Unknown)
return Status("SVE disabled or not supported");
else {
- if (GetRegisterInfo().IsSVERegVG(reg))
-return Status("SVE state change operation not supported");
-
// Target has SVE enabled, we will read and cache SVE ptrace data
error = ReadAllSVE();
if (error.Fail())
return error;
+ if (GetRegisterInfo().IsSVERegVG(reg)) {
+uint64_t vg_value = reg_value.GetAsUInt64();
+
+if (sve_vl_valid(vg_value * 8)) {
+ if (m_sve_header_is_valid && vg_value == GetSVERegVG())
+return error;
+
+ SetSVERegVG(vg_value);
+
+ error = WriteSVEHeader();
+ if (error.Success())
+ConfigureRegisterContext();
+
+ if (m_sve_header_is_valid && vg_value == GetSVERegVG())
+return error;
+}
+
+return Status("SVE vector length update failed.");
+ }
+
// If target supports SVE but currently in FPSIMD mode.
if (m_sve_state == SVEState::FPSIMD) {
// Here we will check if writing this SVE register enables
diff --git a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
index 8b85c7805f5b..5463a071503c 100644
--- a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
+++ b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
@@ -617,6 +617,17 @@ void DynamicRegisterInfo::Finalize(const ArchSpec &arch) {
// targets supporting dynamic offset calculation. It also calculates
// total byte size of register data.
ConfigureOffsets();
+
+ // Check if register info is reconfigurable
+ // AArch64 SVE register set has configurable register sizes
+ if (arch.GetTriple().isAArch64()) {
+for (const auto ® : m_regs) {
+ if (strcmp(reg.name, "vg") == 0) {
+m_is_reconfigurable = true;
+break;
+ }
+}
+ }
}
void DynamicRegisterInfo::ConfigureOffsets() {
diff --git a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.h
b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.h
index 31d040e2e137..fbf9db685b71 100644
--- a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.h
+++ b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.h
@@ -66,6 +66,9 @@ class DynamicRegisterInfo {
bool IsReconfigurable();
+ const lldb_private::RegisterInfo *
+ GetRegisterInfo(llvm::StringRef reg_name) const;
+
protected:
// Classes that inherit from DynamicRegisterInfo can see and modify these
typedef std::vector reg_collection;
@@ -77,9 +80,6 @@ class DynamicRegisterInfo {
typedef std::vector dwarf_opcode;
typedef std::map dynamic_reg_size_map;
- const lldb_private::RegisterInfo *
- GetRegisterInfo(llvm::StringRef reg_name) const;
-
void MoveFrom(DynamicRegisterInfo &&info);
void ConfigureOffsets();
diff --git
a/lldb/source/Plugins/
[llvm-branch-commits] [lldb] 4d30813 - [LLDB] Test SVE dynamic resize with multiple threads
Author: Muhammad Omair Javaid
Date: 2021-01-19T15:01:32+05:00
New Revision: 4d3081331ad854e0bff5032c818ec6414fb974c0
URL:
https://github.com/llvm/llvm-project/commit/4d3081331ad854e0bff5032c818ec6414fb974c0
DIFF:
https://github.com/llvm/llvm-project/commit/4d3081331ad854e0bff5032c818ec6414fb974c0.diff
LOG: [LLDB] Test SVE dynamic resize with multiple threads
This patch adds a new test case which depends on AArch64 SVE support and
dynamic resize capability enabled. It created two seperate threads which
have different values of sve registers and SVE vector granule at various
points during execution.
We test that LLDB is doing the size and offset updates properly for all
of the threads including the main thread and when we VG is updated using
prctl call or by 'register write vg' command the appropriate changes are
also update in register infos.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D82866
Added:
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/Makefile
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/main.c
Modified:
Removed:
diff --git
a/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/Makefile
b/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/Makefile
new file mode 100644
index ..efa5ca913f6e
--- /dev/null
+++
b/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/Makefile
@@ -0,0 +1,5 @@
+C_SOURCES := main.c
+
+CFLAGS_EXTRAS := -march=armv8-a+sve -lpthread
+
+include Makefile.rules
diff --git
a/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
b/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
new file mode 100644
index ..4d9cb686818e
--- /dev/null
+++
b/lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_dynamic_resize/TestSVEThreadedDynamic.py
@@ -0,0 +1,138 @@
+"""
+Test the AArch64 SVE registers dynamic resize with multiple threads.
+"""
+
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class RegisterCommandsTestCase(TestBase):
+
+def check_sve_registers(self, vg_test_value):
+z_reg_size = vg_test_value * 8
+p_reg_size = int(z_reg_size / 8)
+
+p_value_bytes = ['0xff', '0x55', '0x11', '0x01', '0x00']
+
+for i in range(32):
+s_reg_value = 's%i = 0x' % (i) + \
+''.join('{:02x}'.format(i + 1) for _ in range(4))
+
+d_reg_value = 'd%i = 0x' % (i) + \
+''.join('{:02x}'.format(i + 1) for _ in range(8))
+
+v_reg_value = 'v%i = 0x' % (i) + \
+''.join('{:02x}'.format(i + 1) for _ in range(16))
+
+z_reg_value = '{' + \
+' '.join('0x{:02x}'.format(i + 1)
+ for _ in range(z_reg_size)) + '}'
+
+self.expect("register read -f hex " + 's%i' %
+(i), substrs=[s_reg_value])
+
+self.expect("register read -f hex " + 'd%i' %
+(i), substrs=[d_reg_value])
+
+self.expect("register read -f hex " + 'v%i' %
+(i), substrs=[v_reg_value])
+
+self.expect("register read " + 'z%i' %
+(i), substrs=[z_reg_value])
+
+for i in range(16):
+p_regs_value = '{' + \
+' '.join(p_value_bytes[i % 5] for _ in range(p_reg_size)) + '}'
+self.expect("register read " + 'p%i' % (i), substrs=[p_regs_value])
+
+self.expect("register read ffr", substrs=[p_regs_value])
+
+mydir = TestBase.compute_mydir(__file__)
+
+@no_debug_info_test
+@skipIf(archs=no_match(["aarch64"]))
+@skipIf(oslist=no_match(['linux']))
+def test_sve_registers_dynamic_config(self):
+"""Test AArch64 SVE registers multi-threaded dynamic resize. """
+
+self.build()
+exe = self.getBuildArtifact("a.out")
+self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+if not self.isAArch64SVE():
+self.skipTest('SVE registers must be supported.')
+
+main_thread_stop_line = line_number(
+"main.c", "// Break in main thread")
+lldbutil.run_break_set_by_file_and_line(
+self, "main.c", main_thread_stop_line)
+
+thX_break_line1 = line_number("main.c", "// Thread X breakpoint 1")
+lldbutil.run_break_set_by_file_and_line(
+self, "main.c", thX_break_line1)
+
+thX_break_line2 = line_num
[llvm-branch-commits] [llvm] 1f7e8b1 - [Docs] Added note about LLDB Win/Arm64 binary release
Author: Muhammad Omair Javaid Date: 2022-02-25T17:51:46+05:00 New Revision: 1f7e8b1c6893d0c5337441ff3726c64cdf54b618 URL: https://github.com/llvm/llvm-project/commit/1f7e8b1c6893d0c5337441ff3726c64cdf54b618 DIFF: https://github.com/llvm/llvm-project/commit/1f7e8b1c6893d0c5337441ff3726c64cdf54b618.diff LOG: [Docs] Added note about LLDB Win/Arm64 binary release LLDB windows on ARM64 14.0.0 release will include LLDB binary. This patch adds a release note about it. Added: Modified: llvm/docs/ReleaseNotes.rst Removed: diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 1ac4cca463794..c6e6e445f709d 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -252,6 +252,9 @@ Changes to LLDB * Fixed continuing from breakpoints and singlestepping on Windows on ARM/ARM64. +* LLDB has been included in Windows on ARM64 binary release with Python support + disabled. + Changes to Sanitizers - ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] 9f80ab1 - Revert "[LLDB] Remove AArch64/Linux xfail decorator from TestGuiBasicDebug"
Author: Muhammad Omair Javaid Date: 2020-12-16T16:03:32+05:00 New Revision: 9f80ab1213e9f28b1b86f133fa7edf9a61c6f8fd URL: https://github.com/llvm/llvm-project/commit/9f80ab1213e9f28b1b86f133fa7edf9a61c6f8fd DIFF: https://github.com/llvm/llvm-project/commit/9f80ab1213e9f28b1b86f133fa7edf9a61c6f8fd.diff LOG: Revert "[LLDB] Remove AArch64/Linux xfail decorator from TestGuiBasicDebug" This reverts commit 3d27a99b2ed24e1951483cf13357ec188ad44bb0. Added: Modified: lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py Removed: diff --git a/lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py b/lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py index 9deb700da39c..81067bf776e3 100644 --- a/lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py +++ b/lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py @@ -15,6 +15,7 @@ class TestGuiBasicDebugCommandTest(PExpectTest): # under ASAN on a loaded machine.. @skipIfAsan @skipIfCursesSupportMissing +@expectedFailureAll(archs=["aarch64"], oslist=["linux"]) def test_gui(self): self.build() ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] 9322e57 - [LLDB] Skip TestGuiBasicDebug.py on Arm and AArch64/Linux
Author: Muhammad Omair Javaid Date: 2020-12-16T17:16:03+05:00 New Revision: 9322e571d7356a9a0e86aab954c3a916f0f07855 URL: https://github.com/llvm/llvm-project/commit/9322e571d7356a9a0e86aab954c3a916f0f07855 DIFF: https://github.com/llvm/llvm-project/commit/9322e571d7356a9a0e86aab954c3a916f0f07855.diff LOG: [LLDB] Skip TestGuiBasicDebug.py on Arm and AArch64/Linux TestGuiBasicDebug.py is intermittenly timing out on LLDB AArch64/Linux buildbot. Putting SkipIf decorator untill root cuase is identified. Added: Modified: lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py Removed: diff --git a/lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py b/lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py index 81067bf776e3..d2e223a57be9 100644 --- a/lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py +++ b/lldb/test/API/commands/gui/basicdebug/TestGuiBasicDebug.py @@ -15,7 +15,7 @@ class TestGuiBasicDebugCommandTest(PExpectTest): # under ASAN on a loaded machine.. @skipIfAsan @skipIfCursesSupportMissing -@expectedFailureAll(archs=["aarch64"], oslist=["linux"]) +@skipIf(archs=["arm", "aarch64"], oslist=["linux"]) def test_gui(self): self.build() ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] 2bd4540 - [LLDB] Fix typo in RegisterContextPOSIXProcessMonitor_arm64
Author: Muhammad Omair Javaid
Date: 2020-11-24T07:09:00+05:00
New Revision: 2bd4540f3816bb7acda31cba5351d02192d63f81
URL:
https://github.com/llvm/llvm-project/commit/2bd4540f3816bb7acda31cba5351d02192d63f81
DIFF:
https://github.com/llvm/llvm-project/commit/2bd4540f3816bb7acda31cba5351d02192d63f81.diff
LOG: [LLDB] Fix typo in RegisterContextPOSIXProcessMonitor_arm64
This patch fixes a minor typo in RegisterContextPOSIXProcessMonitor_arm64
constructor where memset target was wrongly specified as m_fpr instead of
m_gpr_arm64.
Added:
Modified:
lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp
Removed:
diff --git
a/lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp
b/lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp
index 035bf59cc9c9..39ae0b9b9e7f 100644
---
a/lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp
+++
b/lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp
@@ -25,7 +25,7 @@ RegisterContextPOSIXProcessMonitor_arm64::
lldb_private::Thread &thread,
std::unique_ptr register_info)
: RegisterContextPOSIX_arm64(thread, std::move(register_info)) {
- ::memset(&m_fpr, 0, sizeof m_gpr_arm64);
+ ::memset(&m_gpr_arm64, 0, sizeof m_gpr_arm64);
::memset(&m_fpr, 0, sizeof m_fpr);
}
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[llvm-branch-commits] [lldb] b69c09b - Support custom expedited register set in gdb-remote
Author: Muhammad Omair Javaid
Date: 2020-11-30T17:34:19+05:00
New Revision: b69c09bf43527e79a770efd9886b79e611f8fd59
URL:
https://github.com/llvm/llvm-project/commit/b69c09bf43527e79a770efd9886b79e611f8fd59
DIFF:
https://github.com/llvm/llvm-project/commit/b69c09bf43527e79a770efd9886b79e611f8fd59.diff
LOG: Support custom expedited register set in gdb-remote
This patch adds capability to introduce a custom expedited register set
in gdb remote. Currently we send register set 0 as expedited register set
but for the case of AArch64 SVE we intend to send additional information
about SVE registers size/offset configuration which can be calculated
from vg register. Therefore we will expedited Vg register in case of
AArch64 is in SVE mode to speedup register configuration calculations.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D82853
Added:
Modified:
lldb/include/lldb/Host/common/NativeRegisterContext.h
lldb/source/Host/common/NativeRegisterContext.cpp
lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
Removed:
diff --git a/lldb/include/lldb/Host/common/NativeRegisterContext.h
b/lldb/include/lldb/Host/common/NativeRegisterContext.h
index 3480d5d59217..a8c74358c718 100644
--- a/lldb/include/lldb/Host/common/NativeRegisterContext.h
+++ b/lldb/include/lldb/Host/common/NativeRegisterContext.h
@@ -16,6 +16,8 @@ namespace lldb_private {
class NativeThreadProtocol;
+enum class ExpeditedRegs { Minimal, Full };
+
class NativeRegisterContext
: public std::enable_shared_from_this {
public:
@@ -116,6 +118,9 @@ class NativeRegisterContext
virtual NativeThreadProtocol &GetThread() { return m_thread; }
+ virtual std::vector
+ GetExpeditedRegisters(ExpeditedRegs expType) const;
+
const RegisterInfo *GetRegisterInfoByName(llvm::StringRef reg_name,
uint32_t start_idx = 0);
diff --git a/lldb/source/Host/common/NativeRegisterContext.cpp
b/lldb/source/Host/common/NativeRegisterContext.cpp
index f6d16dcf2551..9bb877fff878 100644
--- a/lldb/source/Host/common/NativeRegisterContext.cpp
+++ b/lldb/source/Host/common/NativeRegisterContext.cpp
@@ -424,3 +424,32 @@
NativeRegisterContext::ConvertRegisterKindToRegisterNumber(uint32_t kind,
return LLDB_INVALID_REGNUM;
}
+
+std::vector
+NativeRegisterContext::GetExpeditedRegisters(ExpeditedRegs expType) const {
+ if (expType == ExpeditedRegs::Minimal) {
+// Expedite only a minimum set of important generic registers.
+static const uint32_t k_expedited_registers[] = {
+LLDB_REGNUM_GENERIC_PC, LLDB_REGNUM_GENERIC_SP, LLDB_REGNUM_GENERIC_FP,
+LLDB_REGNUM_GENERIC_RA};
+
+std::vector expedited_reg_nums;
+for (uint32_t gen_reg : k_expedited_registers) {
+ uint32_t reg_num =
+ ConvertRegisterKindToRegisterNumber(eRegisterKindGeneric, gen_reg);
+ if (reg_num == LLDB_INVALID_REGNUM)
+continue; // Target does not support the given register.
+ else
+expedited_reg_nums.push_back(reg_num);
+}
+
+return expedited_reg_nums;
+ }
+
+ if (GetRegisterSetCount() > 0 && expType == ExpeditedRegs::Full)
+return std::vector(GetRegisterSet(0)->registers,
+ GetRegisterSet(0)->registers +
+ GetRegisterSet(0)->num_registers);
+
+ return std::vector();
+}
diff --git
a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
index 2cf88c0d9f70..694c88c49eba 100644
---
a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+++
b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
@@ -503,7 +503,7 @@ static void WriteRegisterValueInHexFixedWidth(
}
}
-static llvm::Expected
+static llvm::Optional
GetRegistersAsJSON(NativeThreadProtocol &thread) {
Log *log(GetLogIfAnyCategoriesSet(LIBLLDB_LOG_THREAD));
@@ -512,30 +512,16 @@ GetRegistersAsJSON(NativeThreadProtocol &thread) {
json::Object register_object;
#ifdef LLDB_JTHREADSINFO_FULL_REGISTER_SET
- // Expedite all registers in the first register set (i.e. should be GPRs)
- // that are not contained in other registers.
- const RegisterSet *reg_set_p = reg_ctx_sp->GetRegisterSet(0);
- if (!reg_set_p)
-return llvm::make_error("failed to get registers",
- llvm::inconvertibleErrorCode());
- for (const uint32_t *reg_num_p = reg_set_p->registers;
- *reg_num_p != LLDB_INVALID_REGNUM; ++reg_num_p) {
-uint32_t reg_num = *reg_num_p;
+ const auto expedited_regs =
+ reg_ctx.GetExpeditedRegisters(ExpeditedRegs::Full);
#else
- // Expedite only a couple of registers until we figure out why sending
- // registers is expensive.
- static const uint32_t k_exped
[llvm-branch-commits] [lldb] 4e8aeb9 - Send SVE vg register in custom expedited registerset
Author: Muhammad Omair Javaid
Date: 2020-11-30T17:34:19+05:00
New Revision: 4e8aeb97ca41eb202c9c90a9c640a630903c769b
URL:
https://github.com/llvm/llvm-project/commit/4e8aeb97ca41eb202c9c90a9c640a630903c769b
DIFF:
https://github.com/llvm/llvm-project/commit/4e8aeb97ca41eb202c9c90a9c640a630903c769b.diff
LOG: Send SVE vg register in custom expedited registerset
This patch ovverides GetExpeditedRegisterSet for
NativeRegisterContextLinux_arm64 to send vector granule register in
expedited register set if SVE mode is selected.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D82855
Added:
Modified:
lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
lldb/test/API/tools/lldb-server/TestGdbRemoteExpeditedRegisters.py
Removed:
diff --git
a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
index ce700d9403f4..a1c420d1fa03 100644
---
a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
+++
b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
@@ -992,6 +992,13 @@ def find_generic_register_with_name(self, reg_infos,
generic_name):
return reg_info
return None
+def find_register_with_name_and_dwarf_regnum(self, reg_infos, name,
dwarf_num):
+self.assertIsNotNone(reg_infos)
+for reg_info in reg_infos:
+if (reg_info["name"] == name) and (reg_info["dwarf"] == dwarf_num):
+return reg_info
+return None
+
def decode_gdbremote_binary(self, encoded_bytes):
decoded_bytes = ""
i = 0
diff --git
a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
index 1fa87e13a0aa..49badd8ef940 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -1125,4 +1125,14 @@ void *NativeRegisterContextLinux_arm64::GetSVEBuffer() {
return m_sve_ptrace_payload.data();
}
+std::vector NativeRegisterContextLinux_arm64::GetExpeditedRegisters(
+ExpeditedRegs expType) const {
+ std::vector expedited_reg_nums =
+ NativeRegisterContext::GetExpeditedRegisters(expType);
+ if (m_sve_state == SVEState::FPSIMD || m_sve_state == SVEState::Full)
+expedited_reg_nums.push_back(GetRegisterInfo().GetRegNumSVEVG());
+
+ return expedited_reg_nums;
+}
+
#endif // defined (__arm64__) || defined (__aarch64__)
diff --git
a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
index da45f1c2d2c3..3d0656dceb62 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -44,6 +44,9 @@ class NativeRegisterContextLinux_arm64 : public
NativeRegisterContextLinux {
void InvalidateAllRegisters() override;
+ std::vector
+ GetExpeditedRegisters(ExpeditedRegs expType) const override;
+
// Hardware breakpoints/watchpoint management functions
uint32_t NumSupportedHardwareBreakpoints() override;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
index 701c88c31258..515c9f44e1e2 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -342,3 +342,5 @@ uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const {
return sve_ffr; }
uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
+
+uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
index d5eaf4cfbe9e..37f7c23b62c5 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -101,6 +101,7 @@ class RegisterInfoPOSIX_arm64
uint32_t GetRegNumSVEFFR() const;
uint32_t GetRegNumFPCR() const;
uint32_t GetRegNumFPSR() const;
+ uint32_t GetRegNumSVEVG() const;
private:
typedef std::map>
diff --git
a/lldb/test/API/tools/lldb-server/TestGdbRemoteExpeditedRegisters.py
b/lldb/test/AP
[llvm-branch-commits] [lldb] 26b8ea2 - RegisterInfoPOSIX_arm64 remove unused bytes from g/G packet
Author: Muhammad Omair Javaid
Date: 2020-12-02T03:19:39+05:00
New Revision: 26b8ea2e3782890be96612701866d8ccec616bdc
URL:
https://github.com/llvm/llvm-project/commit/26b8ea2e3782890be96612701866d8ccec616bdc
DIFF:
https://github.com/llvm/llvm-project/commit/26b8ea2e3782890be96612701866d8ccec616bdc.diff
LOG: RegisterInfoPOSIX_arm64 remove unused bytes from g/G packet
This came up while putting together our new strategy to create g/G packets
in compliance with GDB RSP protocol where register offsets are calculated in
increasing order of register numbers without any unused spacing.
RegisterInfoPOSIX_arm64::GPR size was being calculated after alignment
correction to 8 bytes which meant there was a 4 bytes unused space between
last gpr (cpsr) and first vector register V. We have put LLVM_PACKED_START
decorator on RegisterInfoPOSIX_arm64::GPR to make sure single byte
alignment is enforced. Moreover we are now doing to use arm64 user_pt_regs
struct defined in ptrace.h for accessing ptrace user registers.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D92063
Added:
Modified:
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
Removed:
diff --git
a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
index 49badd8ef940..6b2dd25ba44d 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -936,9 +936,9 @@ Status NativeRegisterContextLinux_arm64::ReadGPR() {
struct iovec ioVec;
ioVec.iov_base = GetGPRBuffer();
- ioVec.iov_len = GetGPRSize();
+ ioVec.iov_len = GetGPRBufferSize();
- error = ReadRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS);
+ error = ReadRegisterSet(&ioVec, GetGPRBufferSize(), NT_PRSTATUS);
if (error.Success())
m_gpr_is_valid = true;
@@ -953,11 +953,11 @@ Status NativeRegisterContextLinux_arm64::WriteGPR() {
struct iovec ioVec;
ioVec.iov_base = GetGPRBuffer();
- ioVec.iov_len = GetGPRSize();
+ ioVec.iov_len = GetGPRBufferSize();
m_gpr_is_valid = false;
- return WriteRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS);
+ return WriteRegisterSet(&ioVec, GetGPRBufferSize(), NT_PRSTATUS);
}
Status NativeRegisterContextLinux_arm64::ReadFPR() {
diff --git
a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
index 3d0656dceb62..9ba8c7699a56 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -95,6 +95,10 @@ class NativeRegisterContextLinux_arm64 : public
NativeRegisterContextLinux {
void *GetGPRBuffer() override { return &m_gpr_arm64; }
+ // GetGPRBufferSize returns sizeof arm64 GPR ptrace buffer, it is
diff erent
+ // from GetGPRSize which returns sizeof RegisterInfoPOSIX_arm64::GPR.
+ size_t GetGPRBufferSize() { return sizeof(m_gpr_arm64); }
+
void *GetFPRBuffer() override { return &m_fpr; }
size_t GetFPRSize() override { return sizeof(m_fpr); }
@@ -106,7 +110,7 @@ class NativeRegisterContextLinux_arm64 : public
NativeRegisterContextLinux {
bool m_sve_header_is_valid;
- RegisterInfoPOSIX_arm64::GPR m_gpr_arm64; // 64-bit general purpose
registers.
+ struct user_pt_regs m_gpr_arm64; // 64-bit general purpose registers.
RegisterInfoPOSIX_arm64::FPU
m_fpr; // floating-point registers including extended register sets.
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
index 37f7c23b62c5..1cbed5acb41c 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -29,6 +29,7 @@ class RegisterInfoPOSIX_arm64
};
// based on RegisterContextDarwin_arm64.h
+ LLVM_PACKED_START
struct GPR {
uint64_t x[29]; // x0-x28
uint64_t fp;// x29
@@ -37,6 +38,7 @@ class RegisterInfoPOSIX_arm64
uint64_t pc;// pc
uint32_t cpsr; // cpsr
};
+ LLVM_PACKED_END
// based on RegisterContextDarwin_arm64.h
struct VReg {
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[llvm-branch-commits] [lldb] 78cb456 - Make offset field optional in RegisterInfo packet for Arm64
Author: Muhammad Omair Javaid
Date: 2020-12-02T03:19:43+05:00
New Revision: 78cb4562faa7315fff030593bc6bca4dc033f803
URL:
https://github.com/llvm/llvm-project/commit/78cb4562faa7315fff030593bc6bca4dc033f803
DIFF:
https://github.com/llvm/llvm-project/commit/78cb4562faa7315fff030593bc6bca4dc033f803.diff
LOG: Make offset field optional in RegisterInfo packet for Arm64
This patch carries forward our aim to remove offset field from qRegisterInfo
packets and XML register description. I have created a new function which
returns if offset fields are dynamic meaning client can calculate offset on
its own based on register number sequence and register size. For now this
function only returns true for NativeRegisterContextLinux_arm64 but we can
test this for other architectures and make it standard later.
As a consequence we do not send offset field from lldb-server (arm64 for now)
while other stubs dont have an offset field so it wont effect them for now.
On the client side we have replaced previous offset calculation algorithm
with a new scheme, where we sort all primary registers in increasing
order of remote regnum and then calculate offset incrementally.
This committ also includes a test to verify all of above functionality
on Arm64.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D91241
Added:
lldb/test/API/functionalities/gdb_remote_client/TestAArch64XMLRegOffsets.py
Modified:
lldb/include/lldb/Host/common/NativeRegisterContext.h
lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
lldb/test/API/tools/lldb-server/registers-target-xml-reading/TestGdbRemoteTargetXmlPacket.py
lldb/unittests/tools/lldb-server/tests/MessageObjects.cpp
lldb/unittests/tools/lldb-server/tests/TestClient.cpp
Removed:
diff --git a/lldb/include/lldb/Host/common/NativeRegisterContext.h
b/lldb/include/lldb/Host/common/NativeRegisterContext.h
index a8c74358c718..f7568fe31b80 100644
--- a/lldb/include/lldb/Host/common/NativeRegisterContext.h
+++ b/lldb/include/lldb/Host/common/NativeRegisterContext.h
@@ -121,6 +121,8 @@ class NativeRegisterContext
virtual std::vector
GetExpeditedRegisters(ExpeditedRegs expType) const;
+ virtual bool RegisterOffsetIsDynamic() const { return false; }
+
const RegisterInfo *GetRegisterInfoByName(llvm::StringRef reg_name,
uint32_t start_idx = 0);
diff --git
a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
index a1c420d1fa03..2f278289988c 100644
---
a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
+++
b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
@@ -664,7 +664,10 @@ def assert_valid_reg_info(self, reg_info):
# Check the bare-minimum expected set of register info keys.
self.assertTrue("name" in reg_info)
self.assertTrue("bitsize" in reg_info)
-self.assertTrue("offset" in reg_info)
+
+if not self.getArchitecture() == 'aarch64':
+self.assertTrue("offset" in reg_info)
+
self.assertTrue("encoding" in reg_info)
self.assertTrue("format" in reg_info)
diff --git
a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
index 9ba8c7699a56..344eae247e91 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -47,6 +47,8 @@ class NativeRegisterContextLinux_arm64 : public
NativeRegisterContextLinux {
std::vector
GetExpeditedRegisters(ExpeditedRegs expType) const override;
+ bool RegisterOffsetIsDynamic() const override { return true; }
+
// Hardware breakpoints/watchpoint management functions
uint32_t NumSupportedHardwareBreakpoints() override;
diff --git a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
index fd9e1923104d..71e9b5ea4b2a 100644
--- a/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
+++ b/lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
@@ -428,9 +428,6 @@ void DynamicRegisterInfo::AddRegister(RegisterInfo
®_info,
assert(set < m_set_reg_nums.size());
assert(set < m_set_names.size());
m_set_reg_nums[set].push_back(reg_num);
- size_t end_reg_offset = reg_info.byte_offset + reg_info.byte_siz
[llvm-branch-commits] [lldb] fa7fabb - [LLDB] Rename duplicate TestAlignAsBaseClass.py
Author: Muhammad Omair Javaid Date: 2020-12-02T07:31:29+05:00 New Revision: fa7fabb644f8645442cbe42c78420240b6657160 URL: https://github.com/llvm/llvm-project/commit/fa7fabb644f8645442cbe42c78420240b6657160 DIFF: https://github.com/llvm/llvm-project/commit/fa7fabb644f8645442cbe42c78420240b6657160.diff LOG: [LLDB] Rename duplicate TestAlignAsBaseClass.py lldb-dotest breaks due to duplicate TestAlignAsBaseClass.py. I have renamed later version to TestAlignAsBaseClassNonTemplateParam.py. Added: lldb/test/API/lang/cpp/non-type-template-param/TestAlignAsBaseClassNonTemplateParam.py Modified: Removed: lldb/test/API/lang/cpp/non-type-template-param/TestAlignAsBaseClass.py diff --git a/lldb/test/API/lang/cpp/non-type-template-param/TestAlignAsBaseClass.py b/lldb/test/API/lang/cpp/non-type-template-param/TestAlignAsBaseClassNonTemplateParam.py similarity index 100% rename from lldb/test/API/lang/cpp/non-type-template-param/TestAlignAsBaseClass.py rename to lldb/test/API/lang/cpp/non-type-template-param/TestAlignAsBaseClassNonTemplateParam.py ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] 85a3daa - [LLDB] Fix failing test dwp-separate-debug-file.cpp
Author: Muhammad Omair Javaid Date: 2020-12-09T14:57:50+05:00 New Revision: 85a3daa107fb0340f3b74f1719a3dc6cdb1586ee URL: https://github.com/llvm/llvm-project/commit/85a3daa107fb0340f3b74f1719a3dc6cdb1586ee DIFF: https://github.com/llvm/llvm-project/commit/85a3daa107fb0340f3b74f1719a3dc6cdb1586ee.diff LOG: [LLDB] Fix failing test dwp-separate-debug-file.cpp Fix failure introduced by 843f2dbf003f2a51d0d4ab8cf40647c99ded2e93. Added: Modified: lldb/test/Shell/SymbolFile/DWARF/dwp-separate-debug-file.cpp Removed: diff --git a/lldb/test/Shell/SymbolFile/DWARF/dwp-separate-debug-file.cpp b/lldb/test/Shell/SymbolFile/DWARF/dwp-separate-debug-file.cpp index 26fd34d374a7..cda299260451 100644 --- a/lldb/test/Shell/SymbolFile/DWARF/dwp-separate-debug-file.cpp +++ b/lldb/test/Shell/SymbolFile/DWARF/dwp-separate-debug-file.cpp @@ -1,6 +1,6 @@ // REQUIRES: lld -// RUN: %clang -target x86_64-pc-linux -gsplit-dwarf -c %s -o %t.o +// RUN: %clang -target x86_64-pc-linux -gsplit-dwarf -g -c %s -o %t.o // RUN: ld.lld %t.o -o %t // RUN: llvm-dwp %t.dwo -o %t.dwp // RUN: rm %t.dwo ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] 10edd10 - [LLDB] Temporarily incrase DEFAULT_TIMEOUT on gdbremote_testcase.py
Author: Muhammad Omair Javaid
Date: 2020-12-09T18:44:21+05:00
New Revision: 10edd103483027fad1f106ae2d250136b83f1d4d
URL:
https://github.com/llvm/llvm-project/commit/10edd103483027fad1f106ae2d250136b83f1d4d
DIFF:
https://github.com/llvm/llvm-project/commit/10edd103483027fad1f106ae2d250136b83f1d4d.diff
LOG: [LLDB] Temporarily incrase DEFAULT_TIMEOUT on gdbremote_testcase.py
TestLldbGdbServer.py testcases are timing out on LLDB/AArch64 Linux
buildbot since recent changes. I am temporarily increasing
DEFAULT_TIMEOUT to 20 seconds to see impact.
Added:
Modified:
lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
Removed:
diff --git
a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
index d7bfb7fbda327..2908ca2809a9d 100644
---
a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
+++
b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
@@ -32,7 +32,7 @@ class GdbRemoteTestCaseBase(TestBase):
NO_DEBUG_INFO_TESTCASE = True
# Default time out in seconds. The timeout is increased tenfold under Asan.
-DEFAULT_TIMEOUT = 10 * (10 if ('ASAN_OPTIONS' in os.environ) else 1)
+DEFAULT_TIMEOUT = 20 * (10 if ('ASAN_OPTIONS' in os.environ) else 1)
# Default sleep time in seconds. The sleep time is doubled under Asan.
DEFAULT_SLEEP = 5 * (2 if ('ASAN_OPTIONS' in os.environ) else 1)
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[llvm-branch-commits] [lldb] 5ab44f3 - Revert "Fix lookup of symbols at the same address with no size vs. size"
Author: Muhammad Omair Javaid
Date: 2019-11-13T03:15:42+05:00
New Revision: 5ab44f3ec15f2be1e244c1b565381e0011985365
URL:
https://github.com/llvm/llvm-project/commit/5ab44f3ec15f2be1e244c1b565381e0011985365
DIFF:
https://github.com/llvm/llvm-project/commit/5ab44f3ec15f2be1e244c1b565381e0011985365.diff
LOG: Revert "Fix lookup of symbols at the same address with no size vs. size"
This reverts commit 3f594ed1686b44138bee245c708773e526643aaf.
This change has cause LLDB expression evaluation to fail on Arm Linux.
Differential Revision: https://reviews.llvm.org/D63540
(cherry picked from commit a6c40f56aed1556a80867209b6846f7eedc4dc78)
Added:
Modified:
lldb/source/Symbol/Symtab.cpp
Removed:
lldb/lit/SymbolFile/Inputs/sizeless-symbol.s
lldb/lit/SymbolFile/sizeless-symbol.test
diff --git a/lldb/lit/SymbolFile/Inputs/sizeless-symbol.s
b/lldb/lit/SymbolFile/Inputs/sizeless-symbol.s
deleted file mode 100644
index ac08dddb0e2c..
--- a/lldb/lit/SymbolFile/Inputs/sizeless-symbol.s
+++ /dev/null
@@ -1,8 +0,0 @@
-.text
-.byte 0
-sizeless:
-sizeful:
-.byte 0
-.byte 0
-sizeend:
-.size sizeful, sizeend - sizeful
diff --git a/lldb/lit/SymbolFile/sizeless-symbol.test
b/lldb/lit/SymbolFile/sizeless-symbol.test
deleted file mode 100644
index 1459d6ada8de..
--- a/lldb/lit/SymbolFile/sizeless-symbol.test
+++ /dev/null
@@ -1,14 +0,0 @@
-# Some targets do not have the .size directive.
-# RUN: %clang -target x86_64-unknown-unknown-elf %S/Inputs/sizeless-symbol.s
-c -o %t.o
-# RUN: %lldb %t.o -s %s -o quit | FileCheck %s
-
-image lookup --address 1
-# CHECK: Summary: sizeless-symbol.test.tmp.o`sizeful
-image lookup --address 2
-# CHECK: Summary: sizeless-symbol.test.tmp.o`sizeful + 1
-image dump symtab
-# CHECK: Index UserID DSX TypeFile Address/Value Load
Address Size Flags Name
-# CHECK-NEXT:--- -- --- --- --
-- -- --
--
-# CHECK-NEXT:[0] 1 Code0x0003
0x 0x sizeend
-# CHECK-NEXT:[1] 2 Code0x0001
0x0002 0x sizeful
-# CHECK-NEXT:[2] 3 Code0x0001
0x 0x sizeless
diff --git a/lldb/source/Symbol/Symtab.cpp b/lldb/source/Symbol/Symtab.cpp
index 29c390e83878..5203eba15b49 100644
--- a/lldb/source/Symbol/Symtab.cpp
+++ b/lldb/source/Symbol/Symtab.cpp
@@ -896,14 +896,8 @@ void Symtab::InitAddressIndexes() {
for (size_t i = 0; i < num_entries; i++) {
FileRangeToIndexMap::Entry *entry =
m_file_addr_to_index.GetMutableEntryAtIndex(i);
-if (entry->GetByteSize() > 0)
- continue;
-addr_t curr_base_addr = entry->GetRangeBase();
-// Symbols with non-zero size will show after zero-sized symbols on the
-// same address. So do not set size of a non-last zero-sized symbol.
-if (i == num_entries - 1 ||
-m_file_addr_to_index.GetMutableEntryAtIndex(i + 1)
-->GetRangeBase() != curr_base_addr) {
+if (entry->GetByteSize() == 0) {
+ addr_t curr_base_addr = entry->GetRangeBase();
const RangeVector::Entry *containing_section =
section_ranges.FindEntryThatContains(curr_base_addr);
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