Author: Muhammad Omair Javaid Date: 2021-01-25T20:48:15+05:00 New Revision: b45020cf63f6f3a1de0f8d2b8be3c527f6cbdfd5
URL: https://github.com/llvm/llvm-project/commit/b45020cf63f6f3a1de0f8d2b8be3c527f6cbdfd5 DIFF: https://github.com/llvm/llvm-project/commit/b45020cf63f6f3a1de0f8d2b8be3c527f6cbdfd5.diff LOG: [LLDB] Remove leftovers and typos from RegisterInfos_arm64_sve.h This patch removes a couple of left-overs and a typo from RegisterInfos_arm64_sve.h and RegisterInfoPOSIX_arm64.h. Added: Modified: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h Removed: ################################################################################ diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h index 1cbed5acb41c..2929f2009dd9 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h +++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h @@ -85,7 +85,7 @@ class RegisterInfoPOSIX_arm64 size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override; - uint32_t ConfigureVectorRegisterInfos(uint32_t mode); + uint32_t ConfigureVectorRegisterInfos(uint32_t sve_vq); bool VectorSizeIsValid(uint32_t vq) { if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax) diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h index ea43ef8fe457..9551db7e8ebf 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h +++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h @@ -9,9 +9,6 @@ #ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT enum { - sve_fpsr = fpu_fpsr, - sve_fpcr = fpu_fpcr, - sve_vg = exc_far, sve_z0, _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
