[llvm-branch-commits] [llvm] eff062e - [ReleaseNotes] Add scalable matrix extension support to AArch64 changes
Author: Cullen Rhodes Date: 2021-08-03T15:24:36Z New Revision: eff062e5206a5751c51f03f6a6dc35937d1c95c7 URL: https://github.com/llvm/llvm-project/commit/eff062e5206a5751c51f03f6a6dc35937d1c95c7 DIFF: https://github.com/llvm/llvm-project/commit/eff062e5206a5751c51f03f6a6dc35937d1c95c7.diff LOG: [ReleaseNotes] Add scalable matrix extension support to AArch64 changes Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D106853 Added: Modified: llvm/docs/ReleaseNotes.rst Removed: diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 9f0befb33249..de442580a149 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -77,7 +77,8 @@ Changes to TableGen Changes to the AArch64 Backend -- -* Introduced support for Armv9-A's Realm Management Extension. +* Introduced assembly support for Armv9-A's Realm Management Extension (RME) + and Scalable Matrix Extension (SME). Changes to the ARM Backend -- ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 3d9c51d - [SVE][NFC] Regenerate a few CodeGen tests
Author: Cullen Rhodes
Date: 2021-01-12T18:10:36Z
New Revision: 3d9c51d111d0c8480d10fc48fb621bac1d080449
URL:
https://github.com/llvm/llvm-project/commit/3d9c51d111d0c8480d10fc48fb621bac1d080449
DIFF:
https://github.com/llvm/llvm-project/commit/3d9c51d111d0c8480d10fc48fb621bac1d080449.diff
LOG: [SVE][NFC] Regenerate a few CodeGen tests
Regenerated using llvm/utils/update_llc_test_checks.py as part of
D94504, committing separately to reduce the diff for D94504.
Added:
Modified:
llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
Removed:
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
index be1c03a754fe..44d4b1d27560 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
@@ -10,18 +11,20 @@
define @ldnf1b( %pg, i8* %a) {
; CHECK-LABEL: ldnf1b:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT:ldnf1b { z0.b }, p0/z, [x0]
+; CHECK-NEXT:ret
%load = call @llvm.aarch64.sve.ldnf1.nxv16i8( %pg, i8* %a)
ret %load
}
define @ldnf1b_out_of_lower_bound( %pg,
i8* %a) {
; CHECK-LABEL: ldnf1b_out_of_lower_bound:
-; CHECK: rdvlx[[OFFSET:[0-9]+]], #-9
-; CHECK-NEXT: add x[[BASE:[0-9]+]], x0, x[[OFFSET]]
-; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x[[BASE]]]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT:rdvl x8, #-9
+; CHECK-NEXT:add x8, x0, x8
+; CHECK-NEXT:ldnf1b { z0.b }, p0/z, [x8]
+; CHECK-NEXT:ret
%base_scalable = bitcast i8* %a to *
%base = getelementptr , *
%base_scalable, i64 -9
%base_scalar = bitcast * %base to i8*
@@ -31,8 +34,9 @@ define @ldnf1b_out_of_lower_bound( %pg, i8*
define @ldnf1b_lower_bound( %pg, i8* %a) {
; CHECK-LABEL: ldnf1b_lower_bound:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0, #-8, mul vl]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT:ldnf1b { z0.b }, p0/z, [x0, #-8, mul vl]
+; CHECK-NEXT:ret
%base_scalable = bitcast i8* %a to *
%base = getelementptr , *
%base_scalable, i64 -8
%base_scalar = bitcast * %base to i8*
@@ -42,8 +46,9 @@ define @ldnf1b_lower_bound( %pg, i8* %a) {
define @ldnf1b_inbound( %pg, i8* %a) {
; CHECK-LABEL: ldnf1b_inbound:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0, #1, mul vl]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT:ldnf1b { z0.b }, p0/z, [x0, #1, mul vl]
+; CHECK-NEXT:ret
%base_scalable = bitcast i8* %a to *
%base = getelementptr , *
%base_scalable, i64 1
%base_scalar = bitcast * %base to i8*
@@ -53,8 +58,9 @@ define @ldnf1b_inbound(
%pg, i8* %a) {
define @ldnf1b_upper_bound( %pg, i8* %a) {
; CHECK-LABEL: ldnf1b_upper_bound:
-; CHECK: ldnf1b { z0.b }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT:ldnf1b { z0.b }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:ret
%base_scalable = bitcast i8* %a to *
%base = getelementptr , *
%base_scalable, i64 7
%base_scalar = bitcast * %base to i8*
@@ -64,10 +70,11 @@ define @ldnf1b_upper_bound( %pg, i8* %a) {
define @ldnf1b_out_of_upper_bound( %pg,
i8* %a) {
; CHECK-LABEL: ldnf1b_out_of_upper_bound:
-; CHECK: rdvlx[[OFFSET:[0-9]+]], #8
-; CHECK-NEXT: add x[[BASE:[0-9]+]], x0, x[[OFFSET]]
-; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x[[BASE]]]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT:rdvl x8, #8
+; CHECK-NEXT:add x8, x0, x8
+; CHECK-NEXT:ldnf1b { z0.b }, p0/z, [x8]
+; CHECK-NEXT:ret
%base_scalable = bitcast i8* %a to *
%base = getelementptr , *
%base_scalable, i64 8
%base_scalar = bitcast * %base to i8*
@@ -77,8 +84,9 @@ define @ldnf1b_out_of_upper_bound( %pg, i8*
define @ldnf1b_h( %pg, i8* %a) {
; CHECK-LABEL: ldnf1b_h:
-; CHECK: ldnf1b { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT:ldnf1b { z0.h }, p0/z, [x0]
+; CHECK-NEXT:ret
%load = call @llvm.aarch64.sve.ldnf1.nxv8i8( %pg, i8* %a)
%res = zext %load to
ret %res
@@ -86,8 +94,9 @@ define @ldnf1b_h( %pg,
i8* %a) {
define @ldnf1b_h_inbound( %pg, i8* %a) {
; CHECK-LABEL: ldnf1b_h_inbound:
-; CHECK: ldnf1b { z0.h }, p0/z, [x0, #7, mul vl]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT:ldnf1b { z0.h }, p0/z, [x0, #7, mul vl]
+; CHECK-NEXT:ret
%base_scalable = bitcast i8* %a to *
%base = getelementptr , * %base_scalable,
i64 7
%base_scalar = bitcast * %bas
[llvm-branch-commits] [llvm] ad85e39 - [SVE] Add ISel pattern for addvl
Author: Cullen Rhodes
Date: 2021-01-13T10:57:49Z
New Revision: ad85e3967067154a579f7989ce0e736f8cd56be9
URL:
https://github.com/llvm/llvm-project/commit/ad85e3967067154a579f7989ce0e736f8cd56be9
DIFF:
https://github.com/llvm/llvm-project/commit/ad85e3967067154a579f7989ce0e736f8cd56be9.diff
LOG: [SVE] Add ISel pattern for addvl
Reviewed By: cameron.mcinally
Differential Revision: https://reviews.llvm.org/D94504
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/split-vector-insert.ll
llvm/test/CodeGen/AArch64/sve-gep.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 50368199effb..cd80f3801fb2 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1648,6 +1648,9 @@ let Predicates = [HasSVE] in {
def : Pat<(vscale (sve_cntd_imm_neg i32:$imm)), (SUBXrs XZR, (CNTD_XPiI
31, $imm), 0)>;
}
+ def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
+(ADDVL_XXI GPR64:$op, $imm)>;
+
// FIXME: BigEndian requires an additional REV instruction to satisfy the
// constraint that none of the bits change when stored to memory as one
// type, and and reloaded as another type.
diff --git a/llvm/test/CodeGen/AArch64/split-vector-insert.ll
b/llvm/test/CodeGen/AArch64/split-vector-insert.ll
index 3fb86ae6b963..cc2ea86cad2e 100644
--- a/llvm/test/CodeGen/AArch64/split-vector-insert.ll
+++ b/llvm/test/CodeGen/AArch64/split-vector-insert.ll
@@ -29,27 +29,27 @@ define @test_nxv2i64_v8i64( %a, <8 x i64> %
; CHECK-NEXT:lsl x10, x10, #3
; CHECK-NEXT:st1d { z0.d }, p0, [sp]
; CHECK-NEXT:str q1, [x9, x10]
-; CHECK-NEXT:addvl x10, sp, #1
; CHECK-NEXT:ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT:mov w9, #2
; CHECK-NEXT:cmp x8, #2 // =2
; CHECK-NEXT:csel x9, x8, x9, lo
+; CHECK-NEXT:addvl x10, sp, #1
; CHECK-NEXT:lsl x9, x9, #3
; CHECK-NEXT:st1d { z0.d }, p0, [sp, #1, mul vl]
; CHECK-NEXT:str q2, [x10, x9]
-; CHECK-NEXT:addvl x10, sp, #2
; CHECK-NEXT:ld1d { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT:mov w9, #4
; CHECK-NEXT:cmp x8, #4 // =4
; CHECK-NEXT:csel x9, x8, x9, lo
+; CHECK-NEXT:addvl x10, sp, #2
; CHECK-NEXT:lsl x9, x9, #3
; CHECK-NEXT:st1d { z0.d }, p0, [sp, #2, mul vl]
; CHECK-NEXT:str q3, [x10, x9]
-; CHECK-NEXT:addvl x10, sp, #3
; CHECK-NEXT:ld1d { z0.d }, p0/z, [sp, #2, mul vl]
; CHECK-NEXT:mov w9, #6
; CHECK-NEXT:cmp x8, #6 // =6
; CHECK-NEXT:csel x8, x8, x9, lo
+; CHECK-NEXT:addvl x10, sp, #3
; CHECK-NEXT:lsl x8, x8, #3
; CHECK-NEXT:st1d { z0.d }, p0, [sp, #3, mul vl]
; CHECK-NEXT:str q4, [x10, x8]
@@ -82,27 +82,27 @@ define @test_nxv2f64_v8f64( %a, <8 x
; CHECK-NEXT:lsl x10, x10, #3
; CHECK-NEXT:st1d { z0.d }, p0, [sp]
; CHECK-NEXT:str q1, [x9, x10]
-; CHECK-NEXT:addvl x10, sp, #1
; CHECK-NEXT:ld1d { z0.d }, p0/z, [sp]
; CHECK-NEXT:mov w9, #2
; CHECK-NEXT:cmp x8, #2 // =2
; CHECK-NEXT:csel x9, x8, x9, lo
+; CHECK-NEXT:addvl x10, sp, #1
; CHECK-NEXT:lsl x9, x9, #3
; CHECK-NEXT:st1d { z0.d }, p0, [sp, #1, mul vl]
; CHECK-NEXT:str q2, [x10, x9]
-; CHECK-NEXT:addvl x10, sp, #2
; CHECK-NEXT:ld1d { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT:mov w9, #4
; CHECK-NEXT:cmp x8, #4 // =4
; CHECK-NEXT:csel x9, x8, x9, lo
+; CHECK-NEXT:addvl x10, sp, #2
; CHECK-NEXT:lsl x9, x9, #3
; CHECK-NEXT:st1d { z0.d }, p0, [sp, #2, mul vl]
; CHECK-NEXT:str q3, [x10, x9]
-; CHECK-NEXT:addvl x10, sp, #3
; CHECK-NEXT:ld1d { z0.d }, p0/z, [sp, #2, mul vl]
; CHECK-NEXT:mov w9, #6
; CHECK-NEXT:cmp x8, #6 // =6
; CHECK-NEXT:csel x8, x8, x9, lo
+; CHECK-NEXT:addvl x10, sp, #3
; CHECK-NEXT:lsl x8, x8, #3
; CHECK-NEXT:st1d { z0.d }, p0, [sp, #3, mul vl]
; CHECK-NEXT:str q4, [x10, x8]
diff --git a/llvm/test/CodeGen/AArch64/sve-gep.ll
b/llvm/test/CodeGen/AArch64/sve-gep.ll
index ffde9289a55d..7e6e8efbb790 100644
--- a/llvm/test/CodeGen/AArch64/sve-gep.ll
+++ b/llvm/test/CodeGen/AArch64/sve-gep.ll
@@ -8,8 +8,7 @@
define * @scalar_of_scalable_1(* %base) {
; CHECK-LABEL: scalar_of_scalable_1:
; CHECK: // %bb.0:
-; CHECK-NEXT:rdvl x8, #4
-; CHECK-NEXT:add x0, x0, x8
+; CHECK-NEXT:addvl x0, x0, #4
; CHECK-NEXT:ret
%d = getelementptr , * %base, i64 4
ret * %d
diff --git a/
[llvm-branch-commits] [llvm] 1e7efd3 - [LV] Legalize scalable VF hints
Author: Cullen Rhodes
Date: 2021-01-08T10:49:44Z
New Revision: 1e7efd397ac259429df9f212c9ec16bec8ff2533
URL:
https://github.com/llvm/llvm-project/commit/1e7efd397ac259429df9f212c9ec16bec8ff2533
DIFF:
https://github.com/llvm/llvm-project/commit/1e7efd397ac259429df9f212c9ec16bec8ff2533.diff
LOG: [LV] Legalize scalable VF hints
In the following loop:
void foo(int *a, int *b, int N) {
for (int i=0; i as the vector type in vectorization.
Extending this to scalable vectorization, a VF of (4, scalable) implies
a vector type of . To determine if this is legal
vscale must be taken into account. For this example, unless
max(vscale)=1, it's unsafe to vectorize.
For SVE, the number of bits in an SVE register is architecturally
defined to be a multiple of 128 bits with a maximum of 2048 bits, thus
the maximum vscale is 16. In the loop above it is therefore unfeasible
to vectorize with SVE. However, in this loop:
void foo(int *a, int *b, int N) {
#pragma clang loop vectorize_width(X, scalable)
for (int i=0; i
will have no dependencies between lanes. For any number of lanes larger
than this it would be unsafe to vectorize.
This patch extends 'computeFeasibleMaxVF' to legalize scalable VFs
specified as loop hints, implementing the following behaviour:
* If the backend does not support scalable vectors, ignore the hint.
* If scalable vectorization is unfeasible given the loop
dependence, like in the first example above for SVE, then use a
fixed VF.
* Accept scalable VFs if it's safe to do so.
* Otherwise, clamp scalable VFs that exceed the maximum safe VF.
Reviewed By: sdesmalen, fhahn, david-arm
Differential Revision: https://reviews.llvm.org/D91718
Added:
llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll
llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-scalable.ll
llvm/test/Transforms/LoopVectorize/scalable-vf-hint.ll
Modified:
llvm/include/llvm/Analysis/LoopAccessAnalysis.h
llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/test/Transforms/LoopVectorize/metadata-width.ll
llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-limitations.ll
llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
Removed:
diff --git a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
index 5ee98f308878..13fbe884eddf 100644
--- a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
+++ b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
@@ -205,6 +205,12 @@ class MemoryDepChecker {
return Status == VectorizationSafetyStatus::Safe;
}
+ /// Return true if the number of elements that are safe to operate on
+ /// simultaneously is not bounded.
+ bool isSafeForAnyVectorWidth() const {
+return MaxSafeVectorWidthInBits == UINT_MAX;
+ }
+
/// The maximum number of bytes of a vector register we can vectorize
/// the accesses safely with.
uint64_t getMaxSafeDepDistBytes() { return MaxSafeDepDistBytes; }
diff --git
a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
index f701e08961a0..7e5a723991d4 100644
--- a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
+++ b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
@@ -325,6 +325,10 @@ class LoopVectorizationLegality {
const LoopAccessInfo *getLAI() const { return LAI; }
+ bool isSafeForAnyVectorWidth() const {
+return LAI->getDepChecker().isSafeForAnyVectorWidth();
+ }
+
unsigned getMaxSafeDepDistBytes() { return LAI->getMaxSafeDepDistBytes(); }
uint64_t getMaxSafeVectorWidthInBits() const {
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 0b58ad1ff2ea..21d614934792 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -272,6 +272,12 @@ static cl::opt ForceTargetInstructionCost(
"an instruction to a single constant value. Mostly "
"useful for getting consistent testing."));
+static cl::opt ForceTargetSupportsScalableVectors(
+"force-target-supports-scalable-vectors", cl::init(false), cl::Hidden,
+cl::desc(
+"Pretend that scalable vectors are supported, even if the target does "
+"not support them. This flag should only be used for testing."));
+
static cl::opt SmallLoopCost(
"small-loop-cost", cl::init(20), cl::Hidden,
cl::desc(
@@ -5592,6 +5598,30 @@ LoopVectorizationCostModel::computeMaxVF(ElementCount
UserVF, unsigned UserIC) {
ElementCount
LoopVectorizationCostModel::computeFeasibleMaxVF(unsigned ConstTripCount,
ElementCount UserVF) {
[llvm-branch-commits] [llvm] 1fd3a04 - [LV] Disable epilogue vectorization for scalable VFs
Author: Cullen Rhodes
Date: 2020-12-17T12:14:03Z
New Revision: 1fd3a04775971d12e1063ceb2b22647fd4643acc
URL:
https://github.com/llvm/llvm-project/commit/1fd3a04775971d12e1063ceb2b22647fd4643acc
DIFF:
https://github.com/llvm/llvm-project/commit/1fd3a04775971d12e1063ceb2b22647fd4643acc.diff
LOG: [LV] Disable epilogue vectorization for scalable VFs
Epilogue vectorization doesn't support scalable vectorization factors
yet, disable it for now.
Reviewed By: sdesmalen, bmahjour
Differential Revision: https://reviews.llvm.org/D93063
Added:
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-limitations.ll
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 37863b035067..e486f7110295 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -5784,6 +5784,15 @@
LoopVectorizationCostModel::selectEpilogueVectorizationFactor(
return Result;
}
+ // FIXME: This can be fixed for scalable vectors later, because at this stage
+ // the LoopVectorizer will only consider vectorizing a loop with scalable
+ // vectors when the loop has a hint to enable vectorization for a given VF.
+ if (MainLoopVF.isScalable()) {
+LLVM_DEBUG(dbgs() << "LEV: Epilogue vectorization for scalable vectors not
"
+ "yet supported.\n");
+return Result;
+ }
+
// Not really a cost consideration, but check for unsupported cases here to
// simplify the logic.
if (!isCandidateForEpilogueVectorization(*TheLoop, MainLoopVF)) {
diff --git
a/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-limitations.ll
b/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-limitations.ll
index c4a8f0ded86b..315b1fed31ab 100644
---
a/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-limitations.ll
+++
b/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-limitations.ll
@@ -99,3 +99,27 @@ for.end.loopexit: ; preds =
%for.body
for.end: ; preds = %for.end.loopexit,
%entry
ret void
}
+
+; Currently we cannot handle scalable vectorization factors.
+; CHECK: LV: Checking a loop in "f4"
+; CHECK: LEV: Epilogue vectorization for scalable vectors not yet supported.
+
+define void @f4(i8* %A) {
+entry:
+ br label %for.body
+
+for.body:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %arrayidx = getelementptr inbounds i8, i8* %A, i64 %iv
+ store i8 1, i8* %arrayidx, align 1
+ %iv.next = add nuw nsw i64 %iv, 1
+ %exitcond = icmp ne i64 %iv.next, 1024
+ br i1 %exitcond, label %for.body, label %exit, !llvm.loop !0
+
+exit:
+ ret void
+}
+
+!0 = !{!0, !1, !2}
+!1 = !{!"llvm.loop.vectorize.width", i32 4}
+!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
___
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[llvm-branch-commits] [llvm] 7c8796f - [TTI] Add supportsScalableVectors target hook
Author: Cullen Rhodes
Date: 2020-12-18T10:37:01Z
New Revision: 7c8796f9db2c82ea6e3721744a7d98ebf0e77cd3
URL:
https://github.com/llvm/llvm-project/commit/7c8796f9db2c82ea6e3721744a7d98ebf0e77cd3
DIFF:
https://github.com/llvm/llvm-project/commit/7c8796f9db2c82ea6e3721744a7d98ebf0e77cd3.diff
LOG: [TTI] Add supportsScalableVectors target hook
This is split off from D91718 and adds a new target hook
supportsScalableVectors that can be queried to check if scalable vectors
are supported by the backend. For AArch64 this returns true if SVE is
enabled.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D93060
Added:
Modified:
llvm/include/llvm/Analysis/TargetTransformInfo.h
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/lib/Analysis/TargetTransformInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
Removed:
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h
b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index b9b9df35cdb0..0953a3b3f451 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -1340,6 +1340,9 @@ class TargetTransformInfo {
/// to a stack reload.
unsigned getGISelRematGlobalCost() const;
+ /// \returns True if the target supports scalable vectors.
+ bool supportsScalableVectors() const;
+
/// \name Vector Predication Information
/// @{
/// Whether the target supports the %evl parameter of VP intrinsic
efficiently
@@ -1634,6 +1637,7 @@ class TargetTransformInfo::Concept {
ReductionFlags) const = 0;
virtual bool shouldExpandReduction(const IntrinsicInst *II) const = 0;
virtual unsigned getGISelRematGlobalCost() const = 0;
+ virtual bool supportsScalableVectors() const = 0;
virtual bool hasActiveVectorLength() const = 0;
virtual int getInstructionLatency(const Instruction *I) = 0;
};
@@ -2163,6 +2167,10 @@ class TargetTransformInfo::Model final : public
TargetTransformInfo::Concept {
return Impl.getGISelRematGlobalCost();
}
+ bool supportsScalableVectors() const override {
+return Impl.supportsScalableVectors();
+ }
+
bool hasActiveVectorLength() const override {
return Impl.hasActiveVectorLength();
}
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index 2c206094ac4a..6415e7bfe7c3 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -685,6 +685,8 @@ class TargetTransformInfoImplBase {
unsigned getGISelRematGlobalCost() const { return 1; }
+ bool supportsScalableVectors() const { return false; }
+
bool hasActiveVectorLength() const { return false; }
protected:
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp
b/llvm/lib/Analysis/TargetTransformInfo.cpp
index 086a212ee65b..becf74c64fd5 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -1056,6 +1056,10 @@ unsigned TargetTransformInfo::getGISelRematGlobalCost()
const {
return TTIImpl->getGISelRematGlobalCost();
}
+bool TargetTransformInfo::supportsScalableVectors() const {
+ return TTIImpl->supportsScalableVectors();
+}
+
int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
return TTIImpl->getInstructionLatency(I);
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index baf11cd7fa23..c8e721b1fb9f 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -228,6 +228,8 @@ class AArch64TTIImpl : public
BasicTTIImplBase {
return 2;
}
+ bool supportsScalableVectors() const { return ST->hasSVE(); }
+
bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
TTI::ReductionFlags Flags) const;
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[llvm-branch-commits] [llvm] 1ba4b82 - [LAA] NFC: Rename [get]MaxSafeRegisterWidth -> [get]MaxSafeVectorWidthInBits
Author: Cullen Rhodes
Date: 2020-11-25T13:06:26Z
New Revision: 1ba4b82f67e2267b156fb77e7d0c0f43e88e9103
URL:
https://github.com/llvm/llvm-project/commit/1ba4b82f67e2267b156fb77e7d0c0f43e88e9103
DIFF:
https://github.com/llvm/llvm-project/commit/1ba4b82f67e2267b156fb77e7d0c0f43e88e9103.diff
LOG: [LAA] NFC: Rename [get]MaxSafeRegisterWidth ->
[get]MaxSafeVectorWidthInBits
MaxSafeRegisterWidth is a misnomer since it actually returns the maximum
safe vector width. Register suggests it relates directly to a physical
register where it could be a vector spanning one or more physical
registers.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D91727
Added:
Modified:
llvm/include/llvm/Analysis/LoopAccessAnalysis.h
llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
llvm/lib/Analysis/LoopAccessAnalysis.cpp
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Removed:
diff --git a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
index 663b9c9935db..5ee98f308878 100644
--- a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
+++ b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h
@@ -171,7 +171,8 @@ class MemoryDepChecker {
MemoryDepChecker(PredicatedScalarEvolution &PSE, const Loop *L)
: PSE(PSE), InnermostLoop(L), AccessIdx(0), MaxSafeDepDistBytes(0),
-MaxSafeRegisterWidth(-1U), FoundNonConstantDistanceDependence(false),
+MaxSafeVectorWidthInBits(-1U),
+FoundNonConstantDistanceDependence(false),
Status(VectorizationSafetyStatus::Safe), RecordDependences(true) {}
/// Register the location (instructions are given increasing numbers)
@@ -210,7 +211,9 @@ class MemoryDepChecker {
/// Return the number of elements that are safe to operate on
/// simultaneously, multiplied by the size of the element in bits.
- uint64_t getMaxSafeRegisterWidth() const { return MaxSafeRegisterWidth; }
+ uint64_t getMaxSafeVectorWidthInBits() const {
+return MaxSafeVectorWidthInBits;
+ }
/// In same cases when the dependency check fails we can still
/// vectorize the loop with a dynamic array access check.
@@ -275,7 +278,7 @@ class MemoryDepChecker {
/// operate on simultaneously, multiplied by the size of the element in bits.
/// The size of the element is taken from the memory access that is most
/// restrictive.
- uint64_t MaxSafeRegisterWidth;
+ uint64_t MaxSafeVectorWidthInBits;
/// If we see a non-constant dependence distance we can still try to
/// vectorize this loop with runtime checks.
diff --git
a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
index ae8d545d6112..2be9ef10ac4f 100644
--- a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
+++ b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
@@ -311,8 +311,8 @@ class LoopVectorizationLegality {
unsigned getMaxSafeDepDistBytes() { return LAI->getMaxSafeDepDistBytes(); }
- uint64_t getMaxSafeRegisterWidth() const {
-return LAI->getDepChecker().getMaxSafeRegisterWidth();
+ uint64_t getMaxSafeVectorWidthInBits() const {
+return LAI->getDepChecker().getMaxSafeVectorWidthInBits();
}
bool hasStride(Value *V) { return LAI->hasStride(V); }
diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp
b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
index 78f63c63cb40..19a8ea23b70b 100644
--- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp
+++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
@@ -1654,7 +1654,7 @@ MemoryDepChecker::isDependent(const MemAccessInfo &A,
unsigned AIdx,
LLVM_DEBUG(dbgs() << "LAA: Positive distance " << Val.getSExtValue()
<< " with max VF = " << MaxVF << '\n');
uint64_t MaxVFInBits = MaxVF * TypeByteSize * 8;
- MaxSafeRegisterWidth = std::min(MaxSafeRegisterWidth, MaxVFInBits);
+ MaxSafeVectorWidthInBits = std::min(MaxSafeVectorWidthInBits, MaxVFInBits);
return Dependence::BackwardVectorizable;
}
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 97c9011d8086..c9d6a6199476 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -5369,9 +5369,9 @@ LoopVectorizationCostModel::computeFeasibleMaxVF(unsigned
ConstTripCount) {
// It is computed by MaxVF * sizeOf(type) * 8, where type is taken from
// the memory accesses that is most restrictive (involved in the smallest
// dependence distance).
- unsigned MaxSafeRegisterWidth = Legal->getMaxSafeRegisterWidth();
+ unsigned MaxSafeVectorWidthInBits = Legal->getMaxSafeVectorWidthInBits();
- WidestRegister = std::min(WidestRegister, MaxSafeRegisterWidth);
+ WidestRegister = std::min(WidestRegister, MaxSafeVectorWidthInBits);
[llvm-branch-commits] [llvm] 7b8d50b - [InstSimplify] Clarify use of FixedVectorType in SimplifySelectInst
Author: Cullen Rhodes
Date: 2020-11-27T09:55:29Z
New Revision: 7b8d50b141bbf223eab33a75f468be4ee92ad052
URL:
https://github.com/llvm/llvm-project/commit/7b8d50b141bbf223eab33a75f468be4ee92ad052
DIFF:
https://github.com/llvm/llvm-project/commit/7b8d50b141bbf223eab33a75f468be4ee92ad052.diff
LOG: [InstSimplify] Clarify use of FixedVectorType in SimplifySelectInst
Folding a select of vector constants that include undef elements only
applies to fixed vectors, but there's no earlier check the type is not
scalable so it crashes for scalable vectors. This adds a check so this
optimization is only attempted for fixed vectors.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D92046
Added:
Modified:
llvm/lib/Analysis/InstructionSimplify.cpp
llvm/test/Transforms/InstSimplify/select.ll
Removed:
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 813fb6c89863..6b116eb0ed00 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -4136,7 +4136,8 @@ static Value *SimplifySelectInst(Value *Cond, Value
*TrueVal, Value *FalseVal,
// Deal with partial undef vector constants: select ?, VecC, VecC' --> VecC''
Constant *TrueC, *FalseC;
- if (TrueVal->getType()->isVectorTy() && match(TrueVal, m_Constant(TrueC)) &&
+ if (isa(TrueVal->getType()) &&
+ match(TrueVal, m_Constant(TrueC)) &&
match(FalseVal, m_Constant(FalseC))) {
unsigned NumElts =
cast(TrueC->getType())->getNumElements();
diff --git a/llvm/test/Transforms/InstSimplify/select.ll
b/llvm/test/Transforms/InstSimplify/select.ll
index 2dcd29753788..4cbc5832d234 100644
--- a/llvm/test/Transforms/InstSimplify/select.ll
+++ b/llvm/test/Transforms/InstSimplify/select.ll
@@ -957,3 +957,14 @@ define i32 @pr47322_more_poisonous_replacement(i32 %arg) {
ret i32 %r1.sroa.0.1
}
declare i32 @llvm.cttz.i32(i32, i1 immarg)
+
+; Partial undef scalable vectors should be ignored.
+define @ignore_scalable_undef( %cond) {
+; CHECK-LABEL: @ignore_scalable_undef(
+; CHECK-NEXT:[[S:%.*]] = select [[COND:%.*]], undef, insertelement ( undef, i1
true, i32 0)
+; CHECK-NEXT:ret [[S]]
+;
+ %vec = insertelement undef, i1 true, i32 0
+ %s = select %cond, undef, %vec
+ ret %s
+}
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[llvm-branch-commits] [llvm] cba4acc - [LV] Clamp VF hint when unsafe
Author: Cullen Rhodes
Date: 2020-12-01T11:30:34Z
New Revision: cba4accda08f90bbc96d7662ef6b1bb12a7733f2
URL:
https://github.com/llvm/llvm-project/commit/cba4accda08f90bbc96d7662ef6b1bb12a7733f2
DIFF:
https://github.com/llvm/llvm-project/commit/cba4accda08f90bbc96d7662ef6b1bb12a7733f2.diff
LOG: [LV] Clamp VF hint when unsafe
In the following loop the dependence distance is 2 and can only be
vectorized if the vector length is no larger than this.
void foo(int *a, int *b, int N) {
#pragma clang loop vectorize(enable) vectorize_width(4)
for (int i=0; ihttps://llvm.org/docs/LangRef.html#llvm-loop-vectorize-and-llvm-loop-interleave
[2]
https://clang.llvm.org/docs/LanguageExtensions.html#extensions-for-loop-hint-optimizations
Reviewed By: sdesmalen, fhahn, Meinersbur
Differential Revision: https://reviews.llvm.org/D90687
Added:
llvm/test/Transforms/LoopVectorize/AArch64/unsafe-vf-hint-remark.ll
llvm/test/Transforms/LoopVectorize/unsafe-vf-hint-remark.ll
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index d389e03e9c04..d87938bb1464 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -1443,7 +1443,8 @@ class LoopVectorizationCostModel {
/// \return An upper bound for the vectorization factor, a power-of-2 larger
/// than zero. One is returned if vectorization should best be avoided due
/// to cost.
- ElementCount computeFeasibleMaxVF(unsigned ConstTripCount);
+ ElementCount computeFeasibleMaxVF(unsigned ConstTripCount,
+ElementCount UserVF);
/// The vectorization cost is a combination of the cost itself and a boolean
/// indicating whether any of the contributing operations will actually
@@ -5270,9 +5271,11 @@ LoopVectorizationCostModel::computeMaxVF(ElementCount
UserVF, unsigned UserIC) {
return None;
}
+ ElementCount MaxVF = computeFeasibleMaxVF(TC, UserVF);
+
switch (ScalarEpilogueStatus) {
case CM_ScalarEpilogueAllowed:
-return UserVF ? UserVF : computeFeasibleMaxVF(TC);
+return MaxVF;
case CM_ScalarEpilogueNotNeededUsePredicate:
LLVM_DEBUG(
dbgs() << "LV: vector predicate hint/switch found.\n"
@@ -5308,7 +5311,6 @@ LoopVectorizationCostModel::computeMaxVF(ElementCount
UserVF, unsigned UserIC) {
InterleaveInfo.invalidateGroupsRequiringScalarEpilogue();
}
- ElementCount MaxVF = UserVF ? UserVF : computeFeasibleMaxVF(TC);
assert(!MaxVF.isScalable() &&
"Scalable vectors do not yet support tail folding");
assert((UserVF.isNonZero() || isPowerOf2_32(MaxVF.getFixedValue())) &&
@@ -5361,7 +5363,9 @@ LoopVectorizationCostModel::computeMaxVF(ElementCount
UserVF, unsigned UserIC) {
}
ElementCount
-LoopVectorizationCostModel::computeFeasibleMaxVF(unsigned ConstTripCount) {
+LoopVectorizationCostModel::computeFeasibleMaxVF(unsigned ConstTripCount,
+ ElementCount UserVF) {
+ assert(!UserVF.isScalable() && "scalable vectorization not yet handled");
MinBWs = computeMinimumValueSizes(TheLoop->getBlocks(), *DB, &TTI);
unsigned SmallestType, WidestType;
std::tie(SmallestType, WidestType) = getSmallestAndWidestTypes();
@@ -5373,6 +5377,27 @@
LoopVectorizationCostModel::computeFeasibleMaxVF(unsigned ConstTripCount) {
// dependence distance).
unsigned MaxSafeVectorWidthInBits = Legal->getMaxSafeVectorWidthInBits();
+ if (UserVF.isNonZero()) {
+// If legally unsafe, clamp the user vectorization factor to a safe value.
+unsigned MaxSafeVF = PowerOf2Floor(MaxSafeVectorWidthInBits / WidestType);
+if (UserVF.getFixedValue() <= MaxSafeVF)
+ return UserVF;
+
+LLVM_DEBUG(dbgs() << "LV: User VF=" << UserVF
+ << " is unsafe, clamping to max safe VF=" << MaxSafeVF
+ << ".\n");
+ORE->emit([&]() {
+ return OptimizationRemarkAnalysis(DEBUG_TYPE, "VectorizationFactor",
+TheLoop->getStartLoc(),
+TheLoop->getHeader())
+ << "User-specified vectorization factor "
+ << ore::NV("UserVectorizationFactor", UserVF)
+ << " is unsafe, clamping to maximum safe vectorization factor "
+ << ore::NV("VectorizationFactor", MaxSafeVF);
+});
+return ElementCount::getFixed(MaxSafeVF);
+ }
+
WidestRegister = std::min(WidestRegister, MaxSafeVectorWidthInBits);
// Ensure MaxVF is a power of 2; the dependence distance bound may not be.
@@ -7031,9 +7056,12 @@ LoopVectorizationPlanner::plan(ElementCount UserVF,
unsigned UserIC) {
CM.invalidateCostModelingDecisions();
}
- if (!UserVF.isZero()) {
+ ElementCount MaxVF = MaybeMaxVF.g
[llvm-branch-commits] [llvm] 14557cd - [InstructionsTest] NFC: Replace VectorType::get(.., .., true) with ScalableVectorType::get
Author: Cullen Rhodes
Date: 2020-12-02T10:50:05Z
New Revision: 14557cdf9427341e60b9bd34807c46b2ee826f99
URL:
https://github.com/llvm/llvm-project/commit/14557cdf9427341e60b9bd34807c46b2ee826f99
DIFF:
https://github.com/llvm/llvm-project/commit/14557cdf9427341e60b9bd34807c46b2ee826f99.diff
LOG: [InstructionsTest] NFC: Replace VectorType::get(.., .., true) with
ScalableVectorType::get
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D92467
Added:
Modified:
llvm/unittests/IR/InstructionsTest.cpp
Removed:
diff --git a/llvm/unittests/IR/InstructionsTest.cpp
b/llvm/unittests/IR/InstructionsTest.cpp
index dfd292ff60bb..b2cfa891dcca 100644
--- a/llvm/unittests/IR/InstructionsTest.cpp
+++ b/llvm/unittests/IR/InstructionsTest.cpp
@@ -200,10 +200,10 @@ TEST(InstructionsTest, CastInst) {
Type *V4Int16Ty = FixedVectorType::get(Int16Ty, 4);
Type *V1Int16Ty = FixedVectorType::get(Int16Ty, 1);
- Type *VScaleV2Int32Ty = VectorType::get(Int32Ty, 2, true);
- Type *VScaleV2Int64Ty = VectorType::get(Int64Ty, 2, true);
- Type *VScaleV4Int16Ty = VectorType::get(Int16Ty, 4, true);
- Type *VScaleV1Int16Ty = VectorType::get(Int16Ty, 1, true);
+ Type *VScaleV2Int32Ty = ScalableVectorType::get(Int32Ty, 2);
+ Type *VScaleV2Int64Ty = ScalableVectorType::get(Int64Ty, 2);
+ Type *VScaleV4Int16Ty = ScalableVectorType::get(Int16Ty, 4);
+ Type *VScaleV1Int16Ty = ScalableVectorType::get(Int16Ty, 1);
Type *Int32PtrTy = PointerType::get(Int32Ty, 0);
Type *Int64PtrTy = PointerType::get(Int64Ty, 0);
@@ -214,15 +214,15 @@ TEST(InstructionsTest, CastInst) {
Type *V2Int32PtrAS1Ty = FixedVectorType::get(Int32PtrAS1Ty, 2);
Type *V2Int64PtrAS1Ty = FixedVectorType::get(Int64PtrAS1Ty, 2);
Type *V4Int32PtrAS1Ty = FixedVectorType::get(Int32PtrAS1Ty, 4);
- Type *VScaleV4Int32PtrAS1Ty = VectorType::get(Int32PtrAS1Ty, 4, true);
+ Type *VScaleV4Int32PtrAS1Ty = ScalableVectorType::get(Int32PtrAS1Ty, 4);
Type *V4Int64PtrAS1Ty = FixedVectorType::get(Int64PtrAS1Ty, 4);
Type *V2Int64PtrTy = FixedVectorType::get(Int64PtrTy, 2);
Type *V2Int32PtrTy = FixedVectorType::get(Int32PtrTy, 2);
- Type *VScaleV2Int32PtrTy = VectorType::get(Int32PtrTy, 2, true);
+ Type *VScaleV2Int32PtrTy = ScalableVectorType::get(Int32PtrTy, 2);
Type *V4Int32PtrTy = FixedVectorType::get(Int32PtrTy, 4);
- Type *VScaleV4Int32PtrTy = VectorType::get(Int32PtrTy, 4, true);
- Type *VScaleV4Int64PtrTy = VectorType::get(Int64PtrTy, 4, true);
+ Type *VScaleV4Int32PtrTy = ScalableVectorType::get(Int32PtrTy, 4);
+ Type *VScaleV4Int64PtrTy = ScalableVectorType::get(Int64PtrTy, 4);
const Constant* c8 = Constant::getNullValue(V8x8Ty);
const Constant* c64 = Constant::getNullValue(V8x64Ty);
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[llvm-branch-commits] [llvm] 333de69 - [IR] Disallow scalable vectors in ShuffleVectorInst::isExtractSubvectorMask
Author: Cullen Rhodes
Date: 2020-12-04T11:30:51Z
New Revision: 333de690ea730abd3b23945c0605ebda290ce1b7
URL:
https://github.com/llvm/llvm-project/commit/333de690ea730abd3b23945c0605ebda290ce1b7
DIFF:
https://github.com/llvm/llvm-project/commit/333de690ea730abd3b23945c0605ebda290ce1b7.diff
LOG: [IR] Disallow scalable vectors in ShuffleVectorInst::isExtractSubvectorMask
It's not possible to express an extract subvector shuffle mask for
a scalable vector.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D92312
Added:
Modified:
llvm/include/llvm/IR/Instructions.h
llvm/unittests/IR/InstructionsTest.cpp
Removed:
diff --git a/llvm/include/llvm/IR/Instructions.h
b/llvm/include/llvm/IR/Instructions.h
index eb855972256b..4b08de66e398 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -2268,6 +2268,10 @@ class ShuffleVectorInst : public Instruction {
static bool isExtractSubvectorMask(const Constant *Mask, int NumSrcElts,
int &Index) {
assert(Mask->getType()->isVectorTy() && "Shuffle needs vector constant.");
+// Not possible to express a shuffle mask for a scalable vector for this
+// case.
+if (isa(Mask->getType()))
+ return false;
SmallVector MaskAsInts;
getShuffleMask(Mask, MaskAsInts);
return isExtractSubvectorMask(MaskAsInts, NumSrcElts, Index);
@@ -2275,6 +2279,11 @@ class ShuffleVectorInst : public Instruction {
/// Return true if this shuffle mask is an extract subvector mask.
bool isExtractSubvectorMask(int &Index) const {
+// Not possible to express a shuffle mask for a scalable vector for this
+// case.
+if (isa(getType()))
+ return false;
+
int NumSrcElts =
cast(Op<0>()->getType())->getNumElements();
return isExtractSubvectorMask(ShuffleMask, NumSrcElts, Index);
diff --git a/llvm/unittests/IR/InstructionsTest.cpp
b/llvm/unittests/IR/InstructionsTest.cpp
index b2cfa891dcca..f98ef4b52ccd 100644
--- a/llvm/unittests/IR/InstructionsTest.cpp
+++ b/llvm/unittests/IR/InstructionsTest.cpp
@@ -1073,6 +1073,17 @@ TEST(InstructionsTest, ShuffleMaskQueries) {
EXPECT_FALSE(Id12->isIdentityWithExtract());
EXPECT_FALSE(Id12->isConcat());
delete Id12;
+
+ // Not possible to express shuffle mask for scalable vector for extract
+ // subvector.
+ Type *VScaleV4Int32Ty = ScalableVectorType::get(Int32Ty, 4);
+ ShuffleVectorInst *Id13 =
+ new ShuffleVectorInst(Constant::getAllOnesValue(VScaleV4Int32Ty),
+UndefValue::get(VScaleV4Int32Ty),
+Constant::getNullValue(VScaleV4Int32Ty));
+ int Index = 0;
+ EXPECT_FALSE(Id13->isExtractSubvectorMask(Index));
+ delete Id13;
}
TEST(InstructionsTest, GetSplat) {
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[llvm-branch-commits] [llvm] 9b01896 - [IR] Support scalable vectors in ShuffleVectorInst::increasesLength
Author: Cullen Rhodes
Date: 2020-12-07T10:42:48Z
New Revision: 9b0189655500c30c4ccb0fb5f3ce14a2ac9c6682
URL:
https://github.com/llvm/llvm-project/commit/9b0189655500c30c4ccb0fb5f3ce14a2ac9c6682
DIFF:
https://github.com/llvm/llvm-project/commit/9b0189655500c30c4ccb0fb5f3ce14a2ac9c6682.diff
LOG: [IR] Support scalable vectors in ShuffleVectorInst::increasesLength
Since the length of the llvm::SmallVector shufflemask is related to the
minimum number of elements in a scalable vector, it is fine to just get
the Min field of the ElementCount. This is already done for the similar
function changesLength, tests have been added for both.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D92472
Added:
Modified:
llvm/include/llvm/IR/Instructions.h
llvm/unittests/IR/InstructionsTest.cpp
Removed:
diff --git a/llvm/include/llvm/IR/Instructions.h
b/llvm/include/llvm/IR/Instructions.h
index 4b08de66e398..00ecc2aa7f37 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -2081,8 +2081,9 @@ class ShuffleVectorInst : public Instruction {
/// elements than its source vectors.
/// Example: shufflevector <2 x n> A, <2 x n> B, <1,2,3>
bool increasesLength() const {
-unsigned NumSourceElts =
-cast(Op<0>()->getType())->getNumElements();
+unsigned NumSourceElts = cast(Op<0>()->getType())
+ ->getElementCount()
+ .getKnownMinValue();
unsigned NumMaskElts = ShuffleMask.size();
return NumSourceElts < NumMaskElts;
}
diff --git a/llvm/unittests/IR/InstructionsTest.cpp
b/llvm/unittests/IR/InstructionsTest.cpp
index f98ef4b52ccd..09260d347840 100644
--- a/llvm/unittests/IR/InstructionsTest.cpp
+++ b/llvm/unittests/IR/InstructionsTest.cpp
@@ -1083,7 +1083,19 @@ TEST(InstructionsTest, ShuffleMaskQueries) {
Constant::getNullValue(VScaleV4Int32Ty));
int Index = 0;
EXPECT_FALSE(Id13->isExtractSubvectorMask(Index));
+ EXPECT_FALSE(Id13->changesLength());
+ EXPECT_FALSE(Id13->increasesLength());
delete Id13;
+
+ // Result has twice as many operands.
+ Type *VScaleV2Int32Ty = ScalableVectorType::get(Int32Ty, 2);
+ ShuffleVectorInst *Id14 =
+ new ShuffleVectorInst(Constant::getAllOnesValue(VScaleV2Int32Ty),
+UndefValue::get(VScaleV2Int32Ty),
+Constant::getNullValue(VScaleV4Int32Ty));
+ EXPECT_TRUE(Id14->changesLength());
+ EXPECT_TRUE(Id14->increasesLength());
+ delete Id14;
}
TEST(InstructionsTest, GetSplat) {
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[llvm-branch-commits] [llvm] 7b1cb47 - [IR] Bail out for scalable vectors in ShuffleVectorInst::isConcat
Author: Cullen Rhodes
Date: 2020-12-07T10:48:35Z
New Revision: 7b1cb4715063679531e51127eee869cd03df88da
URL:
https://github.com/llvm/llvm-project/commit/7b1cb4715063679531e51127eee869cd03df88da
DIFF:
https://github.com/llvm/llvm-project/commit/7b1cb4715063679531e51127eee869cd03df88da.diff
LOG: [IR] Bail out for scalable vectors in ShuffleVectorInst::isConcat
Shuffle mask for concat can't be expressed for scalable vectors, so we
should bail out. A test has been added that previously crashed, also
tested isIdentityWithPadding and isIdentityWithExtract where we already
bail out.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D92475
Added:
Modified:
llvm/lib/IR/Instructions.cpp
llvm/unittests/IR/InstructionsTest.cpp
Removed:
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index 10427b22d5d7..5de1addabbe2 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -2274,6 +2274,11 @@ bool ShuffleVectorInst::isConcat() const {
isa(Op<2>()))
return false;
+ // FIXME: Not currently possible to express a shuffle mask for a scalable
+ // vector for this case.
+ if (isa(getType()))
+return false;
+
int NumOpElts = cast(Op<0>()->getType())->getNumElements();
int NumMaskElts = cast(getType())->getNumElements();
if (NumMaskElts != NumOpElts * 2)
diff --git a/llvm/unittests/IR/InstructionsTest.cpp
b/llvm/unittests/IR/InstructionsTest.cpp
index 09260d347840..2c67ff4286e7 100644
--- a/llvm/unittests/IR/InstructionsTest.cpp
+++ b/llvm/unittests/IR/InstructionsTest.cpp
@@ -1096,6 +1096,17 @@ TEST(InstructionsTest, ShuffleMaskQueries) {
EXPECT_TRUE(Id14->changesLength());
EXPECT_TRUE(Id14->increasesLength());
delete Id14;
+
+ // Not possible to express these masks for scalable vectors, make sure we
+ // don't crash.
+ ShuffleVectorInst *Id15 =
+ new ShuffleVectorInst(Constant::getAllOnesValue(VScaleV2Int32Ty),
+Constant::getNullValue(VScaleV2Int32Ty),
+Constant::getNullValue(VScaleV2Int32Ty));
+ EXPECT_FALSE(Id15->isIdentityWithPadding());
+ EXPECT_FALSE(Id15->isIdentityWithExtract());
+ EXPECT_FALSE(Id15->isConcat());
+ delete Id15;
}
TEST(InstructionsTest, GetSplat) {
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[llvm-branch-commits] [llvm] 2cfbdaf - [IR] Remove CastInst::isCastable since it is not used
Author: Cullen Rhodes
Date: 2020-12-08T10:31:53Z
New Revision: 2cfbdaf601049faafb2f1b40f63a3b2bef74a464
URL:
https://github.com/llvm/llvm-project/commit/2cfbdaf601049faafb2f1b40f63a3b2bef74a464
DIFF:
https://github.com/llvm/llvm-project/commit/2cfbdaf601049faafb2f1b40f63a3b2bef74a464.diff
LOG: [IR] Remove CastInst::isCastable since it is not used
It was removed back in 2013 (f63dfbb) by Matt Arsenault but then
reverted since DragonEgg used it, but that project is no longer
maintained.
Reviewed By: ldionne, dexonsmith
Differential Revision: https://reviews.llvm.org/D92571
Added:
Modified:
llvm/include/llvm/IR/InstrTypes.h
llvm/lib/IR/Instructions.cpp
llvm/unittests/IR/InstructionsTest.cpp
Removed:
diff --git a/llvm/include/llvm/IR/InstrTypes.h
b/llvm/include/llvm/IR/InstrTypes.h
index 1091c4b0dc0f..23e030e94953 100644
--- a/llvm/include/llvm/IR/InstrTypes.h
+++ b/llvm/include/llvm/IR/InstrTypes.h
@@ -599,12 +599,6 @@ class CastInst : public UnaryInstruction {
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
- /// Check whether it is valid to call getCastOpcode for these types.
- static bool isCastable(
-Type *SrcTy, ///< The Type from which the value should be cast.
-Type *DestTy ///< The Type to which the value should be cast.
- );
-
/// Check whether a bitcast between these types is valid
static bool isBitCastable(
Type *SrcTy, ///< The Type from which the value should be cast.
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index 5de1addabbe2..cfc6d05ecaba 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -3142,64 +3142,6 @@ CastInst *CastInst::CreateFPCast(Value *C, Type *Ty,
return Create(opcode, C, Ty, Name, InsertAtEnd);
}
-// Check whether it is valid to call getCastOpcode for these types.
-// This routine must be kept in sync with getCastOpcode.
-bool CastInst::isCastable(Type *SrcTy, Type *DestTy) {
- if (!SrcTy->isFirstClassType() || !DestTy->isFirstClassType())
-return false;
-
- if (SrcTy == DestTy)
-return true;
-
- if (VectorType *SrcVecTy = dyn_cast(SrcTy))
-if (VectorType *DestVecTy = dyn_cast(DestTy))
- if (cast(SrcVecTy)->getNumElements() ==
- cast(DestVecTy)->getNumElements()) {
-// An element by element cast. Valid if casting the elements is valid.
-SrcTy = SrcVecTy->getElementType();
-DestTy = DestVecTy->getElementType();
- }
-
- // Get the bit sizes, we'll need these
- TypeSize SrcBits = SrcTy->getPrimitiveSizeInBits(); // 0 for ptr
- TypeSize DestBits = DestTy->getPrimitiveSizeInBits(); // 0 for ptr
-
- // Run through the possibilities ...
- if (DestTy->isIntegerTy()) { // Casting to integral
-if (SrcTy->isIntegerTy())// Casting from integral
-return true;
-if (SrcTy->isFloatingPointTy()) // Casting from floating pt
- return true;
-if (SrcTy->isVectorTy()) // Casting from vector
- return DestBits == SrcBits;
- // Casting from something else
-return SrcTy->isPointerTy();
- }
- if (DestTy->isFloatingPointTy()) { // Casting to floating pt
-if (SrcTy->isIntegerTy())// Casting from integral
- return true;
-if (SrcTy->isFloatingPointTy()) // Casting from floating pt
- return true;
-if (SrcTy->isVectorTy()) // Casting from vector
- return DestBits == SrcBits;
-// Casting from something else
-return false;
- }
- if (DestTy->isVectorTy()) // Casting to vector
-return DestBits == SrcBits;
- if (DestTy->isPointerTy()) {// Casting to pointer
-if (SrcTy->isPointerTy())// Casting from pointer
- return true;
-return SrcTy->isIntegerTy(); // Casting from integral
- }
- if (DestTy->isX86_MMXTy()) {
-if (SrcTy->isVectorTy())
- return DestBits == SrcBits; // 64-bit vector to MMX
-return false;
- }// Casting to something else
- return false;
-}
-
bool CastInst::isBitCastable(Type *SrcTy, Type *DestTy) {
if (!SrcTy->isFirstClassType() || !DestTy->isFirstClassType())
return false;
@@ -3261,7 +3203,6 @@ bool CastInst::isBitOrNoopPointerCastable(Type *SrcTy,
Type *DestTy,
// castIsValid( getCastOpcode(Val, Ty), Val, Ty)
// should not assert in castIsValid. In other words, this produces a "correct"
// casting opcode for the arguments passed to it.
-// This routine must be kept in sync with isCastable.
Instruction::CastOps
CastInst::getCastOpcode(
const Value *Src, bool SrcIsSigned, Type *DestTy, bool DestIsSigned) {
diff --git a/llvm/unittests/IR/InstructionsTest.cpp
b/llvm/unittests/IR/InstructionsTest.cpp
index 2c67ff4286e7..7a4dad21ecc9 100644
--- a/llvm/u
[llvm-branch-commits] [llvm] 4167a02 - [IR] Support scalable vectors in CastInst::CreatePointerCast
Author: Cullen Rhodes
Date: 2020-12-09T10:39:36Z
New Revision: 4167a0259ec33a11530a6503e96acedaf3cb6a3d
URL:
https://github.com/llvm/llvm-project/commit/4167a0259ec33a11530a6503e96acedaf3cb6a3d
DIFF:
https://github.com/llvm/llvm-project/commit/4167a0259ec33a11530a6503e96acedaf3cb6a3d.diff
LOG: [IR] Support scalable vectors in CastInst::CreatePointerCast
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D92482
Added:
Modified:
llvm/lib/IR/Instructions.cpp
llvm/unittests/IR/InstructionsTest.cpp
Removed:
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index 282746619d22..74a95da79932 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -3022,8 +3022,8 @@ CastInst *CastInst::CreatePointerCast(Value *S, Type *Ty,
"Invalid cast");
assert(Ty->isVectorTy() == S->getType()->isVectorTy() && "Invalid cast");
assert((!Ty->isVectorTy() ||
- cast(Ty)->getNumElements() ==
- cast(S->getType())->getNumElements()) &&
+ cast(Ty)->getElementCount() ==
+ cast(S->getType())->getElementCount()) &&
"Invalid cast");
if (Ty->isIntOrIntVectorTy())
@@ -3041,8 +3041,8 @@ CastInst *CastInst::CreatePointerCast(Value *S, Type *Ty,
"Invalid cast");
assert(Ty->isVectorTy() == S->getType()->isVectorTy() && "Invalid cast");
assert((!Ty->isVectorTy() ||
- cast(Ty)->getNumElements() ==
- cast(S->getType())->getNumElements()) &&
+ cast(Ty)->getElementCount() ==
+ cast(S->getType())->getElementCount()) &&
"Invalid cast");
if (Ty->isIntOrIntVectorTy())
diff --git a/llvm/unittests/IR/InstructionsTest.cpp
b/llvm/unittests/IR/InstructionsTest.cpp
index 7a4dad21ecc9..419cddc0c370 100644
--- a/llvm/unittests/IR/InstructionsTest.cpp
+++ b/llvm/unittests/IR/InstructionsTest.cpp
@@ -368,11 +368,19 @@ TEST(InstructionsTest, CastInst) {
Constant *NullV2I32Ptr = Constant::getNullValue(V2Int32PtrTy);
auto Inst1 = CastInst::CreatePointerCast(NullV2I32Ptr, V2Int32Ty, "foo", BB);
+ Constant *NullVScaleV2I32Ptr = Constant::getNullValue(VScaleV2Int32PtrTy);
+ auto Inst1VScale = CastInst::CreatePointerCast(
+ NullVScaleV2I32Ptr, VScaleV2Int32Ty, "foo.vscale", BB);
+
// Second form
auto Inst2 = CastInst::CreatePointerCast(NullV2I32Ptr, V2Int32Ty);
+ auto Inst2VScale =
+ CastInst::CreatePointerCast(NullVScaleV2I32Ptr, VScaleV2Int32Ty);
delete Inst2;
+ delete Inst2VScale;
Inst1->eraseFromParent();
+ Inst1VScale->eraseFromParent();
delete BB;
}
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