Author: Cullen Rhodes Date: 2021-01-12T18:10:36Z New Revision: 3d9c51d111d0c8480d10fc48fb621bac1d080449
URL: https://github.com/llvm/llvm-project/commit/3d9c51d111d0c8480d10fc48fb621bac1d080449 DIFF: https://github.com/llvm/llvm-project/commit/3d9c51d111d0c8480d10fc48fb621bac1d080449.diff LOG: [SVE][NFC] Regenerate a few CodeGen tests Regenerated using llvm/utils/update_llc_test_checks.py as part of D94504, committing separately to reduce the diff for D94504. Added: Modified: llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll Removed: ################################################################################ diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll index be1c03a754fe..44d4b1d27560 100644 --- a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll +++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t @@ -10,18 +11,20 @@ define <vscale x 16 x i8> @ldnf1b(<vscale x 16 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b: -; CHECK: ldnf1b { z0.b }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnf1.nxv16i8(<vscale x 16 x i1> %pg, i8* %a) ret <vscale x 16 x i8> %load } define <vscale x 16 x i8> @ldnf1b_out_of_lower_bound(<vscale x 16 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b_out_of_lower_bound: -; CHECK: rdvl x[[OFFSET:[0-9]+]], #-9 -; CHECK-NEXT: add x[[BASE:[0-9]+]], x0, x[[OFFSET]] -; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x[[BASE]]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: rdvl x8, #-9 +; CHECK-NEXT: add x8, x0, x8 +; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x8] +; CHECK-NEXT: ret %base_scalable = bitcast i8* %a to <vscale x 16 x i8>* %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 -9 %base_scalar = bitcast <vscale x 16 x i8>* %base to i8* @@ -31,8 +34,9 @@ define <vscale x 16 x i8> @ldnf1b_out_of_lower_bound(<vscale x 16 x i1> %pg, i8* define <vscale x 16 x i8> @ldnf1b_lower_bound(<vscale x 16 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b_lower_bound: -; CHECK: ldnf1b { z0.b }, p0/z, [x0, #-8, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x0, #-8, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i8* %a to <vscale x 16 x i8>* %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 -8 %base_scalar = bitcast <vscale x 16 x i8>* %base to i8* @@ -42,8 +46,9 @@ define <vscale x 16 x i8> @ldnf1b_lower_bound(<vscale x 16 x i1> %pg, i8* %a) { define <vscale x 16 x i8> @ldnf1b_inbound(<vscale x 16 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b_inbound: -; CHECK: ldnf1b { z0.b }, p0/z, [x0, #1, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x0, #1, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i8* %a to <vscale x 16 x i8>* %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 1 %base_scalar = bitcast <vscale x 16 x i8>* %base to i8* @@ -53,8 +58,9 @@ define <vscale x 16 x i8> @ldnf1b_inbound(<vscale x 16 x i1> %pg, i8* %a) { define <vscale x 16 x i8> @ldnf1b_upper_bound(<vscale x 16 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b_upper_bound: -; CHECK: ldnf1b { z0.b }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i8* %a to <vscale x 16 x i8>* %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 16 x i8>* %base to i8* @@ -64,10 +70,11 @@ define <vscale x 16 x i8> @ldnf1b_upper_bound(<vscale x 16 x i1> %pg, i8* %a) { define <vscale x 16 x i8> @ldnf1b_out_of_upper_bound(<vscale x 16 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b_out_of_upper_bound: -; CHECK: rdvl x[[OFFSET:[0-9]+]], #8 -; CHECK-NEXT: add x[[BASE:[0-9]+]], x0, x[[OFFSET]] -; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x[[BASE]]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: rdvl x8, #8 +; CHECK-NEXT: add x8, x0, x8 +; CHECK-NEXT: ldnf1b { z0.b }, p0/z, [x8] +; CHECK-NEXT: ret %base_scalable = bitcast i8* %a to <vscale x 16 x i8>* %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base_scalable, i64 8 %base_scalar = bitcast <vscale x 16 x i8>* %base to i8* @@ -77,8 +84,9 @@ define <vscale x 16 x i8> @ldnf1b_out_of_upper_bound(<vscale x 16 x i1> %pg, i8* define <vscale x 8 x i16> @ldnf1b_h(<vscale x 8 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b_h: -; CHECK: ldnf1b { z0.h }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1b { z0.h }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8(<vscale x 8 x i1> %pg, i8* %a) %res = zext <vscale x 8 x i8> %load to <vscale x 8 x i16> ret <vscale x 8 x i16> %res @@ -86,8 +94,9 @@ define <vscale x 8 x i16> @ldnf1b_h(<vscale x 8 x i1> %pg, i8* %a) { define <vscale x 8 x i16> @ldnf1b_h_inbound(<vscale x 8 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b_h_inbound: -; CHECK: ldnf1b { z0.h }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1b { z0.h }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i8* %a to <vscale x 8 x i8>* %base = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 8 x i8>* %base to i8* @@ -98,8 +107,9 @@ define <vscale x 8 x i16> @ldnf1b_h_inbound(<vscale x 8 x i1> %pg, i8* %a) { define <vscale x 8 x i16> @ldnf1sb_h(<vscale x 8 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1sb_h: -; CHECK: ldnf1sb { z0.h }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sb { z0.h }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 8 x i8> @llvm.aarch64.sve.ldnf1.nxv8i8(<vscale x 8 x i1> %pg, i8* %a) %res = sext <vscale x 8 x i8> %load to <vscale x 8 x i16> ret <vscale x 8 x i16> %res @@ -107,8 +117,9 @@ define <vscale x 8 x i16> @ldnf1sb_h(<vscale x 8 x i1> %pg, i8* %a) { define <vscale x 8 x i16> @ldnf1sb_h_inbound(<vscale x 8 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1sb_h_inbound: -; CHECK: ldnf1sb { z0.h }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sb { z0.h }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i8* %a to <vscale x 8 x i8>* %base = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 8 x i8>* %base to i8* @@ -119,16 +130,18 @@ define <vscale x 8 x i16> @ldnf1sb_h_inbound(<vscale x 8 x i1> %pg, i8* %a) { define <vscale x 8 x i16> @ldnf1h(<vscale x 8 x i1> %pg, i16* %a) { ; CHECK-LABEL: ldnf1h: -; CHECK: ldnf1h { z0.h }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1h { z0.h }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnf1.nxv8i16(<vscale x 8 x i1> %pg, i16* %a) ret <vscale x 8 x i16> %load } define <vscale x 8 x i16> @ldnf1h_inbound(<vscale x 8 x i1> %pg, i16* %a) { ; CHECK-LABEL: ldnf1h_inbound: -; CHECK: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i16* %a to <vscale x 8 x i16>* %base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %base_scalable, i64 1 %base_scalar = bitcast <vscale x 8 x i16>* %base to i16* @@ -138,24 +151,27 @@ define <vscale x 8 x i16> @ldnf1h_inbound(<vscale x 8 x i1> %pg, i16* %a) { define <vscale x 8 x half> @ldnf1h_f16(<vscale x 8 x i1> %pg, half* %a) { ; CHECK-LABEL: ldnf1h_f16: -; CHECK: ldnf1h { z0.h }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1h { z0.h }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 8 x half> @llvm.aarch64.sve.ldnf1.nxv8f16(<vscale x 8 x i1> %pg, half* %a) ret <vscale x 8 x half> %load } define <vscale x 8 x bfloat> @ldnf1h_bf16(<vscale x 8 x i1> %pg, bfloat* %a) #0 { ; CHECK-LABEL: ldnf1h_bf16: -; CHECK: ldnf1h { z0.h }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1h { z0.h }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ldnf1.nxv8bf16(<vscale x 8 x i1> %pg, bfloat* %a) ret <vscale x 8 x bfloat> %load } define <vscale x 8 x half> @ldnf1h_f16_inbound(<vscale x 8 x i1> %pg, half* %a) { ; CHECK-LABEL: ldnf1h_f16_inbound: -; CHECK: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast half* %a to <vscale x 8 x half>* %base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %base_scalable, i64 1 %base_scalar = bitcast <vscale x 8 x half>* %base to half* @@ -165,8 +181,9 @@ define <vscale x 8 x half> @ldnf1h_f16_inbound(<vscale x 8 x i1> %pg, half* %a) define <vscale x 8 x bfloat> @ldnf1h_bf16_inbound(<vscale x 8 x i1> %pg, bfloat* %a) #0 { ; CHECK-LABEL: ldnf1h_bf16_inbound: -; CHECK: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1h { z0.h }, p0/z, [x0, #1, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast bfloat* %a to <vscale x 8 x bfloat>* %base = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %base_scalable, i64 1 %base_scalar = bitcast <vscale x 8 x bfloat>* %base to bfloat* @@ -176,8 +193,9 @@ define <vscale x 8 x bfloat> @ldnf1h_bf16_inbound(<vscale x 8 x i1> %pg, bfloat* define <vscale x 4 x i32> @ldnf1b_s(<vscale x 4 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b_s: -; CHECK: ldnf1b { z0.s }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1b { z0.s }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8(<vscale x 4 x i1> %pg, i8* %a) %res = zext <vscale x 4 x i8> %load to <vscale x 4 x i32> ret <vscale x 4 x i32> %res @@ -185,8 +203,9 @@ define <vscale x 4 x i32> @ldnf1b_s(<vscale x 4 x i1> %pg, i8* %a) { define <vscale x 4 x i32> @ldnf1b_s_inbound(<vscale x 4 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b_s_inbound: -; CHECK: ldnf1b { z0.s }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1b { z0.s }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i8* %a to <vscale x 4 x i8>* %base = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 4 x i8>* %base to i8* @@ -197,8 +216,9 @@ define <vscale x 4 x i32> @ldnf1b_s_inbound(<vscale x 4 x i1> %pg, i8* %a) { define <vscale x 4 x i32> @ldnf1sb_s(<vscale x 4 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1sb_s: -; CHECK: ldnf1sb { z0.s }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sb { z0.s }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldnf1.nxv4i8(<vscale x 4 x i1> %pg, i8* %a) %res = sext <vscale x 4 x i8> %load to <vscale x 4 x i32> ret <vscale x 4 x i32> %res @@ -206,8 +226,9 @@ define <vscale x 4 x i32> @ldnf1sb_s(<vscale x 4 x i1> %pg, i8* %a) { define <vscale x 4 x i32> @ldnf1sb_s_inbound(<vscale x 4 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1sb_s_inbound: -; CHECK: ldnf1sb { z0.s }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sb { z0.s }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i8* %a to <vscale x 4 x i8>* %base = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 4 x i8>* %base to i8* @@ -218,8 +239,9 @@ define <vscale x 4 x i32> @ldnf1sb_s_inbound(<vscale x 4 x i1> %pg, i8* %a) { define <vscale x 4 x i32> @ldnf1h_s(<vscale x 4 x i1> %pg, i16* %a) { ; CHECK-LABEL: ldnf1h_s: -; CHECK: ldnf1h { z0.s }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1h { z0.s }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %pg, i16* %a) %res = zext <vscale x 4 x i16> %load to <vscale x 4 x i32> ret <vscale x 4 x i32> %res @@ -227,8 +249,9 @@ define <vscale x 4 x i32> @ldnf1h_s(<vscale x 4 x i1> %pg, i16* %a) { define <vscale x 4 x i32> @ldnf1h_s_inbound(<vscale x 4 x i1> %pg, i16* %a) { ; CHECK-LABEL: ldnf1h_s_inbound: -; CHECK: ldnf1h { z0.s }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1h { z0.s }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i16* %a to <vscale x 4 x i16>* %base = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 4 x i16>* %base to i16* @@ -239,8 +262,9 @@ define <vscale x 4 x i32> @ldnf1h_s_inbound(<vscale x 4 x i1> %pg, i16* %a) { define <vscale x 4 x i32> @ldnf1sh_s(<vscale x 4 x i1> %pg, i16* %a) { ; CHECK-LABEL: ldnf1sh_s: -; CHECK: ldnf1sh { z0.s }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sh { z0.s }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %pg, i16* %a) %res = sext <vscale x 4 x i16> %load to <vscale x 4 x i32> ret <vscale x 4 x i32> %res @@ -248,8 +272,9 @@ define <vscale x 4 x i32> @ldnf1sh_s(<vscale x 4 x i1> %pg, i16* %a) { define <vscale x 4 x i32> @ldnf1sh_s_inbound(<vscale x 4 x i1> %pg, i16* %a) { ; CHECK-LABEL: ldnf1sh_s_inbound: -; CHECK: ldnf1sh { z0.s }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sh { z0.s }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i16* %a to <vscale x 4 x i16>* %base = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 4 x i16>* %base to i16* @@ -260,16 +285,18 @@ define <vscale x 4 x i32> @ldnf1sh_s_inbound(<vscale x 4 x i1> %pg, i16* %a) { define <vscale x 4 x i32> @ldnf1w(<vscale x 4 x i1> %pg, i32* %a) { ; CHECK-LABEL: ldnf1w: -; CHECK: ldnf1w { z0.s }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1w { z0.s }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnf1.nxv4i32(<vscale x 4 x i1> %pg, i32* %a) ret <vscale x 4 x i32> %load } define <vscale x 4 x i32> @ldnf1w_inbound(<vscale x 4 x i1> %pg, i32* %a) { ; CHECK-LABEL: ldnf1w_inbound: -; CHECK: ldnf1w { z0.s }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1w { z0.s }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i32* %a to <vscale x 4 x i32>* %base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 4 x i32>* %base to i32* @@ -279,16 +306,18 @@ define <vscale x 4 x i32> @ldnf1w_inbound(<vscale x 4 x i1> %pg, i32* %a) { define <vscale x 4 x float> @ldnf1w_f32(<vscale x 4 x i1> %pg, float* %a) { ; CHECK-LABEL: ldnf1w_f32: -; CHECK: ldnf1w { z0.s }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1w { z0.s }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 4 x float> @llvm.aarch64.sve.ldnf1.nxv4f32(<vscale x 4 x i1> %pg, float* %a) ret <vscale x 4 x float> %load } define <vscale x 4 x float> @ldnf1w_f32_inbound(<vscale x 4 x i1> %pg, float* %a) { ; CHECK-LABEL: ldnf1w_f32_inbound: -; CHECK: ldnf1w { z0.s }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1w { z0.s }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast float* %a to <vscale x 4 x float>* %base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 4 x float>* %base to float* @@ -298,8 +327,9 @@ define <vscale x 4 x float> @ldnf1w_f32_inbound(<vscale x 4 x i1> %pg, float* %a define <vscale x 2 x i64> @ldnf1b_d(<vscale x 2 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b_d: -; CHECK: ldnf1b { z0.d }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1b { z0.d }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8(<vscale x 2 x i1> %pg, i8* %a) %res = zext <vscale x 2 x i8> %load to <vscale x 2 x i64> ret <vscale x 2 x i64> %res @@ -307,8 +337,9 @@ define <vscale x 2 x i64> @ldnf1b_d(<vscale x 2 x i1> %pg, i8* %a) { define <vscale x 2 x i64> @ldnf1b_d_inbound(<vscale x 2 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1b_d_inbound: -; CHECK: ldnf1b { z0.d }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1b { z0.d }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i8* %a to <vscale x 2 x i8>* %base = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 2 x i8>* %base to i8* @@ -319,8 +350,9 @@ define <vscale x 2 x i64> @ldnf1b_d_inbound(<vscale x 2 x i1> %pg, i8* %a) { define <vscale x 2 x i64> @ldnf1sb_d(<vscale x 2 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1sb_d: -; CHECK: ldnf1sb { z0.d }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sb { z0.d }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldnf1.nxv2i8(<vscale x 2 x i1> %pg, i8* %a) %res = sext <vscale x 2 x i8> %load to <vscale x 2 x i64> ret <vscale x 2 x i64> %res @@ -328,8 +360,9 @@ define <vscale x 2 x i64> @ldnf1sb_d(<vscale x 2 x i1> %pg, i8* %a) { define <vscale x 2 x i64> @ldnf1sb_d_inbound(<vscale x 2 x i1> %pg, i8* %a) { ; CHECK-LABEL: ldnf1sb_d_inbound: -; CHECK: ldnf1sb { z0.d }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sb { z0.d }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i8* %a to <vscale x 2 x i8>* %base = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 2 x i8>* %base to i8* @@ -340,8 +373,9 @@ define <vscale x 2 x i64> @ldnf1sb_d_inbound(<vscale x 2 x i1> %pg, i8* %a) { define <vscale x 2 x i64> @ldnf1h_d(<vscale x 2 x i1> %pg, i16* %a) { ; CHECK-LABEL: ldnf1h_d: -; CHECK: ldnf1h { z0.d }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1h { z0.d }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %pg, i16* %a) %res = zext <vscale x 2 x i16> %load to <vscale x 2 x i64> ret <vscale x 2 x i64> %res @@ -349,8 +383,9 @@ define <vscale x 2 x i64> @ldnf1h_d(<vscale x 2 x i1> %pg, i16* %a) { define <vscale x 2 x i64> @ldnf1h_d_inbound(<vscale x 2 x i1> %pg, i16* %a) { ; CHECK-LABEL: ldnf1h_d_inbound: -; CHECK: ldnf1h { z0.d }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1h { z0.d }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i16* %a to <vscale x 2 x i16>* %base = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 2 x i16>* %base to i16* @@ -361,8 +396,9 @@ define <vscale x 2 x i64> @ldnf1h_d_inbound(<vscale x 2 x i1> %pg, i16* %a) { define <vscale x 2 x i64> @ldnf1sh_d(<vscale x 2 x i1> %pg, i16* %a) { ; CHECK-LABEL: ldnf1sh_d: -; CHECK: ldnf1sh { z0.d }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sh { z0.d }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %pg, i16* %a) %res = sext <vscale x 2 x i16> %load to <vscale x 2 x i64> ret <vscale x 2 x i64> %res @@ -370,8 +406,9 @@ define <vscale x 2 x i64> @ldnf1sh_d(<vscale x 2 x i1> %pg, i16* %a) { define <vscale x 2 x i64> @ldnf1sh_d_inbound(<vscale x 2 x i1> %pg, i16* %a) { ; CHECK-LABEL: ldnf1sh_d_inbound: -; CHECK: ldnf1sh { z0.d }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sh { z0.d }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i16* %a to <vscale x 2 x i16>* %base = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 2 x i16>* %base to i16* @@ -382,8 +419,9 @@ define <vscale x 2 x i64> @ldnf1sh_d_inbound(<vscale x 2 x i1> %pg, i16* %a) { define <vscale x 2 x i64> @ldnf1w_d(<vscale x 2 x i1> %pg, i32* %a) { ; CHECK-LABEL: ldnf1w_d: -; CHECK: ldnf1w { z0.d }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1w { z0.d }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %pg, i32* %a) %res = zext <vscale x 2 x i32> %load to <vscale x 2 x i64> ret <vscale x 2 x i64> %res @@ -391,8 +429,9 @@ define <vscale x 2 x i64> @ldnf1w_d(<vscale x 2 x i1> %pg, i32* %a) { define <vscale x 2 x i64> @ldnf1w_d_inbound(<vscale x 2 x i1> %pg, i32* %a) { ; CHECK-LABEL: ldnf1w_d_inbound: -; CHECK: ldnf1w { z0.d }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1w { z0.d }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i32* %a to <vscale x 2 x i32>* %base = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 2 x i32>* %base to i32* @@ -403,8 +442,9 @@ define <vscale x 2 x i64> @ldnf1w_d_inbound(<vscale x 2 x i1> %pg, i32* %a) { define <vscale x 2 x i64> @ldnf1sw_d(<vscale x 2 x i1> %pg, i32* %a) { ; CHECK-LABEL: ldnf1sw_d: -; CHECK: ldnf1sw { z0.d }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sw { z0.d }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %pg, i32* %a) %res = sext <vscale x 2 x i32> %load to <vscale x 2 x i64> ret <vscale x 2 x i64> %res @@ -412,8 +452,9 @@ define <vscale x 2 x i64> @ldnf1sw_d(<vscale x 2 x i1> %pg, i32* %a) { define <vscale x 2 x i64> @ldnf1sw_d_inbound(<vscale x 2 x i1> %pg, i32* %a) { ; CHECK-LABEL: ldnf1sw_d_inbound: -; CHECK: ldnf1sw { z0.d }, p0/z, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1sw { z0.d }, p0/z, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i32* %a to <vscale x 2 x i32>* %base = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base_scalable, i64 7 %base_scalar = bitcast <vscale x 2 x i32>* %base to i32* @@ -424,16 +465,18 @@ define <vscale x 2 x i64> @ldnf1sw_d_inbound(<vscale x 2 x i1> %pg, i32* %a) { define <vscale x 2 x i64> @ldnf1d(<vscale x 2 x i1> %pg, i64* %a) { ; CHECK-LABEL: ldnf1d: -; CHECK: ldnf1d { z0.d }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1d { z0.d }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnf1.nxv2i64(<vscale x 2 x i1> %pg, i64* %a) ret <vscale x 2 x i64> %load } define <vscale x 2 x i64> @ldnf1d_inbound(<vscale x 2 x i1> %pg, i64* %a) { ; CHECK-LABEL: ldnf1d_inbound: -; CHECK: ldnf1d { z0.d }, p0/z, [x0, #1, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1d { z0.d }, p0/z, [x0, #1, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast i64* %a to <vscale x 2 x i64>* %base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base_scalable, i64 1 %base_scalar = bitcast <vscale x 2 x i64>* %base to i64* @@ -443,16 +486,18 @@ define <vscale x 2 x i64> @ldnf1d_inbound(<vscale x 2 x i1> %pg, i64* %a) { define <vscale x 2 x double> @ldnf1d_f64(<vscale x 2 x i1> %pg, double* %a) { ; CHECK-LABEL: ldnf1d_f64: -; CHECK: ldnf1d { z0.d }, p0/z, [x0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1d { z0.d }, p0/z, [x0] +; CHECK-NEXT: ret %load = call <vscale x 2 x double> @llvm.aarch64.sve.ldnf1.nxv2f64(<vscale x 2 x i1> %pg, double* %a) ret <vscale x 2 x double> %load } define <vscale x 2 x double> @ldnf1d_f64_inbound(<vscale x 2 x i1> %pg, double* %a) { ; CHECK-LABEL: ldnf1d_f64_inbound: -; CHECK: ldnf1d { z0.d }, p0/z, [x0, #1, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnf1d { z0.d }, p0/z, [x0, #1, mul vl] +; CHECK-NEXT: ret %base_scalable = bitcast double* %a to <vscale x 2 x double>* %base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %base_scalable, i64 1 %base_scalar = bitcast <vscale x 2 x double>* %base to double* diff --git a/llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll b/llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll index 6065dbdd2765..ed0c9f278f0a 100644 --- a/llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll +++ b/llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve --asm-verbose=false < %s 2>%t | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. @@ -11,13 +12,14 @@ define void @imm_out_of_range(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: imm_out_of_range: -; CHECK-NEXT: rdvl x8, #8 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ld1d { z[[DATA:[0-9]+]].d }, p0/z, [x{{[0-9]+}}] -; CHECK-NEXT: rdvl x8, #-9 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: st1d { z[[DATA]].d }, p0, [x{{[0-9]+}}] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: rdvl x8, #8 +; CHECK-NEXT: add x8, x0, x8 +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8] +; CHECK-NEXT: rdvl x8, #-9 +; CHECK-NEXT: add x8, x0, x8 +; CHECK-NEXT: st1d { z0.d }, p0, [x8] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 8 %data = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>* %base_load, i32 1, @@ -35,9 +37,10 @@ define void @imm_out_of_range(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mas define void @test_masked_ldst_sv2i8(<vscale x 2 x i8> * %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv2i8: -; CHECK-NEXT: ld1sb { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl] -; CHECK-NEXT: st1b { z[[DATA]].d }, p0, [x0, #-7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, #-8, mul vl] +; CHECK-NEXT: st1b { z0.d }, p0, [x0, #-7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 -8 %data = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>* %base_load, i32 1, @@ -53,9 +56,10 @@ define void @test_masked_ldst_sv2i8(<vscale x 2 x i8> * %base, <vscale x 2 x i1> define void @test_masked_ldst_sv2i16(<vscale x 2 x i16> * %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv2i16: -; CHECK-NEXT: ld1sh { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl] -; CHECK-NEXT: st1h { z[[DATA]].d }, p0, [x0, #-7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, #-8, mul vl] +; CHECK-NEXT: st1h { z0.d }, p0, [x0, #-7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 -8 %data = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>* %base_load, i32 1, @@ -72,9 +76,10 @@ define void @test_masked_ldst_sv2i16(<vscale x 2 x i16> * %base, <vscale x 2 x i define void @test_masked_ldst_sv2i32(<vscale x 2 x i32> * %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv2i32: -; CHECK-NEXT: ld1sw { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl] -; CHECK-NEXT: st1w { z[[DATA]].d }, p0, [x0, #-7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, #-8, mul vl] +; CHECK-NEXT: st1w { z0.d }, p0, [x0, #-7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 -8 %data = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>* %base_load, i32 1, @@ -90,9 +95,10 @@ define void @test_masked_ldst_sv2i32(<vscale x 2 x i32> * %base, <vscale x 2 x i define void @test_masked_ldst_sv2i64(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv2i64: -; CHECK-NEXT: ld1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl] -; CHECK-NEXT: st1d { z[[DATA]].d }, p0, [x0, #-7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #-8, mul vl] +; CHECK-NEXT: st1d { z0.d }, p0, [x0, #-7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 -8 %data = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>* %base_load, i32 1, @@ -108,9 +114,10 @@ define void @test_masked_ldst_sv2i64(<vscale x 2 x i64> * %base, <vscale x 2 x i define void @test_masked_ldst_sv2f16(<vscale x 2 x half> * %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv2f16: -; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl] -; CHECK-NEXT: st1h { z[[DATA]].d }, p0, [x0, #-7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #-8, mul vl] +; CHECK-NEXT: st1h { z0.d }, p0, [x0, #-7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x half>, <vscale x 2 x half>* %base, i64 -8 %data = call <vscale x 2 x half> @llvm.masked.load.nxv2f16(<vscale x 2 x half>* %base_load, i32 1, @@ -127,9 +134,10 @@ define void @test_masked_ldst_sv2f16(<vscale x 2 x half> * %base, <vscale x 2 x define void @test_masked_ldst_sv2f32(<vscale x 2 x float> * %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv2f32: -; CHECK-NEXT: ld1w { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl] -; CHECK-NEXT: st1w { z[[DATA]].d }, p0, [x0, #-7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, #-8, mul vl] +; CHECK-NEXT: st1w { z0.d }, p0, [x0, #-7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x float>, <vscale x 2 x float>* %base, i64 -8 %data = call <vscale x 2 x float> @llvm.masked.load.nxv2f32(<vscale x 2 x float>* %base_load, i32 1, @@ -145,9 +153,10 @@ define void @test_masked_ldst_sv2f32(<vscale x 2 x float> * %base, <vscale x 2 x define void @test_masked_ldst_sv2f64(<vscale x 2 x double> * %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv2f64: -; CHECK-NEXT: ld1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-6, mul vl] -; CHECK-NEXT: st1d { z[[DATA]].d }, p0, [x0, #-5, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, #-6, mul vl] +; CHECK-NEXT: st1d { z0.d }, p0, [x0, #-5, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %base, i64 -6 %data = call <vscale x 2 x double> @llvm.masked.load.nxv2f64(<vscale x 2 x double>* %base_load, i32 1, @@ -165,8 +174,9 @@ define void @test_masked_ldst_sv2f64(<vscale x 2 x double> * %base, <vscale x 2 define <vscale x 2 x i64> @masked_zload_sv2i8_to_sv2i64(<vscale x 2 x i8>* %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: masked_zload_sv2i8_to_sv2i64: -; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, #-4, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, #-4, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 -4 %load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>* %base_load, i32 1, @@ -178,8 +188,9 @@ define <vscale x 2 x i64> @masked_zload_sv2i8_to_sv2i64(<vscale x 2 x i8>* %base define <vscale x 2 x i64> @masked_sload_sv2i8_to_sv2i64(<vscale x 2 x i8>* %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: masked_sload_sv2i8_to_sv2i64: -; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, #-3, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0, #-3, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 -3 %load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>* %base_load, i32 1, @@ -191,8 +202,9 @@ define <vscale x 2 x i64> @masked_sload_sv2i8_to_sv2i64(<vscale x 2 x i8>* %base define <vscale x 2 x i64> @masked_zload_sv2i16_to_sv2i64(<vscale x 2 x i16>* %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: masked_zload_sv2i16_to_sv2i64: -; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #1, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #1, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 1 %load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>* %base_load, i32 1, @@ -204,8 +216,9 @@ define <vscale x 2 x i64> @masked_zload_sv2i16_to_sv2i64(<vscale x 2 x i16>* %ba define <vscale x 2 x i64> @masked_sload_sv2i16_to_sv2i64(<vscale x 2 x i16>* %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: masked_sload_sv2i16_to_sv2i64: -; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, #2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, #2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 2 %load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>* %base_load, i32 1, @@ -217,8 +230,9 @@ define <vscale x 2 x i64> @masked_sload_sv2i16_to_sv2i64(<vscale x 2 x i16>* %ba define <vscale x 2 x i64> @masked_zload_sv2i32_to_sv2i64(<vscale x 2 x i32>* %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: masked_zload_sv2i32_to_sv2i64: -; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, #-2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, #-2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 -2 %load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>* %base_load, i32 1, @@ -230,8 +244,9 @@ define <vscale x 2 x i64> @masked_zload_sv2i32_to_sv2i64(<vscale x 2 x i32>* %ba define <vscale x 2 x i64> @masked_sload_sv2i32_to_sv2i64(<vscale x 2 x i32>* %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: masked_sload_sv2i32_to_sv2i64: -; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, #-1, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, #-1, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 -1 %load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>* %base_load, i32 1, @@ -245,8 +260,9 @@ define <vscale x 2 x i64> @masked_sload_sv2i32_to_sv2i64(<vscale x 2 x i32>* %ba define void @masked_trunc_store_sv2i64_to_sv2i8(<vscale x 2 x i64> %val, <vscale x 2 x i8> *%base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: masked_trunc_store_sv2i64_to_sv2i8: -; CHECK-NEXT: st1b { z0.d }, p0, [x0, #3, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: st1b { z0.d }, p0, [x0, #3, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %base, i64 3 %trunc = trunc <vscale x 2 x i64> %val to <vscale x 2 x i8> call void @llvm.masked.store.nxv2i8(<vscale x 2 x i8> %trunc, @@ -259,8 +275,9 @@ define void @masked_trunc_store_sv2i64_to_sv2i8(<vscale x 2 x i64> %val, <vscale define void @masked_trunc_store_sv2i64_to_sv2i16(<vscale x 2 x i64> %val, <vscale x 2 x i16> *%base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: masked_trunc_store_sv2i64_to_sv2i16: -; CHECK-NEXT: st1h { z0.d }, p0, [x0, #4, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: st1h { z0.d }, p0, [x0, #4, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %base, i64 4 %trunc = trunc <vscale x 2 x i64> %val to <vscale x 2 x i16> call void @llvm.masked.store.nxv2i16(<vscale x 2 x i16> %trunc, @@ -272,8 +289,9 @@ define void @masked_trunc_store_sv2i64_to_sv2i16(<vscale x 2 x i64> %val, <vscal define void @masked_trunc_store_sv2i64_to_sv2i32(<vscale x 2 x i64> %val, <vscale x 2 x i32> *%base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: masked_trunc_store_sv2i64_to_sv2i32: -; CHECK-NEXT: st1w { z0.d }, p0, [x0, #5, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: st1w { z0.d }, p0, [x0, #5, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %base, i64 5 %trunc = trunc <vscale x 2 x i64> %val to <vscale x 2 x i32> call void @llvm.masked.store.nxv2i32(<vscale x 2 x i32> %trunc, @@ -287,9 +305,10 @@ define void @masked_trunc_store_sv2i64_to_sv2i32(<vscale x 2 x i64> %val, <vscal define void @test_masked_ldst_sv4i8(<vscale x 4 x i8> * %base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv4i8: -; CHECK-NEXT: ld1sb { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl] -; CHECK-NEXT: st1b { z[[DATA]].s }, p0, [x0, #2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0, #-1, mul vl] +; CHECK-NEXT: st1b { z0.s }, p0, [x0, #2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 -1 %data = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>* %base_load, i32 1, @@ -305,9 +324,10 @@ define void @test_masked_ldst_sv4i8(<vscale x 4 x i8> * %base, <vscale x 4 x i1> define void @test_masked_ldst_sv4i16(<vscale x 4 x i16> * %base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv4i16: -; CHECK-NEXT: ld1sh { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl] -; CHECK-NEXT: st1h { z[[DATA]].s }, p0, [x0, #2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, #-1, mul vl] +; CHECK-NEXT: st1h { z0.s }, p0, [x0, #2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 -1 %data = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>* %base_load, i32 1, @@ -323,9 +343,10 @@ define void @test_masked_ldst_sv4i16(<vscale x 4 x i16> * %base, <vscale x 4 x i define void @test_masked_ldst_sv4i32(<vscale x 4 x i32> * %base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv4i32: -; CHECK-NEXT: ld1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #6, mul vl] -; CHECK-NEXT: st1w { z[[DATA]].s }, p0, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, #6, mul vl] +; CHECK-NEXT: st1w { z0.s }, p0, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %base, i64 6 %data = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(<vscale x 4 x i32>* %base_load, i32 1, @@ -341,9 +362,10 @@ define void @test_masked_ldst_sv4i32(<vscale x 4 x i32> * %base, <vscale x 4 x i define void @test_masked_ldst_sv4f16(<vscale x 4 x half> * %base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv4f16: -; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl] -; CHECK-NEXT: st1h { z[[DATA]].s }, p0, [x0, #2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, #-1, mul vl] +; CHECK-NEXT: st1h { z0.s }, p0, [x0, #2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x half>, <vscale x 4 x half>* %base, i64 -1 %data = call <vscale x 4 x half> @llvm.masked.load.nxv4f16(<vscale x 4 x half>* %base_load, i32 1, @@ -359,9 +381,10 @@ define void @test_masked_ldst_sv4f16(<vscale x 4 x half> * %base, <vscale x 4 x define void @test_masked_ldst_sv4f32(<vscale x 4 x float> * %base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv4f32: -; CHECK-NEXT: ld1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl] -; CHECK-NEXT: st1w { z[[DATA]].s }, p0, [x0, #2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, #-1, mul vl] +; CHECK-NEXT: st1w { z0.s }, p0, [x0, #2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %base, i64 -1 %data = call <vscale x 4 x float> @llvm.masked.load.nxv4f32(<vscale x 4 x float>* %base_load, i32 1, @@ -379,8 +402,9 @@ define void @test_masked_ldst_sv4f32(<vscale x 4 x float> * %base, <vscale x 4 x define <vscale x 4 x i32> @masked_zload_sv4i8_to_sv4i32(<vscale x 4 x i8>* %base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: masked_zload_sv4i8_to_sv4i32: -; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, #-4, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, #-4, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 -4 %load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>* %base_load, i32 1, @@ -392,8 +416,9 @@ define <vscale x 4 x i32> @masked_zload_sv4i8_to_sv4i32(<vscale x 4 x i8>* %base define <vscale x 4 x i32> @masked_sload_sv4i8_to_sv4i32(<vscale x 4 x i8>* %base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: masked_sload_sv4i8_to_sv4i32: -; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0, #-3, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0, #-3, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 -3 %load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>* %base_load, i32 1, @@ -405,8 +430,9 @@ define <vscale x 4 x i32> @masked_sload_sv4i8_to_sv4i32(<vscale x 4 x i8>* %base define <vscale x 4 x i32> @masked_zload_sv4i16_to_sv4i32(<vscale x 4 x i16>* %base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: masked_zload_sv4i16_to_sv4i32: -; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, #1, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, #1, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 1 %load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>* %base_load, i32 1, @@ -418,8 +444,9 @@ define <vscale x 4 x i32> @masked_zload_sv4i16_to_sv4i32(<vscale x 4 x i16>* %ba define <vscale x 4 x i32> @masked_sload_sv4i16_to_sv4i32(<vscale x 4 x i16>* %base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: masked_sload_sv4i16_to_sv4i32: -; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, #2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, #2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 2 %load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>* %base_load, i32 1, @@ -433,8 +460,9 @@ define <vscale x 4 x i32> @masked_sload_sv4i16_to_sv4i32(<vscale x 4 x i16>* %ba define void @masked_trunc_store_sv4i32_to_sv4i8(<vscale x 4 x i32> %val, <vscale x 4 x i8> *%base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: masked_trunc_store_sv4i32_to_sv4i8: -; CHECK-NEXT: st1b { z0.s }, p0, [x0, #3, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: st1b { z0.s }, p0, [x0, #3, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %base, i64 3 %trunc = trunc <vscale x 4 x i32> %val to <vscale x 4 x i8> call void @llvm.masked.store.nxv4i8(<vscale x 4 x i8> %trunc, @@ -447,8 +475,9 @@ define void @masked_trunc_store_sv4i32_to_sv4i8(<vscale x 4 x i32> %val, <vscale define void @masked_trunc_store_sv4i32_to_sv4i16(<vscale x 4 x i32> %val, <vscale x 4 x i16> *%base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: masked_trunc_store_sv4i32_to_sv4i16: -; CHECK-NEXT: st1h { z0.s }, p0, [x0, #4, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: st1h { z0.s }, p0, [x0, #4, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %base, i64 4 %trunc = trunc <vscale x 4 x i32> %val to <vscale x 4 x i16> call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %trunc, @@ -462,9 +491,10 @@ define void @masked_trunc_store_sv4i32_to_sv4i16(<vscale x 4 x i32> %val, <vscal define void @test_masked_ldst_sv8i8(<vscale x 8 x i8> * %base, <vscale x 8 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv8i8: -; CHECK-NEXT: ld1sb { z[[DATA:[0-9]+]].h }, p0/z, [x0, #6, mul vl] -; CHECK-NEXT: st1b { z[[DATA]].h }, p0, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sb { z0.h }, p0/z, [x0, #6, mul vl] +; CHECK-NEXT: st1b { z0.h }, p0, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 6 %data = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>* %base_load, i32 1, @@ -480,9 +510,10 @@ define void @test_masked_ldst_sv8i8(<vscale x 8 x i8> * %base, <vscale x 8 x i1> define void @test_masked_ldst_sv8i16(<vscale x 8 x i16> * %base, <vscale x 8 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv8i16: -; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #6, mul vl] -; CHECK-NEXT: st1h { z[[DATA]].h }, p0, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, #6, mul vl] +; CHECK-NEXT: st1h { z0.h }, p0, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %base, i64 6 %data = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16(<vscale x 8 x i16>* %base_load, i32 1, @@ -498,9 +529,10 @@ define void @test_masked_ldst_sv8i16(<vscale x 8 x i16> * %base, <vscale x 8 x i define void @test_masked_ldst_sv8f16(<vscale x 8 x half> * %base, <vscale x 8 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv8f16: -; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl] -; CHECK-NEXT: st1h { z[[DATA]].h }, p0, [x0, #2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, #-1, mul vl] +; CHECK-NEXT: st1h { z0.h }, p0, [x0, #2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %base, i64 -1 %data = call <vscale x 8 x half> @llvm.masked.load.nxv8f16(<vscale x 8 x half>* %base_load, i32 1, @@ -516,9 +548,10 @@ define void @test_masked_ldst_sv8f16(<vscale x 8 x half> * %base, <vscale x 8 x define void @test_masked_ldst_sv8bf16(<vscale x 8 x bfloat> * %base, <vscale x 8 x i1> %mask) nounwind #0 { ; CHECK-LABEL: test_masked_ldst_sv8bf16: -; CHECK-NEXT: ld1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl] -; CHECK-NEXT: st1h { z[[DATA]].h }, p0, [x0, #2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, #-1, mul vl] +; CHECK-NEXT: st1h { z0.h }, p0, [x0, #2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %base, i64 -1 %data = call <vscale x 8 x bfloat> @llvm.masked.load.nxv8bf16(<vscale x 8 x bfloat>* %base_load, i32 1, @@ -536,8 +569,9 @@ define void @test_masked_ldst_sv8bf16(<vscale x 8 x bfloat> * %base, <vscale x 8 define <vscale x 8 x i16> @masked_zload_sv8i8_to_sv8i16(<vscale x 8 x i8>* %base, <vscale x 8 x i1> %mask) nounwind { ; CHECK-LABEL: masked_zload_sv8i8_to_sv8i16: -; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0, #-4, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0, #-4, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 -4 %load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>* %base_load, i32 1, @@ -549,8 +583,9 @@ define <vscale x 8 x i16> @masked_zload_sv8i8_to_sv8i16(<vscale x 8 x i8>* %base define <vscale x 8 x i16> @masked_sload_sv8i8_to_sv8i16(<vscale x 8 x i8>* %base, <vscale x 8 x i1> %mask) nounwind { ; CHECK-LABEL: masked_sload_sv8i8_to_sv8i16: -; CHECK-NEXT: ld1sb { z0.h }, p0/z, [x0, #-3, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1sb { z0.h }, p0/z, [x0, #-3, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 -3 %load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>* %base_load, i32 1, @@ -564,8 +599,9 @@ define <vscale x 8 x i16> @masked_sload_sv8i8_to_sv8i16(<vscale x 8 x i8>* %base define void @masked_trunc_store_sv8i16_to_sv8i8(<vscale x 8 x i16> %val, <vscale x 8 x i8> *%base, <vscale x 8 x i1> %mask) nounwind { ; CHECK-LABEL: masked_trunc_store_sv8i16_to_sv8i8: -; CHECK-NEXT: st1b { z0.h }, p0, [x0, #3, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: st1b { z0.h }, p0, [x0, #3, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %base, i64 3 %trunc = trunc <vscale x 8 x i16> %val to <vscale x 8 x i8> call void @llvm.masked.store.nxv8i8(<vscale x 8 x i8> %trunc, @@ -579,9 +615,10 @@ define void @masked_trunc_store_sv8i16_to_sv8i8(<vscale x 8 x i16> %val, <vscale define void @test_masked_ldst_sv16i8(<vscale x 16 x i8> * %base, <vscale x 16 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv16i8: -; CHECK-NEXT: ld1b { z[[DATA:[0-9]+]].b }, p0/z, [x0, #6, mul vl] -; CHECK-NEXT: st1b { z[[DATA]].b }, p0, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, #6, mul vl] +; CHECK-NEXT: st1b { z0.b }, p0, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base, i64 6 %data = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8(<vscale x 16 x i8>* %base_load, i32 1, diff --git a/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll b/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll index 6917d1d549ab..d4d0b965b235 100644 --- a/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll +++ b/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve --asm-verbose=false < %s 2>%t | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. @@ -11,13 +12,14 @@ define void @imm_out_of_range(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: imm_out_of_range: -; CHECK-NEXT: rdvl x8, #8 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x{{[0-9]+}}] -; CHECK-NEXT: rdvl x8, #-9 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x{{[0-9]+}}] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: rdvl x8, #8 +; CHECK-NEXT: add x8, x0, x8 +; CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x8] +; CHECK-NEXT: rdvl x8, #-9 +; CHECK-NEXT: add x8, x0, x8 +; CHECK-NEXT: stnt1d { z0.d }, p0, [x8] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 8 %base_load_bc = bitcast <vscale x 2 x i64>* %base_load to i64* %data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask, @@ -35,9 +37,10 @@ define void @imm_out_of_range(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mas define void @test_masked_ldst_sv2i64(<vscale x 2 x i64> * %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv2i64: -; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl] -; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, #-7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x0, #-8, mul vl] +; CHECK-NEXT: stnt1d { z0.d }, p0, [x0, #-7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, i64 -8 %base_load_bc = bitcast <vscale x 2 x i64>* %base_load to i64* %data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask, @@ -52,9 +55,10 @@ define void @test_masked_ldst_sv2i64(<vscale x 2 x i64> * %base, <vscale x 2 x i define void @test_masked_ldst_sv2f64(<vscale x 2 x double> * %base, <vscale x 2 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv2f64: -; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-6, mul vl] -; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, #-5, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x0, #-6, mul vl] +; CHECK-NEXT: stnt1d { z0.d }, p0, [x0, #-5, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %base, i64 -6 %base_load_bc = bitcast <vscale x 2 x double>* %base_load to double* %data = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1> %mask, @@ -71,9 +75,10 @@ define void @test_masked_ldst_sv2f64(<vscale x 2 x double> * %base, <vscale x 2 define void @test_masked_ldst_sv4i32(<vscale x 4 x i32> * %base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv4i32: -; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #6, mul vl] -; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0, #6, mul vl] +; CHECK-NEXT: stnt1w { z0.s }, p0, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %base, i64 6 %base_load_bc = bitcast <vscale x 4 x i32>* %base_load to i32* %data = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1> %mask, @@ -88,9 +93,10 @@ define void @test_masked_ldst_sv4i32(<vscale x 4 x i32> * %base, <vscale x 4 x i define void @test_masked_ldst_sv4f32(<vscale x 4 x float> * %base, <vscale x 4 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv4f32: -; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl] -; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, #2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0, #-1, mul vl] +; CHECK-NEXT: stnt1w { z0.s }, p0, [x0, #2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %base, i64 -1 %base_load_bc = bitcast <vscale x 4 x float>* %base_load to float* %data = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1> %mask, @@ -108,9 +114,10 @@ define void @test_masked_ldst_sv4f32(<vscale x 4 x float> * %base, <vscale x 4 x define void @test_masked_ldst_sv8i16(<vscale x 8 x i16> * %base, <vscale x 8 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv8i16: -; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #6, mul vl] -; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, #6, mul vl] +; CHECK-NEXT: stnt1h { z0.h }, p0, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %base, i64 6 %base_load_bc = bitcast <vscale x 8 x i16>* %base_load to i16* %data = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1> %mask, @@ -125,9 +132,10 @@ define void @test_masked_ldst_sv8i16(<vscale x 8 x i16> * %base, <vscale x 8 x i define void @test_masked_ldst_sv8f16(<vscale x 8 x half> * %base, <vscale x 8 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv8f16: -; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl] -; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, #-1, mul vl] +; CHECK-NEXT: stnt1h { z0.h }, p0, [x0, #2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %base, i64 -1 %base_load_bc = bitcast <vscale x 8 x half>* %base_load to half* %data = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1> %mask, @@ -142,9 +150,10 @@ define void @test_masked_ldst_sv8f16(<vscale x 8 x half> * %base, <vscale x 8 x define void @test_masked_ldst_sv8bf16(<vscale x 8 x bfloat> * %base, <vscale x 8 x i1> %mask) nounwind #0 { ; CHECK-LABEL: test_masked_ldst_sv8bf16: -; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, #-1, mul vl] -; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #2, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, #-1, mul vl] +; CHECK-NEXT: stnt1h { z0.h }, p0, [x0, #2, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 8 x bfloat>, <vscale x 8 x bfloat>* %base, i64 -1 %base_load_bc = bitcast <vscale x 8 x bfloat>* %base_load to bfloat* %data = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ldnt1.nxv8bf16(<vscale x 8 x i1> %mask, @@ -161,9 +170,10 @@ define void @test_masked_ldst_sv8bf16(<vscale x 8 x bfloat> * %base, <vscale x 8 define void @test_masked_ldst_sv16i8(<vscale x 16 x i8> * %base, <vscale x 16 x i1> %mask) nounwind { ; CHECK-LABEL: test_masked_ldst_sv16i8: -; CHECK-NEXT: ldnt1b { z[[DATA:[0-9]+]].b }, p0/z, [x0, #6, mul vl] -; CHECK-NEXT: stnt1b { z[[DATA]].b }, p0, [x0, #7, mul vl] -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ldnt1b { z0.b }, p0/z, [x0, #6, mul vl] +; CHECK-NEXT: stnt1b { z0.b }, p0, [x0, #7, mul vl] +; CHECK-NEXT: ret %base_load = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %base, i64 6 %base_load_bc = bitcast <vscale x 16 x i8>* %base_load to i8* %data = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1> %mask, _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
