date:20250915

[llvm-branch-commits] [llvm] release/21.x: [VPlan] Don't narrow op multiple times in narrowInterleaveGroups. (PR #158013)

2025-09-15 Thread Nikita Popov via llvm-branch-commits


https://github.com/nikic approved this pull request.


https://github.com/llvm/llvm-project/pull/158013
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[llvm-branch-commits] [llvm] CodeGen: Remove TRI argument from getRegClass (PR #158225)

2025-09-15 Thread via llvm-branch-commits


llvmbot wrote:




@llvm/pr-subscribers-backend-msp430

Author: Matt Arsenault (arsenm)


Changes

TargetInstrInfo now directly holds a reference to TargetRegisterInfo
and does not need TRI passed in anywhere.

---

Patch is 51.28 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/158225.diff


45 Files Affected:

- (modified) llvm/include/llvm/CodeGen/TargetInstrInfo.h (+2-3) 
- (modified) llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp (+2-2) 
- (modified) llvm/lib/CodeGen/BreakFalseDeps.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp (+2-2) 
- (modified) llvm/lib/CodeGen/GlobalISel/Utils.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/InitUndef.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/MachineInstr.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/MachineLICM.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/MachineVerifier.cpp (+4-7) 
- (modified) llvm/lib/CodeGen/RegisterCoalescer.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/SelectionDAG/FastISel.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (+4-5) 
- (modified) llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (+1-1) 
- (modified) llvm/lib/CodeGen/TargetInstrInfo.cpp (+2-3) 
- (modified) llvm/lib/CodeGen/TwoAddressInstructionPass.cpp (+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp (+4-6) 
- (modified) llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 
(+1-1) 
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+1-4) 
- (modified) llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp (+6-6) 
- (modified) llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp (+1-1) 
- (modified) llvm/lib/Target/AMDGPU/SIFoldOperands.cpp (+2-2) 
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+5-6) 
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+2-3) 
- (modified) llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp (+2-4) 
- (modified) llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp (+2-3) 
- (modified) llvm/lib/Target/ARM/ARMFrameLowering.cpp (+1-2) 
- (modified) llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (+4-4) 
- (modified) llvm/lib/Target/ARM/MLxExpansionPass.cpp (+1-1) 
- (modified) llvm/lib/Target/ARM/Thumb2InstrInfo.cpp (+1-1) 
- (modified) llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp (+1-1) 
- (modified) llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp (+2-2) 
- (modified) llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp (+2-2) 
- (modified) llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (+2-2) 
- (modified) llvm/lib/Target/LoongArch/LoongArchDeadRegisterDefinitions.cpp 
(+1-2) 
- (modified) llvm/lib/Target/Mips/MipsSEInstrInfo.cpp (+2-2) 
- (modified) llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp (+2-2) 
- (modified) llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp (+1-2) 
- (modified) llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp (+2-2) 
- (modified) llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp (+1-2) 
- (modified) llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp (+3-3) 
- (modified) llvm/lib/Target/X86/X86DomainReassignment.cpp (+2-2) 
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+12-14) 
- (modified) llvm/lib/Target/X86/X86InstrInfo.h (+2-3) 
- (modified) llvm/lib/Target/X86/X86OptimizeLEAs.cpp (+1-1) 
- (modified) llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp (+1-1) 


``diff
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h 
b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 802cca6022074..b333465e712b4 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -140,9 +140,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
 
   /// Given a machine instruction descriptor, returns the register
   /// class constraint for OpNum, or NULL.
-  virtual const TargetRegisterClass *
-  getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
-  const TargetRegisterInfo *TRI) const;
+  virtual const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID,
+ unsigned OpNum) const;
 
   /// Returns true if MI is an instruction we are unable to reason about
   /// (like a call or something with unmodeled side effects).
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp 
b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
index e0f80b0a57f2b..27c2c6a9162bc 100644
--- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -395,7 +395,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
 // Note register reference...
 const TargetRegisterClass *RC = nullptr;
 if (i < MI.getDesc().getNumOperands())
-  RC = TII->getRegClass(MI.getDesc(), i, TRI);
+  RC = TII->getRegClass(MI.getDesc(), i);
 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
 RegRefs.emplace(Reg.asMCReg(), RR);
   }
@@ -479,7 +479,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr 
&MI,
 // Note register reference...
 const Targ

[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


https://github.com/makslevental updated 
https://github.com/llvm/llvm-project/pull/157944

>From f9dbe48eaa691ca9f8161e9dc3a800bb613d5bc9 Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 12:57:54 -0700
Subject: [PATCH 01/14] [MLIR][Standalone] test Standalone against install
 distributions

---
 mlir/test/Examples/standalone/lit.local.cfg  |  2 ++
 .../Examples/standalone/test.toy.install-dir | 16 
 mlir/test/lit.cfg.py |  3 +++
 mlir/test/lit.site.cfg.py.in |  1 +
 4 files changed, 22 insertions(+)
 create mode 100644 mlir/test/Examples/standalone/test.toy.install-dir

diff --git a/mlir/test/Examples/standalone/lit.local.cfg 
b/mlir/test/Examples/standalone/lit.local.cfg
index fe8397c6b9a10..bc9928decf527 100644
--- a/mlir/test/Examples/standalone/lit.local.cfg
+++ b/mlir/test/Examples/standalone/lit.local.cfg
@@ -10,3 +10,5 @@ config.substitutions.append(("%host_cc", config.host_cc))
 config.substitutions.append(("%enable_libcxx", config.enable_libcxx))
 config.substitutions.append(("%mlir_cmake_dir", config.mlir_cmake_dir))
 config.substitutions.append(("%llvm_use_linker", config.llvm_use_linker))
+config.substitutions.append(("%llvm_obj_root", config.llvm_obj_root))
+config.substitutions.append(("%host_cmake_install_prefix", 
config.host_cmake_install_prefix))
diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.toy.install-dir
new file mode 100644
index 0..5c33a70491ae1
--- /dev/null
+++ b/mlir/test/Examples/standalone/test.toy.install-dir
@@ -0,0 +1,16 @@
+# REQUIRES: github-actions
+# RUN: "%cmake_exe" --build %llvm_obj_root --target install
+# RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
+# RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DLLVM_ENABLE_LIBCXX=%enable_libcxx 
-DMLIR_DIR=%host_cmake_install_prefix \
+# RUN: -DLLVM_USE_LINKER=%llvm_use_linker \
+# RUN: -DPython3_EXECUTABLE=%python \
+# RUN: -DPython_EXECUTABLE=%python
+# RUN: "%cmake_exe" --build . --target check-standalone | tee %t
+# RUN: FileCheck --input-file=%t %s
+
+# Note: The number of checked tests is not important. The command will fail
+# if any fail.
+# CHECK: Passed
+# CHECK-NOT: Failed
+# UNSUPPORTED: target={{.*(windows|android).*}}
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index f99c24d6e299a..08c7947c1e9a6 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -383,3 +383,6 @@ def have_host_jit_feature_support(feature_name):
 
 if sys.version_info >= (3, 11):
 config.available_features.add("python-ge-311")
+
+if "GITHUB_ACTIONS" in os.environ:
+config.available_features.add("github-actions")
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 8a742a227847b..7e22ebf23c773 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -18,6 +18,7 @@ config.host_cxx = "@HOST_CXX@"
 config.enable_libcxx = "@LLVM_ENABLE_LIBCXX@"
 config.host_cmake = "@CMAKE_COMMAND@"
 config.host_cmake_generator = "@CMAKE_GENERATOR@"
+config.host_cmake_install_prefix = "@CMAKE_INSTALL_PREFIX@"
 config.llvm_use_linker = "@LLVM_USE_LINKER@"
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.host_arch = "@HOST_ARCH@"

>From fc56d49c9481aed16b79f391368f4c3824a90695 Mon Sep 17 00:00:00 2001
From: Maksim Levental 
Date: Wed, 10 Sep 2025 13:23:07 -0700
Subject: [PATCH 02/14] Update lit.site.cfg.py.in

---
 .../standalone/{test.toy.install-dir => test.install-dir.toy}| 0
 mlir/test/lit.site.cfg.py.in | 1 +
 2 files changed, 1 insertion(+)
 rename mlir/test/Examples/standalone/{test.toy.install-dir => 
test.install-dir.toy} (100%)

diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.install-dir.toy
similarity index 100%
rename from mlir/test/Examples/standalone/test.toy.install-dir
rename to mlir/test/Examples/standalone/test.install-dir.toy
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 7e22ebf23c773..eadfd047d15f7 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -3,6 +3,7 @@
 import sys
 
 config.target_triple = "@LLVM_TARGET_TRIPLE@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_tools_dir = lit_config.substitute("@LLVM_TOOLS_DIR@")
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"

>From 67ce5b688657d38b6792b05712d1de6f56e726fe Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 15:54:54 -0700
Subject: [PATCH 03/14] add test.install-distribution-dir.toy

---
 mlir/test/Examples/standalone/lit.local.cfg |  1 +
 .../Examples/standalone/test.install-dir.toy|  4 ++--
 .../test.install-distribution-dir.toy   | 17 +
 3 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 
mlir/test/Examples/stand

[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


https://github.com/makslevental updated 
https://github.com/llvm/llvm-project/pull/157944

>From f9dbe48eaa691ca9f8161e9dc3a800bb613d5bc9 Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 12:57:54 -0700
Subject: [PATCH 01/14] [MLIR][Standalone] test Standalone against install
 distributions

---
 mlir/test/Examples/standalone/lit.local.cfg  |  2 ++
 .../Examples/standalone/test.toy.install-dir | 16 
 mlir/test/lit.cfg.py |  3 +++
 mlir/test/lit.site.cfg.py.in |  1 +
 4 files changed, 22 insertions(+)
 create mode 100644 mlir/test/Examples/standalone/test.toy.install-dir

diff --git a/mlir/test/Examples/standalone/lit.local.cfg 
b/mlir/test/Examples/standalone/lit.local.cfg
index fe8397c6b9a10..bc9928decf527 100644
--- a/mlir/test/Examples/standalone/lit.local.cfg
+++ b/mlir/test/Examples/standalone/lit.local.cfg
@@ -10,3 +10,5 @@ config.substitutions.append(("%host_cc", config.host_cc))
 config.substitutions.append(("%enable_libcxx", config.enable_libcxx))
 config.substitutions.append(("%mlir_cmake_dir", config.mlir_cmake_dir))
 config.substitutions.append(("%llvm_use_linker", config.llvm_use_linker))
+config.substitutions.append(("%llvm_obj_root", config.llvm_obj_root))
+config.substitutions.append(("%host_cmake_install_prefix", 
config.host_cmake_install_prefix))
diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.toy.install-dir
new file mode 100644
index 0..5c33a70491ae1
--- /dev/null
+++ b/mlir/test/Examples/standalone/test.toy.install-dir
@@ -0,0 +1,16 @@
+# REQUIRES: github-actions
+# RUN: "%cmake_exe" --build %llvm_obj_root --target install
+# RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
+# RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DLLVM_ENABLE_LIBCXX=%enable_libcxx 
-DMLIR_DIR=%host_cmake_install_prefix \
+# RUN: -DLLVM_USE_LINKER=%llvm_use_linker \
+# RUN: -DPython3_EXECUTABLE=%python \
+# RUN: -DPython_EXECUTABLE=%python
+# RUN: "%cmake_exe" --build . --target check-standalone | tee %t
+# RUN: FileCheck --input-file=%t %s
+
+# Note: The number of checked tests is not important. The command will fail
+# if any fail.
+# CHECK: Passed
+# CHECK-NOT: Failed
+# UNSUPPORTED: target={{.*(windows|android).*}}
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index f99c24d6e299a..08c7947c1e9a6 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -383,3 +383,6 @@ def have_host_jit_feature_support(feature_name):
 
 if sys.version_info >= (3, 11):
 config.available_features.add("python-ge-311")
+
+if "GITHUB_ACTIONS" in os.environ:
+config.available_features.add("github-actions")
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 8a742a227847b..7e22ebf23c773 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -18,6 +18,7 @@ config.host_cxx = "@HOST_CXX@"
 config.enable_libcxx = "@LLVM_ENABLE_LIBCXX@"
 config.host_cmake = "@CMAKE_COMMAND@"
 config.host_cmake_generator = "@CMAKE_GENERATOR@"
+config.host_cmake_install_prefix = "@CMAKE_INSTALL_PREFIX@"
 config.llvm_use_linker = "@LLVM_USE_LINKER@"
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.host_arch = "@HOST_ARCH@"

>From fc56d49c9481aed16b79f391368f4c3824a90695 Mon Sep 17 00:00:00 2001
From: Maksim Levental 
Date: Wed, 10 Sep 2025 13:23:07 -0700
Subject: [PATCH 02/14] Update lit.site.cfg.py.in

---
 .../standalone/{test.toy.install-dir => test.install-dir.toy}| 0
 mlir/test/lit.site.cfg.py.in | 1 +
 2 files changed, 1 insertion(+)
 rename mlir/test/Examples/standalone/{test.toy.install-dir => 
test.install-dir.toy} (100%)

diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.install-dir.toy
similarity index 100%
rename from mlir/test/Examples/standalone/test.toy.install-dir
rename to mlir/test/Examples/standalone/test.install-dir.toy
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 7e22ebf23c773..eadfd047d15f7 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -3,6 +3,7 @@
 import sys
 
 config.target_triple = "@LLVM_TARGET_TRIPLE@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_tools_dir = lit_config.substitute("@LLVM_TOOLS_DIR@")
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"

>From 67ce5b688657d38b6792b05712d1de6f56e726fe Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 15:54:54 -0700
Subject: [PATCH 03/14] add test.install-distribution-dir.toy

---
 mlir/test/Examples/standalone/lit.local.cfg |  1 +
 .../Examples/standalone/test.install-dir.toy|  4 ++--
 .../test.install-distribution-dir.toy   | 17 +
 3 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 
mlir/test/Examples/stand

[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


makslevental wrote:

I've refactored the test to work exactly like the `libcxx` tests. It now runs 
as quickly as the other standalone test:

```
13.38s: MLIR :: Examples/standalone/test.toy
12.82s: MLIR :: Examples/standalone/test.install-dir.toy
```

@boomanaiden154 @christopherbate any other TODOs here?

https://github.com/llvm/llvm-project/pull/157944
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[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


https://github.com/makslevental updated 
https://github.com/llvm/llvm-project/pull/157944

>From f9dbe48eaa691ca9f8161e9dc3a800bb613d5bc9 Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 12:57:54 -0700
Subject: [PATCH 01/14] [MLIR][Standalone] test Standalone against install
 distributions

---
 mlir/test/Examples/standalone/lit.local.cfg  |  2 ++
 .../Examples/standalone/test.toy.install-dir | 16 
 mlir/test/lit.cfg.py |  3 +++
 mlir/test/lit.site.cfg.py.in |  1 +
 4 files changed, 22 insertions(+)
 create mode 100644 mlir/test/Examples/standalone/test.toy.install-dir

diff --git a/mlir/test/Examples/standalone/lit.local.cfg 
b/mlir/test/Examples/standalone/lit.local.cfg
index fe8397c6b9a10..bc9928decf527 100644
--- a/mlir/test/Examples/standalone/lit.local.cfg
+++ b/mlir/test/Examples/standalone/lit.local.cfg
@@ -10,3 +10,5 @@ config.substitutions.append(("%host_cc", config.host_cc))
 config.substitutions.append(("%enable_libcxx", config.enable_libcxx))
 config.substitutions.append(("%mlir_cmake_dir", config.mlir_cmake_dir))
 config.substitutions.append(("%llvm_use_linker", config.llvm_use_linker))
+config.substitutions.append(("%llvm_obj_root", config.llvm_obj_root))
+config.substitutions.append(("%host_cmake_install_prefix", 
config.host_cmake_install_prefix))
diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.toy.install-dir
new file mode 100644
index 0..5c33a70491ae1
--- /dev/null
+++ b/mlir/test/Examples/standalone/test.toy.install-dir
@@ -0,0 +1,16 @@
+# REQUIRES: github-actions
+# RUN: "%cmake_exe" --build %llvm_obj_root --target install
+# RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
+# RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DLLVM_ENABLE_LIBCXX=%enable_libcxx 
-DMLIR_DIR=%host_cmake_install_prefix \
+# RUN: -DLLVM_USE_LINKER=%llvm_use_linker \
+# RUN: -DPython3_EXECUTABLE=%python \
+# RUN: -DPython_EXECUTABLE=%python
+# RUN: "%cmake_exe" --build . --target check-standalone | tee %t
+# RUN: FileCheck --input-file=%t %s
+
+# Note: The number of checked tests is not important. The command will fail
+# if any fail.
+# CHECK: Passed
+# CHECK-NOT: Failed
+# UNSUPPORTED: target={{.*(windows|android).*}}
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index f99c24d6e299a..08c7947c1e9a6 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -383,3 +383,6 @@ def have_host_jit_feature_support(feature_name):
 
 if sys.version_info >= (3, 11):
 config.available_features.add("python-ge-311")
+
+if "GITHUB_ACTIONS" in os.environ:
+config.available_features.add("github-actions")
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 8a742a227847b..7e22ebf23c773 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -18,6 +18,7 @@ config.host_cxx = "@HOST_CXX@"
 config.enable_libcxx = "@LLVM_ENABLE_LIBCXX@"
 config.host_cmake = "@CMAKE_COMMAND@"
 config.host_cmake_generator = "@CMAKE_GENERATOR@"
+config.host_cmake_install_prefix = "@CMAKE_INSTALL_PREFIX@"
 config.llvm_use_linker = "@LLVM_USE_LINKER@"
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.host_arch = "@HOST_ARCH@"

>From fc56d49c9481aed16b79f391368f4c3824a90695 Mon Sep 17 00:00:00 2001
From: Maksim Levental 
Date: Wed, 10 Sep 2025 13:23:07 -0700
Subject: [PATCH 02/14] Update lit.site.cfg.py.in

---
 .../standalone/{test.toy.install-dir => test.install-dir.toy}| 0
 mlir/test/lit.site.cfg.py.in | 1 +
 2 files changed, 1 insertion(+)
 rename mlir/test/Examples/standalone/{test.toy.install-dir => 
test.install-dir.toy} (100%)

diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.install-dir.toy
similarity index 100%
rename from mlir/test/Examples/standalone/test.toy.install-dir
rename to mlir/test/Examples/standalone/test.install-dir.toy
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 7e22ebf23c773..eadfd047d15f7 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -3,6 +3,7 @@
 import sys
 
 config.target_triple = "@LLVM_TARGET_TRIPLE@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_tools_dir = lit_config.substitute("@LLVM_TOOLS_DIR@")
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"

>From 67ce5b688657d38b6792b05712d1de6f56e726fe Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 15:54:54 -0700
Subject: [PATCH 03/14] add test.install-distribution-dir.toy

---
 mlir/test/Examples/standalone/lit.local.cfg |  1 +
 .../Examples/standalone/test.install-dir.toy|  4 ++--
 .../test.install-distribution-dir.toy   | 17 +
 3 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 
mlir/test/Examples/stand

[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


https://github.com/makslevental updated 
https://github.com/llvm/llvm-project/pull/157944

>From f9dbe48eaa691ca9f8161e9dc3a800bb613d5bc9 Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 12:57:54 -0700
Subject: [PATCH 01/14] [MLIR][Standalone] test Standalone against install
 distributions

---
 mlir/test/Examples/standalone/lit.local.cfg  |  2 ++
 .../Examples/standalone/test.toy.install-dir | 16 
 mlir/test/lit.cfg.py |  3 +++
 mlir/test/lit.site.cfg.py.in |  1 +
 4 files changed, 22 insertions(+)
 create mode 100644 mlir/test/Examples/standalone/test.toy.install-dir

diff --git a/mlir/test/Examples/standalone/lit.local.cfg 
b/mlir/test/Examples/standalone/lit.local.cfg
index fe8397c6b9a10..bc9928decf527 100644
--- a/mlir/test/Examples/standalone/lit.local.cfg
+++ b/mlir/test/Examples/standalone/lit.local.cfg
@@ -10,3 +10,5 @@ config.substitutions.append(("%host_cc", config.host_cc))
 config.substitutions.append(("%enable_libcxx", config.enable_libcxx))
 config.substitutions.append(("%mlir_cmake_dir", config.mlir_cmake_dir))
 config.substitutions.append(("%llvm_use_linker", config.llvm_use_linker))
+config.substitutions.append(("%llvm_obj_root", config.llvm_obj_root))
+config.substitutions.append(("%host_cmake_install_prefix", 
config.host_cmake_install_prefix))
diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.toy.install-dir
new file mode 100644
index 0..5c33a70491ae1
--- /dev/null
+++ b/mlir/test/Examples/standalone/test.toy.install-dir
@@ -0,0 +1,16 @@
+# REQUIRES: github-actions
+# RUN: "%cmake_exe" --build %llvm_obj_root --target install
+# RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
+# RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DLLVM_ENABLE_LIBCXX=%enable_libcxx 
-DMLIR_DIR=%host_cmake_install_prefix \
+# RUN: -DLLVM_USE_LINKER=%llvm_use_linker \
+# RUN: -DPython3_EXECUTABLE=%python \
+# RUN: -DPython_EXECUTABLE=%python
+# RUN: "%cmake_exe" --build . --target check-standalone | tee %t
+# RUN: FileCheck --input-file=%t %s
+
+# Note: The number of checked tests is not important. The command will fail
+# if any fail.
+# CHECK: Passed
+# CHECK-NOT: Failed
+# UNSUPPORTED: target={{.*(windows|android).*}}
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index f99c24d6e299a..08c7947c1e9a6 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -383,3 +383,6 @@ def have_host_jit_feature_support(feature_name):
 
 if sys.version_info >= (3, 11):
 config.available_features.add("python-ge-311")
+
+if "GITHUB_ACTIONS" in os.environ:
+config.available_features.add("github-actions")
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 8a742a227847b..7e22ebf23c773 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -18,6 +18,7 @@ config.host_cxx = "@HOST_CXX@"
 config.enable_libcxx = "@LLVM_ENABLE_LIBCXX@"
 config.host_cmake = "@CMAKE_COMMAND@"
 config.host_cmake_generator = "@CMAKE_GENERATOR@"
+config.host_cmake_install_prefix = "@CMAKE_INSTALL_PREFIX@"
 config.llvm_use_linker = "@LLVM_USE_LINKER@"
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.host_arch = "@HOST_ARCH@"

>From fc56d49c9481aed16b79f391368f4c3824a90695 Mon Sep 17 00:00:00 2001
From: Maksim Levental 
Date: Wed, 10 Sep 2025 13:23:07 -0700
Subject: [PATCH 02/14] Update lit.site.cfg.py.in

---
 .../standalone/{test.toy.install-dir => test.install-dir.toy}| 0
 mlir/test/lit.site.cfg.py.in | 1 +
 2 files changed, 1 insertion(+)
 rename mlir/test/Examples/standalone/{test.toy.install-dir => 
test.install-dir.toy} (100%)

diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.install-dir.toy
similarity index 100%
rename from mlir/test/Examples/standalone/test.toy.install-dir
rename to mlir/test/Examples/standalone/test.install-dir.toy
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 7e22ebf23c773..eadfd047d15f7 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -3,6 +3,7 @@
 import sys
 
 config.target_triple = "@LLVM_TARGET_TRIPLE@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_tools_dir = lit_config.substitute("@LLVM_TOOLS_DIR@")
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"

>From 67ce5b688657d38b6792b05712d1de6f56e726fe Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 15:54:54 -0700
Subject: [PATCH 03/14] add test.install-distribution-dir.toy

---
 mlir/test/Examples/standalone/lit.local.cfg |  1 +
 .../Examples/standalone/test.install-dir.toy|  4 ++--
 .../test.install-distribution-dir.toy   | 17 +
 3 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 
mlir/test/Examples/stand

[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


https://github.com/makslevental updated 
https://github.com/llvm/llvm-project/pull/157944

>From f9dbe48eaa691ca9f8161e9dc3a800bb613d5bc9 Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 12:57:54 -0700
Subject: [PATCH 01/14] [MLIR][Standalone] test Standalone against install
 distributions

---
 mlir/test/Examples/standalone/lit.local.cfg  |  2 ++
 .../Examples/standalone/test.toy.install-dir | 16 
 mlir/test/lit.cfg.py |  3 +++
 mlir/test/lit.site.cfg.py.in |  1 +
 4 files changed, 22 insertions(+)
 create mode 100644 mlir/test/Examples/standalone/test.toy.install-dir

diff --git a/mlir/test/Examples/standalone/lit.local.cfg 
b/mlir/test/Examples/standalone/lit.local.cfg
index fe8397c6b9a10..bc9928decf527 100644
--- a/mlir/test/Examples/standalone/lit.local.cfg
+++ b/mlir/test/Examples/standalone/lit.local.cfg
@@ -10,3 +10,5 @@ config.substitutions.append(("%host_cc", config.host_cc))
 config.substitutions.append(("%enable_libcxx", config.enable_libcxx))
 config.substitutions.append(("%mlir_cmake_dir", config.mlir_cmake_dir))
 config.substitutions.append(("%llvm_use_linker", config.llvm_use_linker))
+config.substitutions.append(("%llvm_obj_root", config.llvm_obj_root))
+config.substitutions.append(("%host_cmake_install_prefix", 
config.host_cmake_install_prefix))
diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.toy.install-dir
new file mode 100644
index 0..5c33a70491ae1
--- /dev/null
+++ b/mlir/test/Examples/standalone/test.toy.install-dir
@@ -0,0 +1,16 @@
+# REQUIRES: github-actions
+# RUN: "%cmake_exe" --build %llvm_obj_root --target install
+# RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
+# RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DLLVM_ENABLE_LIBCXX=%enable_libcxx 
-DMLIR_DIR=%host_cmake_install_prefix \
+# RUN: -DLLVM_USE_LINKER=%llvm_use_linker \
+# RUN: -DPython3_EXECUTABLE=%python \
+# RUN: -DPython_EXECUTABLE=%python
+# RUN: "%cmake_exe" --build . --target check-standalone | tee %t
+# RUN: FileCheck --input-file=%t %s
+
+# Note: The number of checked tests is not important. The command will fail
+# if any fail.
+# CHECK: Passed
+# CHECK-NOT: Failed
+# UNSUPPORTED: target={{.*(windows|android).*}}
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index f99c24d6e299a..08c7947c1e9a6 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -383,3 +383,6 @@ def have_host_jit_feature_support(feature_name):
 
 if sys.version_info >= (3, 11):
 config.available_features.add("python-ge-311")
+
+if "GITHUB_ACTIONS" in os.environ:
+config.available_features.add("github-actions")
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 8a742a227847b..7e22ebf23c773 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -18,6 +18,7 @@ config.host_cxx = "@HOST_CXX@"
 config.enable_libcxx = "@LLVM_ENABLE_LIBCXX@"
 config.host_cmake = "@CMAKE_COMMAND@"
 config.host_cmake_generator = "@CMAKE_GENERATOR@"
+config.host_cmake_install_prefix = "@CMAKE_INSTALL_PREFIX@"
 config.llvm_use_linker = "@LLVM_USE_LINKER@"
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.host_arch = "@HOST_ARCH@"

>From fc56d49c9481aed16b79f391368f4c3824a90695 Mon Sep 17 00:00:00 2001
From: Maksim Levental 
Date: Wed, 10 Sep 2025 13:23:07 -0700
Subject: [PATCH 02/14] Update lit.site.cfg.py.in

---
 .../standalone/{test.toy.install-dir => test.install-dir.toy}| 0
 mlir/test/lit.site.cfg.py.in | 1 +
 2 files changed, 1 insertion(+)
 rename mlir/test/Examples/standalone/{test.toy.install-dir => 
test.install-dir.toy} (100%)

diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.install-dir.toy
similarity index 100%
rename from mlir/test/Examples/standalone/test.toy.install-dir
rename to mlir/test/Examples/standalone/test.install-dir.toy
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 7e22ebf23c773..eadfd047d15f7 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -3,6 +3,7 @@
 import sys
 
 config.target_triple = "@LLVM_TARGET_TRIPLE@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_tools_dir = lit_config.substitute("@LLVM_TOOLS_DIR@")
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"

>From 67ce5b688657d38b6792b05712d1de6f56e726fe Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 15:54:54 -0700
Subject: [PATCH 03/14] add test.install-distribution-dir.toy

---
 mlir/test/Examples/standalone/lit.local.cfg |  1 +
 .../Examples/standalone/test.install-dir.toy|  4 ++--
 .../test.install-distribution-dir.toy   | 17 +
 3 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 
mlir/test/Examples/stand

[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits



@@ -1,5 +1,6 @@
 # RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
 # RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DCMAKE_CXX_COMPILER_LAUNCHER=%cmake_cxx_compiler_launcher 
-DCMAKE_C_COMPILER_LAUNCHER=%cmake_c_compiler_launcher \

boomanaiden154 wrote:

Can this be dropped now that we aren't doing any substantial compilation?

https://github.com/llvm/llvm-project/pull/157944
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[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits


https://github.com/boomanaiden154 commented:

Given this runs quickly and doesn't need any special handling around 
`CMAKE_INSTALL_PREFIX`, I think we can probably drop the 
`MLIR_RUN_STANDALONE_INSTALL_TEST` CMake option and associated 
`run-standalone-install-test` lit option to cut down a bit on complexity. 
Although not a big deal if we keep them.

https://github.com/llvm/llvm-project/pull/157944
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[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


https://github.com/makslevental updated 
https://github.com/llvm/llvm-project/pull/157944

>From f9dbe48eaa691ca9f8161e9dc3a800bb613d5bc9 Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 12:57:54 -0700
Subject: [PATCH 01/14] [MLIR][Standalone] test Standalone against install
 distributions

---
 mlir/test/Examples/standalone/lit.local.cfg  |  2 ++
 .../Examples/standalone/test.toy.install-dir | 16 
 mlir/test/lit.cfg.py |  3 +++
 mlir/test/lit.site.cfg.py.in |  1 +
 4 files changed, 22 insertions(+)
 create mode 100644 mlir/test/Examples/standalone/test.toy.install-dir

diff --git a/mlir/test/Examples/standalone/lit.local.cfg 
b/mlir/test/Examples/standalone/lit.local.cfg
index fe8397c6b9a10..bc9928decf527 100644
--- a/mlir/test/Examples/standalone/lit.local.cfg
+++ b/mlir/test/Examples/standalone/lit.local.cfg
@@ -10,3 +10,5 @@ config.substitutions.append(("%host_cc", config.host_cc))
 config.substitutions.append(("%enable_libcxx", config.enable_libcxx))
 config.substitutions.append(("%mlir_cmake_dir", config.mlir_cmake_dir))
 config.substitutions.append(("%llvm_use_linker", config.llvm_use_linker))
+config.substitutions.append(("%llvm_obj_root", config.llvm_obj_root))
+config.substitutions.append(("%host_cmake_install_prefix", 
config.host_cmake_install_prefix))
diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.toy.install-dir
new file mode 100644
index 0..5c33a70491ae1
--- /dev/null
+++ b/mlir/test/Examples/standalone/test.toy.install-dir
@@ -0,0 +1,16 @@
+# REQUIRES: github-actions
+# RUN: "%cmake_exe" --build %llvm_obj_root --target install
+# RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
+# RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DLLVM_ENABLE_LIBCXX=%enable_libcxx 
-DMLIR_DIR=%host_cmake_install_prefix \
+# RUN: -DLLVM_USE_LINKER=%llvm_use_linker \
+# RUN: -DPython3_EXECUTABLE=%python \
+# RUN: -DPython_EXECUTABLE=%python
+# RUN: "%cmake_exe" --build . --target check-standalone | tee %t
+# RUN: FileCheck --input-file=%t %s
+
+# Note: The number of checked tests is not important. The command will fail
+# if any fail.
+# CHECK: Passed
+# CHECK-NOT: Failed
+# UNSUPPORTED: target={{.*(windows|android).*}}
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index f99c24d6e299a..08c7947c1e9a6 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -383,3 +383,6 @@ def have_host_jit_feature_support(feature_name):
 
 if sys.version_info >= (3, 11):
 config.available_features.add("python-ge-311")
+
+if "GITHUB_ACTIONS" in os.environ:
+config.available_features.add("github-actions")
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 8a742a227847b..7e22ebf23c773 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -18,6 +18,7 @@ config.host_cxx = "@HOST_CXX@"
 config.enable_libcxx = "@LLVM_ENABLE_LIBCXX@"
 config.host_cmake = "@CMAKE_COMMAND@"
 config.host_cmake_generator = "@CMAKE_GENERATOR@"
+config.host_cmake_install_prefix = "@CMAKE_INSTALL_PREFIX@"
 config.llvm_use_linker = "@LLVM_USE_LINKER@"
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.host_arch = "@HOST_ARCH@"

>From fc56d49c9481aed16b79f391368f4c3824a90695 Mon Sep 17 00:00:00 2001
From: Maksim Levental 
Date: Wed, 10 Sep 2025 13:23:07 -0700
Subject: [PATCH 02/14] Update lit.site.cfg.py.in

---
 .../standalone/{test.toy.install-dir => test.install-dir.toy}| 0
 mlir/test/lit.site.cfg.py.in | 1 +
 2 files changed, 1 insertion(+)
 rename mlir/test/Examples/standalone/{test.toy.install-dir => 
test.install-dir.toy} (100%)

diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.install-dir.toy
similarity index 100%
rename from mlir/test/Examples/standalone/test.toy.install-dir
rename to mlir/test/Examples/standalone/test.install-dir.toy
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 7e22ebf23c773..eadfd047d15f7 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -3,6 +3,7 @@
 import sys
 
 config.target_triple = "@LLVM_TARGET_TRIPLE@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_tools_dir = lit_config.substitute("@LLVM_TOOLS_DIR@")
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"

>From 67ce5b688657d38b6792b05712d1de6f56e726fe Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 15:54:54 -0700
Subject: [PATCH 03/14] add test.install-distribution-dir.toy

---
 mlir/test/Examples/standalone/lit.local.cfg |  1 +
 .../Examples/standalone/test.install-dir.toy|  4 ++--
 .../test.install-distribution-dir.toy   | 17 +
 3 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 
mlir/test/Examples/stand

[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


https://github.com/makslevental updated 
https://github.com/llvm/llvm-project/pull/157944

>From f9dbe48eaa691ca9f8161e9dc3a800bb613d5bc9 Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 12:57:54 -0700
Subject: [PATCH 01/14] [MLIR][Standalone] test Standalone against install
 distributions

---
 mlir/test/Examples/standalone/lit.local.cfg  |  2 ++
 .../Examples/standalone/test.toy.install-dir | 16 
 mlir/test/lit.cfg.py |  3 +++
 mlir/test/lit.site.cfg.py.in |  1 +
 4 files changed, 22 insertions(+)
 create mode 100644 mlir/test/Examples/standalone/test.toy.install-dir

diff --git a/mlir/test/Examples/standalone/lit.local.cfg 
b/mlir/test/Examples/standalone/lit.local.cfg
index fe8397c6b9a10..bc9928decf527 100644
--- a/mlir/test/Examples/standalone/lit.local.cfg
+++ b/mlir/test/Examples/standalone/lit.local.cfg
@@ -10,3 +10,5 @@ config.substitutions.append(("%host_cc", config.host_cc))
 config.substitutions.append(("%enable_libcxx", config.enable_libcxx))
 config.substitutions.append(("%mlir_cmake_dir", config.mlir_cmake_dir))
 config.substitutions.append(("%llvm_use_linker", config.llvm_use_linker))
+config.substitutions.append(("%llvm_obj_root", config.llvm_obj_root))
+config.substitutions.append(("%host_cmake_install_prefix", 
config.host_cmake_install_prefix))
diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.toy.install-dir
new file mode 100644
index 0..5c33a70491ae1
--- /dev/null
+++ b/mlir/test/Examples/standalone/test.toy.install-dir
@@ -0,0 +1,16 @@
+# REQUIRES: github-actions
+# RUN: "%cmake_exe" --build %llvm_obj_root --target install
+# RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
+# RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DLLVM_ENABLE_LIBCXX=%enable_libcxx 
-DMLIR_DIR=%host_cmake_install_prefix \
+# RUN: -DLLVM_USE_LINKER=%llvm_use_linker \
+# RUN: -DPython3_EXECUTABLE=%python \
+# RUN: -DPython_EXECUTABLE=%python
+# RUN: "%cmake_exe" --build . --target check-standalone | tee %t
+# RUN: FileCheck --input-file=%t %s
+
+# Note: The number of checked tests is not important. The command will fail
+# if any fail.
+# CHECK: Passed
+# CHECK-NOT: Failed
+# UNSUPPORTED: target={{.*(windows|android).*}}
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index f99c24d6e299a..08c7947c1e9a6 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -383,3 +383,6 @@ def have_host_jit_feature_support(feature_name):
 
 if sys.version_info >= (3, 11):
 config.available_features.add("python-ge-311")
+
+if "GITHUB_ACTIONS" in os.environ:
+config.available_features.add("github-actions")
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 8a742a227847b..7e22ebf23c773 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -18,6 +18,7 @@ config.host_cxx = "@HOST_CXX@"
 config.enable_libcxx = "@LLVM_ENABLE_LIBCXX@"
 config.host_cmake = "@CMAKE_COMMAND@"
 config.host_cmake_generator = "@CMAKE_GENERATOR@"
+config.host_cmake_install_prefix = "@CMAKE_INSTALL_PREFIX@"
 config.llvm_use_linker = "@LLVM_USE_LINKER@"
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.host_arch = "@HOST_ARCH@"

>From fc56d49c9481aed16b79f391368f4c3824a90695 Mon Sep 17 00:00:00 2001
From: Maksim Levental 
Date: Wed, 10 Sep 2025 13:23:07 -0700
Subject: [PATCH 02/14] Update lit.site.cfg.py.in

---
 .../standalone/{test.toy.install-dir => test.install-dir.toy}| 0
 mlir/test/lit.site.cfg.py.in | 1 +
 2 files changed, 1 insertion(+)
 rename mlir/test/Examples/standalone/{test.toy.install-dir => 
test.install-dir.toy} (100%)

diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.install-dir.toy
similarity index 100%
rename from mlir/test/Examples/standalone/test.toy.install-dir
rename to mlir/test/Examples/standalone/test.install-dir.toy
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 7e22ebf23c773..eadfd047d15f7 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -3,6 +3,7 @@
 import sys
 
 config.target_triple = "@LLVM_TARGET_TRIPLE@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_tools_dir = lit_config.substitute("@LLVM_TOOLS_DIR@")
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"

>From 67ce5b688657d38b6792b05712d1de6f56e726fe Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 15:54:54 -0700
Subject: [PATCH 03/14] add test.install-distribution-dir.toy

---
 mlir/test/Examples/standalone/lit.local.cfg |  1 +
 .../Examples/standalone/test.install-dir.toy|  4 ++--
 .../test.install-distribution-dir.toy   | 17 +
 3 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 
mlir/test/Examples/stand

[llvm-branch-commits] [Clang] Enable lit internal shell by default (PR #158465)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits


https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/158465


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[llvm-branch-commits] [clang] [HLSL] Use static create methods to initialize resources in arrays (PR #157005)

2025-09-15 Thread Farzon Lotfi via llvm-branch-commits


https://github.com/farzonl approved this pull request.


https://github.com/llvm/llvm-project/pull/157005
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[llvm-branch-commits] [flang] [mlir] [MLIR] Add new complex.powi op (PR #158722)

2025-09-15 Thread Akash Banerjee via llvm-branch-commits


https://github.com/TIFitis updated 
https://github.com/llvm/llvm-project/pull/158722

>From 8c9a156aa4f682ca836403bd71608c5aa2352d46 Mon Sep 17 00:00:00 2001
From: Akash Banerjee 
Date: Mon, 15 Sep 2025 20:35:29 +0100
Subject: [PATCH 1/2] Add complex.powi op.

---
 flang/lib/Optimizer/Builder/IntrinsicCall.cpp | 20 ++--
 .../Transforms/ConvertComplexPow.cpp  | 92 +--
 flang/test/Lower/HLFIR/binary-ops.f90 |  2 +-
 .../test/Lower/Intrinsics/pow_complex16i.f90  |  2 +-
 .../test/Lower/Intrinsics/pow_complex16k.f90  |  2 +-
 flang/test/Lower/amdgcn-complex.f90   |  9 ++
 flang/test/Lower/power-operator.f90   |  9 +-
 flang/test/Transforms/convert-complex-pow.fir | 42 +++--
 .../mlir/Dialect/Complex/IR/ComplexOps.td | 26 ++
 .../ComplexToROCDLLibraryCalls.cpp| 41 -
 .../Transforms/AlgebraicSimplification.cpp| 24 +++--
 .../Dialect/Math/Transforms/CMakeLists.txt|  1 +
 .../complex-to-rocdl-library-calls.mlir   | 14 +++
 mlir/test/Dialect/Complex/powi-simplify.mlir  | 20 
 14 files changed, 198 insertions(+), 106 deletions(-)
 create mode 100644 mlir/test/Dialect/Complex/powi-simplify.mlir

diff --git a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp 
b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp
index 466458c05dba7..74a4e8f85c8ff 100644
--- a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp
+++ b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp
@@ -1331,14 +1331,20 @@ mlir::Value genComplexPow(fir::FirOpBuilder &builder, 
mlir::Location loc,
 return genLibCall(builder, loc, mathOp, mathLibFuncType, args);
   auto complexTy = mlir::cast(mathLibFuncType.getInput(0));
   mlir::Value exp = args[1];
-  if (!mlir::isa(exp.getType())) {
-auto realTy = complexTy.getElementType();
-mlir::Value realExp = builder.createConvert(loc, realTy, exp);
-mlir::Value zero = builder.createRealConstant(loc, realTy, 0);
-exp =
-builder.create(loc, complexTy, realExp, zero);
+  mlir::Value result;
+  if (mlir::isa(exp.getType()) ||
+  mlir::isa(exp.getType())) {
+result = builder.create(loc, args[0], exp);
+  } else {
+if (!mlir::isa(exp.getType())) {
+  auto realTy = complexTy.getElementType();
+  mlir::Value realExp = builder.createConvert(loc, realTy, exp);
+  mlir::Value zero = builder.createRealConstant(loc, realTy, 0);
+  exp = builder.create(loc, complexTy, realExp,
+zero);
+}
+result = builder.create(loc, args[0], exp);
   }
-  mlir::Value result = builder.create(loc, args[0], exp);
   result = builder.createConvert(loc, mathLibFuncType.getResult(0), result);
   return result;
 }
diff --git a/flang/lib/Optimizer/Transforms/ConvertComplexPow.cpp 
b/flang/lib/Optimizer/Transforms/ConvertComplexPow.cpp
index dced5f90d6924..42f5df160798c 100644
--- a/flang/lib/Optimizer/Transforms/ConvertComplexPow.cpp
+++ b/flang/lib/Optimizer/Transforms/ConvertComplexPow.cpp
@@ -61,63 +61,55 @@ void ConvertComplexPowPass::runOnOperation() {
 
   fir::FirOpBuilder builder(mod, fir::getKindMapping(mod));
 
-  mod.walk([&](complex::PowOp op) {
+  mod.walk([&](complex::PowiOp op) {
 builder.setInsertionPoint(op);
 Location loc = op.getLoc();
 auto complexTy = cast(op.getType());
 auto elemTy = complexTy.getElementType();
-
 Value base = op.getLhs();
-Value rhs = op.getRhs();
-
-Value intExp;
-if (auto create = rhs.getDefiningOp()) {
-  if (isZero(create.getImaginary())) {
-if (auto conv = create.getReal().getDefiningOp()) {
-  if (auto intTy = dyn_cast(conv.getValue().getType()))
-intExp = conv.getValue();
-}
-  }
-}
-
+Value intExp = op.getRhs();
 func::FuncOp callee;
-SmallVector args;
-if (intExp) {
-  unsigned realBits = cast(elemTy).getWidth();
-  unsigned intBits = cast(intExp.getType()).getWidth();
-  auto funcTy = builder.getFunctionType(
-  {complexTy, builder.getIntegerType(intBits)}, {complexTy});
-  if (realBits == 32 && intBits == 32)
-callee = getOrDeclare(builder, loc, RTNAME_STRING(cpowi), funcTy);
-  else if (realBits == 32 && intBits == 64)
-callee = getOrDeclare(builder, loc, RTNAME_STRING(cpowk), funcTy);
-  else if (realBits == 64 && intBits == 32)
-callee = getOrDeclare(builder, loc, RTNAME_STRING(zpowi), funcTy);
-  else if (realBits == 64 && intBits == 64)
-callee = getOrDeclare(builder, loc, RTNAME_STRING(zpowk), funcTy);
-  else if (realBits == 128 && intBits == 32)
-callee = getOrDeclare(builder, loc, RTNAME_STRING(cqpowi), funcTy);
-  else if (realBits == 128 && intBits == 64)
-callee = getOrDeclare(builder, loc, RTNAME_STRING(cqpowk), funcTy);
-  else
-return;
-  args = {base, intExp};
-} else {
-  unsigned realBits = cast(elemTy).getWidth();
-  auto funcTy =
-  builder.getFunctionType({complexTy,

[llvm-branch-commits] [clang] release/21.x: [clang-format] Handle C digit separators (#158418) (PR #158512)

2025-09-15 Thread Björn Schäpers via llvm-branch-commits


https://github.com/HazardyKnusperkeks approved this pull request.


https://github.com/llvm/llvm-project/pull/158512
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[llvm-branch-commits] [llvm] [DirectX] Validating Root flags are denying shader stage (PR #153287)

2025-09-15 Thread Finn Plummer via llvm-branch-commits



@@ -225,7 +237,9 @@ static void validateRootSignature(Module &M,
 Builder.findOverlapping(ReportedBinding);
 reportOverlappingRegisters(M, ReportedBinding, Overlaping);
   });
+
   const hlsl::BoundRegs &BoundRegs = Builder.takeBoundRegs();
+  bool HasBindings = false;

inbelic wrote:

IIUC I think the logic below could be simplified a bit to something like:

```c++
if (!Reg) {
  reportRegNotBound(M, RC, Binding);
  continue;
}

bool IsRootSRVOrUAV = RC == ResourceClass::SRV || RC == ResourceClass::UAV;
bool IsRawOrStructuredBuffer = RK != ResourceKind::RawBuffer && RK != 
ResourceKind::StructuredBuffer;
if (IsRootSRVOrUAV && !IsRawOrStructuredBuffer) {
  reportInvalidHandleTyError(M, RC, Binding);
  continue;
}

HasBindings = true;
```

https://github.com/llvm/llvm-project/pull/153287
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[llvm-branch-commits] [llvm] [LoopUnroll] Fix block frequencies when no runtime (PR #157754)

2025-09-15 Thread Joel E. Denny via llvm-branch-commits


https://github.com/jdenny-ornl updated 
https://github.com/llvm/llvm-project/pull/157754

>From 75a8df62df2ef7e8c02d7a76120e57e2dd1a1539 Mon Sep 17 00:00:00 2001
From: "Joel E. Denny" 
Date: Tue, 9 Sep 2025 17:33:38 -0400
Subject: [PATCH] [LoopUnroll] Fix block frequencies when no runtime

This patch implements the LoopUnroll changes discussed in [[RFC] Fix
Loop Transformations to Preserve Block
Frequencies](https://discourse.llvm.org/t/rfc-fix-loop-transformations-to-preserve-block-frequencies/85785)
and is thus another step in addressing issue #135812.

In summary, for the case of partial loop unrolling without a runtime,
this patch changes LoopUnroll to:

- Maintain branch weights consistently with the original loop for the
  sake of preserving the total frequency of the original loop body.
- Store the new estimated trip count in the
  `llvm.loop.estimated_trip_count` metadata, introduced by PR #148758.
- Correct the new estimated trip count (e.g., 3 instead of 2) when the
  original estimated trip count (e.g., 10) divided by the unroll count
  (e.g., 4) leaves a remainder (e.g., 2).

There are loop unrolling cases this patch does not fully fix, such as
partial unrolling with a runtime and complete unrolling, and there are
two associated tests this patch marks as XFAIL.  They will be
addressed in future patches that should land with this patch.
---
 llvm/lib/Transforms/Utils/LoopUnroll.cpp  | 36 --
 .../peel.ll}  |  0
 .../branch-weights-freq/unroll-partial.ll | 68 +++
 .../LoopUnroll/runtime-loop-branchweight.ll   |  1 +
 .../LoopUnroll/unroll-heuristics-pgo.ll   |  1 +
 5 files changed, 100 insertions(+), 6 deletions(-)
 rename llvm/test/Transforms/LoopUnroll/{peel-branch-weights-freq.ll => 
branch-weights-freq/peel.ll} (100%)
 create mode 100644 
llvm/test/Transforms/LoopUnroll/branch-weights-freq/unroll-partial.ll

diff --git a/llvm/lib/Transforms/Utils/LoopUnroll.cpp 
b/llvm/lib/Transforms/Utils/LoopUnroll.cpp
index 8a6c7789d1372..93c43396c54b6 100644
--- a/llvm/lib/Transforms/Utils/LoopUnroll.cpp
+++ b/llvm/lib/Transforms/Utils/LoopUnroll.cpp
@@ -499,9 +499,8 @@ llvm::UnrollLoop(Loop *L, UnrollLoopOptions ULO, LoopInfo 
*LI,
 
   const unsigned MaxTripCount = SE->getSmallConstantMaxTripCount(L);
   const bool MaxOrZero = SE->isBackedgeTakenCountMaxOrZero(L);
-  unsigned EstimatedLoopInvocationWeight = 0;
   std::optional OriginalTripCount =
-  llvm::getLoopEstimatedTripCount(L, &EstimatedLoopInvocationWeight);
+  llvm::getLoopEstimatedTripCount(L);
 
   // Effectively "DCE" unrolled iterations that are beyond the max tripcount
   // and will never be executed.
@@ -1130,10 +1129,35 @@ llvm::UnrollLoop(Loop *L, UnrollLoopOptions ULO, 
LoopInfo *LI,
 // We shouldn't try to use `L` anymore.
 L = nullptr;
   } else if (OriginalTripCount) {
-// Update the trip count. Note that the remainder has already logic
-// computing it in `UnrollRuntimeLoopRemainder`.
-setLoopEstimatedTripCount(L, *OriginalTripCount / ULO.Count,
-  EstimatedLoopInvocationWeight);
+// Update metadata for the estimated trip count.
+//
+// If ULO.Runtime, UnrollRuntimeLoopRemainder handles branch weights for 
the
+// remainder loop it creates, and the unrolled loop's branch weights are
+// adjusted below.  Otherwise, if unrolled loop iterations' latches become
+// unconditional, branch weights are adjusted above.  Otherwise, the
+// original loop's branch weights are correct for the unrolled loop, so do
+// not adjust them.
+// FIXME: Actually handle such unconditional latches and ULO.Runtime.
+//
+// For example, consider what happens if the unroll count is 4 for a loop
+// with an estimated trip count of 10 when we do not create a remainder 
loop
+// and all iterations' latches remain conditional.  Each unrolled
+// iteration's latch still has the same probability of exiting the loop as
+// it did when in the original loop, and thus it should still have the same
+// branch weights.  Each unrolled iteration's non-zero probability of
+// exiting already appropriately reduces the probability of reaching the
+// remaining iterations just as it did in the original loop.  Trying to 
also
+// adjust the branch weights of the final unrolled iteration's latch (i.e.,
+// the backedge for the unrolled loop as a whole) to reflect its new trip
+// count of 3 will erroneously further reduce its block frequencies.
+// However, in case an analysis later needs to estimate the trip count of
+// the unrolled loop as a whole without considering the branch weights for
+// each unrolled iteration's latch within it, we store the new trip count 
as
+// separate metadata.
+unsigned NewTripCount = *OriginalTripCount / ULO.Count;
+if (!ULO.Runtime && *OriginalTripCount % ULO.Count)
+  NewTripCount += 1;
+setLoopEstimatedT

[llvm-branch-commits] [llvm] [DirectX] Validating Root flags are denying shader stage (PR #153287)

2025-09-15 Thread Finn Plummer via llvm-branch-commits


https://github.com/inbelic edited 
https://github.com/llvm/llvm-project/pull/153287
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[llvm-branch-commits] [llvm] [DirectX] Validating Root flags are denying shader stage (PR #153287)

2025-09-15 Thread Finn Plummer via llvm-branch-commits


https://github.com/inbelic commented:

Mostly LGTM, just some clean ups I think we should do

https://github.com/llvm/llvm-project/pull/153287
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[llvm-branch-commits] [llvm] [DirectX] Validating Root flags are denying shader stage (PR #153287)

2025-09-15 Thread Finn Plummer via llvm-branch-commits



@@ -240,18 +254,63 @@ static void validateRootSignature(Module &M,
   const auto *ParamInfo =
   static_cast(Reg->Cookie);
 
-  if (RC != ResourceClass::SRV && RC != ResourceClass::UAV)
+  if (RC != ResourceClass::SRV && RC != ResourceClass::UAV) {
+HasBindings = true;
 continue;
+  }
 
-  if (ParamInfo->Type == dxbc::RootParameterType::DescriptorTable)
+  if (ParamInfo->Type == dxbc::RootParameterType::DescriptorTable) {
+HasBindings = true;
 continue;
+  }
 
-  if (RK != ResourceKind::RawBuffer && RK != 
ResourceKind::StructuredBuffer)
+  if (RK != ResourceKind::RawBuffer &&
+  RK != ResourceKind::StructuredBuffer) {
 reportInvalidHandleTyError(M, RC, Binding);
+continue;
+  }
+  HasBindings = true;
+
 } else {
   reportRegNotBound(M, RC, Binding);
 }
   }
+
+  if (HasBindings && MMI.ShaderProfile != Triple::Compute) {
+dxbc::RootFlags Flags = dxbc::RootFlags(RSD.Flags);

inbelic wrote:

nit: it may be nicer if we define a separate function like 
`getEnvironmentDenyFlag` and then just invoked 
`reportIfDeniedShaderStageAccess` once. Might prevent a copy of this switch 
table appearing elsewhere

https://github.com/llvm/llvm-project/pull/153287
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[llvm-branch-commits] [flang] [mlir] [MLIR] Add new complex.powi op (PR #158722)

2025-09-15 Thread Mehdi Amini via llvm-branch-commits


joker-eph wrote:

What is the LLVM lowering here?

https://github.com/llvm/llvm-project/pull/158722
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[llvm-branch-commits] [flang] [mlir] [MLIR] Add new complex.powi op (PR #158722)

2025-09-15 Thread Mehdi Amini via llvm-branch-commits



@@ -443,6 +443,32 @@ def PowOp : ComplexArithmeticOp<"pow"> {
   }];
 }
 
+//===--===//
+// PowiOp
+//===--===//
+
+def PowiOp : Complex_Op<"powi",
+[Pure, Elementwise, SameOperandsAndResultShape,
+ AllTypesMatch<["lhs", "result"]>]> {
+  let summary = "complex number raised to integer power";
+  let description = [{
+The `powi` operation takes a complex number and an integer exponent.

joker-eph wrote:

The signed aspects of the operands, as well at the overflow behaviors should be 
specified here.
This may need an overflow flag by the way.

https://github.com/llvm/llvm-project/pull/158722
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[llvm-branch-commits] [llvm] release/21.x: [VPlan] Don't narrow op multiple times in narrowInterleaveGroups. (PR #158013)

2025-09-15 Thread Tobias Hieta via llvm-branch-commits


tru wrote:

Is there someone else that can or should review this?

https://github.com/llvm/llvm-project/pull/158013
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[llvm-branch-commits] [clang] f490704 - [Clang][Cygwin] Use correct mangling rule (#158404)

2025-09-15 Thread via llvm-branch-commits


Author: Tomohiro Kashiwada
Date: 2025-09-13T21:46:42Z
New Revision: f4907049285ca0875cc91770e3ceb3f162ec7c48

URL: 
https://github.com/llvm/llvm-project/commit/f4907049285ca0875cc91770e3ceb3f162ec7c48
DIFF: 
https://github.com/llvm/llvm-project/commit/f4907049285ca0875cc91770e3ceb3f162ec7c48.diff

LOG: [Clang][Cygwin] Use correct mangling rule (#158404)

In
https://github.com/llvm/llvm-project/commit/45ca613c135ea7b5fbc63bff003f20bf20f62081,
whether to mangle names based on calling conventions according to
Microsoft conventions was refactored to a bool in the TargetInfo. Cygwin
targets also require this mangling, but were missed, presumably due to
lack of test coverage of these targets. This commit enables the name
mangling for Cygwin, and also enables test coverage of this mangling on
Cygwin targets.

(cherry picked from commit 4abcbb053f8adaf48dbfff677e8ccda1f6d52b33)

Added: 


Modified: 
clang/lib/Basic/Targets/X86.h
clang/test/CodeGen/mangle-windows.c
clang/test/CodeGenCXX/mangle-windows.cpp

Removed: 




diff  --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index ebc59c92f4c24..a7be080695ed3 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -649,6 +649,7 @@ class LLVM_LIBRARY_VISIBILITY CygwinX86_32TargetInfo : 
public X86_32TargetInfo {
   : X86_32TargetInfo(Triple, Opts) {
 this->WCharType = TargetInfo::UnsignedShort;
 this->WIntType = TargetInfo::UnsignedInt;
+this->UseMicrosoftManglingForC = true;
 DoubleAlign = LongLongAlign = 64;
 resetDataLayout("e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-"
 "i128:128-f80:32-n8:16:32-a:0:32-S32",
@@ -986,6 +987,7 @@ class LLVM_LIBRARY_VISIBILITY CygwinX86_64TargetInfo : 
public X86_64TargetInfo {
   : X86_64TargetInfo(Triple, Opts) {
 this->WCharType = TargetInfo::UnsignedShort;
 this->WIntType = TargetInfo::UnsignedInt;
+this->UseMicrosoftManglingForC = true;
   }
 
   void getTargetDefines(const LangOptions &Opts,

diff  --git a/clang/test/CodeGen/mangle-windows.c 
b/clang/test/CodeGen/mangle-windows.c
index 046b1e8815a8a..e1b06e72a9635 100644
--- a/clang/test/CodeGen/mangle-windows.c
+++ b/clang/test/CodeGen/mangle-windows.c
@@ -1,8 +1,10 @@
 // RUN: %clang_cc1 -emit-llvm %s -o - -triple=i386-pc-win32 | FileCheck %s
-// RUN: %clang_cc1 -emit-llvm %s -o - -triple=i386-mingw32 | FileCheck %s
+// RUN: %clang_cc1 -emit-llvm %s -o - -triple=i386-mingw32  | FileCheck %s
+// RUN: %clang_cc1 -emit-llvm %s -o - -triple=i386-cygwin   | FileCheck %s
 // RUN: %clang_cc1 -emit-llvm %s -o - -triple=i386-pc-windows-msvc-elf | 
FileCheck %s --check-prefix=ELF32
 // RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-pc-win32 | FileCheck %s 
--check-prefix=X64
-// RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-mingw32 | FileCheck %s 
--check-prefix=X64
+// RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-mingw32  | FileCheck %s 
--check-prefix=X64
+// RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-cygwin   | FileCheck %s 
--check-prefix=X64
 // RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-pc-windows-msvc-elf | 
FileCheck %s --check-prefix=ELF64
 
 // CHECK: target datalayout = "e-m:x-{{.*}}"

diff  --git a/clang/test/CodeGenCXX/mangle-windows.cpp 
b/clang/test/CodeGenCXX/mangle-windows.cpp
index 3d5a1e9a868ef..737abcf6e3498 100644
--- a/clang/test/CodeGenCXX/mangle-windows.cpp
+++ b/clang/test/CodeGenCXX/mangle-windows.cpp
@@ -4,6 +4,9 @@
 // RUN: %clang_cc1 -emit-llvm %s -o - -triple=i386-mingw32 | \
 // RUN: FileCheck --check-prefix=ITANIUM %s
 
+// RUN: %clang_cc1 -emit-llvm %s -o - -triple=i386-cygwin | \
+// RUN: FileCheck --check-prefix=ITANIUM %s
+
 void __stdcall f1(void) {}
 // WIN: define dso_local x86_stdcallcc void @"?f1@@YGXXZ"
 // ITANIUM: define dso_local x86_stdcallcc void @"\01__Z2f1v@0"



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[llvm-branch-commits] [clang] release/21.x: [CMake][Release] Build with -ffat-lto-objects (#140381) (PR #151245)

2025-09-15 Thread Tobias Hieta via llvm-branch-commits


tru wrote:

Ping - do we still want to include this in 21.x?

https://github.com/llvm/llvm-project/pull/151245
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[llvm-branch-commits] [llvm] AMDGPU: Stop using aligned VGPR classes for addRegisterClass (PR #158278)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158278

>From b70040bb06ddec1f28c0e7e5eb842fa0072d3daf Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 12 Sep 2025 20:45:56 +0900
Subject: [PATCH] AMDGPU: Stop using aligned VGPR classes for addRegisterClass

This is unnecessary. At use emission time, InstrEmitter will
use the common subclass of the value type's register class and
the use instruction register classes. This removes one of the
obstacles to treating special case instructions that do not have
the alignment requirement overly conservatively.
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 32 +++
 llvm/test/CodeGen/AMDGPU/mfma-loop.ll | 14 +-
 2 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp 
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 9acc4b6de3501..8974198a82f01 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -110,52 +110,52 @@ SITargetLowering::SITargetLowering(const TargetMachine 
&TM,
   addRegisterClass(MVT::Untyped, V64RegClass);
 
   addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
-  addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96));
+  addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
 
   addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
   addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
 
   addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
-  addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128));
+  addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
 
   addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
-  addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160));
+  addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
 
   addRegisterClass(MVT::v6i32, &AMDGPU::SGPR_192RegClass);
-  addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192));
+  addRegisterClass(MVT::v6f32, &AMDGPU::VReg_192RegClass);
 
   addRegisterClass(MVT::v3i64, &AMDGPU::SGPR_192RegClass);
-  addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192));
+  addRegisterClass(MVT::v3f64, &AMDGPU::VReg_192RegClass);
 
   addRegisterClass(MVT::v7i32, &AMDGPU::SGPR_224RegClass);
-  addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224));
+  addRegisterClass(MVT::v7f32, &AMDGPU::VReg_224RegClass);
 
   addRegisterClass(MVT::v8i32, &AMDGPU::SGPR_256RegClass);
-  addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256));
+  addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
 
   addRegisterClass(MVT::v4i64, &AMDGPU::SGPR_256RegClass);
-  addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256));
+  addRegisterClass(MVT::v4f64, &AMDGPU::VReg_256RegClass);
 
   addRegisterClass(MVT::v9i32, &AMDGPU::SGPR_288RegClass);
-  addRegisterClass(MVT::v9f32, TRI->getVGPRClassForBitWidth(288));
+  addRegisterClass(MVT::v9f32, &AMDGPU::VReg_288RegClass);
 
   addRegisterClass(MVT::v10i32, &AMDGPU::SGPR_320RegClass);
-  addRegisterClass(MVT::v10f32, TRI->getVGPRClassForBitWidth(320));
+  addRegisterClass(MVT::v10f32, &AMDGPU::VReg_320RegClass);
 
   addRegisterClass(MVT::v11i32, &AMDGPU::SGPR_352RegClass);
-  addRegisterClass(MVT::v11f32, TRI->getVGPRClassForBitWidth(352));
+  addRegisterClass(MVT::v11f32, &AMDGPU::VReg_352RegClass);
 
   addRegisterClass(MVT::v12i32, &AMDGPU::SGPR_384RegClass);
-  addRegisterClass(MVT::v12f32, TRI->getVGPRClassForBitWidth(384));
+  addRegisterClass(MVT::v12f32, &AMDGPU::VReg_384RegClass);
 
   addRegisterClass(MVT::v16i32, &AMDGPU::SGPR_512RegClass);
-  addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512));
+  addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
 
   addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);
-  addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512));
+  addRegisterClass(MVT::v8f64, &AMDGPU::VReg_512RegClass);
 
   addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);
-  addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024));
+  addRegisterClass(MVT::v16f64, &AMDGPU::VReg_1024RegClass);
 
   if (Subtarget->has16BitInsts()) {
 if (Subtarget->useRealTrue16Insts()) {
@@ -187,7 +187,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
   }
 
   addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
-  addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024));
+  addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
 
   computeRegisterProperties(Subtarget->getRegisterInfo());
 
diff --git a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll 
b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
index d39daaade677f..3657a6b1b7415 100644
--- a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
@@ -2430,8 +2430,9 @@ define amdgpu_kernel void 
@test_mfma_nested_loop_zeroinit(ptr addrspace(1) %arg)
 ; GFX90A-NEXT:v_accvgpr_mov_b32 a29, a0
 ; GFX90A-NEXT:v_accvgpr_mov_b32 a30, a0
 ; GFX90A-NEXT

[llvm-branch-commits] [Clang] Make rewrite-includes-bom.c work with internal shell (PR #158463)

2025-09-15 Thread Paul Kirth via llvm-branch-commits


https://github.com/ilovepi approved this pull request.


https://github.com/llvm/llvm-project/pull/158463
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[llvm-branch-commits] [llvm] [Offload] Add GenericPluginTy::get_mem_info (PR #157484)

2025-09-15 Thread Jan Patrick Lehr via llvm-branch-commits



@@ -3561,6 +3564,26 @@ struct AMDGPUPluginTy final : public GenericPluginTy {
 return KernelAgents;
   }
 
+  Expected get_memory_info(const void *TgtPtr) override {

jplehr wrote:

```suggestion
  Expected getMemoryInfo(const void *TgtPtr) override {
```

https://github.com/llvm/llvm-project/pull/157484
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[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


https://github.com/makslevental edited 
https://github.com/llvm/llvm-project/pull/157944
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[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


https://github.com/makslevental updated 
https://github.com/llvm/llvm-project/pull/157944

>From f9dbe48eaa691ca9f8161e9dc3a800bb613d5bc9 Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 12:57:54 -0700
Subject: [PATCH 01/14] [MLIR][Standalone] test Standalone against install
 distributions

---
 mlir/test/Examples/standalone/lit.local.cfg  |  2 ++
 .../Examples/standalone/test.toy.install-dir | 16 
 mlir/test/lit.cfg.py |  3 +++
 mlir/test/lit.site.cfg.py.in |  1 +
 4 files changed, 22 insertions(+)
 create mode 100644 mlir/test/Examples/standalone/test.toy.install-dir

diff --git a/mlir/test/Examples/standalone/lit.local.cfg 
b/mlir/test/Examples/standalone/lit.local.cfg
index fe8397c6b9a10..bc9928decf527 100644
--- a/mlir/test/Examples/standalone/lit.local.cfg
+++ b/mlir/test/Examples/standalone/lit.local.cfg
@@ -10,3 +10,5 @@ config.substitutions.append(("%host_cc", config.host_cc))
 config.substitutions.append(("%enable_libcxx", config.enable_libcxx))
 config.substitutions.append(("%mlir_cmake_dir", config.mlir_cmake_dir))
 config.substitutions.append(("%llvm_use_linker", config.llvm_use_linker))
+config.substitutions.append(("%llvm_obj_root", config.llvm_obj_root))
+config.substitutions.append(("%host_cmake_install_prefix", 
config.host_cmake_install_prefix))
diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.toy.install-dir
new file mode 100644
index 0..5c33a70491ae1
--- /dev/null
+++ b/mlir/test/Examples/standalone/test.toy.install-dir
@@ -0,0 +1,16 @@
+# REQUIRES: github-actions
+# RUN: "%cmake_exe" --build %llvm_obj_root --target install
+# RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
+# RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DLLVM_ENABLE_LIBCXX=%enable_libcxx 
-DMLIR_DIR=%host_cmake_install_prefix \
+# RUN: -DLLVM_USE_LINKER=%llvm_use_linker \
+# RUN: -DPython3_EXECUTABLE=%python \
+# RUN: -DPython_EXECUTABLE=%python
+# RUN: "%cmake_exe" --build . --target check-standalone | tee %t
+# RUN: FileCheck --input-file=%t %s
+
+# Note: The number of checked tests is not important. The command will fail
+# if any fail.
+# CHECK: Passed
+# CHECK-NOT: Failed
+# UNSUPPORTED: target={{.*(windows|android).*}}
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index f99c24d6e299a..08c7947c1e9a6 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -383,3 +383,6 @@ def have_host_jit_feature_support(feature_name):
 
 if sys.version_info >= (3, 11):
 config.available_features.add("python-ge-311")
+
+if "GITHUB_ACTIONS" in os.environ:
+config.available_features.add("github-actions")
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 8a742a227847b..7e22ebf23c773 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -18,6 +18,7 @@ config.host_cxx = "@HOST_CXX@"
 config.enable_libcxx = "@LLVM_ENABLE_LIBCXX@"
 config.host_cmake = "@CMAKE_COMMAND@"
 config.host_cmake_generator = "@CMAKE_GENERATOR@"
+config.host_cmake_install_prefix = "@CMAKE_INSTALL_PREFIX@"
 config.llvm_use_linker = "@LLVM_USE_LINKER@"
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.host_arch = "@HOST_ARCH@"

>From fc56d49c9481aed16b79f391368f4c3824a90695 Mon Sep 17 00:00:00 2001
From: Maksim Levental 
Date: Wed, 10 Sep 2025 13:23:07 -0700
Subject: [PATCH 02/14] Update lit.site.cfg.py.in

---
 .../standalone/{test.toy.install-dir => test.install-dir.toy}| 0
 mlir/test/lit.site.cfg.py.in | 1 +
 2 files changed, 1 insertion(+)
 rename mlir/test/Examples/standalone/{test.toy.install-dir => 
test.install-dir.toy} (100%)

diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.install-dir.toy
similarity index 100%
rename from mlir/test/Examples/standalone/test.toy.install-dir
rename to mlir/test/Examples/standalone/test.install-dir.toy
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 7e22ebf23c773..eadfd047d15f7 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -3,6 +3,7 @@
 import sys
 
 config.target_triple = "@LLVM_TARGET_TRIPLE@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_tools_dir = lit_config.substitute("@LLVM_TOOLS_DIR@")
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"

>From 67ce5b688657d38b6792b05712d1de6f56e726fe Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 15:54:54 -0700
Subject: [PATCH 03/14] add test.install-distribution-dir.toy

---
 mlir/test/Examples/standalone/lit.local.cfg |  1 +
 .../Examples/standalone/test.install-dir.toy|  4 ++--
 .../test.install-distribution-dir.toy   | 17 +
 3 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 
mlir/test/Examples/stand

[llvm-branch-commits] [Clang] Make rewrite-includes-bom.c work with internal shell (PR #158463)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits


https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/158463


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[llvm-branch-commits] [clang] [llvm] [lit] Make builtin cat work with stdin (PR #158447)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits


https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/158447

>From 5bd8d4f925f3b5f82d85ef693861b6b1067d9f38 Mon Sep 17 00:00:00 2001
From: Aiden Grossman 
Date: Sat, 13 Sep 2025 22:54:58 +
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6
---
 clang/test/Misc/dev-fd-fs.c| 1 -
 llvm/utils/lit/lit/builtin_commands/cat.py | 3 +++
 llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt | 4 
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/clang/test/Misc/dev-fd-fs.c b/clang/test/Misc/dev-fd-fs.c
index ea94d950b0716..b989ab8a439cf 100644
--- a/clang/test/Misc/dev-fd-fs.c
+++ b/clang/test/Misc/dev-fd-fs.c
@@ -1,6 +1,5 @@
 // Check that we can operate on files from /dev/fd.
 // REQUIRES: dev-fd-fs
-// REQUIRES: shell
 
 // Check reading from named pipes. We cat the input here instead of redirecting
 // it to ensure that /dev/fd/0 is a named pipe, not just a redirected file.
diff --git a/llvm/utils/lit/lit/builtin_commands/cat.py 
b/llvm/utils/lit/lit/builtin_commands/cat.py
index ddab555662045..2797e0cbb4154 100644
--- a/llvm/utils/lit/lit/builtin_commands/cat.py
+++ b/llvm/utils/lit/lit/builtin_commands/cat.py
@@ -49,6 +49,9 @@ def main(argv):
 import os, msvcrt
 
 msvcrt.setmode(sys.stdout.fileno(), os.O_BINARY)
+if len(filenames) == 0:
+sys.stdout.write(sys.stdin.read())
+sys.exit(0)
 for filename in filenames:
 try:
 contents = None
diff --git a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt 
b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
index 4014b0fca1f24..c5b5d247c2f95 100644
--- a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
+++ b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
@@ -70,3 +70,7 @@
 # 
NP-CAT-OUTPUT-NEXT:M-HM-IM-JM-KM-LM-MM-NM-OM-PM-QM-RM-SM-TM-UM-VM-WM-XM-YM-ZM-[
 # 
NP-CAT-OUTPUT-NEXT:M-\M-]M-^M-_M-`M-aM-bM-cM-dM-eM-fM-gM-hM-iM-jM-kM-lM-mM-nM-o
 # NP-CAT-OUTPUT-NEXT:M-pM-qM-rM-sM-tM-uM-vM-wM-xM-yM-zM-{M-|M-}M-~M-^?
+
+## Test that cat will pipe stdin to stdout if no other files are specified.
+# RUN: echo test | cat | FileCheck --check-prefix=CAT-STDIN %s
+# CAT-STDIN: test

>From 572975066e843b76e51020bcf6abc7822d3dfb75 Mon Sep 17 00:00:00 2001
From: Aiden Grossman 
Date: Sat, 13 Sep 2025 23:14:52 +
Subject: [PATCH 2/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?=
 =?UTF-8?q?anges=20introduced=20through=20rebase?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6

[skip ci]
---
 clang/test/ClangScanDeps/pr61006.cppm |  3 ++-
 clang/test/ClangScanDeps/resource_directory.c |  9 -
 clang/test/Driver/env.c   |  5 +++--
 clang/test/Driver/program-path-priority.c | 16 +++
 clang/test/Modules/relative-resource-dir.m|  6 +++---
 llvm/docs/CommandGuide/lit.rst|  1 +
 llvm/test/tools/llvm-cgdata/empty.test|  1 +
 llvm/utils/lit/lit/TestRunner.py  | 20 +++
 .../Inputs/shtest-readfile/absolute-paths.txt |  6 ++
 .../lit/tests/Inputs/shtest-readfile/lit.cfg  |  8 
 .../Inputs/shtest-readfile/relative-paths.txt |  7 +++
 .../Inputs/shtest-readfile/two-same-line.txt  |  8 
 llvm/utils/lit/tests/shtest-readfile.py   | 17 
 13 files changed, 88 insertions(+), 19 deletions(-)
 create mode 100644 
llvm/utils/lit/tests/Inputs/shtest-readfile/absolute-paths.txt
 create mode 100644 llvm/utils/lit/tests/Inputs/shtest-readfile/lit.cfg
 create mode 100644 
llvm/utils/lit/tests/Inputs/shtest-readfile/relative-paths.txt
 create mode 100644 
llvm/utils/lit/tests/Inputs/shtest-readfile/two-same-line.txt
 create mode 100644 llvm/utils/lit/tests/shtest-readfile.py

diff --git a/clang/test/ClangScanDeps/pr61006.cppm 
b/clang/test/ClangScanDeps/pr61006.cppm
index f75edd38c81ba..f10bc1e673987 100644
--- a/clang/test/ClangScanDeps/pr61006.cppm
+++ b/clang/test/ClangScanDeps/pr61006.cppm
@@ -6,7 +6,8 @@
 // RUN: mkdir -p %t
 // RUN: split-file %s %t
 //
-// RUN: EXPECTED_RESOURCE_DIR=`%clang -print-resource-dir` && \
+// RUN: %clang -print-resource-dir | tr -d '\n' > %t/resource-dir
+// RUN: env EXPECTED_RESOURCE_DIR=%{readfile:%t/resource-dir} && \
 // RUN: ln -s %clang++ %t/clang++ && \
 // RUN: sed "s|EXPECTED_RESOURCE_DIR|$EXPECTED_RESOURCE_DIR|g; s|DIR|%/t|g" 
%t/P1689.json.in > %t/P1689.json && \
 // RUN: clang-scan-deps -compilation-database %t/P1689.json -format=p1689 | 
FileCheck %t/a.cpp -DPREFIX=%/t && \
diff --git a/clang/test/ClangScanDeps/resource_directory.c 
b/clang/test/ClangScanDeps/resource_directory.c
index 55d5d90bbcdea..6183e8aefacfa 100644
--- a/clang/test/ClangScanDeps/resource_directory.c
+++ b/clang/test/ClangScanDeps/resource_directory.c
@@ -12,14 +12,14 @@
 //

[llvm-branch-commits] [lit] Add support for deleting symlinks to directories without -r (PR #158464)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits


https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/158464


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[llvm-branch-commits] [Clang] Make rewrite-includes-bom.c work with internal shell (PR #158463)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits


https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/158463


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[llvm-branch-commits] [Clang] Rewrite tests using subshells to set env variables (PR #158446)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits


https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/158446


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[llvm-branch-commits] [lit] Add support for deleting symlinks to directories without -r (PR #158464)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits


https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/158464


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[llvm-branch-commits] [Clang] Enable lit internal shell by default (PR #158465)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits


https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/158465


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[llvm-branch-commits] [clang] [llvm] [lit] Make builtin cat work with stdin (PR #158447)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits


https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/158447

>From 5bd8d4f925f3b5f82d85ef693861b6b1067d9f38 Mon Sep 17 00:00:00 2001
From: Aiden Grossman 
Date: Sat, 13 Sep 2025 22:54:58 +
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
 =?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6
---
 clang/test/Misc/dev-fd-fs.c| 1 -
 llvm/utils/lit/lit/builtin_commands/cat.py | 3 +++
 llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt | 4 
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/clang/test/Misc/dev-fd-fs.c b/clang/test/Misc/dev-fd-fs.c
index ea94d950b0716..b989ab8a439cf 100644
--- a/clang/test/Misc/dev-fd-fs.c
+++ b/clang/test/Misc/dev-fd-fs.c
@@ -1,6 +1,5 @@
 // Check that we can operate on files from /dev/fd.
 // REQUIRES: dev-fd-fs
-// REQUIRES: shell
 
 // Check reading from named pipes. We cat the input here instead of redirecting
 // it to ensure that /dev/fd/0 is a named pipe, not just a redirected file.
diff --git a/llvm/utils/lit/lit/builtin_commands/cat.py 
b/llvm/utils/lit/lit/builtin_commands/cat.py
index ddab555662045..2797e0cbb4154 100644
--- a/llvm/utils/lit/lit/builtin_commands/cat.py
+++ b/llvm/utils/lit/lit/builtin_commands/cat.py
@@ -49,6 +49,9 @@ def main(argv):
 import os, msvcrt
 
 msvcrt.setmode(sys.stdout.fileno(), os.O_BINARY)
+if len(filenames) == 0:
+sys.stdout.write(sys.stdin.read())
+sys.exit(0)
 for filename in filenames:
 try:
 contents = None
diff --git a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt 
b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
index 4014b0fca1f24..c5b5d247c2f95 100644
--- a/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
+++ b/llvm/utils/lit/tests/Inputs/shtest-cat/cat.txt
@@ -70,3 +70,7 @@
 # 
NP-CAT-OUTPUT-NEXT:M-HM-IM-JM-KM-LM-MM-NM-OM-PM-QM-RM-SM-TM-UM-VM-WM-XM-YM-ZM-[
 # 
NP-CAT-OUTPUT-NEXT:M-\M-]M-^M-_M-`M-aM-bM-cM-dM-eM-fM-gM-hM-iM-jM-kM-lM-mM-nM-o
 # NP-CAT-OUTPUT-NEXT:M-pM-qM-rM-sM-tM-uM-vM-wM-xM-yM-zM-{M-|M-}M-~M-^?
+
+## Test that cat will pipe stdin to stdout if no other files are specified.
+# RUN: echo test | cat | FileCheck --check-prefix=CAT-STDIN %s
+# CAT-STDIN: test

>From 572975066e843b76e51020bcf6abc7822d3dfb75 Mon Sep 17 00:00:00 2001
From: Aiden Grossman 
Date: Sat, 13 Sep 2025 23:14:52 +
Subject: [PATCH 2/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?=
 =?UTF-8?q?anges=20introduced=20through=20rebase?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Created using spr 1.3.6

[skip ci]
---
 clang/test/ClangScanDeps/pr61006.cppm |  3 ++-
 clang/test/ClangScanDeps/resource_directory.c |  9 -
 clang/test/Driver/env.c   |  5 +++--
 clang/test/Driver/program-path-priority.c | 16 +++
 clang/test/Modules/relative-resource-dir.m|  6 +++---
 llvm/docs/CommandGuide/lit.rst|  1 +
 llvm/test/tools/llvm-cgdata/empty.test|  1 +
 llvm/utils/lit/lit/TestRunner.py  | 20 +++
 .../Inputs/shtest-readfile/absolute-paths.txt |  6 ++
 .../lit/tests/Inputs/shtest-readfile/lit.cfg  |  8 
 .../Inputs/shtest-readfile/relative-paths.txt |  7 +++
 .../Inputs/shtest-readfile/two-same-line.txt  |  8 
 llvm/utils/lit/tests/shtest-readfile.py   | 17 
 13 files changed, 88 insertions(+), 19 deletions(-)
 create mode 100644 
llvm/utils/lit/tests/Inputs/shtest-readfile/absolute-paths.txt
 create mode 100644 llvm/utils/lit/tests/Inputs/shtest-readfile/lit.cfg
 create mode 100644 
llvm/utils/lit/tests/Inputs/shtest-readfile/relative-paths.txt
 create mode 100644 
llvm/utils/lit/tests/Inputs/shtest-readfile/two-same-line.txt
 create mode 100644 llvm/utils/lit/tests/shtest-readfile.py

diff --git a/clang/test/ClangScanDeps/pr61006.cppm 
b/clang/test/ClangScanDeps/pr61006.cppm
index f75edd38c81ba..f10bc1e673987 100644
--- a/clang/test/ClangScanDeps/pr61006.cppm
+++ b/clang/test/ClangScanDeps/pr61006.cppm
@@ -6,7 +6,8 @@
 // RUN: mkdir -p %t
 // RUN: split-file %s %t
 //
-// RUN: EXPECTED_RESOURCE_DIR=`%clang -print-resource-dir` && \
+// RUN: %clang -print-resource-dir | tr -d '\n' > %t/resource-dir
+// RUN: env EXPECTED_RESOURCE_DIR=%{readfile:%t/resource-dir} && \
 // RUN: ln -s %clang++ %t/clang++ && \
 // RUN: sed "s|EXPECTED_RESOURCE_DIR|$EXPECTED_RESOURCE_DIR|g; s|DIR|%/t|g" 
%t/P1689.json.in > %t/P1689.json && \
 // RUN: clang-scan-deps -compilation-database %t/P1689.json -format=p1689 | 
FileCheck %t/a.cpp -DPREFIX=%/t && \
diff --git a/clang/test/ClangScanDeps/resource_directory.c 
b/clang/test/ClangScanDeps/resource_directory.c
index 55d5d90bbcdea..6183e8aefacfa 100644
--- a/clang/test/ClangScanDeps/resource_directory.c
+++ b/clang/test/ClangScanDeps/resource_directory.c
@@ -12,14 +12,14 @@
 //

[llvm-branch-commits] [Clang] Rewrite tests using subshells to set env variables (PR #158446)

2025-09-15 Thread Aiden Grossman via llvm-branch-commits


https://github.com/boomanaiden154 updated 
https://github.com/llvm/llvm-project/pull/158446


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[llvm-branch-commits] [llvm] AMDGPU: Stop using aligned VGPR classes for addRegisterClass (PR #158278)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158278

>From 4171b6826460f3f902c49aba03c2c6446ef61001 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 12 Sep 2025 20:45:56 +0900
Subject: [PATCH] AMDGPU: Stop using aligned VGPR classes for addRegisterClass

This is unnecessary. At use emission time, InstrEmitter will
use the common subclass of the value type's register class and
the use instruction register classes. This removes one of the
obstacles to treating special case instructions that do not have
the alignment requirement overly conservatively.
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 32 +++
 llvm/test/CodeGen/AMDGPU/mfma-loop.ll | 14 +-
 2 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp 
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 6a4df5eeb9779..4369b40e65103 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -111,52 +111,52 @@ SITargetLowering::SITargetLowering(const TargetMachine 
&TM,
   addRegisterClass(MVT::Untyped, V64RegClass);
 
   addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
-  addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96));
+  addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
 
   addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
   addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
 
   addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
-  addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128));
+  addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
 
   addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
-  addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160));
+  addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
 
   addRegisterClass(MVT::v6i32, &AMDGPU::SGPR_192RegClass);
-  addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192));
+  addRegisterClass(MVT::v6f32, &AMDGPU::VReg_192RegClass);
 
   addRegisterClass(MVT::v3i64, &AMDGPU::SGPR_192RegClass);
-  addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192));
+  addRegisterClass(MVT::v3f64, &AMDGPU::VReg_192RegClass);
 
   addRegisterClass(MVT::v7i32, &AMDGPU::SGPR_224RegClass);
-  addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224));
+  addRegisterClass(MVT::v7f32, &AMDGPU::VReg_224RegClass);
 
   addRegisterClass(MVT::v8i32, &AMDGPU::SGPR_256RegClass);
-  addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256));
+  addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
 
   addRegisterClass(MVT::v4i64, &AMDGPU::SGPR_256RegClass);
-  addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256));
+  addRegisterClass(MVT::v4f64, &AMDGPU::VReg_256RegClass);
 
   addRegisterClass(MVT::v9i32, &AMDGPU::SGPR_288RegClass);
-  addRegisterClass(MVT::v9f32, TRI->getVGPRClassForBitWidth(288));
+  addRegisterClass(MVT::v9f32, &AMDGPU::VReg_288RegClass);
 
   addRegisterClass(MVT::v10i32, &AMDGPU::SGPR_320RegClass);
-  addRegisterClass(MVT::v10f32, TRI->getVGPRClassForBitWidth(320));
+  addRegisterClass(MVT::v10f32, &AMDGPU::VReg_320RegClass);
 
   addRegisterClass(MVT::v11i32, &AMDGPU::SGPR_352RegClass);
-  addRegisterClass(MVT::v11f32, TRI->getVGPRClassForBitWidth(352));
+  addRegisterClass(MVT::v11f32, &AMDGPU::VReg_352RegClass);
 
   addRegisterClass(MVT::v12i32, &AMDGPU::SGPR_384RegClass);
-  addRegisterClass(MVT::v12f32, TRI->getVGPRClassForBitWidth(384));
+  addRegisterClass(MVT::v12f32, &AMDGPU::VReg_384RegClass);
 
   addRegisterClass(MVT::v16i32, &AMDGPU::SGPR_512RegClass);
-  addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512));
+  addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
 
   addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);
-  addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512));
+  addRegisterClass(MVT::v8f64, &AMDGPU::VReg_512RegClass);
 
   addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);
-  addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024));
+  addRegisterClass(MVT::v16f64, &AMDGPU::VReg_1024RegClass);
 
   if (Subtarget->has16BitInsts()) {
 if (Subtarget->useRealTrue16Insts()) {
@@ -188,7 +188,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
   }
 
   addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
-  addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024));
+  addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
 
   computeRegisterProperties(Subtarget->getRegisterInfo());
 
diff --git a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll 
b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
index d39daaade677f..3657a6b1b7415 100644
--- a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
@@ -2430,8 +2430,9 @@ define amdgpu_kernel void 
@test_mfma_nested_loop_zeroinit(ptr addrspace(1) %arg)
 ; GFX90A-NEXT:v_accvgpr_mov_b32 a29, a0
 ; GFX90A-NEXT:v_accvgpr_mov_b32 a30, a0
 ; GFX90A-NEXT

[llvm-branch-commits] [llvm] Mips: Switch to RegClassByHwMode (PR #158273)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158273

>From cc9b01e0048fccbc36cc5c1b6b94e723b6636262 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Sat, 6 Sep 2025 21:14:45 +0900
Subject: [PATCH] Mips: Switch to RegClassByHwMode

---
 .../Target/Mips/AsmParser/MipsAsmParser.cpp   |  9 +--
 .../Mips/Disassembler/MipsDisassembler.cpp| 24 +++
 llvm/lib/Target/Mips/MicroMipsInstrInfo.td| 12 +++---
 llvm/lib/Target/Mips/Mips.td  | 15 
 llvm/lib/Target/Mips/MipsInstrInfo.td | 20 +++-
 llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 16 ++---
 llvm/lib/Target/Mips/MipsRegisterInfo.td  | 16 +
 7 files changed, 76 insertions(+), 36 deletions(-)

diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp 
b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 8a5cb517c94c5..ba70c9e6cb9e8 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3706,7 +3706,9 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc 
IDLoc, MCStreamer &Out,
   MCRegister TmpReg = DstReg;
 
   const MCInstrDesc &Desc = MII.get(OpCode);
-  int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
+  int16_t DstRegClass =
+  MII.getOpRegClassID(Desc.operands()[StartOp],
+  STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo));
   unsigned DstRegClassID =
   getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
@@ -3834,7 +3836,10 @@ void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc 
IDLoc, MCStreamer &Out,
   MCRegister TmpReg = DstReg;
 
   const MCInstrDesc &Desc = MII.get(OpCode);
-  int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
+  int16_t DstRegClass =
+  MII.getOpRegClassID(Desc.operands()[StartOp],
+  STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo));
+
   unsigned DstRegClassID =
   getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp 
b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index c22b8f61b12dc..705695c74803f 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -916,6 +916,30 @@ DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned 
RegNo, uint64_t Address,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
  uint64_t Address,
  const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td 
b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index b3fd8f422f429..b44bf1391b73e 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -57,12 +57,6 @@ def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
   let PredicateMethod = "isMemWithGRPMM16Base";
 }
 
-// Define the classes of pointers used by microMIPS.
-// The numbers must match those in MipsRegisterInfo::MipsPtrClass.
-def ptr_gpr16mm_rc : PointerLikeRegClass<1>;
-def ptr_sp_rc : PointerLikeRegClass<2>;
-def ptr_gp_rc : PointerLikeRegClass<3>;
-
 class mem_mm_4_generic : Operand {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops ptr_gpr16mm_rc, simm4);
@@ -114,7 +108,7 @@ def mem_mm_gp_simm7_lsl2 : Operand {
 
 def mem_mm_9 : Operand {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm9);
+  let MIOperandInfo = (ops mips_ptr_rc, simm9);
   let EncoderMethod = "getMemEncodingMMImm9";
   let ParserMatchClass = MipsMemSimmAsmOperand<9>;
   let OperandType = "OPERAND_MEMORY";
@@ -130,7 +124,7 @@ def mem_mm_11

[llvm-branch-commits] [llvm] AMDGPU: Stop using aligned VGPR classes for addRegisterClass (PR #158278)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158278

>From 4171b6826460f3f902c49aba03c2c6446ef61001 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 12 Sep 2025 20:45:56 +0900
Subject: [PATCH] AMDGPU: Stop using aligned VGPR classes for addRegisterClass

This is unnecessary. At use emission time, InstrEmitter will
use the common subclass of the value type's register class and
the use instruction register classes. This removes one of the
obstacles to treating special case instructions that do not have
the alignment requirement overly conservatively.
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 32 +++
 llvm/test/CodeGen/AMDGPU/mfma-loop.ll | 14 +-
 2 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp 
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 6a4df5eeb9779..4369b40e65103 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -111,52 +111,52 @@ SITargetLowering::SITargetLowering(const TargetMachine 
&TM,
   addRegisterClass(MVT::Untyped, V64RegClass);
 
   addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
-  addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96));
+  addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
 
   addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
   addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
 
   addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
-  addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128));
+  addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
 
   addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
-  addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160));
+  addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
 
   addRegisterClass(MVT::v6i32, &AMDGPU::SGPR_192RegClass);
-  addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192));
+  addRegisterClass(MVT::v6f32, &AMDGPU::VReg_192RegClass);
 
   addRegisterClass(MVT::v3i64, &AMDGPU::SGPR_192RegClass);
-  addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192));
+  addRegisterClass(MVT::v3f64, &AMDGPU::VReg_192RegClass);
 
   addRegisterClass(MVT::v7i32, &AMDGPU::SGPR_224RegClass);
-  addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224));
+  addRegisterClass(MVT::v7f32, &AMDGPU::VReg_224RegClass);
 
   addRegisterClass(MVT::v8i32, &AMDGPU::SGPR_256RegClass);
-  addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256));
+  addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
 
   addRegisterClass(MVT::v4i64, &AMDGPU::SGPR_256RegClass);
-  addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256));
+  addRegisterClass(MVT::v4f64, &AMDGPU::VReg_256RegClass);
 
   addRegisterClass(MVT::v9i32, &AMDGPU::SGPR_288RegClass);
-  addRegisterClass(MVT::v9f32, TRI->getVGPRClassForBitWidth(288));
+  addRegisterClass(MVT::v9f32, &AMDGPU::VReg_288RegClass);
 
   addRegisterClass(MVT::v10i32, &AMDGPU::SGPR_320RegClass);
-  addRegisterClass(MVT::v10f32, TRI->getVGPRClassForBitWidth(320));
+  addRegisterClass(MVT::v10f32, &AMDGPU::VReg_320RegClass);
 
   addRegisterClass(MVT::v11i32, &AMDGPU::SGPR_352RegClass);
-  addRegisterClass(MVT::v11f32, TRI->getVGPRClassForBitWidth(352));
+  addRegisterClass(MVT::v11f32, &AMDGPU::VReg_352RegClass);
 
   addRegisterClass(MVT::v12i32, &AMDGPU::SGPR_384RegClass);
-  addRegisterClass(MVT::v12f32, TRI->getVGPRClassForBitWidth(384));
+  addRegisterClass(MVT::v12f32, &AMDGPU::VReg_384RegClass);
 
   addRegisterClass(MVT::v16i32, &AMDGPU::SGPR_512RegClass);
-  addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512));
+  addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
 
   addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);
-  addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512));
+  addRegisterClass(MVT::v8f64, &AMDGPU::VReg_512RegClass);
 
   addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);
-  addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024));
+  addRegisterClass(MVT::v16f64, &AMDGPU::VReg_1024RegClass);
 
   if (Subtarget->has16BitInsts()) {
 if (Subtarget->useRealTrue16Insts()) {
@@ -188,7 +188,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
   }
 
   addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
-  addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024));
+  addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
 
   computeRegisterProperties(Subtarget->getRegisterInfo());
 
diff --git a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll 
b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
index d39daaade677f..3657a6b1b7415 100644
--- a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
@@ -2430,8 +2430,9 @@ define amdgpu_kernel void 
@test_mfma_nested_loop_zeroinit(ptr addrspace(1) %arg)
 ; GFX90A-NEXT:v_accvgpr_mov_b32 a29, a0
 ; GFX90A-NEXT:v_accvgpr_mov_b32 a30, a0
 ; GFX90A-NEXT

[llvm-branch-commits] [llvm] SPARC: Use RegClassByHwMode instead of PointerLikeRegClass (PR #158271)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158271

>From 7827021f8503e35f4e0a26c51cace91f1eff221e Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Mon, 8 Sep 2025 14:04:59 +0900
Subject: [PATCH] SPARC: Use RegClassByHwMode instead of PointerLikeRegClass

---
 .../Sparc/Disassembler/SparcDisassembler.cpp  |  8 ---
 llvm/lib/Target/Sparc/SparcInstrInfo.td   | 21 +--
 2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp 
b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index c3d60f3689e1f..e585e5af42d32 100644
--- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -159,14 +159,6 @@ static DecodeStatus DecodeI64RegsRegisterClass(MCInst 
&Inst, unsigned RegNo,
   return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-// This is used for the type "ptr_rc", which is either IntRegs or I64Regs
-// depending on SparcRegisterInfo::getPointerRegClass.
-static DecodeStatus DecodePointerLikeRegClass0(MCInst &Inst, unsigned RegNo,
-   uint64_t Address,
-   const MCDisassembler *Decoder) {
-  return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
-}
-
 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
   uint64_t Address,
   const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td 
b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 53972d6c105a4..97e7fd7769edb 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -95,10 +95,27 @@ def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;
 // will pick deprecated instructions.
 def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;
 
+//===--===//
+// HwModes Pattern Stuff
+//===--===//
+
+defvar SPARC32 = DefaultMode;
+def SPARC64 : HwMode<[Is64Bit]>;
+
 
//===--===//
 // Instruction Pattern Stuff
 
//===--===//
 
+def sparc_ptr_rc : RegClassByHwMode<
+  [SPARC32, SPARC64],
+  [IntRegs, I64Regs]>;
+
+// Both cases can use the same decoder method, so avoid the dispatch
+// by hwmode by setting an explicit DecoderMethod
+def ptr_op : RegisterOperand {
+  let DecoderMethod = "DecodeIntRegsRegisterClass";
+}
+
 // FIXME these should have AsmOperandClass.
 def uimm3 : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>;
 
@@ -178,12 +195,12 @@ def simm13Op : Operand {
 
 def MEMrr : Operand {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, ptr_rc);
+  let MIOperandInfo = (ops ptr_op, ptr_op);
   let ParserMatchClass = SparcMEMrrAsmOperand;
 }
 def MEMri : Operand {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm13Op);
+  let MIOperandInfo = (ops ptr_op, simm13Op);
   let ParserMatchClass = SparcMEMriAsmOperand;
 }
 

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[llvm-branch-commits] [llvm] X86: Switch to RegClassByHwMode (PR #158274)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158274

>From ca5e60cdcc0361801f48a32bed21ef65c90db89c Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Tue, 9 Sep 2025 11:15:47 +0900
Subject: [PATCH] X86: Switch to RegClassByHwMode

Replace the target uses of PointerLikeRegClass with RegClassByHwMode
---
 .../X86/MCTargetDesc/X86MCTargetDesc.cpp  |  3 ++
 llvm/lib/Target/X86/X86.td|  2 ++
 llvm/lib/Target/X86/X86InstrInfo.td   |  8 ++---
 llvm/lib/Target/X86/X86InstrOperands.td   | 30 +++-
 llvm/lib/Target/X86/X86InstrPredicates.td | 14 
 llvm/lib/Target/X86/X86RegisterInfo.cpp   | 35 +--
 llvm/lib/Target/X86/X86Subtarget.h|  4 +--
 llvm/utils/TableGen/X86FoldTablesEmitter.cpp  |  4 +--
 8 files changed, 57 insertions(+), 43 deletions(-)

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 
b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index bb1e716c33ed5..1d5ef8b0996dc 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -55,6 +55,9 @@ std::string X86_MC::ParseX86Triple(const Triple &TT) {
   else
 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
 
+  if (TT.isX32())
+FS += ",+x32";
+
   return FS;
 }
 
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 7c9e821c02fda..3af8b3e060a16 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -25,6 +25,8 @@ def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", 
"true",
"32-bit mode (80386)">;
 def Is16Bit : SubtargetFeature<"16bit-mode", "Is16Bit", "true",
"16-bit mode (i8086)">;
+def IsX32 : SubtargetFeature<"x32", "IsX32", "true",
+ "64-bit with ILP32 programming model (e.g. x32 
ABI)">;
 
 
//===--===//
 // X86 Subtarget ISA features
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td 
b/llvm/lib/Target/X86/X86InstrInfo.td
index 7f6c5614847e3..0c4abc2c400f6 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -18,14 +18,14 @@ include "X86InstrFragments.td"
 include "X86InstrFragmentsSIMD.td"
 
 
//===--===//
-// X86 Operand Definitions.
+// X86 Predicate Definitions.
 //
-include "X86InstrOperands.td"
+include "X86InstrPredicates.td"
 
 
//===--===//
-// X86 Predicate Definitions.
+// X86 Operand Definitions.
 //
-include "X86InstrPredicates.td"
+include "X86InstrOperands.td"
 
 
//===--===//
 // X86 Instruction Format Definitions.
diff --git a/llvm/lib/Target/X86/X86InstrOperands.td 
b/llvm/lib/Target/X86/X86InstrOperands.td
index 80843f6bb80e6..5207ecad127a2 100644
--- a/llvm/lib/Target/X86/X86InstrOperands.td
+++ b/llvm/lib/Target/X86/X86InstrOperands.td
@@ -6,9 +6,15 @@
 //
 
//===--===//
 
+def x86_ptr_rc : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32, GR64, LOW32_ADDR_ACCESS]>;
+
 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
 // the index operand of an address, to conform to x86 encoding restrictions.
-def ptr_rc_nosp : PointerLikeRegClass<1>;
+def ptr_rc_nosp : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32_NOSP, GR64_NOSP, GR32_NOSP]>;
 
 // *mem - Operand definitions for the funky X86 addressing mode operands.
 //
@@ -53,7 +59,7 @@ class X86MemOperand : Operand {
   let PrintMethod = printMethod;
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
+  let MIOperandInfo = (ops x86_ptr_rc, i8imm, ptr_rc_nosp, i32imm, 
SEGMENT_REG);
   let ParserMatchClass = parserMatchClass;
   let OperandType = "OPERAND_MEMORY";
   int Size = size;
@@ -63,7 +69,7 @@ class X86MemOperand
 : X86MemOperand {
-  let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG);
+  let MIOperandInfo = (ops x86_ptr_rc, i8imm, RC, i32imm, SEGMENT_REG);
 }
 
 def anymem : X86MemOperand<"printMemReference">;
@@ -113,8 +119,14 @@ def sdmem : X86MemOperand<"printqwordmem", 
X86Mem64AsmOperand>;
 
 // A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead
 // of a plain GPR, so that it doesn't potentially require a REX prefix.
-def ptr_rc_norex : PointerLikeRegClass<2>;
-def ptr_rc_norex_nosp : PointerLikeRegClass<3>;
+def ptr_rc_norex : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32_NOREX, GR64_NOREX, GR32_NOREX]>;
+
+def ptr_rc_norex_nosp : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32_NOREX_NOSP, GR64_NOREX_NOSP, GR32_NOREX_NOSP]>;
+
 
 def i8mem_NOREX : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8> {
   let MIOpe

[llvm-branch-commits] [llvm] PPC: Replace PointerLikeRegClass with RegClassByHwMode (PR #158777)

2025-09-15 Thread via llvm-branch-commits


llvmbot wrote:



@llvm/pr-subscribers-backend-systemz

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)


Changes



---
Full diff: https://github.com/llvm/llvm-project/pull/158777.diff


4 Files Affected:

- (modified) llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp (-3) 
- (modified) llvm/lib/Target/PowerPC/PPC.td (+6) 
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.cpp (+9-19) 
- (modified) llvm/lib/Target/PowerPC/PPCRegisterInfo.td (+8-2) 


``diff
diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp 
b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 47586c417cfe3..70e619cc22b19 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -185,9 +185,6 @@ DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, 
uint64_t Address,
   return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
 }
 
-#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
-#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
-
 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
  uint64_t Address,
  const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 386d0f65d1ed1..d491e88b66ad8 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -394,6 +394,12 @@ def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
 def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
 def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;
 
+//===--===//
+// HwModes
+//===--===//
+
+defvar PPC32 = DefaultMode;
+def PPC64 : HwMode<[In64BitMode]>;
 
 // Since new processors generally contain a superset of features of those that
 // came before them, the idea is to make implementations of new processors
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index db066bc4b7bdd..55e38bcf4afc9 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2142,33 +2142,23 @@ bool PPCInstrInfo::onlyFoldImmediate(MachineInstr 
&UseMI, MachineInstr &DefMI,
   assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
   assert(UseIdx < UseMCID.getNumOperands() && "No operand description for 
Reg");
 
-  const MCOperandInfo *UseInfo = &UseMCID.operands()[UseIdx];
-
   // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
   // register (which might also be specified as a pointer class kind).
-  if (UseInfo->isLookupPtrRegClass()) {
-if (UseInfo->RegClass /* Kind */ != 1)
-  return false;
-  } else {
-if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
-UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
-  return false;
-  }
+
+  const MCOperandInfo &UseInfo = UseMCID.operands()[UseIdx];
+  int16_t RegClass = getOpRegClassID(UseInfo);
+  if (UseInfo.RegClass != PPC::GPRC_NOR0RegClassID &&
+  UseInfo.RegClass != PPC::G8RC_NOX0RegClassID)
+return false;
 
   // Make sure this is not tied to an output register (or otherwise
   // constrained). This is true for ST?UX registers, for example, which
   // are tied to their output registers.
-  if (UseInfo->Constraints != 0)
+  if (UseInfo.Constraints != 0)
 return false;
 
-  MCRegister ZeroReg;
-  if (UseInfo->isLookupPtrRegClass()) {
-bool isPPC64 = Subtarget.isPPC64();
-ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
-  } else {
-ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
-  PPC::ZERO8 : PPC::ZERO;
-  }
+  MCRegister ZeroReg =
+  RegClass == PPC::G8RC_NOX0RegClassID ? PPC::ZERO8 : PPC::ZERO;
 
   LLVM_DEBUG(dbgs() << "Folded immediate zero for: ");
   LLVM_DEBUG(UseMI.dump());
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td 
b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 8b690b7b833b3..adda91786d19c 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -868,7 +868,11 @@ def crbitm: Operand {
 def PPCRegGxRCNoR0Operand : AsmOperandClass {
   let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
 }
-def ptr_rc_nor0 : Operand, PointerLikeRegClass<1> {
+
+def ptr_rc_nor0 : Operand,
+  RegClassByHwMode<
+[PPC32, PPC64],
+[GPRC_NOR0, G8RC_NOX0]> {
   let ParserMatchClass = PPCRegGxRCNoR0Operand;
 }
 
@@ -902,7 +906,9 @@ def memri34_pcrel : Operand { // memri, imm is a 
34-bit value.
 def PPCRegGxRCOperand : AsmOperandClass {
   let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
 }
-def ptr_rc_idx : Operand, PointerLikeRegClass<0> {
+def ptr_rc_idx : Operand,
+  RegClassByHwMode<[PPC32, PPC64],
+   [GPRC, G8RC]> {
   let ParserMatchClass

[llvm-branch-commits] [llvm] X86: Switch to RegClassByHwMode (PR #158274)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158274

>From ca5e60cdcc0361801f48a32bed21ef65c90db89c Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Tue, 9 Sep 2025 11:15:47 +0900
Subject: [PATCH] X86: Switch to RegClassByHwMode

Replace the target uses of PointerLikeRegClass with RegClassByHwMode
---
 .../X86/MCTargetDesc/X86MCTargetDesc.cpp  |  3 ++
 llvm/lib/Target/X86/X86.td|  2 ++
 llvm/lib/Target/X86/X86InstrInfo.td   |  8 ++---
 llvm/lib/Target/X86/X86InstrOperands.td   | 30 +++-
 llvm/lib/Target/X86/X86InstrPredicates.td | 14 
 llvm/lib/Target/X86/X86RegisterInfo.cpp   | 35 +--
 llvm/lib/Target/X86/X86Subtarget.h|  4 +--
 llvm/utils/TableGen/X86FoldTablesEmitter.cpp  |  4 +--
 8 files changed, 57 insertions(+), 43 deletions(-)

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 
b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index bb1e716c33ed5..1d5ef8b0996dc 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -55,6 +55,9 @@ std::string X86_MC::ParseX86Triple(const Triple &TT) {
   else
 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
 
+  if (TT.isX32())
+FS += ",+x32";
+
   return FS;
 }
 
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 7c9e821c02fda..3af8b3e060a16 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -25,6 +25,8 @@ def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", 
"true",
"32-bit mode (80386)">;
 def Is16Bit : SubtargetFeature<"16bit-mode", "Is16Bit", "true",
"16-bit mode (i8086)">;
+def IsX32 : SubtargetFeature<"x32", "IsX32", "true",
+ "64-bit with ILP32 programming model (e.g. x32 
ABI)">;
 
 
//===--===//
 // X86 Subtarget ISA features
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td 
b/llvm/lib/Target/X86/X86InstrInfo.td
index 7f6c5614847e3..0c4abc2c400f6 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -18,14 +18,14 @@ include "X86InstrFragments.td"
 include "X86InstrFragmentsSIMD.td"
 
 
//===--===//
-// X86 Operand Definitions.
+// X86 Predicate Definitions.
 //
-include "X86InstrOperands.td"
+include "X86InstrPredicates.td"
 
 
//===--===//
-// X86 Predicate Definitions.
+// X86 Operand Definitions.
 //
-include "X86InstrPredicates.td"
+include "X86InstrOperands.td"
 
 
//===--===//
 // X86 Instruction Format Definitions.
diff --git a/llvm/lib/Target/X86/X86InstrOperands.td 
b/llvm/lib/Target/X86/X86InstrOperands.td
index 80843f6bb80e6..5207ecad127a2 100644
--- a/llvm/lib/Target/X86/X86InstrOperands.td
+++ b/llvm/lib/Target/X86/X86InstrOperands.td
@@ -6,9 +6,15 @@
 //
 
//===--===//
 
+def x86_ptr_rc : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32, GR64, LOW32_ADDR_ACCESS]>;
+
 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
 // the index operand of an address, to conform to x86 encoding restrictions.
-def ptr_rc_nosp : PointerLikeRegClass<1>;
+def ptr_rc_nosp : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32_NOSP, GR64_NOSP, GR32_NOSP]>;
 
 // *mem - Operand definitions for the funky X86 addressing mode operands.
 //
@@ -53,7 +59,7 @@ class X86MemOperand : Operand {
   let PrintMethod = printMethod;
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
+  let MIOperandInfo = (ops x86_ptr_rc, i8imm, ptr_rc_nosp, i32imm, 
SEGMENT_REG);
   let ParserMatchClass = parserMatchClass;
   let OperandType = "OPERAND_MEMORY";
   int Size = size;
@@ -63,7 +69,7 @@ class X86MemOperand
 : X86MemOperand {
-  let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG);
+  let MIOperandInfo = (ops x86_ptr_rc, i8imm, RC, i32imm, SEGMENT_REG);
 }
 
 def anymem : X86MemOperand<"printMemReference">;
@@ -113,8 +119,14 @@ def sdmem : X86MemOperand<"printqwordmem", 
X86Mem64AsmOperand>;
 
 // A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead
 // of a plain GPR, so that it doesn't potentially require a REX prefix.
-def ptr_rc_norex : PointerLikeRegClass<2>;
-def ptr_rc_norex_nosp : PointerLikeRegClass<3>;
+def ptr_rc_norex : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32_NOREX, GR64_NOREX, GR32_NOREX]>;
+
+def ptr_rc_norex_nosp : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32_NOREX_NOSP, GR64_NOREX_NOSP, GR32_NOREX_NOSP]>;
+
 
 def i8mem_NOREX : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8> {
   let MIOpe

[llvm-branch-commits] [llvm] SPARC: Use RegClassByHwMode instead of PointerLikeRegClass (PR #158271)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158271

>From 7827021f8503e35f4e0a26c51cace91f1eff221e Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Mon, 8 Sep 2025 14:04:59 +0900
Subject: [PATCH] SPARC: Use RegClassByHwMode instead of PointerLikeRegClass

---
 .../Sparc/Disassembler/SparcDisassembler.cpp  |  8 ---
 llvm/lib/Target/Sparc/SparcInstrInfo.td   | 21 +--
 2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp 
b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index c3d60f3689e1f..e585e5af42d32 100644
--- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -159,14 +159,6 @@ static DecodeStatus DecodeI64RegsRegisterClass(MCInst 
&Inst, unsigned RegNo,
   return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-// This is used for the type "ptr_rc", which is either IntRegs or I64Regs
-// depending on SparcRegisterInfo::getPointerRegClass.
-static DecodeStatus DecodePointerLikeRegClass0(MCInst &Inst, unsigned RegNo,
-   uint64_t Address,
-   const MCDisassembler *Decoder) {
-  return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
-}
-
 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo,
   uint64_t Address,
   const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td 
b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 53972d6c105a4..97e7fd7769edb 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -95,10 +95,27 @@ def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;
 // will pick deprecated instructions.
 def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;
 
+//===--===//
+// HwModes Pattern Stuff
+//===--===//
+
+defvar SPARC32 = DefaultMode;
+def SPARC64 : HwMode<[Is64Bit]>;
+
 
//===--===//
 // Instruction Pattern Stuff
 
//===--===//
 
+def sparc_ptr_rc : RegClassByHwMode<
+  [SPARC32, SPARC64],
+  [IntRegs, I64Regs]>;
+
+// Both cases can use the same decoder method, so avoid the dispatch
+// by hwmode by setting an explicit DecoderMethod
+def ptr_op : RegisterOperand {
+  let DecoderMethod = "DecodeIntRegsRegisterClass";
+}
+
 // FIXME these should have AsmOperandClass.
 def uimm3 : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>;
 
@@ -178,12 +195,12 @@ def simm13Op : Operand {
 
 def MEMrr : Operand {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, ptr_rc);
+  let MIOperandInfo = (ops ptr_op, ptr_op);
   let ParserMatchClass = SparcMEMrrAsmOperand;
 }
 def MEMri : Operand {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm13Op);
+  let MIOperandInfo = (ops ptr_op, simm13Op);
   let ParserMatchClass = SparcMEMriAsmOperand;
 }
 

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[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


https://github.com/makslevental updated 
https://github.com/llvm/llvm-project/pull/157944

>From f9dbe48eaa691ca9f8161e9dc3a800bb613d5bc9 Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 12:57:54 -0700
Subject: [PATCH 01/14] [MLIR][Standalone] test Standalone against install
 distributions

---
 mlir/test/Examples/standalone/lit.local.cfg  |  2 ++
 .../Examples/standalone/test.toy.install-dir | 16 
 mlir/test/lit.cfg.py |  3 +++
 mlir/test/lit.site.cfg.py.in |  1 +
 4 files changed, 22 insertions(+)
 create mode 100644 mlir/test/Examples/standalone/test.toy.install-dir

diff --git a/mlir/test/Examples/standalone/lit.local.cfg 
b/mlir/test/Examples/standalone/lit.local.cfg
index fe8397c6b9a10..bc9928decf527 100644
--- a/mlir/test/Examples/standalone/lit.local.cfg
+++ b/mlir/test/Examples/standalone/lit.local.cfg
@@ -10,3 +10,5 @@ config.substitutions.append(("%host_cc", config.host_cc))
 config.substitutions.append(("%enable_libcxx", config.enable_libcxx))
 config.substitutions.append(("%mlir_cmake_dir", config.mlir_cmake_dir))
 config.substitutions.append(("%llvm_use_linker", config.llvm_use_linker))
+config.substitutions.append(("%llvm_obj_root", config.llvm_obj_root))
+config.substitutions.append(("%host_cmake_install_prefix", 
config.host_cmake_install_prefix))
diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.toy.install-dir
new file mode 100644
index 0..5c33a70491ae1
--- /dev/null
+++ b/mlir/test/Examples/standalone/test.toy.install-dir
@@ -0,0 +1,16 @@
+# REQUIRES: github-actions
+# RUN: "%cmake_exe" --build %llvm_obj_root --target install
+# RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
+# RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DLLVM_ENABLE_LIBCXX=%enable_libcxx 
-DMLIR_DIR=%host_cmake_install_prefix \
+# RUN: -DLLVM_USE_LINKER=%llvm_use_linker \
+# RUN: -DPython3_EXECUTABLE=%python \
+# RUN: -DPython_EXECUTABLE=%python
+# RUN: "%cmake_exe" --build . --target check-standalone | tee %t
+# RUN: FileCheck --input-file=%t %s
+
+# Note: The number of checked tests is not important. The command will fail
+# if any fail.
+# CHECK: Passed
+# CHECK-NOT: Failed
+# UNSUPPORTED: target={{.*(windows|android).*}}
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index f99c24d6e299a..08c7947c1e9a6 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -383,3 +383,6 @@ def have_host_jit_feature_support(feature_name):
 
 if sys.version_info >= (3, 11):
 config.available_features.add("python-ge-311")
+
+if "GITHUB_ACTIONS" in os.environ:
+config.available_features.add("github-actions")
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 8a742a227847b..7e22ebf23c773 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -18,6 +18,7 @@ config.host_cxx = "@HOST_CXX@"
 config.enable_libcxx = "@LLVM_ENABLE_LIBCXX@"
 config.host_cmake = "@CMAKE_COMMAND@"
 config.host_cmake_generator = "@CMAKE_GENERATOR@"
+config.host_cmake_install_prefix = "@CMAKE_INSTALL_PREFIX@"
 config.llvm_use_linker = "@LLVM_USE_LINKER@"
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.host_arch = "@HOST_ARCH@"

>From fc56d49c9481aed16b79f391368f4c3824a90695 Mon Sep 17 00:00:00 2001
From: Maksim Levental 
Date: Wed, 10 Sep 2025 13:23:07 -0700
Subject: [PATCH 02/14] Update lit.site.cfg.py.in

---
 .../standalone/{test.toy.install-dir => test.install-dir.toy}| 0
 mlir/test/lit.site.cfg.py.in | 1 +
 2 files changed, 1 insertion(+)
 rename mlir/test/Examples/standalone/{test.toy.install-dir => 
test.install-dir.toy} (100%)

diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.install-dir.toy
similarity index 100%
rename from mlir/test/Examples/standalone/test.toy.install-dir
rename to mlir/test/Examples/standalone/test.install-dir.toy
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 7e22ebf23c773..eadfd047d15f7 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -3,6 +3,7 @@
 import sys
 
 config.target_triple = "@LLVM_TARGET_TRIPLE@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_tools_dir = lit_config.substitute("@LLVM_TOOLS_DIR@")
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"

>From 67ce5b688657d38b6792b05712d1de6f56e726fe Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 15:54:54 -0700
Subject: [PATCH 03/14] add test.install-distribution-dir.toy

---
 mlir/test/Examples/standalone/lit.local.cfg |  1 +
 .../Examples/standalone/test.install-dir.toy|  4 ++--
 .../test.install-distribution-dir.toy   | 17 +
 3 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 
mlir/test/Examples/stand

[llvm-branch-commits] [llvm] PPC: Replace PointerLikeRegClass with RegClassByHwMode (PR #158777)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


arsenm wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/158777?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
> https://graphite.dev/docs/merge-pull-requests";>Learn more

* **#158777** https://app.graphite.dev/github/pr/llvm/llvm-project/158777?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/158777?utm_source=stack-comment-view-in-graphite";
 target="_blank">(View in Graphite)
* **#158269** https://app.graphite.dev/github/pr/llvm/llvm-project/158269?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>: 4 other dependent PRs 
([#158271](https://github.com/llvm/llvm-project/pull/158271) https://app.graphite.dev/github/pr/llvm/llvm-project/158271?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>, 
[#158272](https://github.com/llvm/llvm-project/pull/158272) https://app.graphite.dev/github/pr/llvm/llvm-project/158272?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>, 
[#158273](https://github.com/llvm/llvm-project/pull/158273) https://app.graphite.dev/github/pr/llvm/llvm-project/158273?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/> and 1 other)
* `main`




This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn 
more about https://stacking.dev/?utm_source=stack-comment";>stacking.


https://github.com/llvm/llvm-project/pull/158777
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[llvm-branch-commits] [llvm] PPC: Replace PointerLikeRegClass with RegClassByHwMode (PR #158777)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm created 
https://github.com/llvm/llvm-project/pull/158777

None

>From 0821bf6b56fbcf9aebc2eea8b4e1af02f9f2d1f9 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 5 Sep 2025 18:03:59 +0900
Subject: [PATCH] PPC: Replace PointerLikeRegClass with RegClassByHwMode

---
 .../PowerPC/Disassembler/PPCDisassembler.cpp  |  3 --
 llvm/lib/Target/PowerPC/PPC.td|  6 
 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp  | 28 ++-
 llvm/lib/Target/PowerPC/PPCRegisterInfo.td| 10 +--
 4 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp 
b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 47586c417cfe3..70e619cc22b19 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -185,9 +185,6 @@ DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, 
uint64_t Address,
   return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
 }
 
-#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
-#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
-
 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
  uint64_t Address,
  const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 386d0f65d1ed1..d491e88b66ad8 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -394,6 +394,12 @@ def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
 def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
 def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;
 
+//===--===//
+// HwModes
+//===--===//
+
+defvar PPC32 = DefaultMode;
+def PPC64 : HwMode<[In64BitMode]>;
 
 // Since new processors generally contain a superset of features of those that
 // came before them, the idea is to make implementations of new processors
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index db066bc4b7bdd..55e38bcf4afc9 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2142,33 +2142,23 @@ bool PPCInstrInfo::onlyFoldImmediate(MachineInstr 
&UseMI, MachineInstr &DefMI,
   assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
   assert(UseIdx < UseMCID.getNumOperands() && "No operand description for 
Reg");
 
-  const MCOperandInfo *UseInfo = &UseMCID.operands()[UseIdx];
-
   // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
   // register (which might also be specified as a pointer class kind).
-  if (UseInfo->isLookupPtrRegClass()) {
-if (UseInfo->RegClass /* Kind */ != 1)
-  return false;
-  } else {
-if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
-UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
-  return false;
-  }
+
+  const MCOperandInfo &UseInfo = UseMCID.operands()[UseIdx];
+  int16_t RegClass = getOpRegClassID(UseInfo);
+  if (UseInfo.RegClass != PPC::GPRC_NOR0RegClassID &&
+  UseInfo.RegClass != PPC::G8RC_NOX0RegClassID)
+return false;
 
   // Make sure this is not tied to an output register (or otherwise
   // constrained). This is true for ST?UX registers, for example, which
   // are tied to their output registers.
-  if (UseInfo->Constraints != 0)
+  if (UseInfo.Constraints != 0)
 return false;
 
-  MCRegister ZeroReg;
-  if (UseInfo->isLookupPtrRegClass()) {
-bool isPPC64 = Subtarget.isPPC64();
-ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
-  } else {
-ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
-  PPC::ZERO8 : PPC::ZERO;
-  }
+  MCRegister ZeroReg =
+  RegClass == PPC::G8RC_NOX0RegClassID ? PPC::ZERO8 : PPC::ZERO;
 
   LLVM_DEBUG(dbgs() << "Folded immediate zero for: ");
   LLVM_DEBUG(UseMI.dump());
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td 
b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 8b690b7b833b3..adda91786d19c 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -868,7 +868,11 @@ def crbitm: Operand {
 def PPCRegGxRCNoR0Operand : AsmOperandClass {
   let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
 }
-def ptr_rc_nor0 : Operand, PointerLikeRegClass<1> {
+
+def ptr_rc_nor0 : Operand,
+  RegClassByHwMode<
+[PPC32, PPC64],
+[GPRC_NOR0, G8RC_NOX0]> {
   let ParserMatchClass = PPCRegGxRCNoR0Operand;
 }
 
@@ -902,7 +906,9 @@ def memri34_pcrel : Operand { // memri, imm is a 
34-bit value.
 def PPCRegGxRCOperand : AsmOperandClass {
   let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
 }
-def ptr_rc_idx : Operand, PointerLikeRegClass<0> {
+def ptr_rc_idx : Operan

[llvm-branch-commits] [llvm] PPC: Replace PointerLikeRegClass with RegClassByHwMode (PR #158777)

2025-09-15 Thread Sergei Barannikov via llvm-branch-commits


https://github.com/s-barannikov edited 
https://github.com/llvm/llvm-project/pull/158777
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[llvm-branch-commits] [llvm] PPC: Replace PointerLikeRegClass with RegClassByHwMode (PR #158777)

2025-09-15 Thread Sergei Barannikov via llvm-branch-commits



@@ -868,7 +868,11 @@ def crbitm: Operand {
 def PPCRegGxRCNoR0Operand : AsmOperandClass {
   let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
 }
-def ptr_rc_nor0 : Operand, PointerLikeRegClass<1> {
+
+def ptr_rc_nor0 : Operand,

s-barannikov wrote:

Should it still derive from Operand?

https://github.com/llvm/llvm-project/pull/158777
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[llvm-branch-commits] [llvm] [LoongArch] Make {sadd, ssub, uadd, usub}sat legal for lsx/lasx (PR #158209)

2025-09-15 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining edited 
https://github.com/llvm/llvm-project/pull/158209
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[llvm-branch-commits] [llvm] [LoongArch] Make {sadd, ssub, uadd, usub}sat legal for lsx/lasx (PR #158209)

2025-09-15 Thread Lu Weining via llvm-branch-commits


https://github.com/SixWeining approved this pull request.


https://github.com/llvm/llvm-project/pull/158209
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[llvm-branch-commits] [llvm] [DA] Fix Strong SIV test for symbolic coefficients and deltas (#149977) (PR #157738)

2025-09-15 Thread Sushant Gokhale via llvm-branch-commits



@@ -1293,9 +1316,40 @@ bool DependenceInfo::strongSIVtest(const SCEV *Coeff, 
const SCEV *SrcConst,
   Result.DV[Level].Distance = Delta; // since X/1 == X
   NewConstraint.setDistance(Delta, CurLoop);
 } else {
-  Result.Consistent = false;
-  NewConstraint.setLine(Coeff, SE->getNegativeSCEV(Coeff),
-SE->getNegativeSCEV(Delta), CurLoop);
+  // Try symbolic division: Distance = Delta / Coeff.
+  if (const SCEV *Distance = SE->getUDivExactExpr(Delta, Coeff)) {
+LLVM_DEBUG(dbgs() << "\tSymbolic distance = " << *Distance << 
"\n");
+Result.DV[Level].Distance = Distance;
+NewConstraint.setDistance(Distance, CurLoop);
+  } else {
+// Cannot compute exact division - check if we can add runtime
+// assumptions.
+if (isa(Coeff) && !SE->isKnownNonZero(Coeff)) {
+  // Add runtime assumption that coefficient is non-zero for division.
+  const SCEV *Zero = SE->getZero(Coeff->getType());
+  const SCEVPredicate *NonZeroPred =
+  SE->getComparePredicate(ICmpInst::ICMP_NE, Coeff, Zero);
+  if (UnderRuntimeAssumptions) {
+SmallVector NewPreds(
+Assumptions.getPredicates());
+NewPreds.push_back(NonZeroPred);
+const_cast(this)->Assumptions =
+SCEVUnionPredicate(NewPreds, *SE);

sushgokh wrote:

why are we adding constraint once again when we have already added below 
constraint?
```
const SCEVPredicate *BoundPred =
SE->getComparePredicate(ICmpInst::ICMP_SLE, AbsDelta, Product);
```

https://github.com/llvm/llvm-project/pull/157738
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[llvm-branch-commits] [llvm] [DA] Fix Strong SIV test for symbolic coefficients and deltas (#149977) (PR #157738)

2025-09-15 Thread Sushant Gokhale via llvm-branch-commits



@@ -1249,10 +1249,33 @@ bool DependenceInfo::strongSIVtest(const SCEV *Coeff, 
const SCEV *SrcConst,
 SE->isKnownNonNegative(Coeff) ? Coeff : SE->getNegativeSCEV(Coeff);
 const SCEV *Product = SE->getMulExpr(UpperBound, AbsCoeff);
 if (isKnownPredicate(CmpInst::ICMP_SGT, AbsDelta, Product)) {
-  // Distance greater than trip count - no dependence
-  ++StrongSIVindependence;
-  ++StrongSIVsuccesses;
-  return true;
+  // Check if this involves symbolic expressions where we might be too
+  // conservative.
+  if (isa(Delta) || isa(Coeff) ||
+  !isa(AbsDelta) || !isa(Product)) {
+// For symbolic expressions, add runtime assumption rather than
+// rejecting.
+const SCEVPredicate *BoundPred =
+SE->getComparePredicate(ICmpInst::ICMP_SLE, AbsDelta, Product);

sushgokh wrote:

push this inside if(){...}

https://github.com/llvm/llvm-project/pull/157738
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[llvm-branch-commits] [llvm] [DA] Fix Strong SIV test for symbolic coefficients and deltas (#149977) (PR #157738)

2025-09-15 Thread Sushant Gokhale via llvm-branch-commits



@@ -1249,10 +1249,33 @@ bool DependenceInfo::strongSIVtest(const SCEV *Coeff, 
const SCEV *SrcConst,
 SE->isKnownNonNegative(Coeff) ? Coeff : SE->getNegativeSCEV(Coeff);
 const SCEV *Product = SE->getMulExpr(UpperBound, AbsCoeff);
 if (isKnownPredicate(CmpInst::ICMP_SGT, AbsDelta, Product)) {
-  // Distance greater than trip count - no dependence
-  ++StrongSIVindependence;
-  ++StrongSIVsuccesses;
-  return true;
+  // Check if this involves symbolic expressions where we might be too
+  // conservative.
+  if (isa(Delta) || isa(Coeff) ||
+  !isa(AbsDelta) || !isa(Product)) {

sushgokh wrote:

```
if( isa(Delta) || !isa(Product) )
```
should be sufficient ?

https://github.com/llvm/llvm-project/pull/157738
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[llvm-branch-commits] [llvm] Mips: Switch to RegClassByHwMode (PR #158273)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158273

>From cf6589f28a76cfb0237d654556857b42b991d6ee Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Sat, 6 Sep 2025 21:14:45 +0900
Subject: [PATCH] Mips: Switch to RegClassByHwMode

---
 .../Target/Mips/AsmParser/MipsAsmParser.cpp   |  9 +--
 .../Mips/Disassembler/MipsDisassembler.cpp| 24 +++
 llvm/lib/Target/Mips/MicroMipsInstrInfo.td| 12 +++---
 llvm/lib/Target/Mips/Mips.td  | 15 
 llvm/lib/Target/Mips/MipsInstrInfo.td | 20 +++-
 llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 16 ++---
 llvm/lib/Target/Mips/MipsRegisterInfo.td  | 16 +
 7 files changed, 76 insertions(+), 36 deletions(-)

diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp 
b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 8a5cb517c94c5..ba70c9e6cb9e8 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3706,7 +3706,9 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc 
IDLoc, MCStreamer &Out,
   MCRegister TmpReg = DstReg;
 
   const MCInstrDesc &Desc = MII.get(OpCode);
-  int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
+  int16_t DstRegClass =
+  MII.getOpRegClassID(Desc.operands()[StartOp],
+  STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo));
   unsigned DstRegClassID =
   getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
@@ -3834,7 +3836,10 @@ void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc 
IDLoc, MCStreamer &Out,
   MCRegister TmpReg = DstReg;
 
   const MCInstrDesc &Desc = MII.get(OpCode);
-  int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
+  int16_t DstRegClass =
+  MII.getOpRegClassID(Desc.operands()[StartOp],
+  STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo));
+
   unsigned DstRegClassID =
   getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp 
b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index fa6cc0e3f0187..d569eda328ef0 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -916,6 +916,30 @@ DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned 
RegNo, uint64_t Address,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
  uint64_t Address,
  const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td 
b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index b3fd8f422f429..b44bf1391b73e 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -57,12 +57,6 @@ def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
   let PredicateMethod = "isMemWithGRPMM16Base";
 }
 
-// Define the classes of pointers used by microMIPS.
-// The numbers must match those in MipsRegisterInfo::MipsPtrClass.
-def ptr_gpr16mm_rc : PointerLikeRegClass<1>;
-def ptr_sp_rc : PointerLikeRegClass<2>;
-def ptr_gp_rc : PointerLikeRegClass<3>;
-
 class mem_mm_4_generic : Operand {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops ptr_gpr16mm_rc, simm4);
@@ -114,7 +108,7 @@ def mem_mm_gp_simm7_lsl2 : Operand {
 
 def mem_mm_9 : Operand {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm9);
+  let MIOperandInfo = (ops mips_ptr_rc, simm9);
   let EncoderMethod = "getMemEncodingMMImm9";
   let ParserMatchClass = MipsMemSimmAsmOperand<9>;
   let OperandType = "OPERAND_MEMORY";
@@ -130,7 +124,7 @@ def mem_mm_11

[llvm-branch-commits] [llvm] X86: Switch to RegClassByHwMode (PR #158274)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158274

>From 1a85c9cf7cdf944be302c00efd231eba5d46bdc6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Tue, 9 Sep 2025 11:15:47 +0900
Subject: [PATCH] X86: Switch to RegClassByHwMode

Replace the target uses of PointerLikeRegClass with RegClassByHwMode
---
 .../X86/MCTargetDesc/X86MCTargetDesc.cpp  |  3 ++
 llvm/lib/Target/X86/X86.td|  2 ++
 llvm/lib/Target/X86/X86InstrInfo.td   |  8 ++---
 llvm/lib/Target/X86/X86InstrOperands.td   | 30 +++-
 llvm/lib/Target/X86/X86InstrPredicates.td | 14 
 llvm/lib/Target/X86/X86RegisterInfo.cpp   | 35 +--
 llvm/lib/Target/X86/X86Subtarget.h|  4 +--
 llvm/utils/TableGen/X86FoldTablesEmitter.cpp  |  4 +--
 8 files changed, 57 insertions(+), 43 deletions(-)

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 
b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index bb1e716c33ed5..1d5ef8b0996dc 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -55,6 +55,9 @@ std::string X86_MC::ParseX86Triple(const Triple &TT) {
   else
 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
 
+  if (TT.isX32())
+FS += ",+x32";
+
   return FS;
 }
 
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 7c9e821c02fda..3af8b3e060a16 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -25,6 +25,8 @@ def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", 
"true",
"32-bit mode (80386)">;
 def Is16Bit : SubtargetFeature<"16bit-mode", "Is16Bit", "true",
"16-bit mode (i8086)">;
+def IsX32 : SubtargetFeature<"x32", "IsX32", "true",
+ "64-bit with ILP32 programming model (e.g. x32 
ABI)">;
 
 
//===--===//
 // X86 Subtarget ISA features
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td 
b/llvm/lib/Target/X86/X86InstrInfo.td
index 7f6c5614847e3..0c4abc2c400f6 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -18,14 +18,14 @@ include "X86InstrFragments.td"
 include "X86InstrFragmentsSIMD.td"
 
 
//===--===//
-// X86 Operand Definitions.
+// X86 Predicate Definitions.
 //
-include "X86InstrOperands.td"
+include "X86InstrPredicates.td"
 
 
//===--===//
-// X86 Predicate Definitions.
+// X86 Operand Definitions.
 //
-include "X86InstrPredicates.td"
+include "X86InstrOperands.td"
 
 
//===--===//
 // X86 Instruction Format Definitions.
diff --git a/llvm/lib/Target/X86/X86InstrOperands.td 
b/llvm/lib/Target/X86/X86InstrOperands.td
index 80843f6bb80e6..5207ecad127a2 100644
--- a/llvm/lib/Target/X86/X86InstrOperands.td
+++ b/llvm/lib/Target/X86/X86InstrOperands.td
@@ -6,9 +6,15 @@
 //
 
//===--===//
 
+def x86_ptr_rc : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32, GR64, LOW32_ADDR_ACCESS]>;
+
 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
 // the index operand of an address, to conform to x86 encoding restrictions.
-def ptr_rc_nosp : PointerLikeRegClass<1>;
+def ptr_rc_nosp : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32_NOSP, GR64_NOSP, GR32_NOSP]>;
 
 // *mem - Operand definitions for the funky X86 addressing mode operands.
 //
@@ -53,7 +59,7 @@ class X86MemOperand : Operand {
   let PrintMethod = printMethod;
-  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
+  let MIOperandInfo = (ops x86_ptr_rc, i8imm, ptr_rc_nosp, i32imm, 
SEGMENT_REG);
   let ParserMatchClass = parserMatchClass;
   let OperandType = "OPERAND_MEMORY";
   int Size = size;
@@ -63,7 +69,7 @@ class X86MemOperand
 : X86MemOperand {
-  let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG);
+  let MIOperandInfo = (ops x86_ptr_rc, i8imm, RC, i32imm, SEGMENT_REG);
 }
 
 def anymem : X86MemOperand<"printMemReference">;
@@ -113,8 +119,14 @@ def sdmem : X86MemOperand<"printqwordmem", 
X86Mem64AsmOperand>;
 
 // A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead
 // of a plain GPR, so that it doesn't potentially require a REX prefix.
-def ptr_rc_norex : PointerLikeRegClass<2>;
-def ptr_rc_norex_nosp : PointerLikeRegClass<3>;
+def ptr_rc_norex : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32_NOREX, GR64_NOREX, GR32_NOREX]>;
+
+def ptr_rc_norex_nosp : RegClassByHwMode<
+  [X86_32, X86_64, X86_64_X32],
+  [GR32_NOREX_NOSP, GR64_NOREX_NOSP, GR32_NOREX_NOSP]>;
+
 
 def i8mem_NOREX : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8> {
   let MIOpe

[llvm-branch-commits] [llvm] Mips: Switch to RegClassByHwMode (PR #158273)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158273

>From cf6589f28a76cfb0237d654556857b42b991d6ee Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Sat, 6 Sep 2025 21:14:45 +0900
Subject: [PATCH] Mips: Switch to RegClassByHwMode

---
 .../Target/Mips/AsmParser/MipsAsmParser.cpp   |  9 +--
 .../Mips/Disassembler/MipsDisassembler.cpp| 24 +++
 llvm/lib/Target/Mips/MicroMipsInstrInfo.td| 12 +++---
 llvm/lib/Target/Mips/Mips.td  | 15 
 llvm/lib/Target/Mips/MipsInstrInfo.td | 20 +++-
 llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 16 ++---
 llvm/lib/Target/Mips/MipsRegisterInfo.td  | 16 +
 7 files changed, 76 insertions(+), 36 deletions(-)

diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp 
b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 8a5cb517c94c5..ba70c9e6cb9e8 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3706,7 +3706,9 @@ void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc 
IDLoc, MCStreamer &Out,
   MCRegister TmpReg = DstReg;
 
   const MCInstrDesc &Desc = MII.get(OpCode);
-  int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
+  int16_t DstRegClass =
+  MII.getOpRegClassID(Desc.operands()[StartOp],
+  STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo));
   unsigned DstRegClassID =
   getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
@@ -3834,7 +3836,10 @@ void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc 
IDLoc, MCStreamer &Out,
   MCRegister TmpReg = DstReg;
 
   const MCInstrDesc &Desc = MII.get(OpCode);
-  int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
+  int16_t DstRegClass =
+  MII.getOpRegClassID(Desc.operands()[StartOp],
+  STI->getHwMode(MCSubtargetInfo::HwMode_RegInfo));
+
   unsigned DstRegClassID =
   getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
   bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp 
b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index fa6cc0e3f0187..d569eda328ef0 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -916,6 +916,30 @@ DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned 
RegNo, uint64_t Address,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeGP64RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeSP32RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
+static DecodeStatus DecodeSP64RegisterClass(MCInst &Inst, unsigned RegNo,
+uint64_t Address,
+const MCDisassembler *Decoder) {
+  llvm_unreachable("this is unused");
+}
+
 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
  uint64_t Address,
  const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td 
b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index b3fd8f422f429..b44bf1391b73e 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -57,12 +57,6 @@ def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
   let PredicateMethod = "isMemWithGRPMM16Base";
 }
 
-// Define the classes of pointers used by microMIPS.
-// The numbers must match those in MipsRegisterInfo::MipsPtrClass.
-def ptr_gpr16mm_rc : PointerLikeRegClass<1>;
-def ptr_sp_rc : PointerLikeRegClass<2>;
-def ptr_gp_rc : PointerLikeRegClass<3>;
-
 class mem_mm_4_generic : Operand {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops ptr_gpr16mm_rc, simm4);
@@ -114,7 +108,7 @@ def mem_mm_gp_simm7_lsl2 : Operand {
 
 def mem_mm_9 : Operand {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops ptr_rc, simm9);
+  let MIOperandInfo = (ops mips_ptr_rc, simm9);
   let EncoderMethod = "getMemEncodingMMImm9";
   let ParserMatchClass = MipsMemSimmAsmOperand<9>;
   let OperandType = "OPERAND_MEMORY";
@@ -130,7 +124,7 @@ def mem_mm_11

[llvm-branch-commits] [llvm] AMDGPU: Stop using aligned VGPR classes for addRegisterClass (PR #158278)

2025-09-15 Thread Matt Arsenault via llvm-branch-commits


https://github.com/arsenm updated 
https://github.com/llvm/llvm-project/pull/158278

>From b70040bb06ddec1f28c0e7e5eb842fa0072d3daf Mon Sep 17 00:00:00 2001
From: Matt Arsenault 
Date: Fri, 12 Sep 2025 20:45:56 +0900
Subject: [PATCH] AMDGPU: Stop using aligned VGPR classes for addRegisterClass

This is unnecessary. At use emission time, InstrEmitter will
use the common subclass of the value type's register class and
the use instruction register classes. This removes one of the
obstacles to treating special case instructions that do not have
the alignment requirement overly conservatively.
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 32 +++
 llvm/test/CodeGen/AMDGPU/mfma-loop.ll | 14 +-
 2 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp 
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 9acc4b6de3501..8974198a82f01 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -110,52 +110,52 @@ SITargetLowering::SITargetLowering(const TargetMachine 
&TM,
   addRegisterClass(MVT::Untyped, V64RegClass);
 
   addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
-  addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96));
+  addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
 
   addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
   addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
 
   addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
-  addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128));
+  addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
 
   addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
-  addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160));
+  addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
 
   addRegisterClass(MVT::v6i32, &AMDGPU::SGPR_192RegClass);
-  addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192));
+  addRegisterClass(MVT::v6f32, &AMDGPU::VReg_192RegClass);
 
   addRegisterClass(MVT::v3i64, &AMDGPU::SGPR_192RegClass);
-  addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192));
+  addRegisterClass(MVT::v3f64, &AMDGPU::VReg_192RegClass);
 
   addRegisterClass(MVT::v7i32, &AMDGPU::SGPR_224RegClass);
-  addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224));
+  addRegisterClass(MVT::v7f32, &AMDGPU::VReg_224RegClass);
 
   addRegisterClass(MVT::v8i32, &AMDGPU::SGPR_256RegClass);
-  addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256));
+  addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
 
   addRegisterClass(MVT::v4i64, &AMDGPU::SGPR_256RegClass);
-  addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256));
+  addRegisterClass(MVT::v4f64, &AMDGPU::VReg_256RegClass);
 
   addRegisterClass(MVT::v9i32, &AMDGPU::SGPR_288RegClass);
-  addRegisterClass(MVT::v9f32, TRI->getVGPRClassForBitWidth(288));
+  addRegisterClass(MVT::v9f32, &AMDGPU::VReg_288RegClass);
 
   addRegisterClass(MVT::v10i32, &AMDGPU::SGPR_320RegClass);
-  addRegisterClass(MVT::v10f32, TRI->getVGPRClassForBitWidth(320));
+  addRegisterClass(MVT::v10f32, &AMDGPU::VReg_320RegClass);
 
   addRegisterClass(MVT::v11i32, &AMDGPU::SGPR_352RegClass);
-  addRegisterClass(MVT::v11f32, TRI->getVGPRClassForBitWidth(352));
+  addRegisterClass(MVT::v11f32, &AMDGPU::VReg_352RegClass);
 
   addRegisterClass(MVT::v12i32, &AMDGPU::SGPR_384RegClass);
-  addRegisterClass(MVT::v12f32, TRI->getVGPRClassForBitWidth(384));
+  addRegisterClass(MVT::v12f32, &AMDGPU::VReg_384RegClass);
 
   addRegisterClass(MVT::v16i32, &AMDGPU::SGPR_512RegClass);
-  addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512));
+  addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
 
   addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);
-  addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512));
+  addRegisterClass(MVT::v8f64, &AMDGPU::VReg_512RegClass);
 
   addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);
-  addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024));
+  addRegisterClass(MVT::v16f64, &AMDGPU::VReg_1024RegClass);
 
   if (Subtarget->has16BitInsts()) {
 if (Subtarget->useRealTrue16Insts()) {
@@ -187,7 +187,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
   }
 
   addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
-  addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024));
+  addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
 
   computeRegisterProperties(Subtarget->getRegisterInfo());
 
diff --git a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll 
b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
index d39daaade677f..3657a6b1b7415 100644
--- a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
@@ -2430,8 +2430,9 @@ define amdgpu_kernel void 
@test_mfma_nested_loop_zeroinit(ptr addrspace(1) %arg)
 ; GFX90A-NEXT:v_accvgpr_mov_b32 a29, a0
 ; GFX90A-NEXT:v_accvgpr_mov_b32 a30, a0
 ; GFX90A-NEXT

[llvm-branch-commits] [Remarks] BitstreamRemarkParser: Refactor error handling (PR #156511)

2025-09-15 Thread Tobias Stadler via llvm-branch-commits


https://github.com/tobias-stadler edited 
https://github.com/llvm/llvm-project/pull/156511
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[llvm-branch-commits] [clang] 31a757f - Revert "[HIP][Clang] Remove __AMDGCN_WAVEFRONT_SIZE macros (#157463)"

2025-09-15 Thread via llvm-branch-commits


Author: Fabian Ritter
Date: 2025-09-15T10:04:06+02:00
New Revision: 31a757f2a38c493da868bf97f557c2e30bf24cca

URL: 
https://github.com/llvm/llvm-project/commit/31a757f2a38c493da868bf97f557c2e30bf24cca
DIFF: 
https://github.com/llvm/llvm-project/commit/31a757f2a38c493da868bf97f557c2e30bf24cca.diff

LOG: Revert "[HIP][Clang] Remove __AMDGCN_WAVEFRONT_SIZE macros (#157463)"

This reverts commit 02d3e6ac75e776041fb1782efc4dfccfe6b46218.

Added: 
clang/test/Driver/hip-wavefront-size-deprecation-diagnostics.hip

Modified: 
clang/docs/AMDGPUSupport.rst
clang/docs/HIPSupport.rst
clang/lib/Basic/Targets/AMDGPU.cpp
clang/test/CodeGenHIP/maybe_undef-attr-verify.hip
clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
clang/test/CodeGenOpenCL/builtins-amdgcn-wave64.cl
clang/test/Driver/amdgpu-macros.cl
clang/test/Driver/hip-macros.hip
clang/test/Preprocessor/predefined-arch-macros.c

Removed: 




diff  --git a/clang/docs/AMDGPUSupport.rst b/clang/docs/AMDGPUSupport.rst
index 18e3de8abe92a..3eada5f900613 100644
--- a/clang/docs/AMDGPUSupport.rst
+++ b/clang/docs/AMDGPUSupport.rst
@@ -49,6 +49,10 @@ Predefined Macros
  - Defined as 1 if the CU mode is enabled and 0 if the WGP mode is enabled.
* - ``__AMDGCN_UNSAFE_FP_ATOMICS__``
  - Defined if unsafe floating-point atomics are allowed.
+   * - ``__AMDGCN_WAVEFRONT_SIZE__``
+ - Defines the wavefront size. Allowed values are 32 and 64 (deprecated).
+   * - ``__AMDGCN_WAVEFRONT_SIZE``
+ - Alias to ``__AMDGCN_WAVEFRONT_SIZE__`` (deprecated).
* - ``__HAS_FMAF__``
  - Defined if FMAF instruction is available (deprecated).
* - ``__HAS_LDEXPF__``

diff  --git a/clang/docs/HIPSupport.rst b/clang/docs/HIPSupport.rst
index 0d04b842af025..b4a671e3cfa3c 100644
--- a/clang/docs/HIPSupport.rst
+++ b/clang/docs/HIPSupport.rst
@@ -178,7 +178,8 @@ Predefined Macros
  - Alias to ``__HIP_API_PER_THREAD_DEFAULT_STREAM__``. Deprecated.
 
 Note that some architecture specific AMDGPU macros will have default values 
when
-used from the HIP host compilation.
+used from the HIP host compilation. Other :doc:`AMDGPU macros `
+like ``__AMDGCN_WAVEFRONT_SIZE__`` (deprecated) will default to 64 for example.
 
 Compilation Modes
 =

diff  --git a/clang/lib/Basic/Targets/AMDGPU.cpp 
b/clang/lib/Basic/Targets/AMDGPU.cpp
index 443dfbc93a182..87de9e6865e71 100644
--- a/clang/lib/Basic/Targets/AMDGPU.cpp
+++ b/clang/lib/Basic/Targets/AMDGPU.cpp
@@ -356,6 +356,12 @@ void AMDGPUTargetInfo::getTargetDefines(const LangOptions 
&Opts,
   if (hasFastFMA())
 Builder.defineMacro("FP_FAST_FMA");
 
+  Builder.defineMacro("__AMDGCN_WAVEFRONT_SIZE__", Twine(WavefrontSize),
+  "compile-time-constant access to the wavefront size will 
"
+  "be removed in a future release");
+  Builder.defineMacro("__AMDGCN_WAVEFRONT_SIZE", Twine(WavefrontSize),
+  "compile-time-constant access to the wavefront size will 
"
+  "be removed in a future release");
   Builder.defineMacro("__AMDGCN_CUMODE__", Twine(CUMode));
 }
 

diff  --git a/clang/test/CodeGenHIP/maybe_undef-attr-verify.hip 
b/clang/test/CodeGenHIP/maybe_undef-attr-verify.hip
index 6dc57c4fcc5fc..571fba148f5cc 100644
--- a/clang/test/CodeGenHIP/maybe_undef-attr-verify.hip
+++ b/clang/test/CodeGenHIP/maybe_undef-attr-verify.hip
@@ -20,7 +20,7 @@
 #define __maybe_undef __attribute__((maybe_undef))
 #define WARP_SIZE 64
 
-static constexpr int warpSize = WARP_SIZE;
+static constexpr int warpSize = __AMDGCN_WAVEFRONT_SIZE__;
 
 __device__ static inline unsigned int __lane_id() {
 return  __builtin_amdgcn_mbcnt_hi(

diff  --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
index 31fd0e7bceaf5..d390418523694 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
@@ -1,5 +1,5 @@
 // REQUIRES: amdgpu-registered-target
-// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown 
-target-feature +wavefrontsize32 -emit-llvm -o - %s | FileCheck 
-enable-var-scope %s
+// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown 
-D__AMDGCN_WAVEFRONT_SIZE=32 -target-feature +wavefrontsize32 -emit-llvm -o - 
%s | FileCheck -enable-var-scope %s
 // RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -target-cpu 
gfx1010 -emit-llvm -o - %s | FileCheck -enable-var-scope %s
 // RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -target-cpu 
gfx1010 -target-feature +wavefrontsize32 -emit-llvm -o - %s | FileCheck 
-enable-var-scope %s
 // RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -target-cpu 
gfx1100 -target-feature +wavefrontsize32 -emit-llvm -o - %s | FileCheck 
-enable-var-scope %s
@@ -48,3 +48,7 @@ void test_read_exec_lo(global uint* out) {
 void test_read_exec

[llvm-branch-commits] [clang] [PAC][Driver] Support ptrauth flags only on ARM64 Darwin or with pauthtest ABI (PR #113152)

2025-09-15 Thread Daniil Kovalev via llvm-branch-commits


https://github.com/kovdan01 updated 
https://github.com/llvm/llvm-project/pull/113152

>From f895c68afebcb60c2eaa50960ea0e3f1c1446698 Mon Sep 17 00:00:00 2001
From: Daniil Kovalev 
Date: Mon, 21 Oct 2024 12:18:56 +0300
Subject: [PATCH 1/8] [PAC][Driver] Support ptrauth flags only on ARM64 Darwin

Most ptrauth flags are ABI-affecting, so they should not be exposed to
end users. Under certain conditions, some ptrauth driver flags are intended
to be used for ARM64 Darwin, so allow them in this case.

Leave `-faarch64-jump-table-hardening` available for all AArch64 targets
since it's not ABI-affecting.
---
 clang/lib/Driver/ToolChains/Clang.cpp |  28 -
 clang/lib/Driver/ToolChains/Linux.cpp |  53 ++---
 clang/test/Driver/aarch64-ptrauth.c   | 164 --
 3 files changed, 135 insertions(+), 110 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index 48a457c9bc46a..762bfff615475 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -1662,34 +1662,6 @@ void Clang::AddAArch64TargetArgs(const ArgList &Args,
 
   AddUnalignedAccessWarning(CmdArgs);
 
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_intrinsics,
-options::OPT_fno_ptrauth_intrinsics);
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_calls,
-options::OPT_fno_ptrauth_calls);
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_returns,
-options::OPT_fno_ptrauth_returns);
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_auth_traps,
-options::OPT_fno_ptrauth_auth_traps);
-  Args.addOptInFlag(
-  CmdArgs, options::OPT_fptrauth_vtable_pointer_address_discrimination,
-  options::OPT_fno_ptrauth_vtable_pointer_address_discrimination);
-  Args.addOptInFlag(
-  CmdArgs, options::OPT_fptrauth_vtable_pointer_type_discrimination,
-  options::OPT_fno_ptrauth_vtable_pointer_type_discrimination);
-  Args.addOptInFlag(
-  CmdArgs, options::OPT_fptrauth_type_info_vtable_pointer_discrimination,
-  options::OPT_fno_ptrauth_type_info_vtable_pointer_discrimination);
-  Args.addOptInFlag(
-  CmdArgs, options::OPT_fptrauth_function_pointer_type_discrimination,
-  options::OPT_fno_ptrauth_function_pointer_type_discrimination);
-
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_indirect_gotos,
-options::OPT_fno_ptrauth_indirect_gotos);
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_init_fini,
-options::OPT_fno_ptrauth_init_fini);
-  Args.addOptInFlag(CmdArgs,
-options::OPT_fptrauth_init_fini_address_discrimination,
-options::OPT_fno_ptrauth_init_fini_address_discrimination);
   Args.addOptInFlag(CmdArgs, options::OPT_faarch64_jump_table_hardening,
 options::OPT_fno_aarch64_jump_table_hardening);
 
diff --git a/clang/lib/Driver/ToolChains/Linux.cpp 
b/clang/lib/Driver/ToolChains/Linux.cpp
index 04a8ad1d165d4..1e93b3aafbf47 100644
--- a/clang/lib/Driver/ToolChains/Linux.cpp
+++ b/clang/lib/Driver/ToolChains/Linux.cpp
@@ -484,49 +484,16 @@ std::string Linux::ComputeEffectiveClangTriple(const 
llvm::opt::ArgList &Args,
 // options represent the default signing schema.
 static void handlePAuthABI(const Driver &D, const ArgList &DriverArgs,
ArgStringList &CC1Args) {
-  if (!DriverArgs.hasArg(options::OPT_fptrauth_intrinsics,
- options::OPT_fno_ptrauth_intrinsics))
-CC1Args.push_back("-fptrauth-intrinsics");
-
-  if (!DriverArgs.hasArg(options::OPT_fptrauth_calls,
- options::OPT_fno_ptrauth_calls))
-CC1Args.push_back("-fptrauth-calls");
-
-  if (!DriverArgs.hasArg(options::OPT_fptrauth_returns,
- options::OPT_fno_ptrauth_returns))
-CC1Args.push_back("-fptrauth-returns");
-
-  if (!DriverArgs.hasArg(options::OPT_fptrauth_auth_traps,
- options::OPT_fno_ptrauth_auth_traps))
-CC1Args.push_back("-fptrauth-auth-traps");
-
-  if (!DriverArgs.hasArg(
-  options::OPT_fptrauth_vtable_pointer_address_discrimination,
-  options::OPT_fno_ptrauth_vtable_pointer_address_discrimination))
-CC1Args.push_back("-fptrauth-vtable-pointer-address-discrimination");
-
-  if (!DriverArgs.hasArg(
-  options::OPT_fptrauth_vtable_pointer_type_discrimination,
-  options::OPT_fno_ptrauth_vtable_pointer_type_discrimination))
-CC1Args.push_back("-fptrauth-vtable-pointer-type-discrimination");
-
-  if (!DriverArgs.hasArg(
-  options::OPT_fptrauth_type_info_vtable_pointer_discrimination,
-  options::OPT_fno_ptrauth_type_info_vtable_pointer_discrimination))
-CC1Args.push_back("-fptrauth-type-info-vtable-pointer-discrimination");
-
-  if (!DriverArgs.hasArg(options::OPT_fptrauth_indirect_gotos,
- options::OPT_fno_ptrauth_indirect_gotos))
-CC1Args.

[llvm-branch-commits] [clang] [PAC][Driver] Support ptrauth flags only on ARM64 Darwin or with pauthtest ABI (PR #113152)

2025-09-15 Thread Daniil Kovalev via llvm-branch-commits


https://github.com/kovdan01 updated 
https://github.com/llvm/llvm-project/pull/113152

>From f895c68afebcb60c2eaa50960ea0e3f1c1446698 Mon Sep 17 00:00:00 2001
From: Daniil Kovalev 
Date: Mon, 21 Oct 2024 12:18:56 +0300
Subject: [PATCH 1/8] [PAC][Driver] Support ptrauth flags only on ARM64 Darwin

Most ptrauth flags are ABI-affecting, so they should not be exposed to
end users. Under certain conditions, some ptrauth driver flags are intended
to be used for ARM64 Darwin, so allow them in this case.

Leave `-faarch64-jump-table-hardening` available for all AArch64 targets
since it's not ABI-affecting.
---
 clang/lib/Driver/ToolChains/Clang.cpp |  28 -
 clang/lib/Driver/ToolChains/Linux.cpp |  53 ++---
 clang/test/Driver/aarch64-ptrauth.c   | 164 --
 3 files changed, 135 insertions(+), 110 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index 48a457c9bc46a..762bfff615475 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -1662,34 +1662,6 @@ void Clang::AddAArch64TargetArgs(const ArgList &Args,
 
   AddUnalignedAccessWarning(CmdArgs);
 
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_intrinsics,
-options::OPT_fno_ptrauth_intrinsics);
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_calls,
-options::OPT_fno_ptrauth_calls);
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_returns,
-options::OPT_fno_ptrauth_returns);
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_auth_traps,
-options::OPT_fno_ptrauth_auth_traps);
-  Args.addOptInFlag(
-  CmdArgs, options::OPT_fptrauth_vtable_pointer_address_discrimination,
-  options::OPT_fno_ptrauth_vtable_pointer_address_discrimination);
-  Args.addOptInFlag(
-  CmdArgs, options::OPT_fptrauth_vtable_pointer_type_discrimination,
-  options::OPT_fno_ptrauth_vtable_pointer_type_discrimination);
-  Args.addOptInFlag(
-  CmdArgs, options::OPT_fptrauth_type_info_vtable_pointer_discrimination,
-  options::OPT_fno_ptrauth_type_info_vtable_pointer_discrimination);
-  Args.addOptInFlag(
-  CmdArgs, options::OPT_fptrauth_function_pointer_type_discrimination,
-  options::OPT_fno_ptrauth_function_pointer_type_discrimination);
-
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_indirect_gotos,
-options::OPT_fno_ptrauth_indirect_gotos);
-  Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_init_fini,
-options::OPT_fno_ptrauth_init_fini);
-  Args.addOptInFlag(CmdArgs,
-options::OPT_fptrauth_init_fini_address_discrimination,
-options::OPT_fno_ptrauth_init_fini_address_discrimination);
   Args.addOptInFlag(CmdArgs, options::OPT_faarch64_jump_table_hardening,
 options::OPT_fno_aarch64_jump_table_hardening);
 
diff --git a/clang/lib/Driver/ToolChains/Linux.cpp 
b/clang/lib/Driver/ToolChains/Linux.cpp
index 04a8ad1d165d4..1e93b3aafbf47 100644
--- a/clang/lib/Driver/ToolChains/Linux.cpp
+++ b/clang/lib/Driver/ToolChains/Linux.cpp
@@ -484,49 +484,16 @@ std::string Linux::ComputeEffectiveClangTriple(const 
llvm::opt::ArgList &Args,
 // options represent the default signing schema.
 static void handlePAuthABI(const Driver &D, const ArgList &DriverArgs,
ArgStringList &CC1Args) {
-  if (!DriverArgs.hasArg(options::OPT_fptrauth_intrinsics,
- options::OPT_fno_ptrauth_intrinsics))
-CC1Args.push_back("-fptrauth-intrinsics");
-
-  if (!DriverArgs.hasArg(options::OPT_fptrauth_calls,
- options::OPT_fno_ptrauth_calls))
-CC1Args.push_back("-fptrauth-calls");
-
-  if (!DriverArgs.hasArg(options::OPT_fptrauth_returns,
- options::OPT_fno_ptrauth_returns))
-CC1Args.push_back("-fptrauth-returns");
-
-  if (!DriverArgs.hasArg(options::OPT_fptrauth_auth_traps,
- options::OPT_fno_ptrauth_auth_traps))
-CC1Args.push_back("-fptrauth-auth-traps");
-
-  if (!DriverArgs.hasArg(
-  options::OPT_fptrauth_vtable_pointer_address_discrimination,
-  options::OPT_fno_ptrauth_vtable_pointer_address_discrimination))
-CC1Args.push_back("-fptrauth-vtable-pointer-address-discrimination");
-
-  if (!DriverArgs.hasArg(
-  options::OPT_fptrauth_vtable_pointer_type_discrimination,
-  options::OPT_fno_ptrauth_vtable_pointer_type_discrimination))
-CC1Args.push_back("-fptrauth-vtable-pointer-type-discrimination");
-
-  if (!DriverArgs.hasArg(
-  options::OPT_fptrauth_type_info_vtable_pointer_discrimination,
-  options::OPT_fno_ptrauth_type_info_vtable_pointer_discrimination))
-CC1Args.push_back("-fptrauth-type-info-vtable-pointer-discrimination");
-
-  if (!DriverArgs.hasArg(options::OPT_fptrauth_indirect_gotos,
- options::OPT_fno_ptrauth_indirect_gotos))
-CC1Args.

[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits



@@ -1,5 +1,6 @@
 # RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
 # RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DCMAKE_CXX_COMPILER_LAUNCHER=%cmake_cxx_compiler_launcher 
-DCMAKE_C_COMPILER_LAUNCHER=%cmake_c_compiler_launcher \

makslevental wrote:

sure

https://github.com/llvm/llvm-project/pull/157944
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[llvm-branch-commits] [mlir] [MLIR][Standalone] test Standalone against install distributions (PR #157944)

2025-09-15 Thread Maksim Levental via llvm-branch-commits


https://github.com/makslevental updated 
https://github.com/llvm/llvm-project/pull/157944

>From f9dbe48eaa691ca9f8161e9dc3a800bb613d5bc9 Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 12:57:54 -0700
Subject: [PATCH 01/14] [MLIR][Standalone] test Standalone against install
 distributions

---
 mlir/test/Examples/standalone/lit.local.cfg  |  2 ++
 .../Examples/standalone/test.toy.install-dir | 16 
 mlir/test/lit.cfg.py |  3 +++
 mlir/test/lit.site.cfg.py.in |  1 +
 4 files changed, 22 insertions(+)
 create mode 100644 mlir/test/Examples/standalone/test.toy.install-dir

diff --git a/mlir/test/Examples/standalone/lit.local.cfg 
b/mlir/test/Examples/standalone/lit.local.cfg
index fe8397c6b9a10..bc9928decf527 100644
--- a/mlir/test/Examples/standalone/lit.local.cfg
+++ b/mlir/test/Examples/standalone/lit.local.cfg
@@ -10,3 +10,5 @@ config.substitutions.append(("%host_cc", config.host_cc))
 config.substitutions.append(("%enable_libcxx", config.enable_libcxx))
 config.substitutions.append(("%mlir_cmake_dir", config.mlir_cmake_dir))
 config.substitutions.append(("%llvm_use_linker", config.llvm_use_linker))
+config.substitutions.append(("%llvm_obj_root", config.llvm_obj_root))
+config.substitutions.append(("%host_cmake_install_prefix", 
config.host_cmake_install_prefix))
diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.toy.install-dir
new file mode 100644
index 0..5c33a70491ae1
--- /dev/null
+++ b/mlir/test/Examples/standalone/test.toy.install-dir
@@ -0,0 +1,16 @@
+# REQUIRES: github-actions
+# RUN: "%cmake_exe" --build %llvm_obj_root --target install
+# RUN: "%cmake_exe" "%mlir_src_root/examples/standalone" -G "%cmake_generator" 
\
+# RUN: -DCMAKE_CXX_COMPILER=%host_cxx -DCMAKE_C_COMPILER=%host_cc \
+# RUN: -DLLVM_ENABLE_LIBCXX=%enable_libcxx 
-DMLIR_DIR=%host_cmake_install_prefix \
+# RUN: -DLLVM_USE_LINKER=%llvm_use_linker \
+# RUN: -DPython3_EXECUTABLE=%python \
+# RUN: -DPython_EXECUTABLE=%python
+# RUN: "%cmake_exe" --build . --target check-standalone | tee %t
+# RUN: FileCheck --input-file=%t %s
+
+# Note: The number of checked tests is not important. The command will fail
+# if any fail.
+# CHECK: Passed
+# CHECK-NOT: Failed
+# UNSUPPORTED: target={{.*(windows|android).*}}
diff --git a/mlir/test/lit.cfg.py b/mlir/test/lit.cfg.py
index f99c24d6e299a..08c7947c1e9a6 100644
--- a/mlir/test/lit.cfg.py
+++ b/mlir/test/lit.cfg.py
@@ -383,3 +383,6 @@ def have_host_jit_feature_support(feature_name):
 
 if sys.version_info >= (3, 11):
 config.available_features.add("python-ge-311")
+
+if "GITHUB_ACTIONS" in os.environ:
+config.available_features.add("github-actions")
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 8a742a227847b..7e22ebf23c773 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -18,6 +18,7 @@ config.host_cxx = "@HOST_CXX@"
 config.enable_libcxx = "@LLVM_ENABLE_LIBCXX@"
 config.host_cmake = "@CMAKE_COMMAND@"
 config.host_cmake_generator = "@CMAKE_GENERATOR@"
+config.host_cmake_install_prefix = "@CMAKE_INSTALL_PREFIX@"
 config.llvm_use_linker = "@LLVM_USE_LINKER@"
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.host_arch = "@HOST_ARCH@"

>From fc56d49c9481aed16b79f391368f4c3824a90695 Mon Sep 17 00:00:00 2001
From: Maksim Levental 
Date: Wed, 10 Sep 2025 13:23:07 -0700
Subject: [PATCH 02/14] Update lit.site.cfg.py.in

---
 .../standalone/{test.toy.install-dir => test.install-dir.toy}| 0
 mlir/test/lit.site.cfg.py.in | 1 +
 2 files changed, 1 insertion(+)
 rename mlir/test/Examples/standalone/{test.toy.install-dir => 
test.install-dir.toy} (100%)

diff --git a/mlir/test/Examples/standalone/test.toy.install-dir 
b/mlir/test/Examples/standalone/test.install-dir.toy
similarity index 100%
rename from mlir/test/Examples/standalone/test.toy.install-dir
rename to mlir/test/Examples/standalone/test.install-dir.toy
diff --git a/mlir/test/lit.site.cfg.py.in b/mlir/test/lit.site.cfg.py.in
index 7e22ebf23c773..eadfd047d15f7 100644
--- a/mlir/test/lit.site.cfg.py.in
+++ b/mlir/test/lit.site.cfg.py.in
@@ -3,6 +3,7 @@
 import sys
 
 config.target_triple = "@LLVM_TARGET_TRIPLE@"
+config.llvm_obj_root = "@LLVM_BINARY_DIR@"
 config.llvm_src_root = "@LLVM_SOURCE_DIR@"
 config.llvm_tools_dir = lit_config.substitute("@LLVM_TOOLS_DIR@")
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"

>From 67ce5b688657d38b6792b05712d1de6f56e726fe Mon Sep 17 00:00:00 2001
From: makslevental 
Date: Wed, 10 Sep 2025 15:54:54 -0700
Subject: [PATCH 03/14] add test.install-distribution-dir.toy

---
 mlir/test/Examples/standalone/lit.local.cfg |  1 +
 .../Examples/standalone/test.install-dir.toy|  4 ++--
 .../test.install-distribution-dir.toy   | 17 +
 3 files changed, 20 insertions(+), 2 deletions(-)
 create mode 100644 
mlir/test/Examples/stand

[llvm-branch-commits] [llvm] [AMDGPU] Dynamically set load latency in the scheduler (PR #128930)

2025-09-15 Thread Austin Kerbow via llvm-branch-commits


https://github.com/kerbowa updated 
https://github.com/llvm/llvm-project/pull/128930

>From d57286a6889d75d7dbc2cfebb55b45ee4268f018 Mon Sep 17 00:00:00 2001
From: Austin Kerbow 
Date: Tue, 25 Feb 2025 21:46:05 -0800
Subject: [PATCH] [AMDGPU] Dynamically set load latency in the scheduler

---
 llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp |  34 +
 llvm/lib/Target/AMDGPU/GCNSchedStrategy.h   |   7 +
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp  |  59 +-
 llvm/lib/Target/AMDGPU/SIInstrInfo.h|  39 +
 llvm/test/CodeGen/AMDGPU/res| 793 
 5 files changed, 931 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/res

diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp 
b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 254b75b784e75..ae553da22e509 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -1150,6 +1150,40 @@ void UnclusteredHighRPStage::finalizeGCNSchedStage() {
   GCNSchedStage::finalizeGCNSchedStage();
 }
 
+bool ILPInitialScheduleStage::initGCNSchedStage() {
+  if (!GCNSchedStage::initGCNSchedStage())
+return false;
+
+  const SIInstrInfo *TII = ST.getInstrInfo();
+  OriginalLoadLatencyScaleFactor = TII->getLoadLatencyScaleFactor();
+  OriginalDSReadLatencyScaleFactor = TII->getDSReadLatencyScaleFactor();
+  OriginalVMEMLoadLatencyScaleFactor = TII->getVMEMLoadLatencyScaleFactor();
+  const unsigned ILPLoadLatencyScaleFactorDefault = 300;
+  if (ILPLoadLatencyScaleFactorDefault > TII->getLoadLatencyScaleFactor())
+TII->setLoadLatencyScaleFactor(ILPLoadLatencyScaleFactorDefault);
+  if (ILPLoadLatencyScaleFactorDefault > TII->getDSReadLatencyScaleFactor())
+TII->setDSReadLatencyScaleFactor(ILPLoadLatencyScaleFactorDefault);
+  if (ILPLoadLatencyScaleFactorDefault > TII->getVMEMLoadLatencyScaleFactor())
+TII->setVMEMLoadLatencyScaleFactor(ILPLoadLatencyScaleFactorDefault);
+
+  LLVM_DEBUG(dbgs() << "ILP Initial Schedule: Set load latency scale factor to 
"
+<< TII->getLoadLatencyScaleFactor() << '\n');
+  return true;
+}
+
+void ILPInitialScheduleStage::finalizeGCNSchedStage() {
+  const SIInstrInfo *TII = ST.getInstrInfo();
+  TII->setLoadLatencyScaleFactor(OriginalLoadLatencyScaleFactor);
+  TII->setDSReadLatencyScaleFactor(OriginalDSReadLatencyScaleFactor);
+  TII->setVMEMLoadLatencyScaleFactor(OriginalVMEMLoadLatencyScaleFactor);
+
+  LLVM_DEBUG(
+  dbgs() << "ILP Initial Schedule: Restored load latency scale factor to "
+ << OriginalLoadLatencyScaleFactor << "\n");
+
+  GCNSchedStage::finalizeGCNSchedStage();
+}
+
 bool GCNSchedStage::initGCNRegion() {
   // Check whether this new region is also a new block.
   if (DAG.RegionBegin->getParent() != CurrentMBB)
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h 
b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
index 790370ff8ab4d..5be6d4bde6cd0 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
@@ -515,8 +515,15 @@ class PreRARematStage : public GCNSchedStage {
 };
 
 class ILPInitialScheduleStage : public GCNSchedStage {
+private:
+  unsigned OriginalLoadLatencyScaleFactor = 0;
+  unsigned OriginalDSReadLatencyScaleFactor = 0;
+  unsigned OriginalVMEMLoadLatencyScaleFactor = 0;
+
 public:
   bool shouldRevertScheduling(unsigned WavesAfter) override;
+  bool initGCNSchedStage() override;
+  void finalizeGCNSchedStage() override;
 
   ILPInitialScheduleStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
   : GCNSchedStage(StageID, DAG) {}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp 
b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 5106478a95b43..a35aabd405a1d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -62,9 +62,29 @@ static cl::opt Fix16BitCopies(
   cl::init(true),
   cl::ReallyHidden);
 
+static cl::opt AMDGPULoadLatencyScaleFactor(
+"amdgpu-load-latency-scale-factor",
+cl::desc("Scale factor for load instruction latency. Final latency is "
+ "scalled by `Factor / 100 * Latency`."),
+cl::init(100), cl::ReallyHidden);
+
+static cl::opt AMDGPUDSReadLatencyScaleFactor(
+"amdgpu-ds-read-latency-scale-factor",
+cl::desc("Scale factor for LDS (DS) read instruction latency. Final "
+ "latency is scaled by `Factor / 100 * Latency`."),
+cl::init(100), cl::ReallyHidden);
+
+static cl::opt AMDGPUVMEMLoadLatencyScaleFactor(
+"amdgpu-vmem-load-latency-scale-factor",
+cl::desc("Scale factor for VMEM/BUFFER/FLAT load instruction latency. "
+ "Final latency is scaled by `Factor / 100 * Latency`."),
+cl::init(100), cl::ReallyHidden);
+
 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
 : AMDGPUGenInstrInfo(ST, AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
-  RI(ST), ST(ST) {
+  RI(ST), ST(ST), LoadLatencyScaleFactor(AMDGPULoadLatencyScaleFactor),
+  DSReadLatencyScaleFactor(AMD

[llvm-branch-commits] [llvm] [AMDGPU] Dynamically set load latency in the scheduler (PR #128930)

2025-09-15 Thread Austin Kerbow via llvm-branch-commits


https://github.com/kerbowa updated 
https://github.com/llvm/llvm-project/pull/128930

>From d57286a6889d75d7dbc2cfebb55b45ee4268f018 Mon Sep 17 00:00:00 2001
From: Austin Kerbow 
Date: Tue, 25 Feb 2025 21:46:05 -0800
Subject: [PATCH] [AMDGPU] Dynamically set load latency in the scheduler

---
 llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp |  34 +
 llvm/lib/Target/AMDGPU/GCNSchedStrategy.h   |   7 +
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp  |  59 +-
 llvm/lib/Target/AMDGPU/SIInstrInfo.h|  39 +
 llvm/test/CodeGen/AMDGPU/res| 793 
 5 files changed, 931 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/res

diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp 
b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 254b75b784e75..ae553da22e509 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -1150,6 +1150,40 @@ void UnclusteredHighRPStage::finalizeGCNSchedStage() {
   GCNSchedStage::finalizeGCNSchedStage();
 }
 
+bool ILPInitialScheduleStage::initGCNSchedStage() {
+  if (!GCNSchedStage::initGCNSchedStage())
+return false;
+
+  const SIInstrInfo *TII = ST.getInstrInfo();
+  OriginalLoadLatencyScaleFactor = TII->getLoadLatencyScaleFactor();
+  OriginalDSReadLatencyScaleFactor = TII->getDSReadLatencyScaleFactor();
+  OriginalVMEMLoadLatencyScaleFactor = TII->getVMEMLoadLatencyScaleFactor();
+  const unsigned ILPLoadLatencyScaleFactorDefault = 300;
+  if (ILPLoadLatencyScaleFactorDefault > TII->getLoadLatencyScaleFactor())
+TII->setLoadLatencyScaleFactor(ILPLoadLatencyScaleFactorDefault);
+  if (ILPLoadLatencyScaleFactorDefault > TII->getDSReadLatencyScaleFactor())
+TII->setDSReadLatencyScaleFactor(ILPLoadLatencyScaleFactorDefault);
+  if (ILPLoadLatencyScaleFactorDefault > TII->getVMEMLoadLatencyScaleFactor())
+TII->setVMEMLoadLatencyScaleFactor(ILPLoadLatencyScaleFactorDefault);
+
+  LLVM_DEBUG(dbgs() << "ILP Initial Schedule: Set load latency scale factor to 
"
+<< TII->getLoadLatencyScaleFactor() << '\n');
+  return true;
+}
+
+void ILPInitialScheduleStage::finalizeGCNSchedStage() {
+  const SIInstrInfo *TII = ST.getInstrInfo();
+  TII->setLoadLatencyScaleFactor(OriginalLoadLatencyScaleFactor);
+  TII->setDSReadLatencyScaleFactor(OriginalDSReadLatencyScaleFactor);
+  TII->setVMEMLoadLatencyScaleFactor(OriginalVMEMLoadLatencyScaleFactor);
+
+  LLVM_DEBUG(
+  dbgs() << "ILP Initial Schedule: Restored load latency scale factor to "
+ << OriginalLoadLatencyScaleFactor << "\n");
+
+  GCNSchedStage::finalizeGCNSchedStage();
+}
+
 bool GCNSchedStage::initGCNRegion() {
   // Check whether this new region is also a new block.
   if (DAG.RegionBegin->getParent() != CurrentMBB)
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h 
b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
index 790370ff8ab4d..5be6d4bde6cd0 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
@@ -515,8 +515,15 @@ class PreRARematStage : public GCNSchedStage {
 };
 
 class ILPInitialScheduleStage : public GCNSchedStage {
+private:
+  unsigned OriginalLoadLatencyScaleFactor = 0;
+  unsigned OriginalDSReadLatencyScaleFactor = 0;
+  unsigned OriginalVMEMLoadLatencyScaleFactor = 0;
+
 public:
   bool shouldRevertScheduling(unsigned WavesAfter) override;
+  bool initGCNSchedStage() override;
+  void finalizeGCNSchedStage() override;
 
   ILPInitialScheduleStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG)
   : GCNSchedStage(StageID, DAG) {}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp 
b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 5106478a95b43..a35aabd405a1d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -62,9 +62,29 @@ static cl::opt Fix16BitCopies(
   cl::init(true),
   cl::ReallyHidden);
 
+static cl::opt AMDGPULoadLatencyScaleFactor(
+"amdgpu-load-latency-scale-factor",
+cl::desc("Scale factor for load instruction latency. Final latency is "
+ "scalled by `Factor / 100 * Latency`."),
+cl::init(100), cl::ReallyHidden);
+
+static cl::opt AMDGPUDSReadLatencyScaleFactor(
+"amdgpu-ds-read-latency-scale-factor",
+cl::desc("Scale factor for LDS (DS) read instruction latency. Final "
+ "latency is scaled by `Factor / 100 * Latency`."),
+cl::init(100), cl::ReallyHidden);
+
+static cl::opt AMDGPUVMEMLoadLatencyScaleFactor(
+"amdgpu-vmem-load-latency-scale-factor",
+cl::desc("Scale factor for VMEM/BUFFER/FLAT load instruction latency. "
+ "Final latency is scaled by `Factor / 100 * Latency`."),
+cl::init(100), cl::ReallyHidden);
+
 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
 : AMDGPUGenInstrInfo(ST, AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
-  RI(ST), ST(ST) {
+  RI(ST), ST(ST), LoadLatencyScaleFactor(AMDGPULoadLatencyScaleFactor),
+  DSReadLatencyScaleFactor(AMD

[llvm-branch-commits] [Remarks] BitstreamRemarkParser: Refactor error handling (PR #156511)

2025-09-15 Thread Tobias Stadler via llvm-branch-commits


https://github.com/tobias-stadler updated 
https://github.com/llvm/llvm-project/pull/156511


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[llvm-branch-commits] [compiler-rt] Backport AArch64 sanitizer fixes to 21.x. (PR #157848)

2025-09-15 Thread Michał Górny via llvm-branch-commits


mgorny wrote:

I think so. It doesn't really help testing 21.x releases when a lot of tests 
are failing.

https://github.com/llvm/llvm-project/pull/157848
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[llvm-branch-commits] [clang] [llvm] [lit] Make builtin cat work with stdin (PR #158447)

2025-09-15 Thread Paul Kirth via llvm-branch-commits


https://github.com/ilovepi approved this pull request.

I slightly wonder if we should accept `-` too, but I doubt that would see much 
use in the tests. I figure we can cross that bridge if something needs it.

https://github.com/llvm/llvm-project/pull/158447
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[llvm-branch-commits] [llvm] release/21.x: [VPlan] Don't narrow op multiple times in narrowInterleaveGroups. (PR #158013)

2025-09-15 Thread Tobias Hieta via llvm-branch-commits


tru wrote:

> When I created the PR, the version check failed in CI. I am curious if I did 
> something wrong when I created the PR?

Nope that's mainly a reminder to me to bump the version in the release branch. 
Thanks for checking though.

https://github.com/llvm/llvm-project/pull/158013
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[llvm-branch-commits] [clang] release/21.x: [Clang][Cygwin] Use correct mangling rule (#158404) (PR #158442)

2025-09-15 Thread via llvm-branch-commits


github-actions[bot] wrote:

@mstorsjo (or anyone else). If you would like to add a note about this fix in 
the release notes (completely optional). Please reply to this comment with a 
one or two sentence description of the fix.  When you are done, please add the 
release:note label to this PR. 

https://github.com/llvm/llvm-project/pull/158442
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[llvm-branch-commits] [Remarks] BitstreamRemarkParser: Refactor error handling (PR #156511)

2025-09-15 Thread Tobias Stadler via llvm-branch-commits


https://github.com/tobias-stadler updated 
https://github.com/llvm/llvm-project/pull/156511


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[llvm-branch-commits] [clang] [HLSL] Remove resource constructors with binding (PR #157008)

2025-09-15 Thread Farzon Lotfi via llvm-branch-commits


https://github.com/farzonl approved this pull request.


https://github.com/llvm/llvm-project/pull/157008
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[llvm-branch-commits] [Remarks] BitstreamRemarkParser: Refactor error handling (PR #156511)

2025-09-15 Thread Jon Roelofs via llvm-branch-commits



@@ -52,171 +91,132 @@ static Error parseRecord(BitstreamMetaParserHelper 
&Parser, unsigned Code) {
   switch (*RecordID) {
   case RECORD_META_CONTAINER_INFO: {
 if (Record.size() != 2)
-  return malformedRecord("BLOCK_META", "RECORD_META_CONTAINER_INFO");
-Parser.ContainerVersion = Record[0];
-Parser.ContainerType = Record[1];
+  return malformedRecord(MetaContainerInfoName);
+Container = {Record[0], Record[1]};
+// Error immediately if container version is outdated, so the user sees an
+// explanation instead of a parser error.
+if (Container->Version != CurrentContainerVersion) {
+  return ::error(
+  "Unsupported remark container version (expected: {}, read: {}). "
+  "Please upgrade/downgrade your toolchain to read this container.",
+  CurrentContainerVersion, Container->Version);
+}
 break;
   }
   case RECORD_META_REMARK_VERSION: {
 if (Record.size() != 1)
-  return malformedRecord("BLOCK_META", "RECORD_META_REMARK_VERSION");
-Parser.RemarkVersion = Record[0];
+  return malformedRecord(MetaRemarkVersionName);
+RemarkVersion = Record[0];
+// Error immediately if remark version is outdated, so the user sees an
+// explanation instead of a parser error.
+if (*RemarkVersion != CurrentRemarkVersion) {
+  return ::error(
+  "Unsupported remark version in container (expected: {}, read: {}). "
+  "Please upgrade/downgrade your toolchain to read this container.",
+  CurrentRemarkVersion, *RemarkVersion);
+}
 break;
   }
   case RECORD_META_STRTAB: {
 if (Record.size() != 0)
-  return malformedRecord("BLOCK_META", "RECORD_META_STRTAB");
-Parser.StrTabBuf = Blob;
+  return malformedRecord(MetaStrTabName);
+StrTabBuf = Blob;
 break;
   }
   case RECORD_META_EXTERNAL_FILE: {
 if (Record.size() != 0)
-  return malformedRecord("BLOCK_META", "RECORD_META_EXTERNAL_FILE");
-Parser.ExternalFilePath = Blob;
+  return malformedRecord(MetaExternalFileName);
+ExternalFilePath = Blob;
 break;
   }
   default:
-return unknownRecord("BLOCK_META", *RecordID);
+return unknownRecord(*RecordID);
   }
   return Error::success();
 }
 
-BitstreamRemarkParserHelper::BitstreamRemarkParserHelper(
-BitstreamCursor &Stream)
-: Stream(Stream) {}
-
-/// Parse a record and fill in the fields in the parser.
-static Error parseRecord(BitstreamRemarkParserHelper &Parser, unsigned Code) {
-  BitstreamCursor &Stream = Parser.Stream;
-  // Note: 5 is used here because it's the max number of fields we have per
-  // record.
-  SmallVector Record;
-  StringRef Blob;
-  Expected RecordID = Stream.readRecord(Code, Record, &Blob);
-  if (!RecordID)
-return RecordID.takeError();
+Error BitstreamRemarkParserHelper::parseRecord(unsigned Code) {
+  Record.clear();
+  Expected MaybeRecordID =
+  Stream.readRecord(Code, Record, &RecordBlob);
+  if (!MaybeRecordID)
+return MaybeRecordID.takeError();
+  RecordID = *MaybeRecordID;
+  return handleRecord();
+}
 
-  switch (*RecordID) {
+Error BitstreamRemarkParserHelper::handleRecord() {
+  switch (RecordID) {
   case RECORD_REMARK_HEADER: {
 if (Record.size() != 4)
-  return malformedRecord("BLOCK_REMARK", "RECORD_REMARK_HEADER");
-Parser.Type = Record[0];
-Parser.RemarkNameIdx = Record[1];
-Parser.PassNameIdx = Record[2];
-Parser.FunctionNameIdx = Record[3];
+  return malformedRecord(RemarkHeaderName);
+Type = Record[0];
+RemarkNameIdx = Record[1];
+PassNameIdx = Record[2];
+FunctionNameIdx = Record[3];
 break;
   }
   case RECORD_REMARK_DEBUG_LOC: {
 if (Record.size() != 3)
-  return malformedRecord("BLOCK_REMARK", "RECORD_REMARK_DEBUG_LOC");
-Parser.SourceFileNameIdx = Record[0];
-Parser.SourceLine = Record[1];
-Parser.SourceColumn = Record[2];
+  return malformedRecord(RemarkDebugLocName);
+Loc = {Record[0], Record[1], Record[2]};
 break;
   }
   case RECORD_REMARK_HOTNESS: {
 if (Record.size() != 1)
-  return malformedRecord("BLOCK_REMARK", "RECORD_REMARK_HOTNESS");
-Parser.Hotness = Record[0];
+  return malformedRecord(RemarkHotnessName);
+Hotness = Record[0];
 break;
   }
   case RECORD_REMARK_ARG_WITH_DEBUGLOC: {
 if (Record.size() != 5)
-  return malformedRecord("BLOCK_REMARK", 
"RECORD_REMARK_ARG_WITH_DEBUGLOC");
-// Create a temporary argument. Use that as a valid memory location for 
this
-// argument entry.
-Parser.TmpArgs.emplace_back();
-Parser.TmpArgs.back().KeyIdx = Record[0];
-Parser.TmpArgs.back().ValueIdx = Record[1];
-Parser.TmpArgs.back().SourceFileNameIdx = Record[2];
-Parser.TmpArgs.back().SourceLine = Record[3];
-Parser.TmpArgs.back().SourceColumn = Record[4];
-Parser.Args =
-ArrayRef(Parser.TmpArgs);
+  return malformedRecord(RemarkArgWithDebugLocName);
+auto &Arg = Args.emplace_back(Record[0

[llvm-branch-commits] [clang] [llvm] [lit] Make builtin cat work with stdin (PR #158447)

2025-09-15 Thread via llvm-branch-commits


https://github.com/cmtice approved this pull request.


https://github.com/llvm/llvm-project/pull/158447
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[llvm-branch-commits] [CAS] Add OnDiskHashMappedTrie (PR #114100)

2025-09-15 Thread Steven Wu via llvm-branch-commits


https://github.com/cachemeifyoucan updated 
https://github.com/llvm/llvm-project/pull/114100


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[llvm-branch-commits] [CAS] Add OnDiskHashMappedTrie (PR #114100)

2025-09-15 Thread Steven Wu via llvm-branch-commits


https://github.com/cachemeifyoucan updated 
https://github.com/llvm/llvm-project/pull/114100


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[llvm-branch-commits] [Clang] Enable lit internal shell by default (PR #158465)

2025-09-15 Thread via llvm-branch-commits


https://github.com/cmtice approved this pull request.


https://github.com/llvm/llvm-project/pull/158465
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[llvm-branch-commits] [CAS] Add OnDiskTrieRawHashMap (PR #114100)

2025-09-15 Thread Steven Wu via llvm-branch-commits


https://github.com/cachemeifyoucan edited 
https://github.com/llvm/llvm-project/pull/114100
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[llvm-branch-commits] [llvm] release/21.x: [VPlan] Don't narrow op multiple times in narrowInterleaveGroups. (PR #158013)

2025-09-15 Thread Florian Hahn via llvm-branch-commits


fhahn wrote:

> Is there someone else that can or should review this?

cc @ayalz / @alexey-bataev 

https://github.com/llvm/llvm-project/pull/158013
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[llvm-branch-commits] [compiler-rt] Backport AArch64 sanitizer fixes to 21.x. (PR #157848)

2025-09-15 Thread Tobias Hieta via llvm-branch-commits


tru wrote:

@mgorny This seems to be mostly test related changes. Is there a good 
justification for accepting this in the release branch?

https://github.com/llvm/llvm-project/pull/157848
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[llvm-branch-commits] [llvm] d4cc498 - Revert "[Remarks] BitstreamRemarkParser: Refactor error handling (#156511)"

2025-09-15 Thread via llvm-branch-commits


Author: Tobias Stadler
Date: 2025-09-15T15:29:10+01:00
New Revision: d4cc49816151da4fb8825f5ee910a1bfa679460b

URL: 
https://github.com/llvm/llvm-project/commit/d4cc49816151da4fb8825f5ee910a1bfa679460b
DIFF: 
https://github.com/llvm/llvm-project/commit/d4cc49816151da4fb8825f5ee910a1bfa679460b.diff

LOG: Revert "[Remarks] BitstreamRemarkParser: Refactor error handling (#156511)"

This reverts commit c723cc2a041d6e7e741b0ce6abc1f18d4ada9b4a.

Added: 


Modified: 
llvm/lib/Remarks/BitstreamRemarkParser.cpp
llvm/lib/Remarks/BitstreamRemarkParser.h

Removed: 




diff  --git a/llvm/lib/Remarks/BitstreamRemarkParser.cpp 
b/llvm/lib/Remarks/BitstreamRemarkParser.cpp
index d40b40dfb2ba0..86a6c6dffb187 100644
--- a/llvm/lib/Remarks/BitstreamRemarkParser.cpp
+++ b/llvm/lib/Remarks/BitstreamRemarkParser.cpp
@@ -12,6 +12,7 @@
 
//===--===//
 
 #include "BitstreamRemarkParser.h"
+#include "llvm/Remarks/Remark.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/Path.h"
 #include 
@@ -19,68 +20,27 @@
 using namespace llvm;
 using namespace llvm::remarks;
 
-namespace {
-
-template  Error error(char const *Fmt, const Ts &...Vals) {
-  std::string Buffer;
-  raw_string_ostream OS(Buffer);
-  OS << formatv(Fmt, Vals...);
-  return make_error(
-  std::move(Buffer),
-  std::make_error_code(std::errc::illegal_byte_sequence));
-}
-
-} // namespace
-
-Error BitstreamBlockParserHelperBase::unknownRecord(unsigned AbbrevID) {
-  return error("Unknown record entry ({}).", AbbrevID);
-}
-
-Error BitstreamBlockParserHelperBase::unexpectedRecord(StringRef RecordName) {
-  return error("Unexpected record entry ({}).", RecordName);
-}
-
-Error BitstreamBlockParserHelperBase::malformedRecord(StringRef RecordName) {
-  return error("Malformed record entry ({}).", RecordName);
-}
-
-Error BitstreamBlockParserHelperBase::unexpectedBlock(unsigned Code) {
-  return error("Unexpected subblock ({}).", Code);
+static Error unknownRecord(const char *BlockName, unsigned RecordID) {
+  return createStringError(
+  std::make_error_code(std::errc::illegal_byte_sequence),
+  "Error while parsing %s: unknown record entry (%lu).", BlockName,
+  RecordID);
 }
 
-static Expected expectSubBlock(BitstreamCursor &Stream) {
-  Expected Next = Stream.advance();
-  if (!Next)
-return Next.takeError();
-  switch (Next->Kind) {
-  case BitstreamEntry::SubBlock:
-return Next->ID;
-  case BitstreamEntry::Record:
-  case BitstreamEntry::EndBlock:
-return error("Expected subblock, but got unexpected record.");
-  case BitstreamEntry::Error:
-return error("Expected subblock, but got unexpected end of bitstream.");
-  }
-  llvm_unreachable("Unexpected BitstreamEntry");
+static Error malformedRecord(const char *BlockName, const char *RecordName) {
+  return createStringError(
+  std::make_error_code(std::errc::illegal_byte_sequence),
+  "Error while parsing %s: malformed record entry (%s).", BlockName,
+  RecordName);
 }
 
-Error BitstreamBlockParserHelperBase::expectBlock() {
-  auto MaybeBlockID = expectSubBlock(Stream);
-  if (!MaybeBlockID)
-return MaybeBlockID.takeError();
-  if (*MaybeBlockID != BlockID)
-return error("Expected {} block, but got unexpected block ({}).", 
BlockName,
- *MaybeBlockID);
-  return Error::success();
-}
+BitstreamMetaParserHelper::BitstreamMetaParserHelper(
+BitstreamCursor &Stream, BitstreamBlockInfo &BlockInfo)
+: Stream(Stream), BlockInfo(BlockInfo) {}
 
-Error BitstreamBlockParserHelperBase::enterBlock() {
-  if (Stream.EnterSubBlock(BlockID))
-return error("Error while entering {} block.", BlockName);
-  return Error::success();
-}
-
-Error BitstreamMetaParserHelper::parseRecord(unsigned Code) {
+/// Parse a record and fill in the fields in the parser.
+static Error parseRecord(BitstreamMetaParserHelper &Parser, unsigned Code) {
+  BitstreamCursor &Stream = Parser.Stream;
   // Note: 2 is used here because it's the max number of fields we have per
   // record.
   SmallVector Record;
@@ -92,132 +52,171 @@ Error BitstreamMetaParserHelper::parseRecord(unsigned 
Code) {
   switch (*RecordID) {
   case RECORD_META_CONTAINER_INFO: {
 if (Record.size() != 2)
-  return malformedRecord(MetaContainerInfoName);
-Container = {Record[0], Record[1]};
-// Error immediately if container version is outdated, so the user sees an
-// explanation instead of a parser error.
-if (Container->Version != CurrentContainerVersion) {
-  return ::error(
-  "Unsupported remark container version (expected: {}, read: {}). "
-  "Please upgrade/downgrade your toolchain to read this container.",
-  CurrentContainerVersion, Container->Version);
-}
+  return malformedRecord("BLOCK_META", "RECORD_META_CONTAINER_INFO");
+Parser.ContainerVersion = Re

[llvm-branch-commits] [llvm] release/21.x: [VPlan] Don't narrow op multiple times in narrowInterleaveGroups. (PR #158013)

2025-09-15 Thread Florian Hahn via llvm-branch-commits


fhahn wrote:

When I created the PR, the version check failed in CI. I am curious if I did 
something wrong when I created the PR?

https://github.com/llvm/llvm-project/pull/158013
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[llvm-branch-commits] [llvm] [DA] Add test where ExactSIV misses dependency due to overflow (NFC) (PR #157085)

2025-09-15 Thread Michael Kruse via llvm-branch-commits


https://github.com/Meinersbur edited 
https://github.com/llvm/llvm-project/pull/157085
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[llvm-branch-commits] [llvm] [DA] Add test where ExactSIV misses dependency due to overflow (NFC) (PR #157085)

2025-09-15 Thread Michael Kruse via llvm-branch-commits



@@ -807,3 +807,123 @@ for.body: ; preds 
= %entry, %for.body
 for.end:  ; preds = %for.body
   ret void
 }
+
+;; max_i = INT64_MAX/6  // 1537228672809129301
+;; for (long long i = 0; i <= max_i; i++) {
+;;   A[-6*i + INT64_MAX] = 0;
+;;   if (i)
+;; A[3*i - 2] = 1;
+;; }
+;;
+;; FIXME: There is a loop-carried dependency between
+;; `A[-6*i + INT64_MAX]` and `A[3*i - 2]`. For example,

Meinersbur wrote:

```suggestion
;; FIXME: DependencyAnalsysis currently detects no dependency, but there is a 
loop-carried dependency between
;; `A[-6*i + INT64_MAX]` and `A[3*i - 2]`. For example,
```
[suggestion] Just to make clear what DA's current wrong behaviour is

https://github.com/llvm/llvm-project/pull/157085
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[llvm-branch-commits] [llvm] [DA] Add test where ExactSIV misses dependency due to overflow (NFC) (PR #157085)

2025-09-15 Thread Michael Kruse via llvm-branch-commits


https://github.com/Meinersbur approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/157085
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[llvm-branch-commits] [llvm] 7f74a55 - Revert "[CAS] Add MappedFileRegionArena (#114099)"

2025-09-15 Thread via llvm-branch-commits


Author: Paul Kirth
Date: 2025-09-15T10:31:12-07:00
New Revision: 7f74a55e6401f5c184acae1e5acbf56fe1402e9e

URL: 
https://github.com/llvm/llvm-project/commit/7f74a55e6401f5c184acae1e5acbf56fe1402e9e
DIFF: 
https://github.com/llvm/llvm-project/commit/7f74a55e6401f5c184acae1e5acbf56fe1402e9e.diff

LOG: Revert "[CAS] Add MappedFileRegionArena (#114099)"

This reverts commit f9cd2ee119ff6bd59f48fd71617dc4fc981083c9.

Added: 


Modified: 
llvm/CMakeLists.txt
llvm/include/llvm/Config/llvm-config.h.cmake
llvm/include/llvm/Support/FileSystem.h
llvm/lib/CAS/CMakeLists.txt
llvm/lib/Support/Unix/Path.inc
llvm/lib/Support/Windows/Path.inc
llvm/unittests/CAS/CMakeLists.txt

Removed: 
llvm/include/llvm/CAS/MappedFileRegionArena.h
llvm/lib/CAS/MappedFileRegionArena.cpp
llvm/lib/CAS/OnDiskCommon.cpp
llvm/lib/CAS/OnDiskCommon.h
llvm/unittests/CAS/ProgramTest.cpp



diff  --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index e8af7fb432f40..b98192968a3ab 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -878,7 +878,6 @@ option (LLVM_ENABLE_SPHINX "Use Sphinx to generate llvm 
documentation." OFF)
 option (LLVM_ENABLE_OCAMLDOC "Build OCaml bindings documentation." ON)
 option (LLVM_ENABLE_BINDINGS "Build bindings." ON)
 option (LLVM_ENABLE_TELEMETRY "Enable the telemetry library. If set to OFF, 
library cannot be enabled after build (eg., at runtime)" ON)
-option (LLVM_ENABLE_ONDISK_CAS "Build OnDiskCAS." ON)
 
 set(LLVM_INSTALL_DOXYGEN_HTML_DIR "${CMAKE_INSTALL_DOCDIR}/llvm/doxygen-html"
 CACHE STRING "Doxygen-generated HTML documentation install directory")

diff  --git a/llvm/include/llvm/CAS/MappedFileRegionArena.h 
b/llvm/include/llvm/CAS/MappedFileRegionArena.h
deleted file mode 100644
index ff51f0eb59929..0
--- a/llvm/include/llvm/CAS/MappedFileRegionArena.h
+++ /dev/null
@@ -1,130 +0,0 @@
-//===--===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===--===//
-//
-/// \file
-/// This file declares interface for MappedFileRegionArena, a bump pointer
-/// allocator, backed by a memory-mapped file.
-///
-//===--===//
-
-#ifndef LLVM_CAS_MAPPEDFILEREGIONARENA_H
-#define LLVM_CAS_MAPPEDFILEREGIONARENA_H
-
-#include "llvm/Support/Alignment.h"
-#include "llvm/Support/FileSystem.h"
-#include 
-
-namespace llvm::cas {
-
-/// Allocator for an owned mapped file region that supports thread-safe and
-/// process-safe bump pointer allocation.
-///
-/// This allocator is designed to create a sparse file when supported by the
-/// filesystem's \c ftruncate so that it can be used with a large maximum size.
-/// It will also attempt to shrink the underlying file down to its current
-/// allocation size when the last concurrent mapping is closed.
-///
-/// Process-safe. Uses file locks when resizing the file during initialization
-/// and destruction.
-///
-/// Thread-safe. Requires OS support thread-safe file lock.
-///
-/// Provides 8-byte alignment for all allocations.
-class MappedFileRegionArena {
-public:
-  using RegionT = sys::fs::mapped_file_region;
-
-  /// Header for MappedFileRegionArena. It can be configured to be located
-  /// at any location within the file and the allocation will be appended after
-  /// the header.
-  struct Header {
-// BumpPtr for new allocation.
-std::atomic BumpPtr;
-// Allocated size on disk.
-std::atomic AllocatedSize;
-// Capacity of the file.
-std::atomic Capacity;
-// Offset from the beginning of the file to this header (for verification).
-std::atomic HeaderOffset;
-  };
-
-  /// Create a \c MappedFileRegionArena.
-  ///
-  /// \param Path the path to open the mapped region.
-  /// \param Capacity the maximum size for the mapped file region.
-  /// \param HeaderOffset the offset at which to store the header. This is so
-  /// that information can be stored before the header, like a file magic.
-  /// \param NewFileConstructor is for constructing new files. It has exclusive
-  /// access to the file. Must call \c initializeBumpPtr.
-  static Expected
-  create(const Twine &Path, uint64_t Capacity, uint64_t HeaderOffset,
- function_ref NewFileConstructor);
-
-  /// Minimum alignment for allocations, currently hardcoded to 8B.
-  static constexpr Align getAlign() {
-// Trick Align into giving us '8' as a constexpr.
-struct alignas(8) T {};
-static_assert(alignof(T) == 8, "Tautology failed?");
-return Align::Of();
-  }
-
-  /// Allocate at least \p AllocSize. Rounds up to \a getAlign().
-  Expected allocate(uint64_t

[llvm-branch-commits] [clang] b1c4787 - Revert "[clang] fix clang_cmake_builddir (#155844)"

2025-09-15 Thread via llvm-branch-commits


Author: Nathan Gauër
Date: 2025-09-15T18:13:34+02:00
New Revision: b1c4787e8da9da260ba6d4e692b57fc9cc79dc81

URL: 
https://github.com/llvm/llvm-project/commit/b1c4787e8da9da260ba6d4e692b57fc9cc79dc81
DIFF: 
https://github.com/llvm/llvm-project/commit/b1c4787e8da9da260ba6d4e692b57fc9cc79dc81.diff

LOG: Revert "[clang] fix clang_cmake_builddir (#155844)"

This reverts commit 61664b61032edf8763f48099636bc7cd35ef622e.

Added: 


Modified: 
clang/cmake/modules/CMakeLists.txt

Removed: 




diff  --git a/clang/cmake/modules/CMakeLists.txt 
b/clang/cmake/modules/CMakeLists.txt
index 90fbd88ca9826..d2d68121371bf 100644
--- a/clang/cmake/modules/CMakeLists.txt
+++ b/clang/cmake/modules/CMakeLists.txt
@@ -8,14 +8,15 @@ include(FindPrefixFromConfig)
 # the usual CMake convention seems to be ${Project}Targets.cmake.
 set(CLANG_INSTALL_PACKAGE_DIR "${CMAKE_INSTALL_PACKAGEDIR}/clang" CACHE STRING
   "Path for CMake subdirectory for Clang (defaults to 
'${CMAKE_INSTALL_PACKAGEDIR}/clang')")
+# CMAKE_INSTALL_PACKAGEDIR might be absolute, so don't reuse below.
+set(clang_cmake_builddir 
"${CMAKE_BINARY_DIR}/lib${LLVM_LIBDIR_SUFFIX}/cmake/clang")
 
 # Keep this in sync with llvm/cmake/CMakeLists.txt!
 set(LLVM_INSTALL_PACKAGE_DIR "${CMAKE_INSTALL_PACKAGEDIR}/llvm" CACHE STRING
   "Path for CMake subdirectory for LLVM (defaults to 
'${CMAKE_INSTALL_PACKAGEDIR}/llvm')")
 # CMAKE_INSTALL_PACKAGEDIR might be absolute, so don't reuse below.
-string(REPLACE "${CMAKE_CFG_INTDIR}" "." llvm_builddir "${LLVM_LIBRARY_DIR}")
-set(llvm_cmake_builddir "${llvm_builddir}/cmake/llvm")
-set(clang_cmake_builddir "${llvm_builddir}/cmake/clang")
+string(REPLACE "${CMAKE_CFG_INTDIR}" "." llvm_cmake_builddir 
"${LLVM_LIBRARY_DIR}")
+set(llvm_cmake_builddir "${llvm_cmake_builddir}/cmake/llvm")
 
 get_property(CLANG_EXPORTS GLOBAL PROPERTY CLANG_EXPORTS)
 export(TARGETS ${CLANG_EXPORTS} FILE 
${clang_cmake_builddir}/ClangTargets.cmake)



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[llvm-branch-commits] [Clang] Rewrite tests using subshells to set env variables (PR #158446)

2025-09-15 Thread Paul Kirth via llvm-branch-commits


https://github.com/ilovepi approved this pull request.


https://github.com/llvm/llvm-project/pull/158446
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[llvm-branch-commits] [Clang] Enable lit internal shell by default (PR #158465)

2025-09-15 Thread Paul Kirth via llvm-branch-commits


https://github.com/ilovepi approved this pull request.


https://github.com/llvm/llvm-project/pull/158465
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[llvm-branch-commits] [lit] Add support for deleting symlinks to directories without -r (PR #158464)

2025-09-15 Thread Paul Kirth via llvm-branch-commits


https://github.com/ilovepi approved this pull request.


https://github.com/llvm/llvm-project/pull/158464
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[llvm-branch-commits] [clang] release/21.x: [clang] Followup for constexpr-unknown potential constant expressions. (#151053) (PR #157098)

2025-09-15 Thread Eli Friedman via llvm-branch-commits


efriedma-quic wrote:

This isn't high priority from my perspective; it technically fixes a regression 
in C++23 mode, but only if you do weird stuff with enable_if, or enable 
-Winvalid-constexpr, which is not on by default in C++23 mode.  If there's some 
reason to reprioritize, please let me know.

https://github.com/llvm/llvm-project/pull/157098
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[llvm-branch-commits] [llvm] PPC: Split 64bit target feature into 64bit and 64bit-support (PR #157206)

2025-09-15 Thread Lei Huang via llvm-branch-commits


https://github.com/lei137 approved this pull request.

This seems reasonable to me. Thx for the improvement!

https://github.com/llvm/llvm-project/pull/157206
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[llvm-branch-commits] [clang] [HLSL] Use static create methods to initialize resources in arrays (PR #157005)

2025-09-15 Thread Helena Kotas via llvm-branch-commits


https://github.com/hekota edited 
https://github.com/llvm/llvm-project/pull/157005
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[llvm-branch-commits] [clang] [HLSL] Use static create methods to initialize resources in arrays (PR #157005)

2025-09-15 Thread Helena Kotas via llvm-branch-commits


https://github.com/hekota edited 
https://github.com/llvm/llvm-project/pull/157005
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[llvm-branch-commits] [clang] [HLSL] Use static create methods to initialize resources in arrays (PR #157005)

2025-09-15 Thread Helena Kotas via llvm-branch-commits


https://github.com/hekota edited 
https://github.com/llvm/llvm-project/pull/157005
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