https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/158777
None >From 0821bf6b56fbcf9aebc2eea8b4e1af02f9f2d1f9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault <[email protected]> Date: Fri, 5 Sep 2025 18:03:59 +0900 Subject: [PATCH] PPC: Replace PointerLikeRegClass with RegClassByHwMode --- .../PowerPC/Disassembler/PPCDisassembler.cpp | 3 -- llvm/lib/Target/PowerPC/PPC.td | 6 ++++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 28 ++++++------------- llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 10 +++++-- 4 files changed, 23 insertions(+), 24 deletions(-) diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index 47586c417cfe3..70e619cc22b19 100644 --- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -185,9 +185,6 @@ DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, return decodeRegisterClass(Inst, RegNo, XRegsNoX0); } -#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass -#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass - static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index 386d0f65d1ed1..d491e88b66ad8 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -394,6 +394,12 @@ def NotAIX : Predicate<"!Subtarget->isAIXABI()">; def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">; +//===----------------------------------------------------------------------===// +// HwModes +//===----------------------------------------------------------------------===// + +defvar PPC32 = DefaultMode; +def PPC64 : HwMode<[In64BitMode]>; // Since new processors generally contain a superset of features of those that // came before them, the idea is to make implementations of new processors diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index db066bc4b7bdd..55e38bcf4afc9 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2142,33 +2142,23 @@ bool PPCInstrInfo::onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI"); assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); - const MCOperandInfo *UseInfo = &UseMCID.operands()[UseIdx]; - // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0 // register (which might also be specified as a pointer class kind). - if (UseInfo->isLookupPtrRegClass()) { - if (UseInfo->RegClass /* Kind */ != 1) - return false; - } else { - if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && - UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) - return false; - } + + const MCOperandInfo &UseInfo = UseMCID.operands()[UseIdx]; + int16_t RegClass = getOpRegClassID(UseInfo); + if (UseInfo.RegClass != PPC::GPRC_NOR0RegClassID && + UseInfo.RegClass != PPC::G8RC_NOX0RegClassID) + return false; // Make sure this is not tied to an output register (or otherwise // constrained). This is true for ST?UX registers, for example, which // are tied to their output registers. - if (UseInfo->Constraints != 0) + if (UseInfo.Constraints != 0) return false; - MCRegister ZeroReg; - if (UseInfo->isLookupPtrRegClass()) { - bool isPPC64 = Subtarget.isPPC64(); - ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; - } else { - ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? - PPC::ZERO8 : PPC::ZERO; - } + MCRegister ZeroReg = + RegClass == PPC::G8RC_NOX0RegClassID ? PPC::ZERO8 : PPC::ZERO; LLVM_DEBUG(dbgs() << "Folded immediate zero for: "); LLVM_DEBUG(UseMI.dump()); diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index 8b690b7b833b3..adda91786d19c 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -868,7 +868,11 @@ def crbitm: Operand<i8> { def PPCRegGxRCNoR0Operand : AsmOperandClass { let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; } -def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { + +def ptr_rc_nor0 : Operand<iPTR>, + RegClassByHwMode< + [PPC32, PPC64], + [GPRC_NOR0, G8RC_NOX0]> { let ParserMatchClass = PPCRegGxRCNoR0Operand; } @@ -902,7 +906,9 @@ def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value. def PPCRegGxRCOperand : AsmOperandClass { let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; } -def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { +def ptr_rc_idx : Operand<iPTR>, + RegClassByHwMode<[PPC32, PPC64], + [GPRC, G8RC]> { let ParserMatchClass = PPCRegGxRCOperand; } _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
