[llvm-branch-commits] [lld] [lld][LoongArch] Relax TLS LE/GD/LD (PR #123600)
@@ -0,0 +1,115 @@ +# REQUIRES: loongarch + +# RUN: llvm-mc --filetype=obj --triple=loongarch32 -mattr=+relax --defsym ELF32=1 %s -o %t.32.o +# RUN: llvm-mc --filetype=obj --triple=loongarch64 -mattr=+relax %s -o %t.64.o + +# RUN: ld.lld %t.32.o -o %t.32 +# RUN: llvm-objdump -d --no-show-raw-insn %t.32 | FileCheck --check-prefixes=RELAX32 %s + +# RUN: ld.lld %t.64.o -o %t.64 +# RUN: llvm-objdump -d --no-show-raw-insn %t.64 | FileCheck --check-prefixes=RELAX64 %s + +# RELAX32-LABEL: <_start>: +## .LANCHOR0@tprel = 8 +# RELAX32-NEXT:addi.w $a0, $tp, 8 +# RELAX32-NEXT:ld.w$a1, $a0, 0 +# RELAX32-NEXT:ld.w$a2, $tp, 8 +## .a@tprel - 4 = 0x7fc +# RELAX32-NEXT:addi.w $a1, $zero, 1 +# RELAX32-NEXT:addi.w $a1, $a1, 2 +# RELAX32-NEXT:st.w $a1, $tp, 2044 +## .a@tprel = 0x800 +# RELAX32-NEXT:lu12i.w $a0, 1 +# RELAX32-NEXT:add.w $a0, $a0, $tp +# RELAX32-NEXT:addi.w $a0, $a0, -2048 + +# RELAX64-LABEL: <_start>: +## .LANCHOR0@tprel = 8 +# RELAX64-NEXT:addi.d $a0, $tp, 8 +# RELAX64-NEXT:ld.d$a1, $a0, 0 +# RELAX64-NEXT:ld.d$a2, $tp, 8 +## .a@tprel - 4 = 0x7fc +# RELAX64-NEXT:addi.d $a1, $zero, 1 +# RELAX64-NEXT:addi.d $a1, $a1, 2 +# RELAX64-NEXT:st.d $a1, $tp, 2044 +## .a@tprel = 0x800 +# RELAX64-NEXT:lu12i.w $a0, 1 +# RELAX64-NEXT:add.d $a0, $a0, $tp +# RELAX64-NEXT:addi.d $a0, $a0, -2048 + +.macro add dst, src1, src2, src3 +.ifdef ELF32 +add.w \dst, \src1, \src2, \src3 +.else +add.d \dst, \src1, \src2, \src3 +.endif +.endm +.macro inst op dst, src1, src2 +.ifdef ELF32 + .ifc \op, addi +addi.w \dst, \src1, \src2 + .else;.ifc \op, ld +ld.w\dst, \src1, \src2 + .else;.ifc \op, st +st.w\dst, \src1, \src2 + .else;.ifc \op, ldptr +ldptr.w \dst, \src1, \src2 + .else +.error "Unknown op in ELF32 mode" + .endif; .endif; .endif; .endif +.else + .ifc \op, addi +addi.d \dst, \src1, \src2 + .else;.ifc \op, ld +ld.d\dst, \src1, \src2 + .else;.ifc \op, st +st.d\dst, \src1, \src2 + .else;.ifc \op, ldptr +ldptr.d \dst, \src1, \src2 + .else +.error "Unknown op in ELF64 mode" + .endif; .endif; .endif; .endif +.endif +.endm + +.macro addi dst, src1, src2 +inst addi \dst, \src1, \src2 +.endm +.macro ld dst, src1, src2 +inst ld \dst, \src1, \src2 +.endm +.macro st dst, src1, src2 +inst st \dst, \src1, \src2 +.endm +.macro ldptr dst, src1, src2 +inst ldptr \dst, \src1, \src2 +.endm + +_start: +## Test instructions not in pairs. +lu12i.w $a0, %le_hi20_r(.LANCHOR0) xen0n wrote: Yeah, the instructions should be indented by 2 or 4 spaces for readability. We should re-format some test cases e.g. `loongarch-tlsdesc.s` as well in a separate change. https://github.com/llvm/llvm-project/pull/123600 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [lld][LoongArch] Relax TLS LE/GD/LD (PR #123600)
@@ -1015,8 +1063,20 @@ void LoongArch::finalizeRelax(int passes) const {
r.expr = r.sym->hasFlag(NEEDS_PLT) ? R_PLT_PC : R_PC;
break;
case R_LARCH_B26:
+ case R_LARCH_TLS_LE_LO12_R:
+skip = 4;
+write32le(p, aux.writes[writesIdx++]);
+break;
+ case R_LARCH_TLS_GD_PCREL20_S2:
+// Note: R_LARCH_TLS_LD_PCREL20_S2 must also use R_TLSGD_PC instead
+// of R_TLSLD_PC because the processing of relocation
+// R_LARCH_TLS_LD_PC_HI20 is the same as R_LARCH_TLS_GD_PC_HI20. If
xen0n wrote:
According to [this mold
commit](https://github.com/rui314/mold/commit/5dfa1cf07c03bd57cb3d493b652ef22441bcd71c)
this is mostly due to human error (compiler bug that's unfortunately too late
to fix without revising psABI), so you may want to mention it somehow to reduce
reader confusion. "If not, ... will error" is clearly not the root cause and
likely will not satisfy the curiosity of many.
https://github.com/llvm/llvm-project/pull/123600
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[llvm-branch-commits] [clang-tools-extra] [clangd] Add clangd 20 release notes (PR #127358)
@@ -67,35 +68,84 @@ Semantic Highlighting Compile flags ^ +- Fixed a bug where clangd would unnecessarily reparse open files whose + compile command did not change when receiving a new compile command + via an LSP `workspace/configuration` request (#GH115438) + Hover ^ +- Hovering over a function name now shows the function's documentation + comment even if the comment is written above the function's out-of-line + definition in a different source file (#GH67802) + Code completion ^^^ +- Added an `ArgumentLists` config option under `Completion`. This is a more + flexible version of the `--function-arg-placeholders` command line flag, + allowing users more detailed control of what is inserted in argument list + position when clangd completes the name of a function in a function call + context. (#GH111322) +- Clangd now supports configuring which headers should be inserted using + `<>` vs. `""` syntax using the `QuotedHeaders` and `AngledHeaders` config + options under `Style` (#GH67749) - Added completion for C++20 keywords. +- Clangd's `HeuristicResolver` component was upstreamed to `libSema` where + code completion can take advantage of it, resulting in improved code + completion in templated code +- Code completion proposals for symbols defined in included headers now + include documentation comments (#GH120099) Code actions - Added `Swap operands` tweak for certain binary operators. - - Improved the extract-to-function code action to allow extracting statements with overloaded operators like ``<<`` of ``std::ostream``. +- `Define outline` now handles member functions of class templates, and + member function templates. +- `Extract variable` can now operate on the top-level expression in an + expression statement (#GH112525) Signature help ^^ Cross-references +- Clangd now supports the "outgoing calls" direction of call hierarchy + (#GH77556) +- Call hierarchy can now be invoked on fields and namespace-scope + variables (#GH113900) +- Improved heuristics for filtering out generated Protobuf symbol names + during indexing (#GH110091) +- Compiler intrinsics defined in `*intrin.h` system headers are now + indexed even if they have reserved names (#GH119735) +- Various improvements to go-to-definition in templated code + Objective-C ^^^ +Clang-tidy integration +^^ + +- Improved robustness in handling clang-tidy check names (#GH109421) + +C++20 Modules Support ChuanqiXu9 wrote: I think the current wording is fine. Or we can say we improved the efficiency of support for modules in clangd20. https://github.com/llvm/llvm-project/pull/127358 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [lld][LoongArch] Relax TLS LE/GD/LD (PR #123600)
@@ -863,6 +874,35 @@ static void relaxCall36(Ctx &ctx, const InputSection &sec,
size_t i,
}
}
+// Relax code sequence.
+// From:
+// lu12i.w $rd, %le_hi20_r(sym)
+// add.w/d $rd, $rd, $tp, %le_add_r(sym)
+// addi/ld/st.w/d $rd, $rd, %le_lo12_r(sym)
+// To:
+// addi/ld/st.w/d $rd, $tp, %le_lo12_r(sym)
+static void relaxTlsLe(Ctx &ctx, const InputSection &sec, size_t i,
+ uint64_t loc, Relocation &r, uint32_t &remove) {
+ uint64_t val = r.sym->getVA(ctx, r.addend);
+ // Check if the val exceeds the range of addi/ld/st.
+ if (!isInt<12>(val))
+return;
+ uint32_t currInsn = read32le(sec.content().data() + r.offset);
+ switch (r.type) {
+ case R_LARCH_TLS_LE_HI20_R:
+ case R_LARCH_TLS_LE_ADD_R:
+sec.relaxAux->relocTypes[i] = R_LARCH_RELAX;
+remove = 4;
+break;
+ case R_LARCH_TLS_LE_LO12_R:
+currInsn =
+insn(extractBits(currInsn, 31, 22) << 22, getD5(currInsn), R_TP, 0);
+sec.relaxAux->writes.push_back(currInsn);
xen0n wrote:
It's probably better to add a `setJ` helper (near the `setJ20` helper maybe)
and use it instead, so that the expression becomes shorter and no need to
change the `currInsn` variable.
https://github.com/llvm/llvm-project/pull/123600
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[llvm-branch-commits] [lld] [lld][LoongArch] Relax TLS LE/GD/LD (PR #123600)
@@ -1015,8 +1063,20 @@ void LoongArch::finalizeRelax(int passes) const {
r.expr = r.sym->hasFlag(NEEDS_PLT) ? R_PLT_PC : R_PC;
break;
case R_LARCH_B26:
+ case R_LARCH_TLS_LE_LO12_R:
+skip = 4;
+write32le(p, aux.writes[writesIdx++]);
+break;
+ case R_LARCH_TLS_GD_PCREL20_S2:
+// Note: R_LARCH_TLS_LD_PCREL20_S2 must also use R_TLSGD_PC instead
+// of R_TLSLD_PC because the processing of relocation
+// R_LARCH_TLS_LD_PC_HI20 is the same as R_LARCH_TLS_GD_PC_HI20. If
ylzsx wrote:
Thanks for your review. I will revise it to the following description. Do you
think it is clear?
```
Note: R_LARCH_TLS_LD_PCREL20_S2 must also use R_TLSGD_PC instead
of R_TLSLD_PC due to historical reasons. In fact, TLSLD is not fully supported
on LoongArch. We need to handle relocation of R_LARCH_TLS_LD_PC_HI20
as equivalent to R_LARCH_TLS_GD_PC_HI20.
This reason has also been mentioned in mold commit:
https://github.com/rui314/mold/commit/5dfa1cf07c03bd57cb3d493b652ef22441bcd71c
```
https://github.com/llvm/llvm-project/pull/123600
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[llvm-branch-commits] [lld] [lld][LoongArch] Relax TLS LE/GD/LD (PR #123600)
@@ -1015,8 +1063,20 @@ void LoongArch::finalizeRelax(int passes) const {
r.expr = r.sym->hasFlag(NEEDS_PLT) ? R_PLT_PC : R_PC;
break;
case R_LARCH_B26:
+ case R_LARCH_TLS_LE_LO12_R:
+skip = 4;
+write32le(p, aux.writes[writesIdx++]);
+break;
+ case R_LARCH_TLS_GD_PCREL20_S2:
+// Note: R_LARCH_TLS_LD_PCREL20_S2 must also use R_TLSGD_PC instead
+// of R_TLSLD_PC because the processing of relocation
+// R_LARCH_TLS_LD_PC_HI20 is the same as R_LARCH_TLS_GD_PC_HI20. If
xen0n wrote:
> Thanks for your review. I will revise it to the following description. Do you
> think it is clear?
>
> ```
> Note: R_LARCH_TLS_LD_PCREL20_S2 must also use R_TLSGD_PC instead
> of R_TLSLD_PC due to historical reasons. In fact, TLSLD is not fully supported
> on LoongArch. We need to handle relocation of R_LARCH_TLS_LD_PC_HI20
> as equivalent to R_LARCH_TLS_GD_PC_HI20.
>
> This reason has also been mentioned in mold commit:
> https://github.com/rui314/mold/commit/5dfa1cf07c03bd57cb3d493b652ef22441bcd71c
> ```
"In fact, right now TLS LD behaves exactly like GD on LoongArch." is enough,
and the "We need to ..." sentence can be omitted this way.
https://github.com/llvm/llvm-project/pull/123600
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[llvm-branch-commits] [llvm] [AMDGPU] Change SGPR layout to striped caller/callee saved (PR #127353)
shiltian wrote: This has passed internal PSDB (except the one test case that I has not updated yet). https://github.com/llvm/llvm-project/pull/127353 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [lld][LoongArch] Relax TLS LE/GD/LD (PR #123600)
https://github.com/ylzsx updated
https://github.com/llvm/llvm-project/pull/123600
>From 7993434e2973437b010034051003f8c03d8eff71 Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Fri, 27 Dec 2024 19:29:32 +0800
Subject: [PATCH 1/8] Relax TLS LE/GD/LD.
In local-exec form, the code sequence is converted as follows:
```
From:
lu12i.w $rd, %le_hi20_r(sym)
R_LARCH_TLS_LE_HI20_R, R_LARCH_RELAX
add.w/d $rd, $rd, $tp, %le_add_r(sym)
R_LARCH_TLS_LE_ADD_R, R_LARCH_RELAX
addi/ld/st.w/d $rd, $rd, %le_lo12_r(sym)
R_LARCH_TLS_LE_LO12_R, R_LARCH_RELAX
To:
addi/ld/st.w/d $rd, $tp, %le_lo12_r(sym)
R_LARCH_TLS_LE_LO12_R
```
In global-dynamic or local-dynamic, the code sequence is converted as
follows:
```
From:
pcalau12i $a0, %ld_pc_hi20(sym) | %gd_pc_hi20(sym)
R_LARCH_TLS_GD_PC_HI20 | R_LARCH_TLS_LD_PC_HI20, R_LARCH_RELAX
addi.w/d $a0, $a0, %got_pc_lo12(sym) | %got_pc_lo12(sym)
R_LARCH_GOT_PC_LO12, R_LARCH_RELAX
To:
pcaddi$a0, %got_pc_lo12(sym) | %got_pc_lo12(sym)
R_LARCH_TLS_GD_PCREL20_S2 | R_LARCH_TLS_LD_PCREL20_S2
```
Note: For initial-exec form, since it involves the conversion from IE to
LE, we will implement it in a future patch.
---
lld/ELF/Arch/LoongArch.cpp | 68 +++---
1 file changed, 64 insertions(+), 4 deletions(-)
diff --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp
index 0aa0cf5b657a0..2d6d86d2ca63b 100644
--- a/lld/ELF/Arch/LoongArch.cpp
+++ b/lld/ELF/Arch/LoongArch.cpp
@@ -761,10 +761,10 @@ static bool isPairRelaxable(ArrayRef relocs,
size_t i) {
// Relax code sequence.
// From:
-// pcalau12i $a0, %pc_hi20(sym)
-// addi.w/d $a0, $a0, %pc_lo12(sym)
+// pcalau12i $a0, %pc_hi20(sym) | %ld_pc_hi20(sym) | %gd_pc_hi20(sym)
+// addi.w/d $a0, $a0, %pc_lo12(sym) | %got_pc_lo12(sym) | %got_pc_lo12(sym)
// To:
-// pcaddi $a0, %pc_lo12(sym)
+// pcaddi $a0, %pc_lo12(sym) | %got_pc_lo12(sym) | %got_pc_lo12(sym)
//
// From:
// pcalau12i $a0, %got_pc_hi20(sym_got)
@@ -778,6 +778,10 @@ static void relaxPCHi20Lo12(Ctx &ctx, const InputSection
&sec, size_t i,
if (!((rHi20.type == R_LARCH_PCALA_HI20 &&
rLo12.type == R_LARCH_PCALA_LO12) ||
(rHi20.type == R_LARCH_GOT_PC_HI20 &&
+ rLo12.type == R_LARCH_GOT_PC_LO12) ||
+(rHi20.type == R_LARCH_TLS_GD_PC_HI20 &&
+ rLo12.type == R_LARCH_GOT_PC_LO12) ||
+(rHi20.type == R_LARCH_TLS_LD_PC_HI20 &&
rLo12.type == R_LARCH_GOT_PC_LO12)))
return;
@@ -798,6 +802,8 @@ static void relaxPCHi20Lo12(Ctx &ctx, const InputSection
&sec, size_t i,
else if (rHi20.expr == RE_LOONGARCH_PAGE_PC ||
rHi20.expr == RE_LOONGARCH_GOT_PAGE_PC)
symBase = rHi20.sym->getVA(ctx);
+ else if (rHi20.expr == RE_LOONGARCH_TLSGD_PAGE_PC)
+symBase = ctx.in.got->getGlobalDynAddr(*rHi20.sym);
else {
Err(ctx) << getErrorLoc(ctx, (const uint8_t *)loc) << "unknown expr ("
<< rHi20.expr << ") against symbol " << rHi20.sym
@@ -827,7 +833,12 @@ static void relaxPCHi20Lo12(Ctx &ctx, const InputSection
&sec, size_t i,
return;
sec.relaxAux->relocTypes[i] = R_LARCH_RELAX;
- sec.relaxAux->relocTypes[i + 2] = R_LARCH_PCREL20_S2;
+ if (rHi20.type == R_LARCH_TLS_GD_PC_HI20)
+sec.relaxAux->relocTypes[i + 2] = R_LARCH_TLS_GD_PCREL20_S2;
+ else if (rHi20.type == R_LARCH_TLS_LD_PC_HI20)
+sec.relaxAux->relocTypes[i + 2] = R_LARCH_TLS_LD_PCREL20_S2;
+ else
+sec.relaxAux->relocTypes[i + 2] = R_LARCH_PCREL20_S2;
sec.relaxAux->writes.push_back(insn(PCADDI, getD5(nextInsn), 0, 0));
remove = 4;
}
@@ -863,6 +874,35 @@ static void relaxCall36(Ctx &ctx, const InputSection &sec,
size_t i,
}
}
+// Relax code sequence.
+// From:
+// lu12i.w $rd, %le_hi20_r(sym)
+// add.w/d $rd, $rd, $tp, %le_add_r(sym)
+// addi/ld/st.w/d $rd, $rd, %le_lo12_r(sym)
+// To:
+// addi/ld/st.w/d $rd, $tp, %le_lo12_r(sym)
+static void relaxTlsLe(Ctx &ctx, const InputSection &sec, size_t i,
+ uint64_t loc, Relocation &r, uint32_t &remove) {
+ uint64_t val = r.sym->getVA(ctx, r.addend);
+ // Check if the val exceeds the range of addi/ld/st.
+ if (!isInt<12>(val))
+return;
+ uint32_t currInsn = read32le(sec.content().data() + r.offset);
+ switch (r.type) {
+ case R_LARCH_TLS_LE_HI20_R:
+ case R_LARCH_TLS_LE_ADD_R:
+sec.relaxAux->relocTypes[i] = R_LARCH_RELAX;
+remove = 4;
+break;
+ case R_LARCH_TLS_LE_LO12_R:
+currInsn =
+insn(extractBits(currInsn, 31, 22) << 22, getD5(currInsn), R_TP, 0);
+sec.relaxAux->writes.push_back(currInsn);
+sec.relaxAux->relocTypes[i] = R_LARCH_TLS_LE_LO12_R;
+break;
+ }
+}
+
static bool relax(Ctx &ctx, InputSection &sec) {
const uint64_t secAddr = sec.getVA();
const MutableArrayRef relocs = sec.relocs();
@@ -903,6 +943,8 @@ static bool relax(Ctx &ctx, InputSection &sec) {
}
case R_LARCH_PCALA_HI20:
case R_LARCH_GOT_PC_HI20:
+case R_LARCH_TLS_GD_PC_HI20:
+case R_LARCH_TLS_LD_PC_HI20:
[llvm-branch-commits] [llvm] release/20.x: [InstCombine] Do not keep samesign when speculatively executing icmps (#127007) (PR #127391)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/127391
Backport 29f3a352068ce562bcb65e18a676c82a9991583c
Requested by: @dtcxzyw
>From aa1a0484c95e085b5014e6cae48d2167fc54217d Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 16 Feb 2025 20:18:29 +0800
Subject: [PATCH] [InstCombine] Do not keep samesign when speculatively
executing icmps (#127007)
Closes https://github.com/llvm/llvm-project/issues/126974.
(cherry picked from commit 29f3a352068ce562bcb65e18a676c82a9991583c)
---
.../InstCombine/InstCombineCompares.cpp | 5
llvm/test/Transforms/InstCombine/umax-icmp.ll | 24 +++
2 files changed, 29 insertions(+)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index b64ac20ab0533..810ce7d382ae1 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -5609,6 +5609,11 @@ Instruction
*InstCombinerImpl::foldICmpWithMinMax(Instruction &I,
return false;
return std::nullopt;
};
+ // Remove samesign here since it is illegal to keep it when we speculatively
+ // execute comparisons. For example, `icmp samesign ult umax(X, -46), -32`
+ // cannot be decomposed into `(icmp samesign ult X, -46) or (icmp samesign
ult
+ // -46, -32)`. `X` is allowed to be non-negative here.
+ Pred = static_cast(Pred);
auto CmpXZ = IsCondKnownTrue(simplifyICmpInst(Pred, X, Z, Q));
auto CmpYZ = IsCondKnownTrue(simplifyICmpInst(Pred, Y, Z, Q));
if (!CmpXZ.has_value() && !CmpYZ.has_value())
diff --git a/llvm/test/Transforms/InstCombine/umax-icmp.ll
b/llvm/test/Transforms/InstCombine/umax-icmp.ll
index b4eea30bfc6af..0c42d26750e4b 100644
--- a/llvm/test/Transforms/InstCombine/umax-icmp.ll
+++ b/llvm/test/Transforms/InstCombine/umax-icmp.ll
@@ -804,4 +804,28 @@ end:
ret void
}
+define i1 @pr126974(i8 %x) {
+; CHECK-LABEL: @pr126974(
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[COND:%.*]] = icmp sgt i8 [[X:%.*]], -2
+; CHECK-NEXT:br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:[[CMP:%.*]] = icmp ne i8 [[X]], -1
+; CHECK-NEXT:ret i1 [[CMP]]
+; CHECK: if.else:
+; CHECK-NEXT:ret i1 false
+;
+entry:
+ %cond = icmp sgt i8 %x, -2
+ br i1 %cond, label %if.then, label %if.else
+
+if.then:
+ %umax = call i8 @llvm.umax.i8(i8 %x, i8 -46)
+ %cmp = icmp samesign ult i8 %umax, -32
+ ret i1 %cmp
+
+if.else:
+ ret i1 false
+}
+
declare i32 @llvm.umax.i32(i32, i32)
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[llvm-branch-commits] [llvm] release/20.x: [InstCombine] Do not keep samesign when speculatively executing icmps (#127007) (PR #127391)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: None (llvmbot)
Changes
Backport 29f3a352068ce562bcb65e18a676c82a9991583c
Requested by: @dtcxzyw
---
Full diff: https://github.com/llvm/llvm-project/pull/127391.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp (+5)
- (modified) llvm/test/Transforms/InstCombine/umax-icmp.ll (+24)
``diff
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index b64ac20ab0533..810ce7d382ae1 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -5609,6 +5609,11 @@ Instruction
*InstCombinerImpl::foldICmpWithMinMax(Instruction &I,
return false;
return std::nullopt;
};
+ // Remove samesign here since it is illegal to keep it when we speculatively
+ // execute comparisons. For example, `icmp samesign ult umax(X, -46), -32`
+ // cannot be decomposed into `(icmp samesign ult X, -46) or (icmp samesign
ult
+ // -46, -32)`. `X` is allowed to be non-negative here.
+ Pred = static_cast(Pred);
auto CmpXZ = IsCondKnownTrue(simplifyICmpInst(Pred, X, Z, Q));
auto CmpYZ = IsCondKnownTrue(simplifyICmpInst(Pred, Y, Z, Q));
if (!CmpXZ.has_value() && !CmpYZ.has_value())
diff --git a/llvm/test/Transforms/InstCombine/umax-icmp.ll
b/llvm/test/Transforms/InstCombine/umax-icmp.ll
index b4eea30bfc6af..0c42d26750e4b 100644
--- a/llvm/test/Transforms/InstCombine/umax-icmp.ll
+++ b/llvm/test/Transforms/InstCombine/umax-icmp.ll
@@ -804,4 +804,28 @@ end:
ret void
}
+define i1 @pr126974(i8 %x) {
+; CHECK-LABEL: @pr126974(
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[COND:%.*]] = icmp sgt i8 [[X:%.*]], -2
+; CHECK-NEXT:br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:[[CMP:%.*]] = icmp ne i8 [[X]], -1
+; CHECK-NEXT:ret i1 [[CMP]]
+; CHECK: if.else:
+; CHECK-NEXT:ret i1 false
+;
+entry:
+ %cond = icmp sgt i8 %x, -2
+ br i1 %cond, label %if.then, label %if.else
+
+if.then:
+ %umax = call i8 @llvm.umax.i8(i8 %x, i8 -46)
+ %cmp = icmp samesign ult i8 %umax, -32
+ ret i1 %cmp
+
+if.else:
+ ret i1 false
+}
+
declare i32 @llvm.umax.i32(i32, i32)
``
https://github.com/llvm/llvm-project/pull/127391
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[llvm-branch-commits] [llvm] release/20.x: [InstCombine] Do not keep samesign when speculatively executing icmps (#127007) (PR #127391)
llvmbot wrote: @nikic What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/127391 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [InstCombine] Do not keep samesign when speculatively executing icmps (#127007) (PR #127391)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/127391 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Switch to MF.estimateFunctionSizeInBytes() (PR #127246)
@@ -8978,7 +8978,7 @@ unsigned SIInstrInfo::getInstSizeInBytes(const
MachineInstr &MI) const {
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo(), &ST);
}
default:
-if (MI.isMetaInstruction())
+if (MI.isMetaInstruction() || MI.isDebugInstr())
arsenm wrote:
I'd expect DescSize to be correct for debug insts
https://github.com/llvm/llvm-project/pull/127246
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[llvm-branch-commits] [llvm] [AMDGPU] Switch to MF.estimateFunctionSizeInBytes() (PR #127246)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/127246 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Early bail in getFunctionCodeSize for meta inst. NFC. (PR #127129)
@@ -216,7 +216,7 @@ uint64_t SIProgramInfo::getFunctionCodeSize(const
MachineFunction &MF) {
// TODO: CodeSize should account for multiple functions.
// TODO: Should we count size of debug info?
- if (MI.isDebugInstr())
+ if (MI.isDebugInstr() || MI.isMetaInstruction())
arsenm wrote:
You can remove the isDebugInstr check, the debug pseudos are also marked
isMetaInstruction
https://github.com/llvm/llvm-project/pull/127129
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[llvm-branch-commits] [llvm] [AMDGPU] Respect MBB alignment in the getFunctionCodeSize() (PR #127142)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/127142 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [InstCombine] Do not keep samesign when speculatively executing icmps (#127007) (PR #127391)
https://github.com/nikic approved this pull request. https://github.com/llvm/llvm-project/pull/127391 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] release/20.x: [libc++] Fixes (|multi)_set spaceship operator. (#127326) (PR #127342)
https://github.com/frederick-vs-ja requested changes to this pull request. Let's just backport this fix! https://github.com/llvm/llvm-project/pull/127342 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] release/20.x: [libc++] Fixes (|multi)_set spaceship operator. (#127326) (PR #127342)
https://github.com/frederick-vs-ja approved this pull request. Let's just backport this fix! https://github.com/llvm/llvm-project/pull/127342 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
