[llvm-branch-commits] [llvm] NFC: Move RegAlloc headers to include dir (PR #119672)
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/119672
None
>From 9550da61fb4fea0f231f4e70142c74f3a873b890 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 12 Dec 2024 04:46:50 +
Subject: [PATCH] NFC: Move RegAlloc headers to include dir
---
.../llvm}/CodeGen/InterferenceCache.h | 22 +
.../llvm}/CodeGen/RegAllocBase.h | 2 +-
llvm/{lib => include/llvm}/CodeGen/SplitKit.h | 24 +--
llvm/lib/CodeGen/InlineSpiller.cpp| 2 +-
llvm/lib/CodeGen/InterferenceCache.cpp| 2 +-
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 2 +-
.../lib/CodeGen/MLRegAllocPriorityAdvisor.cpp | 2 +-
llvm/lib/CodeGen/RegAllocBase.cpp | 2 +-
llvm/lib/CodeGen/RegAllocBasic.cpp| 2 +-
llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 8 +++
llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp | 2 +-
llvm/lib/CodeGen/SplitKit.cpp | 2 +-
13 files changed, 32 insertions(+), 42 deletions(-)
rename llvm/{lib => include/llvm}/CodeGen/InterferenceCache.h (95%)
rename llvm/{lib => include/llvm}/CodeGen/RegAllocBase.h (99%)
rename llvm/{lib => include/llvm}/CodeGen/SplitKit.h (97%)
diff --git a/llvm/lib/CodeGen/InterferenceCache.h
b/llvm/include/llvm/CodeGen/InterferenceCache.h
similarity index 95%
rename from llvm/lib/CodeGen/InterferenceCache.h
rename to llvm/include/llvm/CodeGen/InterferenceCache.h
index 2a176b4f2cf7b1..dfe82916224913 100644
--- a/llvm/lib/CodeGen/InterferenceCache.h
+++ b/llvm/include/llvm/CodeGen/InterferenceCache.h
@@ -142,7 +142,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
// Point to an entry for each physreg. The entry pointed to may not be up to
// date, and it may have been reused for a different physreg.
- unsigned char* PhysRegEntries = nullptr;
+ unsigned char *PhysRegEntries = nullptr;
size_t PhysRegEntriesCount = 0;
// Next round-robin entry to be picked.
@@ -158,9 +158,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
InterferenceCache() = default;
InterferenceCache &operator=(const InterferenceCache &other) = delete;
InterferenceCache(const InterferenceCache &other) = delete;
- ~InterferenceCache() {
-free(PhysRegEntries);
- }
+ ~InterferenceCache() { free(PhysRegEntries); }
void reinitPhysRegEntries();
@@ -194,9 +192,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
/// Cursor - Create a dangling cursor.
Cursor() = default;
-Cursor(const Cursor &O) {
- setEntry(O.CacheEntry);
-}
+Cursor(const Cursor &O) { setEntry(O.CacheEntry); }
Cursor &operator=(const Cursor &O) {
setEntry(O.CacheEntry);
@@ -220,21 +216,15 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
}
/// hasInterference - Return true if the current block has any
interference.
-bool hasInterference() {
- return Current->First.isValid();
-}
+bool hasInterference() { return Current->First.isValid(); }
/// first - Return the starting index of the first interfering range in the
/// current block.
-SlotIndex first() {
- return Current->First;
-}
+SlotIndex first() { return Current->First; }
/// last - Return the ending index of the last interfering range in the
/// current block.
-SlotIndex last() {
- return Current->Last;
-}
+SlotIndex last() { return Current->Last; }
};
};
diff --git a/llvm/lib/CodeGen/RegAllocBase.h
b/llvm/include/llvm/CodeGen/RegAllocBase.h
similarity index 99%
rename from llvm/lib/CodeGen/RegAllocBase.h
rename to llvm/include/llvm/CodeGen/RegAllocBase.h
index a1ede08a15356d..4adfdcd866f892 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/include/llvm/CodeGen/RegAllocBase.h
@@ -48,7 +48,7 @@ class LiveIntervals;
class LiveRegMatrix;
class MachineInstr;
class MachineRegisterInfo;
-template class SmallVectorImpl;
+template class SmallVectorImpl;
class Spiller;
class TargetRegisterInfo;
class VirtRegMap;
diff --git a/llvm/lib/CodeGen/SplitKit.h b/llvm/include/llvm/CodeGen/SplitKit.h
similarity index 97%
rename from llvm/lib/CodeGen/SplitKit.h
rename to llvm/include/llvm/CodeGen/SplitKit.h
index cc277ecc0e882b..50b63b9aa2a858 100644
--- a/llvm/lib/CodeGen/SplitKit.h
+++ b/llvm/include/llvm/CodeGen/SplitKit.h
@@ -88,7 +88,6 @@ class LLVM_LIBRARY_VISIBILITY InsertPointAnalysis {
}
return Res;
}
-
};
/// SplitAnalysis - Analyze a LiveInterval, looking for live range splitting
@@ -387,7 +386,7 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
/// removeBackCopies - Remove the copy instructions that defines the values
/// in the vector in the complement interval.
- void removeBackCopies(SmallVectorImpl &Copies);
+ void removeBackCopies(SmallVectorImpl &Copies);
/// getShallowDominator - Returns the least busy dominator of MBB that is
/// also dominated by DefMBB. Busy is measu
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)
https://github.com/optimisan edited https://github.com/llvm/llvm-project/pull/119540 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] NFC: Move RegAlloc headers to include dir (PR #119672)
optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/119672?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#119540** https://app.graphite.dev/github/pr/llvm/llvm-project/119540?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119672** https://app.graphite.dev/github/pr/llvm/llvm-project/119672?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/119672?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#119181** https://app.graphite.dev/github/pr/llvm/llvm-project/119181?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#118462** https://app.graphite.dev/github/pr/llvm/llvm-project/118462?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#117309** https://app.graphite.dev/github/pr/llvm/llvm-project/117309?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/119672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From 9550da61fb4fea0f231f4e70142c74f3a873b890 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 12 Dec 2024 04:46:50 +
Subject: [PATCH 1/2] NFC: Move RegAlloc headers to include dir
---
.../llvm}/CodeGen/InterferenceCache.h | 22 +
.../llvm}/CodeGen/RegAllocBase.h | 2 +-
llvm/{lib => include/llvm}/CodeGen/SplitKit.h | 24 +--
llvm/lib/CodeGen/InlineSpiller.cpp| 2 +-
llvm/lib/CodeGen/InterferenceCache.cpp| 2 +-
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 2 +-
.../lib/CodeGen/MLRegAllocPriorityAdvisor.cpp | 2 +-
llvm/lib/CodeGen/RegAllocBase.cpp | 2 +-
llvm/lib/CodeGen/RegAllocBasic.cpp| 2 +-
llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 8 +++
llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp | 2 +-
llvm/lib/CodeGen/SplitKit.cpp | 2 +-
13 files changed, 32 insertions(+), 42 deletions(-)
rename llvm/{lib => include/llvm}/CodeGen/InterferenceCache.h (95%)
rename llvm/{lib => include/llvm}/CodeGen/RegAllocBase.h (99%)
rename llvm/{lib => include/llvm}/CodeGen/SplitKit.h (97%)
diff --git a/llvm/lib/CodeGen/InterferenceCache.h
b/llvm/include/llvm/CodeGen/InterferenceCache.h
similarity index 95%
rename from llvm/lib/CodeGen/InterferenceCache.h
rename to llvm/include/llvm/CodeGen/InterferenceCache.h
index 2a176b4f2cf7b1..dfe82916224913 100644
--- a/llvm/lib/CodeGen/InterferenceCache.h
+++ b/llvm/include/llvm/CodeGen/InterferenceCache.h
@@ -142,7 +142,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
// Point to an entry for each physreg. The entry pointed to may not be up to
// date, and it may have been reused for a different physreg.
- unsigned char* PhysRegEntries = nullptr;
+ unsigned char *PhysRegEntries = nullptr;
size_t PhysRegEntriesCount = 0;
// Next round-robin entry to be picked.
@@ -158,9 +158,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
InterferenceCache() = default;
InterferenceCache &operator=(const InterferenceCache &other) = delete;
InterferenceCache(const InterferenceCache &other) = delete;
- ~InterferenceCache() {
-free(PhysRegEntries);
- }
+ ~InterferenceCache() { free(PhysRegEntries); }
void reinitPhysRegEntries();
@@ -194,9 +192,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
/// Cursor - Create a dangling cursor.
Cursor() = default;
-Cursor(const Cursor &O) {
- setEntry(O.CacheEntry);
-}
+Cursor(const Cursor &O) { setEntry(O.CacheEntry); }
Cursor &operator=(const Cursor &O) {
setEntry(O.CacheEntry);
@@ -220,21 +216,15 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
}
/// hasInterference - Return true if the current block has any
interference.
-bool hasInterference() {
- return Current->First.isValid();
-}
+bool hasInterference() { return Current->First.isValid(); }
/// first - Return the starting index of the first interfering range in the
/// current block.
-SlotIndex first() {
- return Current->First;
-}
+SlotIndex first() { return Current->First; }
/// last - Return the ending index of the last interfering range in the
/// current block.
-SlotIndex last() {
- return Current->Last;
-}
+SlotIndex last() { return Current->Last; }
};
};
diff --git a/llvm/lib/CodeGen/RegAllocBase.h
b/llvm/include/llvm/CodeGen/RegAllocBase.h
similarity index 99%
rename from llvm/lib/CodeGen/RegAllocBase.h
rename to llvm/include/llvm/CodeGen/RegAllocBase.h
index a1ede08a15356d..4adfdcd866f892 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/include/llvm/CodeGen/RegAllocBase.h
@@ -48,7 +48,7 @@ class LiveIntervals;
class LiveRegMatrix;
class MachineInstr;
class MachineRegisterInfo;
-template class SmallVectorImpl;
+template class SmallVectorImpl;
class Spiller;
class TargetRegisterInfo;
class VirtRegMap;
diff --git a/llvm/lib/CodeGen/SplitKit.h b/llvm/include/llvm/CodeGen/SplitKit.h
similarity index 97%
rename from llvm/lib/CodeGen/SplitKit.h
rename to llvm/include/llvm/CodeGen/SplitKit.h
index cc277ecc0e882b..50b63b9aa2a858 100644
--- a/llvm/lib/CodeGen/SplitKit.h
+++ b/llvm/include/llvm/CodeGen/SplitKit.h
@@ -88,7 +88,6 @@ class LLVM_LIBRARY_VISIBILITY InsertPointAnalysis {
}
return Res;
}
-
};
/// SplitAnalysis - Analyze a LiveInterval, looking for live range splitting
@@ -387,7 +386,7 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
/// removeBackCopies - Remove the copy instructions that defines the values
/// in the vector in the complement interval.
- void removeBackCopies(SmallVectorImpl &Copies);
+ void removeBackCopies(SmallVectorImpl &Copies);
/// getShallowDominator - Returns the least busy dominator of MBB that is
/// also dominated by DefMBB. Busy is measure
[llvm-branch-commits] [llvm] NFC: Move RegAlloc headers to include dir (PR #119672)
llvmbot wrote:
@llvm/pr-subscribers-llvm-regalloc
@llvm/pr-subscribers-mlgo
Author: Akshat Oke (optimisan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/119672.diff
13 Files Affected:
- (renamed) llvm/include/llvm/CodeGen/InterferenceCache.h (+6-16)
- (renamed) llvm/include/llvm/CodeGen/RegAllocBase.h (+1-1)
- (renamed) llvm/include/llvm/CodeGen/SplitKit.h (+12-12)
- (modified) llvm/lib/CodeGen/InlineSpiller.cpp (+1-1)
- (modified) llvm/lib/CodeGen/InterferenceCache.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp (+1-1)
- (modified) llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp (+1-1)
- (modified) llvm/lib/CodeGen/RegAllocBase.cpp (+1-1)
- (modified) llvm/lib/CodeGen/RegAllocBasic.cpp (+1-1)
- (modified) llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp (+1-1)
- (modified) llvm/lib/CodeGen/RegAllocGreedy.cpp (+4-4)
- (modified) llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp (+1-1)
- (modified) llvm/lib/CodeGen/SplitKit.cpp (+1-1)
``diff
diff --git a/llvm/lib/CodeGen/InterferenceCache.h
b/llvm/include/llvm/CodeGen/InterferenceCache.h
similarity index 95%
rename from llvm/lib/CodeGen/InterferenceCache.h
rename to llvm/include/llvm/CodeGen/InterferenceCache.h
index 2a176b4f2cf7b1..dfe82916224913 100644
--- a/llvm/lib/CodeGen/InterferenceCache.h
+++ b/llvm/include/llvm/CodeGen/InterferenceCache.h
@@ -142,7 +142,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
// Point to an entry for each physreg. The entry pointed to may not be up to
// date, and it may have been reused for a different physreg.
- unsigned char* PhysRegEntries = nullptr;
+ unsigned char *PhysRegEntries = nullptr;
size_t PhysRegEntriesCount = 0;
// Next round-robin entry to be picked.
@@ -158,9 +158,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
InterferenceCache() = default;
InterferenceCache &operator=(const InterferenceCache &other) = delete;
InterferenceCache(const InterferenceCache &other) = delete;
- ~InterferenceCache() {
-free(PhysRegEntries);
- }
+ ~InterferenceCache() { free(PhysRegEntries); }
void reinitPhysRegEntries();
@@ -194,9 +192,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
/// Cursor - Create a dangling cursor.
Cursor() = default;
-Cursor(const Cursor &O) {
- setEntry(O.CacheEntry);
-}
+Cursor(const Cursor &O) { setEntry(O.CacheEntry); }
Cursor &operator=(const Cursor &O) {
setEntry(O.CacheEntry);
@@ -220,21 +216,15 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
}
/// hasInterference - Return true if the current block has any
interference.
-bool hasInterference() {
- return Current->First.isValid();
-}
+bool hasInterference() { return Current->First.isValid(); }
/// first - Return the starting index of the first interfering range in the
/// current block.
-SlotIndex first() {
- return Current->First;
-}
+SlotIndex first() { return Current->First; }
/// last - Return the ending index of the last interfering range in the
/// current block.
-SlotIndex last() {
- return Current->Last;
-}
+SlotIndex last() { return Current->Last; }
};
};
diff --git a/llvm/lib/CodeGen/RegAllocBase.h
b/llvm/include/llvm/CodeGen/RegAllocBase.h
similarity index 99%
rename from llvm/lib/CodeGen/RegAllocBase.h
rename to llvm/include/llvm/CodeGen/RegAllocBase.h
index a1ede08a15356d..4adfdcd866f892 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/include/llvm/CodeGen/RegAllocBase.h
@@ -48,7 +48,7 @@ class LiveIntervals;
class LiveRegMatrix;
class MachineInstr;
class MachineRegisterInfo;
-template class SmallVectorImpl;
+template class SmallVectorImpl;
class Spiller;
class TargetRegisterInfo;
class VirtRegMap;
diff --git a/llvm/lib/CodeGen/SplitKit.h b/llvm/include/llvm/CodeGen/SplitKit.h
similarity index 97%
rename from llvm/lib/CodeGen/SplitKit.h
rename to llvm/include/llvm/CodeGen/SplitKit.h
index cc277ecc0e882b..50b63b9aa2a858 100644
--- a/llvm/lib/CodeGen/SplitKit.h
+++ b/llvm/include/llvm/CodeGen/SplitKit.h
@@ -88,7 +88,6 @@ class LLVM_LIBRARY_VISIBILITY InsertPointAnalysis {
}
return Res;
}
-
};
/// SplitAnalysis - Analyze a LiveInterval, looking for live range splitting
@@ -387,7 +386,7 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
/// removeBackCopies - Remove the copy instructions that defines the values
/// in the vector in the complement interval.
- void removeBackCopies(SmallVectorImpl &Copies);
+ void removeBackCopies(SmallVectorImpl &Copies);
/// getShallowDominator - Returns the least busy dominator of MBB that is
/// also dominated by DefMBB. Busy is measured by loop depth.
@@ -430,8 +429,9 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
/// \p InsertBefore. This can be invoked with a \p LaneMask which may make it
/// necessary to construct a sequence of copies to cover it exactly.
SlotIndex buildCopy(Regist
[llvm-branch-commits] [llvm] NFC: Move RegAlloc headers to include dir (PR #119672)
https://github.com/optimisan ready_for_review https://github.com/llvm/llvm-project/pull/119672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] NFC: Move RegAlloc headers to include dir (PR #119672)
@@ -142,7 +142,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
// Point to an entry for each physreg. The entry pointed to may not be up to
// date, and it may have been reused for a different physreg.
- unsigned char* PhysRegEntries = nullptr;
+ unsigned char *PhysRegEntries = nullptr;
arsenm wrote:
Reformat shouldn't be done at same time as the move
https://github.com/llvm/llvm-project/pull/119672
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[llvm-branch-commits] [llvm] NFC: Move RegAlloc headers to include dir (PR #119672)
https://github.com/arsenm commented: Why? These are supposed to be private headers to the regalloc implementation https://github.com/llvm/llvm-project/pull/119672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] NFC: Move RegAlloc headers to include dir (PR #119672)
https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/119672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] NFC: Move RegAlloc headers to include dir (PR #119672)
@@ -142,7 +142,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
// Point to an entry for each physreg. The entry pointed to may not be up to
// date, and it may have been reused for a different physreg.
- unsigned char* PhysRegEntries = nullptr;
+ unsigned char *PhysRegEntries = nullptr;
optimisan wrote:
Yes I can put the new greedy pass in a header instead.
https://github.com/llvm/llvm-project/pull/119672
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[llvm-branch-commits] [llvm] [Statepoint] Treat undef operands less specially (PR #119682)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/119682
This reverts commit f7443905af1e06eaacda1e437fff8d54dc89c487.
This is to avoid an assertion if an undef operand appears in a
stackmap. This is important to avoid hitting verifier errors
when register allocation starts adding undefs in error scenarios.
Rather than trying to treat undef operands as special, leave them
alone and avoid producing an invalid spill. It would a bit more
precise to produce a spill of an undef register here, but that's not
exposed through the storeRegToStackSlot API.
https://reviews.llvm.org/D122605
This was an alternative to https://reviews.llvm.org/D122582
>From 03cca4cf3b65cb6988db7a983f3c3349fa0b390a Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 28 Mar 2022 14:11:28 -0400
Subject: [PATCH] [Statepoint] Treat undef operands less specially
This reverts commit f7443905af1e06eaacda1e437fff8d54dc89c487.
This is to avoid an assertion if an undef operand appears in a
stackmap. This is important to avoid hitting verifier errors
when register allocation starts adding undefs in error scenarios.
Rather than trying to treat undef operands as special, leave them
alone and avoid producing an invalid spill. It would a bit more
precise to produce a spill of an undef register here, but that's not
exposed through the storeRegToStackSlot API.
https://reviews.llvm.org/D122605
This was an alternative to https://reviews.llvm.org/D122582
---
.../CodeGen/FixupStatepointCallerSaved.cpp| 2 -
llvm/lib/CodeGen/StackMaps.cpp| 6 --
.../X86/stackmap-undef-operand-anyregcc.mir | 61 +++
.../CodeGen/X86/statepoint-fixup-undef.mir| 8 +--
4 files changed, 65 insertions(+), 12 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
index 3bb9da5f1a37bb..0ebe845e473fd6 100644
--- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
+++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
@@ -381,8 +381,6 @@ class StatepointState {
EndIdx = MI.getNumOperands();
Idx < EndIdx; ++Idx) {
MachineOperand &MO = MI.getOperand(Idx);
- // Leave `undef` operands as is, StackMaps will rewrite them
- // into a constant.
if (!MO.isReg() || MO.isImplicit() || MO.isUndef())
continue;
Register Reg = MO.getReg();
diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp
index 81b288df3b07e0..7480963c1f5217 100644
--- a/llvm/lib/CodeGen/StackMaps.cpp
+++ b/llvm/lib/CodeGen/StackMaps.cpp
@@ -268,12 +268,6 @@ StackMaps::parseOperand(MachineInstr::const_mop_iterator
MOI,
if (MOI->isImplicit())
return ++MOI;
-if (MOI->isUndef()) {
- // Record `undef` register as constant. Use same value as ISel uses.
- Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, 0xFEFEFEFE);
- return ++MOI;
-}
-
assert(MOI->getReg().isPhysical() &&
"Virtreg operands should have been rewritten before now.");
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());
diff --git a/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
b/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
new file mode 100644
index 00..6a322eb105e6f7
--- /dev/null
+++ b/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
@@ -0,0 +1,61 @@
+# RUN: llc -mtriple=x86_64-apple-darwin -start-after=virtregrewriter -o - %s |
FileCheck %s
+
+# Check there's no assertion for anyregcc with an undef operand to a stackmap.
+
+# CHECK: __LLVM_StackMaps:
+# CHECK-NEXT: .byte3
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long1
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .long1
+# CHECK-NEXT: .quad_undef_anyregcc_patchpoint
+# CHECK-NEXT: .quad8
+# CHECK-NEXT: .quad1
+# CHECK-NEXT: .quad12
+# CHECK-NEXT: .longLtmp0-_undef_anyregcc_patchpoint
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 2
+# CHECK-NEXT: .byte1
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 8
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .byte1
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 8
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .p2align 3
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 2
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 7
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .p2align 3
+---
+name: undef_anyregcc_patchpoint
+tracksRegLiveness: true
+frameInfo:
+ hasPatchPoint: true
+ hasCalls:true
+fixedStack:
+ - { id: 0, type: default, offset: 72, size: 8, alignment: 8, stack-id:
default,
+ isImmutable: true, isAliased: false, callee-saved-register: '',
callee-saved-restore
[llvm-branch-commits] [llvm] [Statepoint] Treat undef operands less specially (PR #119682)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/119682?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#119682** https://app.graphite.dev/github/pr/llvm/llvm-project/119682?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/119682?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#119647** https://app.graphite.dev/github/pr/llvm/llvm-project/119647?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119640** https://app.graphite.dev/github/pr/llvm/llvm-project/119640?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119492** https://app.graphite.dev/github/pr/llvm/llvm-project/119492?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119491** https://app.graphite.dev/github/pr/llvm/llvm-project/119491?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119485** https://app.graphite.dev/github/pr/llvm/llvm-project/119485?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/119682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [Statepoint] Treat undef operands less specially (PR #119682)
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: Matt Arsenault (arsenm)
Changes
This reverts commit f7443905af1e06eaacda1e437fff8d54dc89c487.
This is to avoid an assertion if an undef operand appears in a
stackmap. This is important to avoid hitting verifier errors
when register allocation starts adding undefs in error scenarios.
Rather than trying to treat undef operands as special, leave them
alone and avoid producing an invalid spill. It would a bit more
precise to produce a spill of an undef register here, but that's not
exposed through the storeRegToStackSlot API.
https://reviews.llvm.org/D122605
This was an alternative to https://reviews.llvm.org/D122582
---
Full diff: https://github.com/llvm/llvm-project/pull/119682.diff
4 Files Affected:
- (modified) llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp (-2)
- (modified) llvm/lib/CodeGen/StackMaps.cpp (-6)
- (added) llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir (+61)
- (modified) llvm/test/CodeGen/X86/statepoint-fixup-undef.mir (+4-4)
``diff
diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
index 3bb9da5f1a37bb..0ebe845e473fd6 100644
--- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
+++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
@@ -381,8 +381,6 @@ class StatepointState {
EndIdx = MI.getNumOperands();
Idx < EndIdx; ++Idx) {
MachineOperand &MO = MI.getOperand(Idx);
- // Leave `undef` operands as is, StackMaps will rewrite them
- // into a constant.
if (!MO.isReg() || MO.isImplicit() || MO.isUndef())
continue;
Register Reg = MO.getReg();
diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp
index 81b288df3b07e0..7480963c1f5217 100644
--- a/llvm/lib/CodeGen/StackMaps.cpp
+++ b/llvm/lib/CodeGen/StackMaps.cpp
@@ -268,12 +268,6 @@ StackMaps::parseOperand(MachineInstr::const_mop_iterator
MOI,
if (MOI->isImplicit())
return ++MOI;
-if (MOI->isUndef()) {
- // Record `undef` register as constant. Use same value as ISel uses.
- Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, 0xFEFEFEFE);
- return ++MOI;
-}
-
assert(MOI->getReg().isPhysical() &&
"Virtreg operands should have been rewritten before now.");
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());
diff --git a/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
b/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
new file mode 100644
index 00..6a322eb105e6f7
--- /dev/null
+++ b/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
@@ -0,0 +1,61 @@
+# RUN: llc -mtriple=x86_64-apple-darwin -start-after=virtregrewriter -o - %s |
FileCheck %s
+
+# Check there's no assertion for anyregcc with an undef operand to a stackmap.
+
+# CHECK: __LLVM_StackMaps:
+# CHECK-NEXT: .byte3
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long1
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .long1
+# CHECK-NEXT: .quad_undef_anyregcc_patchpoint
+# CHECK-NEXT: .quad8
+# CHECK-NEXT: .quad1
+# CHECK-NEXT: .quad12
+# CHECK-NEXT: .longLtmp0-_undef_anyregcc_patchpoint
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 2
+# CHECK-NEXT: .byte1
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 8
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .byte1
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 8
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .p2align 3
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 2
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 7
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .p2align 3
+---
+name: undef_anyregcc_patchpoint
+tracksRegLiveness: true
+frameInfo:
+ hasPatchPoint: true
+ hasCalls:true
+fixedStack:
+ - { id: 0, type: default, offset: 72, size: 8, alignment: 8, stack-id:
default,
+ isImmutable: true, isAliased: false, callee-saved-register: '',
callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+body: |
+ bb.0:
+liveins: $rcx, $rdi, $rdx, $rsi, $r8, $r9
+
+ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead
$eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+dead renamable $rax = MOV64rm %fixed-stack.0, 1, $noreg, 0, $noreg ::
(load (s64) from %fixed-stack.0)
+renamable $rax = PATCHPOINT 12, 15, 0, 1, 13, undef renamable $rax,
csr_64_allregs, implicit-def dead early-clobber $r11, implicit-def $rsp,
implicit-def $ssp
+ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags,
implicit-def dead $ssp, implicit $rsp, implicit $ssp
+RET 0, $rax
+
+...
diff --git a/llvm/test/CodeGen/X86/state
[llvm-branch-commits] [clang] [compiler-rt] [TySan] A Type Sanitizer (Runtime Library) (PR #76261)
@@ -0,0 +1,79 @@
+//===-- tysan.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file is a part of TypeSanitizer.
+//
+// Private TySan header.
+//===--===//
+
+#ifndef TYSAN_H
+#define TYSAN_H
+
+#include "sanitizer_common/sanitizer_internal_defs.h"
+
+using __sanitizer::sptr;
+using __sanitizer::u16;
+using __sanitizer::uptr;
+
+#include "tysan_platform.h"
+
+extern "C" {
+void tysan_set_type_unknown(const void *addr, uptr size);
+void tysan_copy_types(const void *daddr, const void *saddr, uptr size);
+}
+
+namespace __tysan {
+extern bool tysan_inited;
+extern bool tysan_init_is_running;
+
+void InitializeInterceptors();
+
+enum { TYSAN_MEMBER_TD = 1, TYSAN_STRUCT_TD = 2 };
+
+struct tysan_member_type_descriptor {
+ struct tysan_type_descriptor *Base;
+ struct tysan_type_descriptor *Access;
+ uptr Offset;
+};
+
+struct tysan_struct_type_descriptor {
+ uptr MemberCount;
+ struct {
+struct tysan_type_descriptor *Type;
+uptr Offset;
+ } Members[1]; // Tail allocated.
+ // char Name[]; // Tail allocated.
fhahn wrote:
Dropped, thanks!
https://github.com/llvm/llvm-project/pull/76261
___
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[llvm-branch-commits] [llvm] [Statepoint] Treat undef operands less specially (PR #119682)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/119682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb][Process] Introduce LoongArch64 hw break/watchpoint support (PR #118770)
DavidSpickett wrote: Linux Arm and AArch64, Windows on Arm and x86 bots are fine with the refactoring PR before this. If you haven't had any complaints from the Apple bots (it's native code, so I'd hope not), then this can land. Thanks for putting in the work on the refactoring! https://github.com/llvm/llvm-project/pull/118770 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/119684
AMDGPU: Delete spills of undef values
It would be a bit more logical to preserve the undef and do the normal
expansion, but this is less work. This avoids verifier errors in a
future patch which starts deleting liveness from registers after
allocation failures which results in spills of undef values.
https://reviews.llvm.org/D122607
Move where undef sgpr spills are deleted
>From ea9cd242330d6938eb3097192cc6e723b43c01fa Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 28 Mar 2022 11:24:48 -0400
Subject: [PATCH 1/2] AMDGPU: Delete spills of undef values
It would be a bit more logical to preserve the undef and do the normal
expansion, but this is less work. This avoids verifier errors in a
future patch which starts deleting liveness from registers after
allocation failures which results in spills of undef values.
https://reviews.llvm.org/D122607
---
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 12 ++
.../AMDGPU/sgpr-spill-partially-undef.mir | 42 +++
.../AMDGPU/spill-agpr-partially-undef.mir | 34 +++
llvm/test/CodeGen/AMDGPU/vgpr-spill.mir | 34 +++
4 files changed, 122 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 296c32fa4e0d09..4f8c5c6756b3bb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1954,6 +1954,13 @@ bool
SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
RegScavenger *RS, SlotIndexes *Indexes,
LiveIntervals *LIS, bool OnlyToVGPR,
bool SpillToPhysVGPRLane) const {
+ if (MI->getOperand(0).isUndef()) {
+if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*MI);
+MI->eraseFromParent();
+return true;
+ }
+
SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS);
ArrayRef VGPRSpills =
@@ -2375,6 +2382,11 @@ bool
SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
case AMDGPU::SI_SPILL_WWM_AV32_SAVE: {
const MachineOperand *VData = TII->getNamedOperand(*MI,
AMDGPU::OpName::vdata);
+ if (VData->isUndef()) {
+MI->eraseFromParent();
+return true;
+ }
+
assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
MFI->getStackPtrOffsetReg());
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
b/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
index 774785fb3966fc..d352e8a13da9f1 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
@@ -54,3 +54,45 @@ body: |
SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec,
implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into
%stack.0, align 4, addrspace 5)
...
+
+---
+name: sgpr_spill_s32_undef
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+ hasSpilledSGPRs: true
+ scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
+ stackPtrOffsetReg: '$sgpr32'
+stack:
+ - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
+body: |
+ bb.0:
+; CHECK-LABEL: name: sgpr_spill_s32_undef
+; CHECK: body:
+; CHECK-NEXT: bb.0:
+; CHECK-NOT: {{.+}}
+; CHECK: ...
+SI_SPILL_S32_SAVE undef $sgpr8, %stack.0, implicit $exec, implicit
$sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s32) into %stack.0,
align 4, addrspace 5)
+
+...
+
+---
+name: sgpr_spill_s64_undef
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+ hasSpilledSGPRs: true
+ scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
+ stackPtrOffsetReg: '$sgpr32'
+stack:
+ - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
+body: |
+ bb.0:
+; CHECK-LABEL: name: sgpr_spill_s64_undef
+; CHECK: body:
+; CHECK-NEXT: bb.0:
+; CHECK-NOT: {{.+}}
+; CHECK: ...
+SI_SPILL_S64_SAVE undef $sgpr8_sgpr9, %stack.0, implicit $exec, implicit
$sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into %stack.0,
align 4, addrspace 5)
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
index c825674de7652c..b02b6e79d7a76f 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
@@ -71,3 +71,37 @@ body: |
; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0,
$sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed
$agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5)
SI_SPILL_A64_SAVE killed $agpr0_agpr1, %stack.0
[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/119684?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#119684** https://app.graphite.dev/github/pr/llvm/llvm-project/119684?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/119684?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#119647** https://app.graphite.dev/github/pr/llvm/llvm-project/119647?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>: 1 other dependent PR ([#119682](https://github.com/llvm/llvm-project/pull/119682) https://app.graphite.dev/github/pr/llvm/llvm-project/119682?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>) * **#119640** https://app.graphite.dev/github/pr/llvm/llvm-project/119640?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119492** https://app.graphite.dev/github/pr/llvm/llvm-project/119492?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119491** https://app.graphite.dev/github/pr/llvm/llvm-project/119491?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119485** https://app.graphite.dev/github/pr/llvm/llvm-project/119485?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/119684 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/119684 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
AMDGPU: Delete spills of undef values
It would be a bit more logical to preserve the undef and do the normal
expansion, but this is less work. This avoids verifier errors in a
future patch which starts deleting liveness from registers after
allocation failures which results in spills of undef values.
https://reviews.llvm.org/D122607
Move where undef sgpr spills are deleted
---
Full diff: https://github.com/llvm/llvm-project/pull/119684.diff
5 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp (+7)
- (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp (+8)
- (modified) llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir (+42)
- (modified) llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir (+34)
- (modified) llvm/test/CodeGen/AMDGPU/vgpr-spill.mir (+34)
``diff
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index f868843318ff6c..d27c523425feb2 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -422,6 +422,13 @@ bool SILowerSGPRSpills::run(MachineFunction &MF) {
if (!TII->isSGPRSpill(MI))
continue;
+if (MI.getOperand(0).isUndef()) {
+ if (Indexes)
+Indexes->removeMachineInstrFromMaps(MI);
+ MI.eraseFromParent();
+ continue;
+}
+
int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill);
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 296c32fa4e0d09..8a23cf5e214967 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1954,6 +1954,9 @@ bool
SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
RegScavenger *RS, SlotIndexes *Indexes,
LiveIntervals *LIS, bool OnlyToVGPR,
bool SpillToPhysVGPRLane) const {
+ assert(!MI->getOperand(0).isUndef() &&
+ "undef spill should have been deleted earlier");
+
SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS);
ArrayRef VGPRSpills =
@@ -2375,6 +2378,11 @@ bool
SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
case AMDGPU::SI_SPILL_WWM_AV32_SAVE: {
const MachineOperand *VData = TII->getNamedOperand(*MI,
AMDGPU::OpName::vdata);
+ if (VData->isUndef()) {
+MI->eraseFromParent();
+return true;
+ }
+
assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
MFI->getStackPtrOffsetReg());
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
b/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
index 774785fb3966fc..d352e8a13da9f1 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
@@ -54,3 +54,45 @@ body: |
SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec,
implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into
%stack.0, align 4, addrspace 5)
...
+
+---
+name: sgpr_spill_s32_undef
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+ hasSpilledSGPRs: true
+ scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
+ stackPtrOffsetReg: '$sgpr32'
+stack:
+ - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
+body: |
+ bb.0:
+; CHECK-LABEL: name: sgpr_spill_s32_undef
+; CHECK: body:
+; CHECK-NEXT: bb.0:
+; CHECK-NOT: {{.+}}
+; CHECK: ...
+SI_SPILL_S32_SAVE undef $sgpr8, %stack.0, implicit $exec, implicit
$sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s32) into %stack.0,
align 4, addrspace 5)
+
+...
+
+---
+name: sgpr_spill_s64_undef
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+ hasSpilledSGPRs: true
+ scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
+ stackPtrOffsetReg: '$sgpr32'
+stack:
+ - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
+body: |
+ bb.0:
+; CHECK-LABEL: name: sgpr_spill_s64_undef
+; CHECK: body:
+; CHECK-NEXT: bb.0:
+; CHECK-NOT: {{.+}}
+; CHECK: ...
+SI_SPILL_S64_SAVE undef $sgpr8_sgpr9, %stack.0, implicit $exec, implicit
$sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into %stack.0,
align 4, addrspace 5)
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
index c825674de7652c..b02b6e79d7a76f 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/s
[llvm-branch-commits] [clang] [compiler-rt] [TySan] A Type Sanitizer (Runtime Library) (PR #76261)
fhahn wrote: The Clang and LLVM parts are now ready to land, with just the compiler-rt bits pending approval. There are a few test failures on Linux which don't fail on macOS, will look at them today probably https://github.com/llvm/llvm-project/pull/76261 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RegAlloc: Fix verifier error after failed allocation (PR #119690)
github-actions[bot] wrote:
:warning: undef deprecator found issues in your code. :warning:
You can test this locally with the following command:
``bash
git diff -U0 --pickaxe-regex -S
'([^a-zA-Z0-9#_-]undef[^a-zA-Z0-9_-]|UndefValue::get)'
2bd0046adb0bdc1b7ae32ba653df59913fe72612
bca529ad0b6fabe5825c3ed305b389d489f7e2c9
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
llvm/lib/CodeGen/RegAllocBase.cpp llvm/lib/CodeGen/RegAllocBase.h
llvm/lib/CodeGen/RegAllocBasic.cpp llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
``
The following files introduce new uses of undef:
- llvm/lib/CodeGen/RegAllocBase.cpp
- llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
[Undef](https://llvm.org/docs/LangRef.html#undefined-values) is now deprecated
and should only be used in the rare cases where no replacement is possible. For
example, a load of uninitialized memory yields `undef`. You should use `poison`
values for placeholders instead.
In tests, avoid using `undef` and having tests that trigger undefined behavior.
If you need an operand with some unimportant value, you can add a new argument
to the function and use that instead.
For example, this is considered a bad practice:
```llvm
define void @fn() {
...
br i1 undef, ...
}
```
Please use the following instead:
```llvm
define void @fn(i1 %cond) {
...
br i1 %cond, ...
}
```
Please refer to the [Undefined Behavior
Manual](https://llvm.org/docs/UndefinedBehavior.html) for more information.
https://github.com/llvm/llvm-project/pull/119690
___
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[llvm-branch-commits] [llvm] NFC: Move RegAlloc headers to include dir (PR #119672)
https://github.com/optimisan closed https://github.com/llvm/llvm-project/pull/119672 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Extend CallSiteInfo with TypeId (PR #87574)
@@ -0,0 +1,68 @@
+# Test MIR printer and parser for type id field in callSites. It is used
+# for propogating call site type identifiers to emit in the call graph section.
+
+# RUN: llc --call-graph-section %s -run-pass=none -o - | FileCheck %s
+# CHECK: name: main
+# CHECK: callSites:
+# CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [], typeId:
+# CHECK-NEXT: 123456789 }
+
+--- |
+ ; ModuleID = 'test.ll'
+ source_filename = "test.ll"
+ target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+ target triple = "x86_64-unknown-linux-gnu"
arsenm wrote:
Don't need this
https://github.com/llvm/llvm-project/pull/87574
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[llvm-branch-commits] [llvm] Extend CallSiteInfo with TypeId (PR #87574)
@@ -0,0 +1,68 @@
+# Test MIR printer and parser for type id field in callSites. It is used
+# for propogating call site type identifiers to emit in the call graph section.
+
+# RUN: llc --call-graph-section %s -run-pass=none -o - | FileCheck %s
+# CHECK: name: main
+# CHECK: callSites:
+# CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [], typeId:
+# CHECK-NEXT: 123456789 }
+
+--- |
+ ; ModuleID = 'test.ll'
+ source_filename = "test.ll"
+ target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+ target triple = "x86_64-unknown-linux-gnu"
+
+ define dso_local void @foo(i8 signext %a) {
+ entry:
+ret void
+ }
+
+ define dso_local i32 @main() {
+ entry:
+%retval = alloca i32, align 4
+%fp = alloca void (i8)*, align 8
+store i32 0, i32* %retval, align 4
+store void (i8)* @foo, void (i8)** %fp, align 8
arsenm wrote:
Needs to use opaque pointers
https://github.com/llvm/llvm-project/pull/87574
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[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
github-actions[bot] wrote:
:warning: undef deprecator found issues in your code. :warning:
You can test this locally with the following command:
``bash
git diff -U0 --pickaxe-regex -S
'([^a-zA-Z0-9#_-]undef[^a-zA-Z0-9_-]|UndefValue::get)'
21a94e80ec529fac5a23febcdf738f01c56d0100
8a05688cca3e32da6e2fe32e847818659881275b
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
``
The following files introduce new uses of undef:
- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
[Undef](https://llvm.org/docs/LangRef.html#undefined-values) is now deprecated
and should only be used in the rare cases where no replacement is possible. For
example, a load of uninitialized memory yields `undef`. You should use `poison`
values for placeholders instead.
In tests, avoid using `undef` and having tests that trigger undefined behavior.
If you need an operand with some unimportant value, you can add a new argument
to the function and use that instead.
For example, this is considered a bad practice:
```llvm
define void @fn() {
...
br i1 undef, ...
}
```
Please use the following instead:
```llvm
define void @fn(i1 %cond) {
...
br i1 %cond, ...
}
```
Please refer to the [Undefined Behavior
Manual](https://llvm.org/docs/UndefinedBehavior.html) for more information.
https://github.com/llvm/llvm-project/pull/119684
___
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[llvm-branch-commits] [llvm] RegAlloc: Fix verifier error after failed allocation (PR #119690)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/119690
In some cases after reporting an allocation failure, this would fail
the verifier. It picks the first allocatable register and assigns it,
but didn't update the liveness appropriately. When VirtRegRewriter
relied on the liveness to set kill flags, it would incorrectly add
kill flags if there was another overlapping kill of the virtual
register.
We can't properly assign the register to an overlapping range, so
break the liveness of the failing register (and any other interfering
registers) instead. Give the virtual register dummy liveness by
effectively deleting all the uses by setting them to undef.
The edge case not tested here which I'm worried about is if the read
of the register is a def of a subregister. I've been unable to come up
with a test where this occurs.
https://reviews.llvm.org/D122616
>From 5c46398f907ca23c93a06d59c99863697271f3c4 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 25 Mar 2022 20:27:39 -0400
Subject: [PATCH] RegAlloc: Fix verifier error after failed allocation
In some cases after reporting an allocation failure, this would fail
the verifier. It picks the first allocatable register and assigns it,
but didn't update the liveness appropriately. When VirtRegRewriter
relied on the liveness to set kill flags, it would incorrectly add
kill flags if there was another overlapping kill of the virtual
register.
We can't properly assign the register to an overlapping range, so
break the liveness of the failing register (and any other interfering
registers) instead. Give the virtual register dummy liveness by
effectively deleting all the uses by setting them to undef.
The edge case not tested here which I'm worried about is if the read
of the register is a def of a subregister. I've been unable to come up
with a test where this occurs.
https://reviews.llvm.org/D122616
---
llvm/lib/CodeGen/RegAllocBase.cpp | 36 +++
llvm/lib/CodeGen/RegAllocBase.h | 6 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 1 +
llvm/lib/CodeGen/RegAllocGreedy.cpp | 1 +
.../AMDGPU/illegal-eviction-assert.mir| 4 +-
llvm/test/CodeGen/AMDGPU/issue48473.mir | 3 +-
...lloc-failure-overlapping-insert-assert.mir | 7 +--
...ster-killed-error-after-alloc-failure0.mir | 59 +++
...ister-killed-error-after-alloc-failure1.ll | 30 ++
.../remaining-virtual-register-operands.ll| 3 +-
10 files changed, 140 insertions(+), 10 deletions(-)
create mode 100644
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
create mode 100644
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp
b/llvm/lib/CodeGen/RegAllocBase.cpp
index 980a6756963d9f..bb0c8a32a7bc92 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -65,6 +65,7 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
Matrix = &mat;
MRI->freezeReservedRegs();
RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
+ FailedVRegs.clear();
}
// Visit all the live registers. If they are already assigned to a physical
@@ -128,6 +129,7 @@ void RegAllocBase::allocatePhysRegs() {
// Keep going after reporting the error.
VRM->assignVirt2Phys(VirtReg->reg(), AvailablePhysReg);
+ FailedVRegs.insert(VirtReg->reg());
} else if (AvailablePhysReg)
Matrix->assign(*VirtReg, AvailablePhysReg);
@@ -161,6 +163,40 @@ void RegAllocBase::postOptimization() {
DeadRemats.clear();
}
+void RegAllocBase::cleanupFailedVRegs() {
+ SmallSet JunkRegs;
+
+ for (Register FailedReg : FailedVRegs) {
+JunkRegs.insert(FailedReg);
+
+MCRegister PhysReg = VRM->getPhys(FailedReg);
+LiveInterval &FailedInterval = LIS->getInterval(FailedReg);
+
+// The liveness information for the failed register and anything
interfering
+// with the physical register we arbitrarily chose is junk and needs to be
+// deleted.
+for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
+ LiveIntervalUnion::Query &Q = Matrix->query(FailedInterval, *Units);
+ for (const LiveInterval *InterferingReg : Q.interferingVRegs())
+JunkRegs.insert(InterferingReg->reg());
+}
+ }
+
+ // TODO: Probably need to set undef on any physreg uses not associated with
+ // a virtual register.
+ for (Register JunkReg : JunkRegs) {
+// We still should produce valid IR. Kill all the uses and reduce the live
+// ranges so that we don't think it's possible to introduce kill flags
+// later which will fail the verifier.
+for (MachineOperand &MO : MRI->reg_operands(JunkReg)) {
+ if (MO.readsReg())
+MO.setIsUndef(true);
+}
+
+LIS->shrinkToUses(&LIS->getInterval(JunkReg));
+ }
+}
+
void RegAllocBase::enqueue(const LiveInterval *LI) {
const Register Reg = LI->reg();
dif
[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/119684
>From 03cca4cf3b65cb6988db7a983f3c3349fa0b390a Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 28 Mar 2022 14:11:28 -0400
Subject: [PATCH 1/3] [Statepoint] Treat undef operands less specially
This reverts commit f7443905af1e06eaacda1e437fff8d54dc89c487.
This is to avoid an assertion if an undef operand appears in a
stackmap. This is important to avoid hitting verifier errors
when register allocation starts adding undefs in error scenarios.
Rather than trying to treat undef operands as special, leave them
alone and avoid producing an invalid spill. It would a bit more
precise to produce a spill of an undef register here, but that's not
exposed through the storeRegToStackSlot API.
https://reviews.llvm.org/D122605
This was an alternative to https://reviews.llvm.org/D122582
---
.../CodeGen/FixupStatepointCallerSaved.cpp| 2 -
llvm/lib/CodeGen/StackMaps.cpp| 6 --
.../X86/stackmap-undef-operand-anyregcc.mir | 61 +++
.../CodeGen/X86/statepoint-fixup-undef.mir| 8 +--
4 files changed, 65 insertions(+), 12 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
index 3bb9da5f1a37bb..0ebe845e473fd6 100644
--- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
+++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
@@ -381,8 +381,6 @@ class StatepointState {
EndIdx = MI.getNumOperands();
Idx < EndIdx; ++Idx) {
MachineOperand &MO = MI.getOperand(Idx);
- // Leave `undef` operands as is, StackMaps will rewrite them
- // into a constant.
if (!MO.isReg() || MO.isImplicit() || MO.isUndef())
continue;
Register Reg = MO.getReg();
diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp
index 81b288df3b07e0..7480963c1f5217 100644
--- a/llvm/lib/CodeGen/StackMaps.cpp
+++ b/llvm/lib/CodeGen/StackMaps.cpp
@@ -268,12 +268,6 @@ StackMaps::parseOperand(MachineInstr::const_mop_iterator
MOI,
if (MOI->isImplicit())
return ++MOI;
-if (MOI->isUndef()) {
- // Record `undef` register as constant. Use same value as ISel uses.
- Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, 0xFEFEFEFE);
- return ++MOI;
-}
-
assert(MOI->getReg().isPhysical() &&
"Virtreg operands should have been rewritten before now.");
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());
diff --git a/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
b/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
new file mode 100644
index 00..6a322eb105e6f7
--- /dev/null
+++ b/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
@@ -0,0 +1,61 @@
+# RUN: llc -mtriple=x86_64-apple-darwin -start-after=virtregrewriter -o - %s |
FileCheck %s
+
+# Check there's no assertion for anyregcc with an undef operand to a stackmap.
+
+# CHECK: __LLVM_StackMaps:
+# CHECK-NEXT: .byte3
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long1
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .long1
+# CHECK-NEXT: .quad_undef_anyregcc_patchpoint
+# CHECK-NEXT: .quad8
+# CHECK-NEXT: .quad1
+# CHECK-NEXT: .quad12
+# CHECK-NEXT: .longLtmp0-_undef_anyregcc_patchpoint
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 2
+# CHECK-NEXT: .byte1
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 8
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .byte1
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 8
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .p2align 3
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 2
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 7
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .p2align 3
+---
+name: undef_anyregcc_patchpoint
+tracksRegLiveness: true
+frameInfo:
+ hasPatchPoint: true
+ hasCalls:true
+fixedStack:
+ - { id: 0, type: default, offset: 72, size: 8, alignment: 8, stack-id:
default,
+ isImmutable: true, isAliased: false, callee-saved-register: '',
callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+body: |
+ bb.0:
+liveins: $rcx, $rdi, $rdx, $rsi, $r8, $r9
+
+ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead
$eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+dead renamable $rax = MOV64rm %fixed-stack.0, 1, $noreg, 0, $noreg ::
(load (s64) from %fixed-stack.0)
+renamable $rax = PATCHPOINT 12, 15, 0, 1, 13, undef renamable $rax,
csr_64_allregs, implicit-def dead early-clobber $r11, implicit-def $rsp,
implicit-def $ssp
+
[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/119684 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RegAlloc: Fix verifier error after failed allocation (PR #119690)
llvmbot wrote:
@llvm/pr-subscribers-llvm-regalloc
Author: Matt Arsenault (arsenm)
Changes
In some cases after reporting an allocation failure, this would fail
the verifier. It picks the first allocatable register and assigns it,
but didn't update the liveness appropriately. When VirtRegRewriter
relied on the liveness to set kill flags, it would incorrectly add
kill flags if there was another overlapping kill of the virtual
register.
We can't properly assign the register to an overlapping range, so
break the liveness of the failing register (and any other interfering
registers) instead. Give the virtual register dummy liveness by
effectively deleting all the uses by setting them to undef.
The edge case not tested here which I'm worried about is if the read
of the register is a def of a subregister. I've been unable to come up
with a test where this occurs.
https://reviews.llvm.org/D122616
---
Full diff: https://github.com/llvm/llvm-project/pull/119690.diff
10 Files Affected:
- (modified) llvm/lib/CodeGen/RegAllocBase.cpp (+36)
- (modified) llvm/lib/CodeGen/RegAllocBase.h (+6)
- (modified) llvm/lib/CodeGen/RegAllocBasic.cpp (+1)
- (modified) llvm/lib/CodeGen/RegAllocGreedy.cpp (+1)
- (modified) llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/issue48473.mir (+2-1)
- (modified)
llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir (+2-5)
- (added)
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir (+59)
- (added)
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll (+30)
- (modified) llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.ll
(+1-2)
``diff
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp
b/llvm/lib/CodeGen/RegAllocBase.cpp
index 980a6756963d9f..bb0c8a32a7bc92 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -65,6 +65,7 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
Matrix = &mat;
MRI->freezeReservedRegs();
RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
+ FailedVRegs.clear();
}
// Visit all the live registers. If they are already assigned to a physical
@@ -128,6 +129,7 @@ void RegAllocBase::allocatePhysRegs() {
// Keep going after reporting the error.
VRM->assignVirt2Phys(VirtReg->reg(), AvailablePhysReg);
+ FailedVRegs.insert(VirtReg->reg());
} else if (AvailablePhysReg)
Matrix->assign(*VirtReg, AvailablePhysReg);
@@ -161,6 +163,40 @@ void RegAllocBase::postOptimization() {
DeadRemats.clear();
}
+void RegAllocBase::cleanupFailedVRegs() {
+ SmallSet JunkRegs;
+
+ for (Register FailedReg : FailedVRegs) {
+JunkRegs.insert(FailedReg);
+
+MCRegister PhysReg = VRM->getPhys(FailedReg);
+LiveInterval &FailedInterval = LIS->getInterval(FailedReg);
+
+// The liveness information for the failed register and anything
interfering
+// with the physical register we arbitrarily chose is junk and needs to be
+// deleted.
+for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
+ LiveIntervalUnion::Query &Q = Matrix->query(FailedInterval, *Units);
+ for (const LiveInterval *InterferingReg : Q.interferingVRegs())
+JunkRegs.insert(InterferingReg->reg());
+}
+ }
+
+ // TODO: Probably need to set undef on any physreg uses not associated with
+ // a virtual register.
+ for (Register JunkReg : JunkRegs) {
+// We still should produce valid IR. Kill all the uses and reduce the live
+// ranges so that we don't think it's possible to introduce kill flags
+// later which will fail the verifier.
+for (MachineOperand &MO : MRI->reg_operands(JunkReg)) {
+ if (MO.readsReg())
+MO.setIsUndef(true);
+}
+
+LIS->shrinkToUses(&LIS->getInterval(JunkReg));
+ }
+}
+
void RegAllocBase::enqueue(const LiveInterval *LI) {
const Register Reg = LI->reg();
diff --git a/llvm/lib/CodeGen/RegAllocBase.h b/llvm/lib/CodeGen/RegAllocBase.h
index 5bd52da61f2dc5..1fdbab694bb0e3 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/lib/CodeGen/RegAllocBase.h
@@ -37,6 +37,7 @@
#define LLVM_LIB_CODEGEN_REGALLOCBASE_H
#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocCommon.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -81,6 +82,7 @@ class RegAllocBase {
/// always available for the remat of all the siblings of the original reg.
SmallPtrSet DeadRemats;
+ SmallSet FailedVRegs;
RegAllocBase(const RegAllocFilterFunc F = nullptr)
: shouldAllocateRegisterImpl(F) {}
@@ -104,6 +106,10 @@ class RegAllocBase {
// rematerialization.
virtual void postOptimization();
+ /// Perform cleanups on registers that failed to allocate. This hacks on the
+ /// liveness in order to avoid spurious verifier errors in later passes.
+ void cleanupFailedVRegs
[llvm-branch-commits] [llvm] RegAlloc: Fix verifier error after failed allocation (PR #119690)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/119690?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#119690** https://app.graphite.dev/github/pr/llvm/llvm-project/119690?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/119690?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#119684** https://app.graphite.dev/github/pr/llvm/llvm-project/119684?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119682** https://app.graphite.dev/github/pr/llvm/llvm-project/119682?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119647** https://app.graphite.dev/github/pr/llvm/llvm-project/119647?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119640** https://app.graphite.dev/github/pr/llvm/llvm-project/119640?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119492** https://app.graphite.dev/github/pr/llvm/llvm-project/119492?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119491** https://app.graphite.dev/github/pr/llvm/llvm-project/119491?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119485** https://app.graphite.dev/github/pr/llvm/llvm-project/119485?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/119690 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RegAlloc: Fix verifier error after failed allocation (PR #119690)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/119690 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RegAlloc: Fix verifier error after failed allocation (PR #119690)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/119690
>From bca529ad0b6fabe5825c3ed305b389d489f7e2c9 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 25 Mar 2022 20:27:39 -0400
Subject: [PATCH] RegAlloc: Fix verifier error after failed allocation
In some cases after reporting an allocation failure, this would fail
the verifier. It picks the first allocatable register and assigns it,
but didn't update the liveness appropriately. When VirtRegRewriter
relied on the liveness to set kill flags, it would incorrectly add
kill flags if there was another overlapping kill of the virtual
register.
We can't properly assign the register to an overlapping range, so
break the liveness of the failing register (and any other interfering
registers) instead. Give the virtual register dummy liveness by
effectively deleting all the uses by setting them to undef.
The edge case not tested here which I'm worried about is if the read
of the register is a def of a subregister. I've been unable to come up
with a test where this occurs.
https://reviews.llvm.org/D122616
---
llvm/lib/CodeGen/RegAllocBase.cpp | 36 +++
llvm/lib/CodeGen/RegAllocBase.h | 6 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 1 +
llvm/lib/CodeGen/RegAllocGreedy.cpp | 1 +
.../AMDGPU/illegal-eviction-assert.mir| 4 +-
llvm/test/CodeGen/AMDGPU/issue48473.mir | 3 +-
...ut-of-registers-error-all-regs-reserved.ll | 8 +--
...lloc-failure-overlapping-insert-assert.mir | 7 +--
...ster-killed-error-after-alloc-failure0.mir | 59 +++
...ister-killed-error-after-alloc-failure1.ll | 30 ++
.../remaining-virtual-register-operands.ll| 3 +-
11 files changed, 143 insertions(+), 15 deletions(-)
create mode 100644
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
create mode 100644
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp
b/llvm/lib/CodeGen/RegAllocBase.cpp
index 980a6756963d9f..bb0c8a32a7bc92 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -65,6 +65,7 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
Matrix = &mat;
MRI->freezeReservedRegs();
RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
+ FailedVRegs.clear();
}
// Visit all the live registers. If they are already assigned to a physical
@@ -128,6 +129,7 @@ void RegAllocBase::allocatePhysRegs() {
// Keep going after reporting the error.
VRM->assignVirt2Phys(VirtReg->reg(), AvailablePhysReg);
+ FailedVRegs.insert(VirtReg->reg());
} else if (AvailablePhysReg)
Matrix->assign(*VirtReg, AvailablePhysReg);
@@ -161,6 +163,40 @@ void RegAllocBase::postOptimization() {
DeadRemats.clear();
}
+void RegAllocBase::cleanupFailedVRegs() {
+ SmallSet JunkRegs;
+
+ for (Register FailedReg : FailedVRegs) {
+JunkRegs.insert(FailedReg);
+
+MCRegister PhysReg = VRM->getPhys(FailedReg);
+LiveInterval &FailedInterval = LIS->getInterval(FailedReg);
+
+// The liveness information for the failed register and anything
interfering
+// with the physical register we arbitrarily chose is junk and needs to be
+// deleted.
+for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
+ LiveIntervalUnion::Query &Q = Matrix->query(FailedInterval, *Units);
+ for (const LiveInterval *InterferingReg : Q.interferingVRegs())
+JunkRegs.insert(InterferingReg->reg());
+}
+ }
+
+ // TODO: Probably need to set undef on any physreg uses not associated with
+ // a virtual register.
+ for (Register JunkReg : JunkRegs) {
+// We still should produce valid IR. Kill all the uses and reduce the live
+// ranges so that we don't think it's possible to introduce kill flags
+// later which will fail the verifier.
+for (MachineOperand &MO : MRI->reg_operands(JunkReg)) {
+ if (MO.readsReg())
+MO.setIsUndef(true);
+}
+
+LIS->shrinkToUses(&LIS->getInterval(JunkReg));
+ }
+}
+
void RegAllocBase::enqueue(const LiveInterval *LI) {
const Register Reg = LI->reg();
diff --git a/llvm/lib/CodeGen/RegAllocBase.h b/llvm/lib/CodeGen/RegAllocBase.h
index 5bd52da61f2dc5..1fdbab694bb0e3 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/lib/CodeGen/RegAllocBase.h
@@ -37,6 +37,7 @@
#define LLVM_LIB_CODEGEN_REGALLOCBASE_H
#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocCommon.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -81,6 +82,7 @@ class RegAllocBase {
/// always available for the remat of all the siblings of the original reg.
SmallPtrSet DeadRemats;
+ SmallSet FailedVRegs;
RegAllocBase(const RegAllocFilterFunc F = nullptr)
: shouldAllocateRegisterImpl(F) {}
@@ -104,6 +106,10 @@ class RegA
[llvm-branch-commits] [llvm] RegAlloc: Do not fatal error if there are no registers in the alloc order (PR #119640)
@@ -192,3 +177,50 @@ void RegAllocBase::enqueue(const LiveInterval *LI) {
<< " in skipped register class\n");
}
}
+
+MCPhysReg RegAllocBase::getErrorAssignment(const TargetRegisterClass &RC,
+ const MachineInstr *CtxMI) {
+ MachineFunction &MF = VRM->getMachineFunction();
+
+ // Avoid printing the error for every single instance of the register. It
+ // would be better if this were per register class.
+ bool EmitError = !MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::FailedRegAlloc);
+ if (EmitError)
+
MF.getProperties().set(MachineFunctionProperties::Property::FailedRegAlloc);
+
+ const Function &Fn = MF.getFunction();
+ LLVMContext &Context = Fn.getContext();
+
+ ArrayRef AllocOrder = RegClassInfo.getOrder(&RC);
+ if (AllocOrder.empty()) {
+// If the allocation order is empty, it likely means all registers in the
+// class are reserved. We still to need to pick something, so look at the
+// underlying class.
+ArrayRef RawRegs = RC.getRegisters();
+
+if (EmitError) {
+ DiagnosticInfoRegAllocFailure DI(
+ "no registers from class available to allocate", Fn,
+ CtxMI ? CtxMI->getDebugLoc() : DiagnosticLocation());
+ Context.diagnose(DI);
+}
+
+assert(!RawRegs.empty() && "register classes cannot have no registers");
+return RawRegs.front();
+ }
+
+ if (EmitError) {
qcolombet wrote:
If we emit only the first error, is there a point in even trying to continue to
compile?
I guess I am asking what is the use cases we are trying to enable with this
patch Series.
https://github.com/llvm/llvm-project/pull/119640
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[llvm-branch-commits] [lld] release/19.x: [lld][WebAssembly] Fix use of uninitialized stack data with --wasm64 (#107780) (PR #119723)
llvmbot wrote: @dschuff What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/119723 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] release/19.x: [lld][WebAssembly] Fix use of uninitialized stack data with --wasm64 (#107780) (PR #119723)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/119723
Backport 5c8fd1eece8fff69871cef57a2363dc0f734a7d1
Requested by: @nikic
>From fc310d328d3954207a775d0f0b17f9796912777a Mon Sep 17 00:00:00 2001
From: Sam Clegg
Date: Mon, 9 Sep 2024 09:28:08 -0700
Subject: [PATCH] [lld][WebAssembly] Fix use of uninitialized stack data with
--wasm64 (#107780)
In the case of `--wasm64` we were setting the type of the init expression
to be 64-bit but were only setting the low 32-bits of the value (by
assigning to Int32).
Fixes: https://github.com/emscripten-core/emscripten/issues/22538
(cherry picked from commit 5c8fd1eece8fff69871cef57a2363dc0f734a7d1)
---
lld/wasm/SyntheticSections.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/lld/wasm/SyntheticSections.cpp b/lld/wasm/SyntheticSections.cpp
index f02f55519a2512..72d08b849d8e86 100644
--- a/lld/wasm/SyntheticSections.cpp
+++ b/lld/wasm/SyntheticSections.cpp
@@ -587,8 +587,7 @@ void ElemSection::writeBody() {
initExpr.Inst.Value.Global = WasmSym::tableBase->getGlobalIndex();
} else {
bool is64 = config->is64.value_or(false);
-initExpr.Inst.Opcode = is64 ? WASM_OPCODE_I64_CONST :
WASM_OPCODE_I32_CONST;
-initExpr.Inst.Value.Int32 = config->tableBase;
+initExpr = intConst(config->tableBase, is64);
}
writeInitExpr(os, initExpr);
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[llvm-branch-commits] [lld] release/19.x: [lld][WebAssembly] Fix use of uninitialized stack data with --wasm64 (#107780) (PR #119723)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/119723 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] release/19.x: [lld][WebAssembly] Fix use of uninitialized stack data with --wasm64 (#107780) (PR #119723)
llvmbot wrote:
@llvm/pr-subscribers-lld
Author: None (llvmbot)
Changes
Backport 5c8fd1eece8fff69871cef57a2363dc0f734a7d1
Requested by: @nikic
---
Full diff: https://github.com/llvm/llvm-project/pull/119723.diff
1 Files Affected:
- (modified) lld/wasm/SyntheticSections.cpp (+1-2)
``diff
diff --git a/lld/wasm/SyntheticSections.cpp b/lld/wasm/SyntheticSections.cpp
index f02f55519a2512..72d08b849d8e86 100644
--- a/lld/wasm/SyntheticSections.cpp
+++ b/lld/wasm/SyntheticSections.cpp
@@ -587,8 +587,7 @@ void ElemSection::writeBody() {
initExpr.Inst.Value.Global = WasmSym::tableBase->getGlobalIndex();
} else {
bool is64 = config->is64.value_or(false);
-initExpr.Inst.Opcode = is64 ? WASM_OPCODE_I64_CONST :
WASM_OPCODE_I32_CONST;
-initExpr.Inst.Value.Int32 = config->tableBase;
+initExpr = intConst(config->tableBase, is64);
}
writeInitExpr(os, initExpr);
``
https://github.com/llvm/llvm-project/pull/119723
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[llvm-branch-commits] [lld] release/19.x: [lld][WebAssembly] Fix use of uninitialized stack data with --wasm64 (#107780) (PR #119723)
llvmbot wrote:
@llvm/pr-subscribers-lld-wasm
Author: None (llvmbot)
Changes
Backport 5c8fd1eece8fff69871cef57a2363dc0f734a7d1
Requested by: @nikic
---
Full diff: https://github.com/llvm/llvm-project/pull/119723.diff
1 Files Affected:
- (modified) lld/wasm/SyntheticSections.cpp (+1-2)
``diff
diff --git a/lld/wasm/SyntheticSections.cpp b/lld/wasm/SyntheticSections.cpp
index f02f55519a2512..72d08b849d8e86 100644
--- a/lld/wasm/SyntheticSections.cpp
+++ b/lld/wasm/SyntheticSections.cpp
@@ -587,8 +587,7 @@ void ElemSection::writeBody() {
initExpr.Inst.Value.Global = WasmSym::tableBase->getGlobalIndex();
} else {
bool is64 = config->is64.value_or(false);
-initExpr.Inst.Opcode = is64 ? WASM_OPCODE_I64_CONST :
WASM_OPCODE_I32_CONST;
-initExpr.Inst.Value.Int32 = config->tableBase;
+initExpr = intConst(config->tableBase, is64);
}
writeInitExpr(os, initExpr);
``
https://github.com/llvm/llvm-project/pull/119723
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[llvm-branch-commits] [lld] release/19.x: [lld][WebAssembly] Fix use of uninitialized stack data with --wasm64 (#107780) (PR #119723)
https://github.com/dschuff approved this pull request. https://github.com/llvm/llvm-project/pull/119723 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [MLIR][OpenMP] Add Lowering support for OpenMP Declare Mapper directive (PR #117046)
kparzysz wrote: I looked at the clang code and it's not clear to me why they do it at runtime. Mappers can refer to other mappers (for sub-objects), but all mappers and all type layouts should be present in (or obtainable from) the AST[1]. In other words, clang should be able to emit all the "expanded" map clauses (i.e. after application of the mappers) at compile-time. It's possible that instead of emitting all that code inline, they put it in a runtime function to save code size. [1] The mapper definition must be visible at the time of use in a clause, so all mappers (recursively) should be visible. https://github.com/llvm/llvm-project/pull/117046 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RegAlloc: Fix verifier error after failed allocation (PR #119690)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/119690
>From 8d34266ce9d4b461da62d63791affce6489686d8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 25 Mar 2022 20:27:39 -0400
Subject: [PATCH] RegAlloc: Fix verifier error after failed allocation
In some cases after reporting an allocation failure, this would fail
the verifier. It picks the first allocatable register and assigns it,
but didn't update the liveness appropriately. When VirtRegRewriter
relied on the liveness to set kill flags, it would incorrectly add
kill flags if there was another overlapping kill of the virtual
register.
We can't properly assign the register to an overlapping range, so
break the liveness of the failing register (and any other interfering
registers) instead. Give the virtual register dummy liveness by
effectively deleting all the uses by setting them to undef.
The edge case not tested here which I'm worried about is if the read
of the register is a def of a subregister. I've been unable to come up
with a test where this occurs.
https://reviews.llvm.org/D122616
---
llvm/lib/CodeGen/RegAllocBase.cpp | 36 +++
llvm/lib/CodeGen/RegAllocBase.h | 6 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 1 +
llvm/lib/CodeGen/RegAllocGreedy.cpp | 1 +
.../AMDGPU/illegal-eviction-assert.mir| 4 +-
llvm/test/CodeGen/AMDGPU/issue48473.mir | 3 +-
...ut-of-registers-error-all-regs-reserved.ll | 8 +--
...lloc-failure-overlapping-insert-assert.mir | 7 +--
...ster-killed-error-after-alloc-failure0.mir | 59 +++
...ister-killed-error-after-alloc-failure1.ll | 30 ++
.../remaining-virtual-register-operands.ll| 3 +-
11 files changed, 143 insertions(+), 15 deletions(-)
create mode 100644
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
create mode 100644
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp
b/llvm/lib/CodeGen/RegAllocBase.cpp
index 980a6756963d9f..bb0c8a32a7bc92 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -65,6 +65,7 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
Matrix = &mat;
MRI->freezeReservedRegs();
RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
+ FailedVRegs.clear();
}
// Visit all the live registers. If they are already assigned to a physical
@@ -128,6 +129,7 @@ void RegAllocBase::allocatePhysRegs() {
// Keep going after reporting the error.
VRM->assignVirt2Phys(VirtReg->reg(), AvailablePhysReg);
+ FailedVRegs.insert(VirtReg->reg());
} else if (AvailablePhysReg)
Matrix->assign(*VirtReg, AvailablePhysReg);
@@ -161,6 +163,40 @@ void RegAllocBase::postOptimization() {
DeadRemats.clear();
}
+void RegAllocBase::cleanupFailedVRegs() {
+ SmallSet JunkRegs;
+
+ for (Register FailedReg : FailedVRegs) {
+JunkRegs.insert(FailedReg);
+
+MCRegister PhysReg = VRM->getPhys(FailedReg);
+LiveInterval &FailedInterval = LIS->getInterval(FailedReg);
+
+// The liveness information for the failed register and anything
interfering
+// with the physical register we arbitrarily chose is junk and needs to be
+// deleted.
+for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
+ LiveIntervalUnion::Query &Q = Matrix->query(FailedInterval, *Units);
+ for (const LiveInterval *InterferingReg : Q.interferingVRegs())
+JunkRegs.insert(InterferingReg->reg());
+}
+ }
+
+ // TODO: Probably need to set undef on any physreg uses not associated with
+ // a virtual register.
+ for (Register JunkReg : JunkRegs) {
+// We still should produce valid IR. Kill all the uses and reduce the live
+// ranges so that we don't think it's possible to introduce kill flags
+// later which will fail the verifier.
+for (MachineOperand &MO : MRI->reg_operands(JunkReg)) {
+ if (MO.readsReg())
+MO.setIsUndef(true);
+}
+
+LIS->shrinkToUses(&LIS->getInterval(JunkReg));
+ }
+}
+
void RegAllocBase::enqueue(const LiveInterval *LI) {
const Register Reg = LI->reg();
diff --git a/llvm/lib/CodeGen/RegAllocBase.h b/llvm/lib/CodeGen/RegAllocBase.h
index 5bd52da61f2dc5..1fdbab694bb0e3 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/lib/CodeGen/RegAllocBase.h
@@ -37,6 +37,7 @@
#define LLVM_LIB_CODEGEN_REGALLOCBASE_H
#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocCommon.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -81,6 +82,7 @@ class RegAllocBase {
/// always available for the remat of all the siblings of the original reg.
SmallPtrSet DeadRemats;
+ SmallSet FailedVRegs;
RegAllocBase(const RegAllocFilterFunc F = nullptr)
: shouldAllocateRegisterImpl(F) {}
@@ -104,6 +106,10 @@ class RegA
[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/119684
>From 3db8f1e5c89a19bf289d6745bca910f220c51dd4 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 28 Mar 2022 11:24:48 -0400
Subject: [PATCH 1/2] AMDGPU: Delete spills of undef values
It would be a bit more logical to preserve the undef and do the normal
expansion, but this is less work. This avoids verifier errors in a
future patch which starts deleting liveness from registers after
allocation failures which results in spills of undef values.
https://reviews.llvm.org/D122607
---
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 12 ++
.../AMDGPU/sgpr-spill-partially-undef.mir | 42 +++
.../AMDGPU/spill-agpr-partially-undef.mir | 34 +++
llvm/test/CodeGen/AMDGPU/vgpr-spill.mir | 34 +++
4 files changed, 122 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 296c32fa4e0d09..4f8c5c6756b3bb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1954,6 +1954,13 @@ bool
SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
RegScavenger *RS, SlotIndexes *Indexes,
LiveIntervals *LIS, bool OnlyToVGPR,
bool SpillToPhysVGPRLane) const {
+ if (MI->getOperand(0).isUndef()) {
+if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*MI);
+MI->eraseFromParent();
+return true;
+ }
+
SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS);
ArrayRef VGPRSpills =
@@ -2375,6 +2382,11 @@ bool
SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
case AMDGPU::SI_SPILL_WWM_AV32_SAVE: {
const MachineOperand *VData = TII->getNamedOperand(*MI,
AMDGPU::OpName::vdata);
+ if (VData->isUndef()) {
+MI->eraseFromParent();
+return true;
+ }
+
assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
MFI->getStackPtrOffsetReg());
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
b/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
index 774785fb3966fc..d352e8a13da9f1 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
@@ -54,3 +54,45 @@ body: |
SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec,
implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into
%stack.0, align 4, addrspace 5)
...
+
+---
+name: sgpr_spill_s32_undef
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+ hasSpilledSGPRs: true
+ scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
+ stackPtrOffsetReg: '$sgpr32'
+stack:
+ - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
+body: |
+ bb.0:
+; CHECK-LABEL: name: sgpr_spill_s32_undef
+; CHECK: body:
+; CHECK-NEXT: bb.0:
+; CHECK-NOT: {{.+}}
+; CHECK: ...
+SI_SPILL_S32_SAVE undef $sgpr8, %stack.0, implicit $exec, implicit
$sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s32) into %stack.0,
align 4, addrspace 5)
+
+...
+
+---
+name: sgpr_spill_s64_undef
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+ hasSpilledSGPRs: true
+ scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
+ stackPtrOffsetReg: '$sgpr32'
+stack:
+ - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
+body: |
+ bb.0:
+; CHECK-LABEL: name: sgpr_spill_s64_undef
+; CHECK: body:
+; CHECK-NEXT: bb.0:
+; CHECK-NOT: {{.+}}
+; CHECK: ...
+SI_SPILL_S64_SAVE undef $sgpr8_sgpr9, %stack.0, implicit $exec, implicit
$sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into %stack.0,
align 4, addrspace 5)
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
index c825674de7652c..b02b6e79d7a76f 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
@@ -71,3 +71,37 @@ body: |
; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0,
$sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed
$agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5)
SI_SPILL_A64_SAVE killed $agpr0_agpr1, %stack.0, $sgpr32, 0, implicit
$exec :: (store (s64) into %stack.0, addrspace 5)
...
+
+---
+name: spill_a32_undef
+tracksRegLiveness: true
+stack:
+ - { id: 0, type: spill-slot, size: 4, alignment: 4 }
+machineFunctionInfo:
+ scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
+ stackPtrOffsetReg: '$sgpr32'
+ frameOffsetReg: '$sgpr33'
+body: |
+ bb.0:
+; CHECK-LABEL: na
[llvm-branch-commits] [llvm] [Statepoint] Treat undef operands less specially (PR #119682)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/119682
>From 31bfcc47ad1e141c3c897514ab5992bb1a56eaa8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 28 Mar 2022 14:11:28 -0400
Subject: [PATCH] [Statepoint] Treat undef operands less specially
This reverts commit f7443905af1e06eaacda1e437fff8d54dc89c487.
This is to avoid an assertion if an undef operand appears in a
stackmap. This is important to avoid hitting verifier errors
when register allocation starts adding undefs in error scenarios.
Rather than trying to treat undef operands as special, leave them
alone and avoid producing an invalid spill. It would a bit more
precise to produce a spill of an undef register here, but that's not
exposed through the storeRegToStackSlot API.
https://reviews.llvm.org/D122605
This was an alternative to https://reviews.llvm.org/D122582
---
.../CodeGen/FixupStatepointCallerSaved.cpp| 2 -
llvm/lib/CodeGen/StackMaps.cpp| 6 --
.../X86/stackmap-undef-operand-anyregcc.mir | 77 +++
.../CodeGen/X86/statepoint-fixup-undef.mir| 8 +-
4 files changed, 81 insertions(+), 12 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
index 3bb9da5f1a37bb..0ebe845e473fd6 100644
--- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
+++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
@@ -381,8 +381,6 @@ class StatepointState {
EndIdx = MI.getNumOperands();
Idx < EndIdx; ++Idx) {
MachineOperand &MO = MI.getOperand(Idx);
- // Leave `undef` operands as is, StackMaps will rewrite them
- // into a constant.
if (!MO.isReg() || MO.isImplicit() || MO.isUndef())
continue;
Register Reg = MO.getReg();
diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp
index 81b288df3b07e0..7480963c1f5217 100644
--- a/llvm/lib/CodeGen/StackMaps.cpp
+++ b/llvm/lib/CodeGen/StackMaps.cpp
@@ -268,12 +268,6 @@ StackMaps::parseOperand(MachineInstr::const_mop_iterator
MOI,
if (MOI->isImplicit())
return ++MOI;
-if (MOI->isUndef()) {
- // Record `undef` register as constant. Use same value as ISel uses.
- Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, 0xFEFEFEFE);
- return ++MOI;
-}
-
assert(MOI->getReg().isPhysical() &&
"Virtreg operands should have been rewritten before now.");
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());
diff --git a/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
b/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
new file mode 100644
index 00..3c6390ba2379c8
--- /dev/null
+++ b/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
@@ -0,0 +1,77 @@
+# RUN: llc -mtriple=x86_64-apple-darwin -start-after=virtregrewriter -o - %s |
FileCheck %s
+
+# Check there's no assertion for anyregcc with an undef operand to a stackmap.
+
+# CHECK: __LLVM_StackMaps:
+# CHECK-NEXT: .byte3
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long1
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .long1
+# CHECK-NEXT: .quad_undef_anyregcc_patchpoint
+# CHECK-NEXT: .quad8
+# CHECK-NEXT: .quad1
+# CHECK-NEXT: .quad12
+# CHECK-NEXT: .longLtmp0-_undef_anyregcc_patchpoint
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 2
+# CHECK-NEXT: .byte1
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 8
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .byte1
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 8
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .p2align 3, 0x0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 7
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 3
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 7
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 12
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 13
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 14
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 15
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .p2align 3
+---
+name: undef_anyregcc_patchpoint
+tracksRegLiveness: true
+frameInfo:
+ hasPatchPoint: true
+ hasCalls:true
+ adjustsStack:true
+fixedStack:
+ - { id: 0, type: default, offset: 72, size: 8, alignment: 8, stack-id:
default,
+ isImmutable: true, isAliased: false, callee-saved-register: '',
callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+body: |
+ bb.0:
+liveins: $rcx, $rdi, $rdx, $rsi, $r8, $r9
[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
cdevadas wrote: Currently, regalloc won't do subreg spilling. But it will be fixed in the foreseeable future. What will happen if you write a test that spills the `undef` subreg of a tuple? Do you want to cover it anyway? https://github.com/llvm/llvm-project/pull/119684 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [compiler-rt] [TySan] A Type Sanitizer (Runtime Library) (PR #76261)
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/76261
>From 524eb555b0473bd93401297c5deba77f4dbd83fe Mon Sep 17 00:00:00 2001
From: Florian Hahn
Date: Fri, 22 Nov 2024 15:01:41 +
Subject: [PATCH 1/4] [TySan] A Type Sanitizer (Runtime Library)
---
clang/runtime/CMakeLists.txt | 2 +-
.../cmake/Modules/AllSupportedArchDefs.cmake | 1 +
compiler-rt/cmake/config-ix.cmake | 15 +-
compiler-rt/lib/tysan/CMakeLists.txt | 64
compiler-rt/lib/tysan/lit.cfg | 35 ++
compiler-rt/lib/tysan/lit.site.cfg.in | 12 +
compiler-rt/lib/tysan/tysan.cpp | 344 ++
compiler-rt/lib/tysan/tysan.h | 79
compiler-rt/lib/tysan/tysan.syms.extra| 2 +
compiler-rt/lib/tysan/tysan_flags.inc | 17 +
compiler-rt/lib/tysan/tysan_interceptors.cpp | 250 +
compiler-rt/lib/tysan/tysan_platform.h| 93 +
compiler-rt/test/tysan/CMakeLists.txt | 32 ++
compiler-rt/test/tysan/anon-ns.cpp| 41 +++
compiler-rt/test/tysan/anon-same-struct.c | 26 ++
compiler-rt/test/tysan/anon-struct.c | 27 ++
compiler-rt/test/tysan/basic.c| 65
compiler-rt/test/tysan/char-memcpy.c | 45 +++
.../test/tysan/constexpr-subobject.cpp| 25 ++
compiler-rt/test/tysan/global.c | 31 ++
compiler-rt/test/tysan/int-long.c | 21 ++
compiler-rt/test/tysan/lit.cfg.py | 139 +++
compiler-rt/test/tysan/lit.site.cfg.py.in | 17 +
compiler-rt/test/tysan/ptr-float.c| 19 +
...ruct-offset-multiple-compilation-units.cpp | 51 +++
compiler-rt/test/tysan/struct-offset.c| 26 ++
compiler-rt/test/tysan/struct.c | 39 ++
compiler-rt/test/tysan/union-wr-wr.c | 18 +
compiler-rt/test/tysan/violation-pr45282.c| 32 ++
compiler-rt/test/tysan/violation-pr47137.c| 40 ++
compiler-rt/test/tysan/violation-pr51837.c| 34 ++
compiler-rt/test/tysan/violation-pr62544.c| 24 ++
compiler-rt/test/tysan/violation-pr62828.cpp | 44 +++
compiler-rt/test/tysan/violation-pr68655.cpp | 40 ++
compiler-rt/test/tysan/violation-pr86685.c| 29 ++
35 files changed, 1777 insertions(+), 2 deletions(-)
create mode 100644 compiler-rt/lib/tysan/CMakeLists.txt
create mode 100644 compiler-rt/lib/tysan/lit.cfg
create mode 100644 compiler-rt/lib/tysan/lit.site.cfg.in
create mode 100644 compiler-rt/lib/tysan/tysan.cpp
create mode 100644 compiler-rt/lib/tysan/tysan.h
create mode 100644 compiler-rt/lib/tysan/tysan.syms.extra
create mode 100644 compiler-rt/lib/tysan/tysan_flags.inc
create mode 100644 compiler-rt/lib/tysan/tysan_interceptors.cpp
create mode 100644 compiler-rt/lib/tysan/tysan_platform.h
create mode 100644 compiler-rt/test/tysan/CMakeLists.txt
create mode 100644 compiler-rt/test/tysan/anon-ns.cpp
create mode 100644 compiler-rt/test/tysan/anon-same-struct.c
create mode 100644 compiler-rt/test/tysan/anon-struct.c
create mode 100644 compiler-rt/test/tysan/basic.c
create mode 100644 compiler-rt/test/tysan/char-memcpy.c
create mode 100644 compiler-rt/test/tysan/constexpr-subobject.cpp
create mode 100644 compiler-rt/test/tysan/global.c
create mode 100644 compiler-rt/test/tysan/int-long.c
create mode 100644 compiler-rt/test/tysan/lit.cfg.py
create mode 100644 compiler-rt/test/tysan/lit.site.cfg.py.in
create mode 100644 compiler-rt/test/tysan/ptr-float.c
create mode 100644
compiler-rt/test/tysan/struct-offset-multiple-compilation-units.cpp
create mode 100644 compiler-rt/test/tysan/struct-offset.c
create mode 100644 compiler-rt/test/tysan/struct.c
create mode 100644 compiler-rt/test/tysan/union-wr-wr.c
create mode 100644 compiler-rt/test/tysan/violation-pr45282.c
create mode 100644 compiler-rt/test/tysan/violation-pr47137.c
create mode 100644 compiler-rt/test/tysan/violation-pr51837.c
create mode 100644 compiler-rt/test/tysan/violation-pr62544.c
create mode 100644 compiler-rt/test/tysan/violation-pr62828.cpp
create mode 100644 compiler-rt/test/tysan/violation-pr68655.cpp
create mode 100644 compiler-rt/test/tysan/violation-pr86685.c
diff --git a/clang/runtime/CMakeLists.txt b/clang/runtime/CMakeLists.txt
index 65fcdc2868f031..ff2605b23d25b0 100644
--- a/clang/runtime/CMakeLists.txt
+++ b/clang/runtime/CMakeLists.txt
@@ -122,7 +122,7 @@ if(LLVM_BUILD_EXTERNAL_COMPILER_RT AND EXISTS
${COMPILER_RT_SRC_ROOT}/)
COMPONENT compiler-rt)
# Add top-level targets that build specific compiler-rt runtimes.
- set(COMPILER_RT_RUNTIMES fuzzer asan builtins dfsan lsan msan profile tsan
ubsan ubsan-minimal)
+ set(COMPILER_RT_RUNTIMES fuzzer asan builtins dfsan lsan msan profile tsan
tysan ubsan ubsan-minimal)
foreach(runtime ${COMPILER_RT_RUNTIMES})
get_ext_project_build_command(build_runtime_cmd ${runtime})
add_custom_target(${runtime}
diff --git a/compil
[llvm-branch-commits] [clang] [compiler-rt] [TySan] A Type Sanitizer (Runtime Library) (PR #76261)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 13c4092708f82809aeec5320c093387aa4e17993
758c99abb36139fe759b51bd70f9ffeac76f21fa --extensions h,cpp,c,inc --
compiler-rt/lib/tysan/tysan.cpp compiler-rt/lib/tysan/tysan.h
compiler-rt/lib/tysan/tysan_flags.inc
compiler-rt/lib/tysan/tysan_interceptors.cpp
compiler-rt/lib/tysan/tysan_platform.h compiler-rt/test/tysan/anon-ns.cpp
compiler-rt/test/tysan/anon-same-struct.c compiler-rt/test/tysan/anon-struct.c
compiler-rt/test/tysan/basic.c compiler-rt/test/tysan/char-memcpy.c
compiler-rt/test/tysan/constexpr-subobject.cpp compiler-rt/test/tysan/global.c
compiler-rt/test/tysan/int-long.c compiler-rt/test/tysan/ptr-float.c
compiler-rt/test/tysan/struct-offset-multiple-compilation-units.cpp
compiler-rt/test/tysan/struct-offset.c compiler-rt/test/tysan/struct.c
compiler-rt/test/tysan/union-wr-wr.c compiler-rt/test/tysan/violation-pr45282.c
compiler-rt/test/tysan/violation-pr47137.c
compiler-rt/test/tysan/violation-pr51837.c
compiler-rt/test/tysan/violation-pr62544.c
compiler-rt/test/tysan/violation-pr62828.cpp
compiler-rt/test/tysan/violation-pr68655.cpp
compiler-rt/test/tysan/violation-pr86685.c
``
View the diff from clang-format here.
``diff
diff --git a/compiler-rt/test/tysan/violation-pr47137.c
b/compiler-rt/test/tysan/violation-pr47137.c
index 11c16cb735..fb895ff729 100644
--- a/compiler-rt/test/tysan/violation-pr47137.c
+++ b/compiler-rt/test/tysan/violation-pr47137.c
@@ -2,9 +2,9 @@
// RUN: FileCheck %s < %t.out
// https://github.com/llvm/llvm-project/issues/47137
+#include
#include
#include
-#include
void f(int m) {
int n = (4 * m + 2) / 3;
``
https://github.com/llvm/llvm-project/pull/76261
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [MLIR][OpenMP] Add Lowering support for OpenMP Declare Mapper directive (PR #117046)
kparzysz wrote: 1. If you want to create an MLIR op for the mapper, you can give it some name (you can mangle it if you want). You will need to store it in the MLIR somewhere/somehow. 2. If you want to record the use of a mapper in a clause, you can just use the name of the mapper in the same form as in (1), i.e. you decide how to generate the name here. 3. If you want to actually apply the mapper, you need to find it, but it's up to you how you do it: if you're looking for it in the MLIR module then your code must have put it there, if you're looking for it in the AST then you can find the declaration of the mapper by the symbol associated with its name. https://github.com/llvm/llvm-project/pull/117046 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [compiler-rt] [TySan] A Type Sanitizer (Runtime Library) (PR #76261)
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/76261
>From 524eb555b0473bd93401297c5deba77f4dbd83fe Mon Sep 17 00:00:00 2001
From: Florian Hahn
Date: Fri, 22 Nov 2024 15:01:41 +
Subject: [PATCH 1/5] [TySan] A Type Sanitizer (Runtime Library)
---
clang/runtime/CMakeLists.txt | 2 +-
.../cmake/Modules/AllSupportedArchDefs.cmake | 1 +
compiler-rt/cmake/config-ix.cmake | 15 +-
compiler-rt/lib/tysan/CMakeLists.txt | 64
compiler-rt/lib/tysan/lit.cfg | 35 ++
compiler-rt/lib/tysan/lit.site.cfg.in | 12 +
compiler-rt/lib/tysan/tysan.cpp | 344 ++
compiler-rt/lib/tysan/tysan.h | 79
compiler-rt/lib/tysan/tysan.syms.extra| 2 +
compiler-rt/lib/tysan/tysan_flags.inc | 17 +
compiler-rt/lib/tysan/tysan_interceptors.cpp | 250 +
compiler-rt/lib/tysan/tysan_platform.h| 93 +
compiler-rt/test/tysan/CMakeLists.txt | 32 ++
compiler-rt/test/tysan/anon-ns.cpp| 41 +++
compiler-rt/test/tysan/anon-same-struct.c | 26 ++
compiler-rt/test/tysan/anon-struct.c | 27 ++
compiler-rt/test/tysan/basic.c| 65
compiler-rt/test/tysan/char-memcpy.c | 45 +++
.../test/tysan/constexpr-subobject.cpp| 25 ++
compiler-rt/test/tysan/global.c | 31 ++
compiler-rt/test/tysan/int-long.c | 21 ++
compiler-rt/test/tysan/lit.cfg.py | 139 +++
compiler-rt/test/tysan/lit.site.cfg.py.in | 17 +
compiler-rt/test/tysan/ptr-float.c| 19 +
...ruct-offset-multiple-compilation-units.cpp | 51 +++
compiler-rt/test/tysan/struct-offset.c| 26 ++
compiler-rt/test/tysan/struct.c | 39 ++
compiler-rt/test/tysan/union-wr-wr.c | 18 +
compiler-rt/test/tysan/violation-pr45282.c| 32 ++
compiler-rt/test/tysan/violation-pr47137.c| 40 ++
compiler-rt/test/tysan/violation-pr51837.c| 34 ++
compiler-rt/test/tysan/violation-pr62544.c| 24 ++
compiler-rt/test/tysan/violation-pr62828.cpp | 44 +++
compiler-rt/test/tysan/violation-pr68655.cpp | 40 ++
compiler-rt/test/tysan/violation-pr86685.c| 29 ++
35 files changed, 1777 insertions(+), 2 deletions(-)
create mode 100644 compiler-rt/lib/tysan/CMakeLists.txt
create mode 100644 compiler-rt/lib/tysan/lit.cfg
create mode 100644 compiler-rt/lib/tysan/lit.site.cfg.in
create mode 100644 compiler-rt/lib/tysan/tysan.cpp
create mode 100644 compiler-rt/lib/tysan/tysan.h
create mode 100644 compiler-rt/lib/tysan/tysan.syms.extra
create mode 100644 compiler-rt/lib/tysan/tysan_flags.inc
create mode 100644 compiler-rt/lib/tysan/tysan_interceptors.cpp
create mode 100644 compiler-rt/lib/tysan/tysan_platform.h
create mode 100644 compiler-rt/test/tysan/CMakeLists.txt
create mode 100644 compiler-rt/test/tysan/anon-ns.cpp
create mode 100644 compiler-rt/test/tysan/anon-same-struct.c
create mode 100644 compiler-rt/test/tysan/anon-struct.c
create mode 100644 compiler-rt/test/tysan/basic.c
create mode 100644 compiler-rt/test/tysan/char-memcpy.c
create mode 100644 compiler-rt/test/tysan/constexpr-subobject.cpp
create mode 100644 compiler-rt/test/tysan/global.c
create mode 100644 compiler-rt/test/tysan/int-long.c
create mode 100644 compiler-rt/test/tysan/lit.cfg.py
create mode 100644 compiler-rt/test/tysan/lit.site.cfg.py.in
create mode 100644 compiler-rt/test/tysan/ptr-float.c
create mode 100644
compiler-rt/test/tysan/struct-offset-multiple-compilation-units.cpp
create mode 100644 compiler-rt/test/tysan/struct-offset.c
create mode 100644 compiler-rt/test/tysan/struct.c
create mode 100644 compiler-rt/test/tysan/union-wr-wr.c
create mode 100644 compiler-rt/test/tysan/violation-pr45282.c
create mode 100644 compiler-rt/test/tysan/violation-pr47137.c
create mode 100644 compiler-rt/test/tysan/violation-pr51837.c
create mode 100644 compiler-rt/test/tysan/violation-pr62544.c
create mode 100644 compiler-rt/test/tysan/violation-pr62828.cpp
create mode 100644 compiler-rt/test/tysan/violation-pr68655.cpp
create mode 100644 compiler-rt/test/tysan/violation-pr86685.c
diff --git a/clang/runtime/CMakeLists.txt b/clang/runtime/CMakeLists.txt
index 65fcdc2868f031..ff2605b23d25b0 100644
--- a/clang/runtime/CMakeLists.txt
+++ b/clang/runtime/CMakeLists.txt
@@ -122,7 +122,7 @@ if(LLVM_BUILD_EXTERNAL_COMPILER_RT AND EXISTS
${COMPILER_RT_SRC_ROOT}/)
COMPONENT compiler-rt)
# Add top-level targets that build specific compiler-rt runtimes.
- set(COMPILER_RT_RUNTIMES fuzzer asan builtins dfsan lsan msan profile tsan
ubsan ubsan-minimal)
+ set(COMPILER_RT_RUNTIMES fuzzer asan builtins dfsan lsan msan profile tsan
tysan ubsan ubsan-minimal)
foreach(runtime ${COMPILER_RT_RUNTIMES})
get_ext_project_build_command(build_runtime_cmd ${runtime})
add_custom_target(${runtime}
diff --git a/compil
[llvm-branch-commits] [llvm] RegAlloc: Fix failure on undef use when all registers are reserved (PR #119647)
@@ -982,16 +982,23 @@ void RegAllocFastImpl::allocVirtRegUndef(MachineOperand
&MO) {
if (!shouldAllocateRegister(VirtReg))
return;
- LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
+ LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
MCPhysReg PhysReg;
if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
PhysReg = LRI->PhysReg;
} else {
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
ArrayRef AllocationOrder = RegClassInfo.getOrder(&RC);
-// FIXME: This can happen, and should fall back to a reserved entry in RC.
-assert(!AllocationOrder.empty() && "Allocation order must not be empty");
-PhysReg = AllocationOrder[0];
+if (AllocationOrder.empty()) {
+ // All registers in the class were reserved.
+ //
+ // It might be OK to take any entry from the class as this is an undef
+ // use, but accepting this would give different behavior than greedy and
+ // basic.
+ PhysReg = getErrorAssignment(*LRI, *MO.getParent(), RC);
+ LRI->Error = true;
+} else
+ PhysReg = AllocationOrder[0];
ilovepi wrote:
Up the stack you're using `AllocationOrder.front()`. Either way is fine, but I
think we should try to keep them consistent.
https://github.com/llvm/llvm-project/pull/119647
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[llvm-branch-commits] [libc] 168b0ea - Revert "[libc] Breakup freelist_malloc into separate files (#98784)"
Author: Petr Hosek
Date: 2024-12-12T11:35:19-08:00
New Revision: 168b0ea705c8e1e46daf89ca587f535c3f02afb0
URL:
https://github.com/llvm/llvm-project/commit/168b0ea705c8e1e46daf89ca587f535c3f02afb0
DIFF:
https://github.com/llvm/llvm-project/commit/168b0ea705c8e1e46daf89ca587f535c3f02afb0.diff
LOG: Revert "[libc] Breakup freelist_malloc into separate files (#98784)"
This reverts commit 4e2a9e50f6dd6760b12838517c7f85a0c9032921.
Added:
libc/src/stdlib/freelist_malloc.cpp
libc/test/src/__support/freelist_malloc_test.cpp
Modified:
libc/config/baremetal/aarch64/entrypoints.txt
libc/config/baremetal/arm/entrypoints.txt
libc/config/baremetal/riscv/entrypoints.txt
libc/src/__support/CMakeLists.txt
libc/src/stdlib/CMakeLists.txt
libc/src/stdlib/baremetal/CMakeLists.txt
libc/test/src/__support/CMakeLists.txt
libc/test/src/__support/freelist_heap_test.cpp
Removed:
libc/src/__support/freelist_heap.cpp
libc/src/stdlib/baremetal/aligned_alloc.cpp
libc/src/stdlib/baremetal/calloc.cpp
libc/src/stdlib/baremetal/free.cpp
libc/src/stdlib/baremetal/malloc.cpp
libc/src/stdlib/baremetal/realloc.cpp
diff --git a/libc/config/baremetal/aarch64/entrypoints.txt
b/libc/config/baremetal/aarch64/entrypoints.txt
index 694cd7b1993ca2..71b49d98942916 100644
--- a/libc/config/baremetal/aarch64/entrypoints.txt
+++ b/libc/config/baremetal/aarch64/entrypoints.txt
@@ -184,6 +184,7 @@ set(TARGET_LIBC_ENTRYPOINTS
libc.src.stdlib.div
libc.src.stdlib.exit
libc.src.stdlib.free
+libc.src.stdlib.freelist_malloc
libc.src.stdlib.labs
libc.src.stdlib.ldiv
libc.src.stdlib.llabs
diff --git a/libc/config/baremetal/arm/entrypoints.txt
b/libc/config/baremetal/arm/entrypoints.txt
index 694cd7b1993ca2..71b49d98942916 100644
--- a/libc/config/baremetal/arm/entrypoints.txt
+++ b/libc/config/baremetal/arm/entrypoints.txt
@@ -184,6 +184,7 @@ set(TARGET_LIBC_ENTRYPOINTS
libc.src.stdlib.div
libc.src.stdlib.exit
libc.src.stdlib.free
+libc.src.stdlib.freelist_malloc
libc.src.stdlib.labs
libc.src.stdlib.ldiv
libc.src.stdlib.llabs
diff --git a/libc/config/baremetal/riscv/entrypoints.txt
b/libc/config/baremetal/riscv/entrypoints.txt
index 6dc5df830eb000..e84d139d09dd8e 100644
--- a/libc/config/baremetal/riscv/entrypoints.txt
+++ b/libc/config/baremetal/riscv/entrypoints.txt
@@ -180,6 +180,7 @@ set(TARGET_LIBC_ENTRYPOINTS
libc.src.stdlib.div
libc.src.stdlib.exit
libc.src.stdlib.free
+libc.src.stdlib.freelist_malloc
libc.src.stdlib.labs
libc.src.stdlib.ldiv
libc.src.stdlib.llabs
diff --git a/libc/src/__support/CMakeLists.txt
b/libc/src/__support/CMakeLists.txt
index 70ed67c156d1ae..8f85740f70a06e 100644
--- a/libc/src/__support/CMakeLists.txt
+++ b/libc/src/__support/CMakeLists.txt
@@ -48,19 +48,13 @@ add_header_library(
.freetrie
)
-add_object_library(
+add_header_library(
freelist_heap
- SRCS
-freelist_heap.cpp
HDRS
freelist_heap.h
- COMPILE_OPTIONS
--DLIBC_FREELIST_MALLOC_SIZE=${LIBC_CONF_FREELIST_MALLOC_BUFFER_SIZE}
DEPENDS
.block
-.freelist
.freestore
-.freetrie
libc.src.__support.CPP.cstddef
libc.src.__support.CPP.array
libc.src.__support.CPP.optional
diff --git a/libc/src/__support/freelist_heap.cpp
b/libc/src/__support/freelist_heap.cpp
deleted file mode 100644
index 4deb0e0f09e223..00
--- a/libc/src/__support/freelist_heap.cpp
+++ /dev/null
@@ -1,19 +0,0 @@
-//===-- Implementation for freelist_heap
--===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===--===//
-
-#include "src/__support/freelist_heap.h"
-#include "src/__support/macros/config.h"
-
-#include
-
-namespace LIBC_NAMESPACE_DECL {
-
-static LIBC_CONSTINIT FreeListHeap freelist_heap_symbols;
-FreeListHeap *freelist_heap = &freelist_heap_symbols;
-
-} // namespace LIBC_NAMESPACE_DECL
diff --git a/libc/src/stdlib/CMakeLists.txt b/libc/src/stdlib/CMakeLists.txt
index 40ba9ead9a7ae6..14d06534a6049a 100644
--- a/libc/src/stdlib/CMakeLists.txt
+++ b/libc/src/stdlib/CMakeLists.txt
@@ -323,7 +323,7 @@ add_entrypoint_object(
.rand_util
)
-if(NOT LIBC_TARGET_OS_IS_BAREMETAL AND NOT LIBC_TARGET_OS_IS_GPU)
+if(NOT LIBC_TARGET_OS_IS_GPU)
if(LLVM_LIBC_INCLUDE_SCUDO)
set(SCUDO_DEPS "")
@@ -349,7 +349,7 @@ if(NOT LIBC_TARGET_OS_IS_BAREMETAL AND NOT
LIBC_TARGET_OS_IS_GPU)
list(APPEND SCUDO_DEPS
RTScudoStandalone.${LIBC_TARGET_ARCHITECTURE_FOR_SCUDO}
RTScudoStandaloneCWrappers.${LIBC_TARGET_ARCHITECTURE_FOR_SCUDO})
-
+
if (COMPILER_RT_BUILD_GWP_ASAN)
list(APP
[llvm-branch-commits] TargetParser: AArch64: Add part numbers for Apple CPUs. (PR #119777)
@@ -347,6 +347,29 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef
ProcCpuinfoContent) {
}
}
+ if (Implementer == "0x61") { // Apple
+return StringSwitch(Part)
+.Case("0x020", "apple-m1")
+.Case("0x021", "apple-m1")
+.Case("0x022", "apple-m1")
+.Case("0x023", "apple-m1")
+.Case("0x024", "apple-m1")
+.Case("0x025", "apple-m1")
+.Case("0x028", "apple-m1")
+.Case("0x029", "apple-m1")
+.Case("0x030", "apple-m2")
+.Case("0x031", "apple-m2")
+.Case("0x032", "apple-m2")
+.Case("0x033", "apple-m2")
+.Case("0x034", "apple-m2")
+.Case("0x035", "apple-m2")
+.Case("0x038", "apple-m2")
+.Case("0x039", "apple-m2")
+.Case("0x049", "apple-m3")
+.Case("0x048", "apple-m3")
+.Default("generic");
jroelofs wrote:
here's where they're "documented" on our end:
https://github.com/apple-oss-distributions/xnu/blob/main/osfmk/arm/cpuid.h
https://github.com/llvm/llvm-project/pull/119777
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[llvm-branch-commits] TargetParser: AArch64: Add part numbers for Apple CPUs. (PR #119777)
https://github.com/jroelofs approved this pull request. https://github.com/llvm/llvm-project/pull/119777 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [flang] [lld] [llvm] [Flang] LLVM_ENABLE_RUNTIMES=flang-rt (PR #110217)
jeanPerier wrote: Thanks for the detailed explanation about the shared/static library builds! I am in line with your plan of going towards libcxx/libc/libunwind options (FLANG_RT_ENABLE_SHARED/FLANG_RT_ENABLE_STATIC.) I feel that in the short term (this patch) loosing the ability to build shared libs is a bit of a regression, and that it would be nice to have an option to do shared library instead of static (or just let `BUILD_SHARED_LIBS` drives that as it currently does until the options are ready). https://github.com/llvm/llvm-project/pull/110217 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] TargetParser: AArch64: Add part numbers for Apple CPUs. (PR #119777)
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/119777 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] TargetParser: AArch64: Add part numbers for Apple CPUs. (PR #119777)
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/119777 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Reduce AddedComplexity on canonicalize pattern (PR #119796)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/119796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Reduce AddedComplexity on canonicalize pattern (PR #119796)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/119796?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#119796** https://app.graphite.dev/github/pr/llvm/llvm-project/119796?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/119796?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#119795** https://app.graphite.dev/github/pr/llvm/llvm-project/119795?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/119796 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Reduce AddedComplexity on canonicalize pattern (PR #119796)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/119796
Pick the minimum complexity required for tests to pass instead of
a giant debug value of 1000.
>From afdc198444b70ea53322321d1e192db0cdee8110 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 13 Dec 2024 08:49:31 +0900
Subject: [PATCH] AMDGPU: Reduce AddedComplexity on canonicalize pattern
Pick the minimum complexity required for tests to pass instead of
a giant debug value of 1000.
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td
b/llvm/lib/Target/AMDGPU/SIInstructions.td
index bc25d75131cc35..9bd04b939c8a55 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3055,7 +3055,7 @@ def : GCNPat<
(V_BFREV_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$a, sub0))), sub1)>;
// If fcanonicalize's operand is implicitly canonicalized, we only need a copy.
-let AddedComplexity = 1000 in {
+let AddedComplexity = 8 in {
foreach vt = [f16, v2f16, f32, v2f32, f64] in {
def : GCNPat<
(fcanonicalize (vt is_canonicalized:$src)),
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[llvm-branch-commits] [llvm] RegAlloc: Fix failure on undef use when all registers are reserved (PR #119647)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/119647
>From 21a94e80ec529fac5a23febcdf738f01c56d0100 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 12 Dec 2024 10:07:10 +0900
Subject: [PATCH 1/2] RegAlloc: Fix failure on undef use when all registers are
reserved
Greedy and fast would hit different assertions on undef uses if all
registers in a class were reserved.
---
llvm/lib/CodeGen/RegAllocFast.cpp | 15 +++
llvm/lib/CodeGen/RegAllocGreedy.cpp | 2 +-
...an-out-of-registers-error-all-regs-reserved.ll | 10 +-
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp
b/llvm/lib/CodeGen/RegAllocFast.cpp
index 8323a050bcbc4a..87c0636fc45188 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -982,16 +982,23 @@ void RegAllocFastImpl::allocVirtRegUndef(MachineOperand
&MO) {
if (!shouldAllocateRegister(VirtReg))
return;
- LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
+ LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
MCPhysReg PhysReg;
if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
PhysReg = LRI->PhysReg;
} else {
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
ArrayRef AllocationOrder = RegClassInfo.getOrder(&RC);
-// FIXME: This can happen, and should fall back to a reserved entry in RC.
-assert(!AllocationOrder.empty() && "Allocation order must not be empty");
-PhysReg = AllocationOrder[0];
+if (AllocationOrder.empty()) {
+ // All registers in the class were reserved.
+ //
+ // It might be OK to take any entry from the class as this is an undef
+ // use, but accepting this would give different behavior than greedy and
+ // basic.
+ PhysReg = getErrorAssignment(*LRI, *MO.getParent(), RC);
+ LRI->Error = true;
+} else
+ PhysReg = AllocationOrder[0];
}
unsigned SubRegIdx = MO.getSubReg();
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index cb29218e966e06..af48e916feab45 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2465,7 +2465,7 @@ MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval
&VirtReg,
return 0;
}
- if (Stage < RS_Spill) {
+ if (Stage < RS_Spill && !VirtReg.empty()) {
// Try splitting VirtReg or interferences.
unsigned NewVRegSizeBefore = NewVRegs.size();
Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
diff --git
a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
index 05975920ebeb8d..388a8e804a8896 100644
--- a/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
+++ b/llvm/test/CodeGen/AMDGPU/ran-out-of-registers-error-all-regs-reserved.ll
@@ -24,10 +24,10 @@ define <32 x i32>
@no_registers_from_class_available_to_allocate_asm_def() #0 {
ret <32 x i32> %ret
}
-; FIXME: Special case in fast RA, asserts. Also asserts in greedy
-; define void @no_registers_from_class_available_to_allocate_undef_asm() #0 {
-; call void asm sideeffect "; use $0", "v"(<32 x i32> poison)
-; ret void
-; }
+; CHECK: error: :0:0: no registers from class available to allocate
in function 'no_registers_from_class_available_to_allocate_undef_asm'
+define void @no_registers_from_class_available_to_allocate_undef_asm() #0 {
+ call void asm sideeffect "; use $0", "v"(<32 x i32> poison)
+ ret void
+}
attributes #0 = { "amdgpu-waves-per-eu"="10,10" }
>From b1776bc892441450ea4711e7ecae7839821c57df Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 13 Dec 2024 10:00:56 +0900
Subject: [PATCH 2/2] Use .front
---
llvm/lib/CodeGen/RegAllocFast.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp
b/llvm/lib/CodeGen/RegAllocFast.cpp
index 87c0636fc45188..fd3914f864c00c 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -998,7 +998,7 @@ void RegAllocFastImpl::allocVirtRegUndef(MachineOperand
&MO) {
PhysReg = getErrorAssignment(*LRI, *MO.getParent(), RC);
LRI->Error = true;
} else
- PhysReg = AllocationOrder[0];
+ PhysReg = AllocationOrder.front();
}
unsigned SubRegIdx = MO.getSubReg();
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[llvm-branch-commits] [llvm] AMDGPU: Reduce AddedComplexity on canonicalize pattern (PR #119796)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
Pick the minimum complexity required for tests to pass instead of
a giant debug value of 1000.
---
Full diff: https://github.com/llvm/llvm-project/pull/119796.diff
1 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+1-1)
``diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td
b/llvm/lib/Target/AMDGPU/SIInstructions.td
index bc25d75131cc35..9bd04b939c8a55 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3055,7 +3055,7 @@ def : GCNPat<
(V_BFREV_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$a, sub0))), sub1)>;
// If fcanonicalize's operand is implicitly canonicalized, we only need a copy.
-let AddedComplexity = 1000 in {
+let AddedComplexity = 8 in {
foreach vt = [f16, v2f16, f32, v2f32, f64] in {
def : GCNPat<
(fcanonicalize (vt is_canonicalized:$src)),
``
https://github.com/llvm/llvm-project/pull/119796
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[llvm-branch-commits] [llvm] [Statepoint] Treat undef operands less specially (PR #119682)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/119682
>From 9af0962247e83d3d270aedf35084f73f17cbc77a Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 28 Mar 2022 14:11:28 -0400
Subject: [PATCH] [Statepoint] Treat undef operands less specially
This reverts commit f7443905af1e06eaacda1e437fff8d54dc89c487.
This is to avoid an assertion if an undef operand appears in a
stackmap. This is important to avoid hitting verifier errors
when register allocation starts adding undefs in error scenarios.
Rather than trying to treat undef operands as special, leave them
alone and avoid producing an invalid spill. It would a bit more
precise to produce a spill of an undef register here, but that's not
exposed through the storeRegToStackSlot API.
https://reviews.llvm.org/D122605
This was an alternative to https://reviews.llvm.org/D122582
---
.../CodeGen/FixupStatepointCallerSaved.cpp| 2 -
llvm/lib/CodeGen/StackMaps.cpp| 6 --
.../X86/stackmap-undef-operand-anyregcc.mir | 77 +++
.../CodeGen/X86/statepoint-fixup-undef.mir| 8 +-
4 files changed, 81 insertions(+), 12 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
index 3bb9da5f1a37bb..0ebe845e473fd6 100644
--- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
+++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
@@ -381,8 +381,6 @@ class StatepointState {
EndIdx = MI.getNumOperands();
Idx < EndIdx; ++Idx) {
MachineOperand &MO = MI.getOperand(Idx);
- // Leave `undef` operands as is, StackMaps will rewrite them
- // into a constant.
if (!MO.isReg() || MO.isImplicit() || MO.isUndef())
continue;
Register Reg = MO.getReg();
diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp
index 81b288df3b07e0..7480963c1f5217 100644
--- a/llvm/lib/CodeGen/StackMaps.cpp
+++ b/llvm/lib/CodeGen/StackMaps.cpp
@@ -268,12 +268,6 @@ StackMaps::parseOperand(MachineInstr::const_mop_iterator
MOI,
if (MOI->isImplicit())
return ++MOI;
-if (MOI->isUndef()) {
- // Record `undef` register as constant. Use same value as ISel uses.
- Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, 0xFEFEFEFE);
- return ++MOI;
-}
-
assert(MOI->getReg().isPhysical() &&
"Virtreg operands should have been rewritten before now.");
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());
diff --git a/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
b/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
new file mode 100644
index 00..3c6390ba2379c8
--- /dev/null
+++ b/llvm/test/CodeGen/X86/stackmap-undef-operand-anyregcc.mir
@@ -0,0 +1,77 @@
+# RUN: llc -mtriple=x86_64-apple-darwin -start-after=virtregrewriter -o - %s |
FileCheck %s
+
+# Check there's no assertion for anyregcc with an undef operand to a stackmap.
+
+# CHECK: __LLVM_StackMaps:
+# CHECK-NEXT: .byte3
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long1
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .long1
+# CHECK-NEXT: .quad_undef_anyregcc_patchpoint
+# CHECK-NEXT: .quad8
+# CHECK-NEXT: .quad1
+# CHECK-NEXT: .quad12
+# CHECK-NEXT: .longLtmp0-_undef_anyregcc_patchpoint
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 2
+# CHECK-NEXT: .byte1
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 8
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .byte1
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .short 8
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .long0
+# CHECK-NEXT: .p2align 3, 0x0
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .short 7
+# CHECK-NEXT: .short 0
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 3
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 7
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 12
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 13
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 14
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .short 15
+# CHECK-NEXT: .byte0
+# CHECK-NEXT: .byte8
+# CHECK-NEXT: .p2align 3
+---
+name: undef_anyregcc_patchpoint
+tracksRegLiveness: true
+frameInfo:
+ hasPatchPoint: true
+ hasCalls:true
+ adjustsStack:true
+fixedStack:
+ - { id: 0, type: default, offset: 72, size: 8, alignment: 8, stack-id:
default,
+ isImmutable: true, isAliased: false, callee-saved-register: '',
callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+body: |
+ bb.0:
+liveins: $rcx, $rdi, $rdx, $rsi, $r8, $r9
[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/119684
>From c56e320b410a50791b006dd75c48ff74c89a735d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 28 Mar 2022 11:24:48 -0400
Subject: [PATCH 1/2] AMDGPU: Delete spills of undef values
It would be a bit more logical to preserve the undef and do the normal
expansion, but this is less work. This avoids verifier errors in a
future patch which starts deleting liveness from registers after
allocation failures which results in spills of undef values.
https://reviews.llvm.org/D122607
---
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 12 ++
.../AMDGPU/sgpr-spill-partially-undef.mir | 42 +++
.../AMDGPU/spill-agpr-partially-undef.mir | 34 +++
llvm/test/CodeGen/AMDGPU/vgpr-spill.mir | 34 +++
4 files changed, 122 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 296c32fa4e0d09..4f8c5c6756b3bb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1954,6 +1954,13 @@ bool
SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
RegScavenger *RS, SlotIndexes *Indexes,
LiveIntervals *LIS, bool OnlyToVGPR,
bool SpillToPhysVGPRLane) const {
+ if (MI->getOperand(0).isUndef()) {
+if (Indexes)
+ Indexes->removeMachineInstrFromMaps(*MI);
+MI->eraseFromParent();
+return true;
+ }
+
SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS);
ArrayRef VGPRSpills =
@@ -2375,6 +2382,11 @@ bool
SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
case AMDGPU::SI_SPILL_WWM_AV32_SAVE: {
const MachineOperand *VData = TII->getNamedOperand(*MI,
AMDGPU::OpName::vdata);
+ if (VData->isUndef()) {
+MI->eraseFromParent();
+return true;
+ }
+
assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
MFI->getStackPtrOffsetReg());
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
b/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
index 774785fb3966fc..d352e8a13da9f1 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
@@ -54,3 +54,45 @@ body: |
SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec,
implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into
%stack.0, align 4, addrspace 5)
...
+
+---
+name: sgpr_spill_s32_undef
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+ hasSpilledSGPRs: true
+ scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
+ stackPtrOffsetReg: '$sgpr32'
+stack:
+ - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
+body: |
+ bb.0:
+; CHECK-LABEL: name: sgpr_spill_s32_undef
+; CHECK: body:
+; CHECK-NEXT: bb.0:
+; CHECK-NOT: {{.+}}
+; CHECK: ...
+SI_SPILL_S32_SAVE undef $sgpr8, %stack.0, implicit $exec, implicit
$sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s32) into %stack.0,
align 4, addrspace 5)
+
+...
+
+---
+name: sgpr_spill_s64_undef
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+ hasSpilledSGPRs: true
+ scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
+ stackPtrOffsetReg: '$sgpr32'
+stack:
+ - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
+body: |
+ bb.0:
+; CHECK-LABEL: name: sgpr_spill_s64_undef
+; CHECK: body:
+; CHECK-NEXT: bb.0:
+; CHECK-NOT: {{.+}}
+; CHECK: ...
+SI_SPILL_S64_SAVE undef $sgpr8_sgpr9, %stack.0, implicit $exec, implicit
$sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into %stack.0,
align 4, addrspace 5)
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
index c825674de7652c..b02b6e79d7a76f 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
@@ -71,3 +71,37 @@ body: |
; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0,
$sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed
$agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5)
SI_SPILL_A64_SAVE killed $agpr0_agpr1, %stack.0, $sgpr32, 0, implicit
$exec :: (store (s64) into %stack.0, addrspace 5)
...
+
+---
+name: spill_a32_undef
+tracksRegLiveness: true
+stack:
+ - { id: 0, type: spill-slot, size: 4, alignment: 4 }
+machineFunctionInfo:
+ scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
+ stackPtrOffsetReg: '$sgpr32'
+ frameOffsetReg: '$sgpr33'
+body: |
+ bb.0:
+; CHECK-LABEL: na
[llvm-branch-commits] [llvm] RegAlloc: Fix verifier error after failed allocation (PR #119690)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/119690
>From 4ef1f6eb46bc892a01e91dae9b6effd94827a32b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 25 Mar 2022 20:27:39 -0400
Subject: [PATCH] RegAlloc: Fix verifier error after failed allocation
In some cases after reporting an allocation failure, this would fail
the verifier. It picks the first allocatable register and assigns it,
but didn't update the liveness appropriately. When VirtRegRewriter
relied on the liveness to set kill flags, it would incorrectly add
kill flags if there was another overlapping kill of the virtual
register.
We can't properly assign the register to an overlapping range, so
break the liveness of the failing register (and any other interfering
registers) instead. Give the virtual register dummy liveness by
effectively deleting all the uses by setting them to undef.
The edge case not tested here which I'm worried about is if the read
of the register is a def of a subregister. I've been unable to come up
with a test where this occurs.
https://reviews.llvm.org/D122616
---
llvm/lib/CodeGen/RegAllocBase.cpp | 36 +++
llvm/lib/CodeGen/RegAllocBase.h | 6 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 1 +
llvm/lib/CodeGen/RegAllocGreedy.cpp | 1 +
.../AMDGPU/illegal-eviction-assert.mir| 4 +-
llvm/test/CodeGen/AMDGPU/issue48473.mir | 3 +-
...ut-of-registers-error-all-regs-reserved.ll | 8 +--
...lloc-failure-overlapping-insert-assert.mir | 7 +--
...ster-killed-error-after-alloc-failure0.mir | 59 +++
...ister-killed-error-after-alloc-failure1.ll | 30 ++
.../remaining-virtual-register-operands.ll| 3 +-
11 files changed, 143 insertions(+), 15 deletions(-)
create mode 100644
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
create mode 100644
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp
b/llvm/lib/CodeGen/RegAllocBase.cpp
index 980a6756963d9f..bb0c8a32a7bc92 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -65,6 +65,7 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
Matrix = &mat;
MRI->freezeReservedRegs();
RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
+ FailedVRegs.clear();
}
// Visit all the live registers. If they are already assigned to a physical
@@ -128,6 +129,7 @@ void RegAllocBase::allocatePhysRegs() {
// Keep going after reporting the error.
VRM->assignVirt2Phys(VirtReg->reg(), AvailablePhysReg);
+ FailedVRegs.insert(VirtReg->reg());
} else if (AvailablePhysReg)
Matrix->assign(*VirtReg, AvailablePhysReg);
@@ -161,6 +163,40 @@ void RegAllocBase::postOptimization() {
DeadRemats.clear();
}
+void RegAllocBase::cleanupFailedVRegs() {
+ SmallSet JunkRegs;
+
+ for (Register FailedReg : FailedVRegs) {
+JunkRegs.insert(FailedReg);
+
+MCRegister PhysReg = VRM->getPhys(FailedReg);
+LiveInterval &FailedInterval = LIS->getInterval(FailedReg);
+
+// The liveness information for the failed register and anything
interfering
+// with the physical register we arbitrarily chose is junk and needs to be
+// deleted.
+for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
+ LiveIntervalUnion::Query &Q = Matrix->query(FailedInterval, *Units);
+ for (const LiveInterval *InterferingReg : Q.interferingVRegs())
+JunkRegs.insert(InterferingReg->reg());
+}
+ }
+
+ // TODO: Probably need to set undef on any physreg uses not associated with
+ // a virtual register.
+ for (Register JunkReg : JunkRegs) {
+// We still should produce valid IR. Kill all the uses and reduce the live
+// ranges so that we don't think it's possible to introduce kill flags
+// later which will fail the verifier.
+for (MachineOperand &MO : MRI->reg_operands(JunkReg)) {
+ if (MO.readsReg())
+MO.setIsUndef(true);
+}
+
+LIS->shrinkToUses(&LIS->getInterval(JunkReg));
+ }
+}
+
void RegAllocBase::enqueue(const LiveInterval *LI) {
const Register Reg = LI->reg();
diff --git a/llvm/lib/CodeGen/RegAllocBase.h b/llvm/lib/CodeGen/RegAllocBase.h
index 5bd52da61f2dc5..1fdbab694bb0e3 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/lib/CodeGen/RegAllocBase.h
@@ -37,6 +37,7 @@
#define LLVM_LIB_CODEGEN_REGALLOCBASE_H
#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocCommon.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -81,6 +82,7 @@ class RegAllocBase {
/// always available for the remat of all the siblings of the original reg.
SmallPtrSet DeadRemats;
+ SmallSet FailedVRegs;
RegAllocBase(const RegAllocFilterFunc F = nullptr)
: shouldAllocateRegisterImpl(F) {}
@@ -104,6 +106,10 @@ class RegA
[llvm-branch-commits] [llvm] RegAlloc: Fix verifier error after failed allocation (PR #119690)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/119690
>From 060a3a68654f59548c0ae5e915c559384a774947 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 25 Mar 2022 20:27:39 -0400
Subject: [PATCH] RegAlloc: Fix verifier error after failed allocation
In some cases after reporting an allocation failure, this would fail
the verifier. It picks the first allocatable register and assigns it,
but didn't update the liveness appropriately. When VirtRegRewriter
relied on the liveness to set kill flags, it would incorrectly add
kill flags if there was another overlapping kill of the virtual
register.
We can't properly assign the register to an overlapping range, so
break the liveness of the failing register (and any other interfering
registers) instead. Give the virtual register dummy liveness by
effectively deleting all the uses by setting them to undef.
The edge case not tested here which I'm worried about is if the read
of the register is a def of a subregister. I've been unable to come up
with a test where this occurs.
https://reviews.llvm.org/D122616
---
llvm/lib/CodeGen/RegAllocBase.cpp | 36 +++
llvm/lib/CodeGen/RegAllocBase.h | 6 ++
llvm/lib/CodeGen/RegAllocBasic.cpp| 1 +
llvm/lib/CodeGen/RegAllocGreedy.cpp | 1 +
.../AMDGPU/illegal-eviction-assert.mir| 4 +-
llvm/test/CodeGen/AMDGPU/issue48473.mir | 3 +-
...ut-of-registers-error-all-regs-reserved.ll | 8 +--
...lloc-failure-overlapping-insert-assert.mir | 7 +--
...ster-killed-error-after-alloc-failure0.mir | 59 +++
...ister-killed-error-after-alloc-failure1.ll | 30 ++
.../remaining-virtual-register-operands.ll| 3 +-
llvm/test/CodeGen/X86/inline-asm-assertion.ll | 2 +-
12 files changed, 144 insertions(+), 16 deletions(-)
create mode 100644
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
create mode 100644
llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure1.ll
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp
b/llvm/lib/CodeGen/RegAllocBase.cpp
index 980a6756963d9f..bb0c8a32a7bc92 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -65,6 +65,7 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
Matrix = &mat;
MRI->freezeReservedRegs();
RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
+ FailedVRegs.clear();
}
// Visit all the live registers. If they are already assigned to a physical
@@ -128,6 +129,7 @@ void RegAllocBase::allocatePhysRegs() {
// Keep going after reporting the error.
VRM->assignVirt2Phys(VirtReg->reg(), AvailablePhysReg);
+ FailedVRegs.insert(VirtReg->reg());
} else if (AvailablePhysReg)
Matrix->assign(*VirtReg, AvailablePhysReg);
@@ -161,6 +163,40 @@ void RegAllocBase::postOptimization() {
DeadRemats.clear();
}
+void RegAllocBase::cleanupFailedVRegs() {
+ SmallSet JunkRegs;
+
+ for (Register FailedReg : FailedVRegs) {
+JunkRegs.insert(FailedReg);
+
+MCRegister PhysReg = VRM->getPhys(FailedReg);
+LiveInterval &FailedInterval = LIS->getInterval(FailedReg);
+
+// The liveness information for the failed register and anything
interfering
+// with the physical register we arbitrarily chose is junk and needs to be
+// deleted.
+for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
+ LiveIntervalUnion::Query &Q = Matrix->query(FailedInterval, *Units);
+ for (const LiveInterval *InterferingReg : Q.interferingVRegs())
+JunkRegs.insert(InterferingReg->reg());
+}
+ }
+
+ // TODO: Probably need to set undef on any physreg uses not associated with
+ // a virtual register.
+ for (Register JunkReg : JunkRegs) {
+// We still should produce valid IR. Kill all the uses and reduce the live
+// ranges so that we don't think it's possible to introduce kill flags
+// later which will fail the verifier.
+for (MachineOperand &MO : MRI->reg_operands(JunkReg)) {
+ if (MO.readsReg())
+MO.setIsUndef(true);
+}
+
+LIS->shrinkToUses(&LIS->getInterval(JunkReg));
+ }
+}
+
void RegAllocBase::enqueue(const LiveInterval *LI) {
const Register Reg = LI->reg();
diff --git a/llvm/lib/CodeGen/RegAllocBase.h b/llvm/lib/CodeGen/RegAllocBase.h
index 5bd52da61f2dc5..1fdbab694bb0e3 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/lib/CodeGen/RegAllocBase.h
@@ -37,6 +37,7 @@
#define LLVM_LIB_CODEGEN_REGALLOCBASE_H
#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocCommon.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -81,6 +82,7 @@ class RegAllocBase {
/// always available for the remat of all the siblings of the original reg.
SmallPtrSet DeadRemats;
+ SmallSet FailedVRegs;
RegAllocBase(const RegAllocFilterFunc F = nullptr)
: shouldAlloc
[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
https://github.com/cdevadas approved this pull request. https://github.com/llvm/llvm-project/pull/119684 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 1f125e3 - Revert "[SLP] Make getSameOpcode support different instructions if they have …"
Author: Han-Kuan Chen
Date: 2024-12-13T12:20:43+08:00
New Revision: 1f125e3075e254918a2742992f458806523c01a3
URL:
https://github.com/llvm/llvm-project/commit/1f125e3075e254918a2742992f458806523c01a3
DIFF:
https://github.com/llvm/llvm-project/commit/1f125e3075e254918a2742992f458806523c01a3.diff
LOG: Revert "[SLP] Make getSameOpcode support different instructions if they
have …"
This reverts commit 82204154b7bd1f8c487c94c7ef00399d776b29f0.
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/test/Transforms/SLPVectorizer/AArch64/vec3-base.ll
llvm/test/Transforms/SLPVectorizer/RISCV/reversed-strided-node-with-external-ptr.ll
llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
llvm/test/Transforms/SLPVectorizer/X86/barriercall.ll
llvm/test/Transforms/SLPVectorizer/X86/bottom-to-top-reorder.ll
llvm/test/Transforms/SLPVectorizer/X86/extract-scalar-from-undef.ll
llvm/test/Transforms/SLPVectorizer/X86/extractcost.ll
llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll
llvm/test/Transforms/SLPVectorizer/X86/multi-extracts-bv-combined.ll
llvm/test/Transforms/SLPVectorizer/X86/vec3-base.ll
llvm/test/Transforms/SLPVectorizer/alternate-opcode-sindle-bv.ll
llvm/test/Transforms/SLPVectorizer/resized-alt-shuffle-after-minbw.ll
llvm/test/Transforms/SLPVectorizer/shuffle-mask-resized.ll
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index f1391ae93c8630..0e11e8704db2f2 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -842,123 +842,8 @@ class InstructionsState {
static InstructionsState invalid() { return {nullptr, nullptr}; }
};
-struct InterchangeableInstruction {
- unsigned Opcode;
- SmallVector Ops;
- template
- InterchangeableInstruction(unsigned Opcode, ArgTypes &&...Args)
- : Opcode(Opcode), Ops{std::forward(Args)...} {}
-};
-
-bool operator<(const InterchangeableInstruction &LHS,
- const InterchangeableInstruction &RHS) {
- return LHS.Opcode < RHS.Opcode;
-}
-
} // end anonymous namespace
-/// \returns a sorted list of interchangeable instructions by instruction
opcode
-/// that \p I can be converted to.
-/// e.g.,
-/// x << y -> x * (2^y)
-/// x << 1 -> x * 2
-/// x << 0 -> x * 1 -> x - 0 -> x + 0 -> x & 11...1 -> x | 0
-/// x * 0 -> x & 0
-/// x * -1 -> 0 - x
-/// TODO: support more patterns
-static SmallVector
-getInterchangeableInstruction(Instruction *I) {
- // PII = Possible Interchangeable Instruction
- SmallVector PII;
- unsigned Opcode = I->getOpcode();
- PII.emplace_back(Opcode, I->operands());
- if (!is_contained({Instruction::Shl, Instruction::Mul, Instruction::Sub,
- Instruction::Add},
-Opcode))
-return PII;
- Constant *C;
- if (match(I, m_BinOp(m_Value(), m_Constant(C {
-ConstantInt *V = nullptr;
-if (auto *CI = dyn_cast(C)) {
- V = CI;
-} else if (auto *CDV = dyn_cast(C)) {
- if (auto *CI = dyn_cast_if_present(CDV->getSplatValue()))
-V = CI;
-}
-if (!V)
- return PII;
-Value *Op0 = I->getOperand(0);
-Type *Op1Ty = I->getOperand(1)->getType();
-const APInt &Op1Int = V->getValue();
-Constant *Zero =
-ConstantInt::get(Op1Ty, APInt::getZero(Op1Int.getBitWidth()));
-Constant *UnsignedMax =
-ConstantInt::get(Op1Ty, APInt::getMaxValue(Op1Int.getBitWidth()));
-switch (Opcode) {
-case Instruction::Shl: {
- PII.emplace_back(Instruction::Mul, Op0,
- ConstantInt::get(Op1Ty, 1 << Op1Int.getZExtValue()));
- if (Op1Int.isZero()) {
-PII.emplace_back(Instruction::Sub, Op0, Zero);
-PII.emplace_back(Instruction::Add, Op0, Zero);
-PII.emplace_back(Instruction::And, Op0, UnsignedMax);
-PII.emplace_back(Instruction::Or, Op0, Zero);
- }
- break;
-}
-case Instruction::Mul: {
- if (Op1Int.isOne()) {
-PII.emplace_back(Instruction::Sub, Op0, Zero);
-PII.emplace_back(Instruction::Add, Op0, Zero);
-PII.emplace_back(Instruction::And, Op0, UnsignedMax);
-PII.emplace_back(Instruction::Or, Op0, Zero);
- } else if (Op1Int.isZero()) {
-PII.emplace_back(Instruction::And, Op0, Zero);
- } else if (Op1Int.isAllOnes()) {
-PII.emplace_back(Instruction::Sub, Zero, Op0);
- }
- break;
-}
-case Instruction::Sub:
- if (Op1Int.isZero()) {
-PII.emplace_back(Instruction::Add, Op0, Zero);
-PII.emplace_back(Instruction::And, Op0, UnsignedMax);
-PII.emplace_back(Instruction::Or, Op0, Zero);
- }
- break;
-case Instruction::Add:
- if (Op1Int.isZero()) {
-PII.emplace_back(Instru
[llvm-branch-commits] [clang-doc][NFC] Make test resilient to line changes (PR #119811)
https://github.com/ilovepi created https://github.com/llvm/llvm-project/pull/119811 This just reorganizes the test code, so its easy to use @LINE directives in the test, and avoid needing to update all the line numbers when making unrelated changes. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-doc] Precommit test case for functions with templated parameters and return (PR #119814)
https://github.com/ilovepi created https://github.com/llvm/llvm-project/pull/119814 To address #67549 we need a test case that will show up in the markdown output for functions. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-doc] Add tests for Markdown output with C++ templates (PR #119813)
https://github.com/ilovepi created https://github.com/llvm/llvm-project/pull/119813 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-doc][NFC] Make test resilient to line changes (PR #119811)
llvmbot wrote:
@llvm/pr-subscribers-clang-tools-extra
Author: Paul Kirth (ilovepi)
Changes
This just reorganizes the test code, so its easy to use @LINE directives
in the test, and avoid needing to update all the line numbers when making
unrelated changes.
---
Full diff: https://github.com/llvm/llvm-project/pull/119811.diff
1 Files Affected:
- (modified) clang-tools-extra/test/clang-doc/templates.cpp (+14-10)
``diff
diff --git a/clang-tools-extra/test/clang-doc/templates.cpp
b/clang-tools-extra/test/clang-doc/templates.cpp
index d5a9e7d201e1e5..1adfbe0cf18282 100644
--- a/clang-tools-extra/test/clang-doc/templates.cpp
+++ b/clang-tools-extra/test/clang-doc/templates.cpp
@@ -6,22 +6,17 @@
// RUN: cat %t/docs/index.yaml | FileCheck %s --check-prefix=YAML
// RUN: rm -rf %t
-template
-void function(T x) {}
-
-template<>
-void function(bool x) {}
+// YAML: ---
+// YAML-NEXT: USR: '{{([0-9A-F]{40})}}'
template
void ParamPackFunction(T... args);
-// YAML: ---
-// YAML-NEXT: USR: '{{([0-9A-F]{40})}}'
// YAML-NEXT: ChildFunctions:
// YAML-NEXT: - USR: '{{([0-9A-F]{40})}}'
// YAML-NEXT:Name:'ParamPackFunction'
// YAML-NEXT:Location:
-// YAML-NEXT: - LineNumber: 16
+// YAML-NEXT: - LineNumber: [[# @LINE - 6]]
// YAML-NEXT:Filename:'{{.*}}'
// YAML-NEXT:Params:
// YAML-NEXT: - Type:
@@ -35,10 +30,14 @@ void ParamPackFunction(T... args);
// YAML-NEXT:Template:
// YAML-NEXT: Params:
// YAML-NEXT:- Contents:'class... T'
+
+template
+void function(T x) {}
+
// YAML-NEXT: - USR: '{{([0-9A-F]{40})}}'
// YAML-NEXT: Name:'function'
// YAML-NEXT: DefLocation:
-// YAML-NEXT: LineNumber: 10
+// YAML-NEXT: LineNumber: [[# @LINE - 5]]
// YAML-NEXT: Filename:'{{.*}}'
// YAML-NEXT: Params:
// YAML-NEXT: - Type:
@@ -53,10 +52,14 @@ void ParamPackFunction(T... args);
// YAML-NEXT: Params:
// YAML-NEXT: - Contents:'typename T'
// YAML-NEXT: - Contents:'int U = 1'
+
+template<>
+void function(bool x) {}
+
// YAML-NEXT: - USR: '{{([0-9A-F]{40})}}'
// YAML-NEXT: Name:'function'
// YAML-NEXT: DefLocation:
-// YAML-NEXT: LineNumber: 12
+// YAML-NEXT: LineNumber: [[# @LINE - 6]]
// YAML-NEXT: Filename:'{{.*}}'
// YAML-NEXT: Params:
// YAML-NEXT: - Type:
@@ -74,3 +77,4 @@ void ParamPackFunction(T... args);
// YAML-NEXT: - Contents:'bool'
// YAML-NEXT: - Contents:'0'
// YAML-NEXT: ...
+
``
https://github.com/llvm/llvm-project/pull/119811
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[llvm-branch-commits] [clang-doc][NFC] Avoid unnecessary operations in the template test (PR #119812)
llvmbot wrote:
@llvm/pr-subscribers-clang-tools-extra
Author: Paul Kirth (ilovepi)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/119812.diff
1 Files Affected:
- (modified) clang-tools-extra/test/clang-doc/templates.cpp (+1-4)
``diff
diff --git a/clang-tools-extra/test/clang-doc/templates.cpp
b/clang-tools-extra/test/clang-doc/templates.cpp
index 1adfbe0cf18282..05a3dab71f48a1 100644
--- a/clang-tools-extra/test/clang-doc/templates.cpp
+++ b/clang-tools-extra/test/clang-doc/templates.cpp
@@ -1,10 +1,7 @@
// RUN: rm -rf %t
// RUN: mkdir %t
-// RUN: echo "" > %t/compile_flags.txt
-// RUN: cp "%s" "%t/test.cpp"
-// RUN: clang-doc --doxygen --executor=standalone -p %t %t/test.cpp
-output=%t/docs
+// RUN: clang-doc --doxygen --executor=standalone %s -output=%t/docs
// RUN: cat %t/docs/index.yaml | FileCheck %s --check-prefix=YAML
-// RUN: rm -rf %t
// YAML: ---
// YAML-NEXT: USR: '{{([0-9A-F]{40})}}'
``
https://github.com/llvm/llvm-project/pull/119812
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[llvm-branch-commits] [clang-doc] Add tests for Markdown output with C++ templates (PR #119813)
llvmbot wrote:
@llvm/pr-subscribers-clang-tools-extra
Author: Paul Kirth (ilovepi)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/119813.diff
1 Files Affected:
- (modified) clang-tools-extra/test/clang-doc/templates.cpp (+19)
``diff
diff --git a/clang-tools-extra/test/clang-doc/templates.cpp
b/clang-tools-extra/test/clang-doc/templates.cpp
index 05a3dab71f48a1..536b24161990aa 100644
--- a/clang-tools-extra/test/clang-doc/templates.cpp
+++ b/clang-tools-extra/test/clang-doc/templates.cpp
@@ -1,11 +1,18 @@
// RUN: rm -rf %t
// RUN: mkdir %t
+
// RUN: clang-doc --doxygen --executor=standalone %s -output=%t/docs
// RUN: cat %t/docs/index.yaml | FileCheck %s --check-prefix=YAML
+// RUN: clang-doc --doxygen --executor=standalone %s -output=%t/docs
--format=md
+// RUN: cat %t/docs/GlobalNamespace/index.md | FileCheck %s --check-prefix=MD
+
// YAML: ---
// YAML-NEXT: USR: '{{([0-9A-F]{40})}}'
+// MD: # Global Namespace
+// MD: ## Functions
+
template
void ParamPackFunction(T... args);
@@ -28,6 +35,9 @@ void ParamPackFunction(T... args);
// YAML-NEXT: Params:
// YAML-NEXT:- Contents:'class... T'
+// MD: ### ParamPackFunction
+// MD: *void ParamPackFunction(T... args)*
+
template
void function(T x) {}
@@ -50,6 +60,10 @@ void function(T x) {}
// YAML-NEXT: - Contents:'typename T'
// YAML-NEXT: - Contents:'int U = 1'
+// MD: ### function
+// MD: *void function(T x)*
+// MD: *Defined at {{.*}}templates.cpp#[[# @LINE - 23]]*
+
template<>
void function(bool x) {}
@@ -75,3 +89,8 @@ void function(bool x) {}
// YAML-NEXT: - Contents:'0'
// YAML-NEXT: ...
+// MD: ### function
+// MD: *void function(_Bool x)*
+// MD: *Defined at {{.*}}templates.cpp#[[# @LINE - 27]]*
+
+
``
https://github.com/llvm/llvm-project/pull/119813
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[llvm-branch-commits] [clang-doc] Precommit test case for functions with templated parameters and return (PR #119814)
llvmbot wrote:
@llvm/pr-subscribers-clang-tools-extra
Author: Paul Kirth (ilovepi)
Changes
To address #67549 we need a test case that will show up in the markdown
output for functions.
---
Full diff: https://github.com/llvm/llvm-project/pull/119814.diff
1 Files Affected:
- (modified) clang-tools-extra/test/clang-doc/templates.cpp (+62-2)
``diff
diff --git a/clang-tools-extra/test/clang-doc/templates.cpp
b/clang-tools-extra/test/clang-doc/templates.cpp
index 536b24161990aa..bf6528437b6ba9 100644
--- a/clang-tools-extra/test/clang-doc/templates.cpp
+++ b/clang-tools-extra/test/clang-doc/templates.cpp
@@ -9,6 +9,12 @@
// YAML: ---
// YAML-NEXT: USR: '{{([0-9A-F]{40})}}'
+// YAML-NEXT: ChildRecords:
+// YAML-NEXT: - Type:Record
+// YAML-NEXT: Name:'tuple'
+// YAML-NEXT: QualName:'tuple'
+// YAML-NEXT: USR: '{{([0-9A-F]{40})}}'
+// YAML-NEXT: Path:'GlobalNamespace'
// MD: # Global Namespace
// MD: ## Functions
@@ -87,10 +93,64 @@ void function(bool x) {}
// YAML-NEXT: Params:
// YAML-NEXT: - Contents:'bool'
// YAML-NEXT: - Contents:'0'
-// YAML-NEXT: ...
// MD: ### function
// MD: *void function(_Bool x)*
-// MD: *Defined at {{.*}}templates.cpp#[[# @LINE - 27]]*
+// MD: *Defined at {{.*}}templates.cpp#[[# @LINE - 26]]*
+
+/// A Tuple type
+///
+/// Does nothing.
+template
+struct tuple{};
+
+/// A function with a tuple parameter
+///
+/// \param t The input to func_with_tuple_param
+tuple func_with_tuple_param(tuple t){ return t;}
+// YAML-NEXT: - USR: '{{([0-9A-F]{40})}}'
+// YAML-NEXT:Name:'func_with_tuple_param'
+// YAML-NEXT:Description:
+// YAML-NEXT: - Kind:'FullComment'
+// YAML-NEXT:Children:
+// YAML-NEXT: - Kind:'ParagraphComment'
+// YAML-NEXT:Children:
+// YAML-NEXT: - Kind:'TextComment'
+// YAML-NEXT:Text:' A function with a tuple
parameter'
+// YAML-NEXT: - Kind:'ParagraphComment'
+// YAML-NEXT:Children:
+// YAML-NEXT: - Kind:'TextComment'
+// YAML-NEXT: - Kind:'ParamCommandComment'
+// YAML-NEXT:Direction: '[in]'
+// YAML-NEXT:ParamName: 't'
+// YAML-NEXT:Children:
+// YAML-NEXT: - Kind:'ParagraphComment'
+// YAML-NEXT:Children:
+// YAML-NEXT: - Kind:'TextComment'
+// YAML-NEXT:Text:' The input to
func_with_tuple_param'
+// YAML-NEXT:DefLocation:
+// YAML-NEXT: LineNumber: [[# @LINE - 23]]
+// YAML-NEXT: Filename:
+// YAML-NEXT:Params:
+// YAML-NEXT: - Type:
+// YAML-NEXT: Type:Record
+// YAML-NEXT: Name:'tuple'
+// YAML-NEXT: QualName:'tuple'
+// YAML-NEXT: USR: '{{([0-9A-F]{40})}}'
+// YAML-NEXT: Path:'GlobalNamespace'
+// YAML-NEXT:Name:'t'
+// YAML-NEXT:ReturnType:
+// YAML-NEXT: Type:
+// YAML-NEXT:Type:Record
+// YAML-NEXT:Name:'tuple'
+// YAML-NEXT:QualName:'tuple'
+// YAML-NEXT:USR: '{{([0-9A-F]{40})}}'
+// YAML-NEXT:Path:'GlobalNamespace'
+// YAML-NEXT: ...
+// MD: ### func_with_tuple_param
+// MD: *tuple func_with_tuple_param(tuple t)*
+// MD: *Defined at {{.*}}templates.cpp#[[# @LINE - 44]]*
+// MD: A function with a tuple parameter
+// MD: **t** The input to func_with_tuple_param
``
https://github.com/llvm/llvm-project/pull/119814
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[llvm-branch-commits] [clang-doc] Use QualName in Markdown output (PR #119815)
https://github.com/ilovepi created https://github.com/llvm/llvm-project/pull/119815 QualName will provide the more useful typename when the type is templated. Fixes #67549 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-doc][NFC] Avoid unnecessary operations in the template test (PR #119812)
https://github.com/ilovepi created https://github.com/llvm/llvm-project/pull/119812 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-doc] Use QualName in Markdown output (PR #119815)
llvmbot wrote:
@llvm/pr-subscribers-clang-tools-extra
Author: Paul Kirth (ilovepi)
Changes
QualName will provide the more useful typename when the type is
templated.
Fixes #67549
---
Full diff: https://github.com/llvm/llvm-project/pull/119815.diff
2 Files Affected:
- (modified) clang-tools-extra/clang-doc/MDGenerator.cpp (+3-3)
- (modified) clang-tools-extra/test/clang-doc/templates.cpp (+1-1)
``diff
diff --git a/clang-tools-extra/clang-doc/MDGenerator.cpp
b/clang-tools-extra/clang-doc/MDGenerator.cpp
index 795eb4b904e3ef..00c6605725dae9 100644
--- a/clang-tools-extra/clang-doc/MDGenerator.cpp
+++ b/clang-tools-extra/clang-doc/MDGenerator.cpp
@@ -157,17 +157,17 @@ static void genMarkdown(const ClangDocContext &CDCtx,
const FunctionInfo &I,
for (const auto &N : I.Params) {
if (!First)
Stream << ", ";
-Stream << N.Type.Name + " " + N.Name;
+Stream << N.Type.QualName + " " + N.Name;
First = false;
}
writeHeader(I.Name, 3, OS);
std::string Access = getAccessSpelling(I.Access).str();
if (Access != "")
-writeLine(genItalic(Access + " " + I.ReturnType.Type.Name + " " + I.Name +
+writeLine(genItalic(Access + " " + I.ReturnType.Type.QualName + " " +
I.Name +
"(" + Stream.str() + ")"),
OS);
else
-writeLine(genItalic(I.ReturnType.Type.Name + " " + I.Name + "(" +
+writeLine(genItalic(I.ReturnType.Type.QualName + " " + I.Name + "(" +
Stream.str() + ")"),
OS);
if (I.DefLoc)
diff --git a/clang-tools-extra/test/clang-doc/templates.cpp
b/clang-tools-extra/test/clang-doc/templates.cpp
index bf6528437b6ba9..b5590a92e7524c 100644
--- a/clang-tools-extra/test/clang-doc/templates.cpp
+++ b/clang-tools-extra/test/clang-doc/templates.cpp
@@ -150,7 +150,7 @@ tuple
func_with_tuple_param(tuple t){ return t;}
// YAML-NEXT: ...
// MD: ### func_with_tuple_param
-// MD: *tuple func_with_tuple_param(tuple t)*
+// MD: *tuple func_with_tuple_param(tuple t)*
// MD: *Defined at {{.*}}templates.cpp#[[# @LINE - 44]]*
// MD: A function with a tuple parameter
// MD: **t** The input to func_with_tuple_param
``
https://github.com/llvm/llvm-project/pull/119815
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[llvm-branch-commits] [clang-doc] Use QualName in Markdown output (PR #119815)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 2fd7f05be97ccdc2bf8c1786e84f7bd531cce785
aeefb3a570b080e9632e81451073b22f8e61fba6 --extensions cpp --
clang-tools-extra/clang-doc/MDGenerator.cpp
clang-tools-extra/test/clang-doc/templates.cpp
``
View the diff from clang-format here.
``diff
diff --git a/clang-tools-extra/clang-doc/MDGenerator.cpp
b/clang-tools-extra/clang-doc/MDGenerator.cpp
index 00c6605725..28b645cf02 100644
--- a/clang-tools-extra/clang-doc/MDGenerator.cpp
+++ b/clang-tools-extra/clang-doc/MDGenerator.cpp
@@ -163,8 +163,8 @@ static void genMarkdown(const ClangDocContext &CDCtx, const
FunctionInfo &I,
writeHeader(I.Name, 3, OS);
std::string Access = getAccessSpelling(I.Access).str();
if (Access != "")
-writeLine(genItalic(Access + " " + I.ReturnType.Type.QualName + " " +
I.Name +
-"(" + Stream.str() + ")"),
+writeLine(genItalic(Access + " " + I.ReturnType.Type.QualName + " " +
+I.Name + "(" + Stream.str() + ")"),
OS);
else
writeLine(genItalic(I.ReturnType.Type.QualName + " " + I.Name + "(" +
``
https://github.com/llvm/llvm-project/pull/119815
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[llvm-branch-commits] [lld, wasm] Replace config-> with ctx.arg. (PR #119835)
llvmbot wrote:
@llvm/pr-subscribers-lld-wasm
Author: Fangrui Song (MaskRay)
Changes
---
Patch is 87.53 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/119835.diff
17 Files Affected:
- (modified) lld/wasm/Driver.cpp (+151-152)
- (modified) lld/wasm/InputChunks.cpp (+4-4)
- (modified) lld/wasm/InputChunks.h (+2-2)
- (modified) lld/wasm/InputElement.h (+2-2)
- (modified) lld/wasm/InputFiles.cpp (+7-7)
- (modified) lld/wasm/InputFiles.h (+1-1)
- (modified) lld/wasm/LTO.cpp (+40-40)
- (modified) lld/wasm/MapFile.cpp (+3-3)
- (modified) lld/wasm/MarkLive.cpp (+5-5)
- (modified) lld/wasm/OutputSections.cpp (+3-3)
- (modified) lld/wasm/Relocations.cpp (+10-10)
- (modified) lld/wasm/SymbolTable.cpp (+14-14)
- (modified) lld/wasm/Symbols.cpp (+3-3)
- (modified) lld/wasm/Symbols.h (+1-1)
- (modified) lld/wasm/SyntheticSections.cpp (+28-28)
- (modified) lld/wasm/SyntheticSections.h (+7-7)
- (modified) lld/wasm/Writer.cpp (+91-91)
``diff
diff --git a/lld/wasm/Driver.cpp b/lld/wasm/Driver.cpp
index 02471950fb5196..7b56bf90af3c1c 100644
--- a/lld/wasm/Driver.cpp
+++ b/lld/wasm/Driver.cpp
@@ -48,7 +48,7 @@ ConfigWrapper config;
Ctx ctx;
void errorOrWarn(const llvm::Twine &msg) {
- if (config->noinhibitExec)
+ if (ctx.arg.noinhibitExec)
warn(msg);
else
error(msg);
@@ -268,7 +268,7 @@ opt::InputArgList WasmOptTable::parse(ArrayRef argv) {
static void readImportFile(StringRef filename) {
if (std::optional buf = readFile(filename))
for (StringRef sym : args::getLines(*buf))
- config->allowUndefinedSymbols.insert(sym);
+ ctx.arg.allowUndefinedSymbols.insert(sym);
}
// Returns slices of MB by parsing MB as an archive file.
@@ -345,7 +345,7 @@ void LinkerDriver::addFile(StringRef path) {
case file_magic::bitcode:
case file_magic::wasm_object: {
auto obj = createObjectFile(mbref, "", 0, inLib);
-if (config->isStatic && isa(obj)) {
+if (ctx.arg.isStatic && isa(obj)) {
error("attempted static link of dynamic object " + path);
break;
}
@@ -364,7 +364,7 @@ void LinkerDriver::addFile(StringRef path) {
}
static std::optional findFromSearchPaths(StringRef path) {
- for (StringRef dir : config->searchPaths)
+ for (StringRef dir : ctx.arg.searchPaths)
if (std::optional s = findFile(dir, path))
return s;
return std::nullopt;
@@ -373,8 +373,8 @@ static std::optional
findFromSearchPaths(StringRef path) {
// This is for -l. We'll look for lib.a from
// search paths.
static std::optional searchLibraryBaseName(StringRef name) {
- for (StringRef dir : config->searchPaths) {
-if (!config->isStatic)
+ for (StringRef dir : ctx.arg.searchPaths) {
+if (!ctx.arg.isStatic)
if (std::optional s = findFile(dir, "lib" + name + ".so"))
return s;
if (std::optional s = findFile(dir, "lib" + name + ".a"))
@@ -408,10 +408,10 @@ void LinkerDriver::createFiles(opt::InputArgList &args) {
addFile(arg->getValue());
break;
case OPT_Bstatic:
- config->isStatic = true;
+ ctx.arg.isStatic = true;
break;
case OPT_Bdynamic:
- config->isStatic = false;
+ ctx.arg.isStatic = false;
break;
case OPT_whole_archive:
inWholeArchive = true;
@@ -527,99 +527,98 @@ getBuildId(opt::InputArgList &args) {
// Initializes Config members by the command line options.
static void readConfigs(opt::InputArgList &args) {
- config->allowMultipleDefinition =
+ ctx.arg.allowMultipleDefinition =
hasZOption(args, "muldefs") ||
args.hasFlag(OPT_allow_multiple_definition,
OPT_no_allow_multiple_definition, false);
- config->bsymbolic = args.hasArg(OPT_Bsymbolic);
- config->checkFeatures =
+ ctx.arg.bsymbolic = args.hasArg(OPT_Bsymbolic);
+ ctx.arg.checkFeatures =
args.hasFlag(OPT_check_features, OPT_no_check_features, true);
- config->compressRelocations = args.hasArg(OPT_compress_relocations);
- config->demangle = args.hasFlag(OPT_demangle, OPT_no_demangle, true);
- config->disableVerify = args.hasArg(OPT_disable_verify);
- config->emitRelocs = args.hasArg(OPT_emit_relocs);
- config->experimentalPic = args.hasArg(OPT_experimental_pic);
- config->entry = getEntry(args);
- config->exportAll = args.hasArg(OPT_export_all);
- config->exportTable = args.hasArg(OPT_export_table);
- config->growableTable = args.hasArg(OPT_growable_table);
- config->noinhibitExec = args.hasArg(OPT_noinhibit_exec);
+ ctx.arg.compressRelocations = args.hasArg(OPT_compress_relocations);
+ ctx.arg.demangle = args.hasFlag(OPT_demangle, OPT_no_demangle, true);
+ ctx.arg.disableVerify = args.hasArg(OPT_disable_verify);
+ ctx.arg.emitRelocs = args.hasArg(OPT_emit_relocs);
+ ctx.arg.experimentalPic = args.hasArg(OPT_experimental_pic);
+ ctx.arg.entry = getEntry(args);
+ ctx.arg.exportAll = args.hasArg(OPT_export_all);
+ ctx.arg.exportTable = args.hasArg(OPT_export_table);
+ ctx.ar
[llvm-branch-commits] [lld, wasm] Replace config-> with ctx.arg. (PR #119835)
llvmbot wrote:
@llvm/pr-subscribers-lld
Author: Fangrui Song (MaskRay)
Changes
---
Patch is 87.53 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/119835.diff
17 Files Affected:
- (modified) lld/wasm/Driver.cpp (+151-152)
- (modified) lld/wasm/InputChunks.cpp (+4-4)
- (modified) lld/wasm/InputChunks.h (+2-2)
- (modified) lld/wasm/InputElement.h (+2-2)
- (modified) lld/wasm/InputFiles.cpp (+7-7)
- (modified) lld/wasm/InputFiles.h (+1-1)
- (modified) lld/wasm/LTO.cpp (+40-40)
- (modified) lld/wasm/MapFile.cpp (+3-3)
- (modified) lld/wasm/MarkLive.cpp (+5-5)
- (modified) lld/wasm/OutputSections.cpp (+3-3)
- (modified) lld/wasm/Relocations.cpp (+10-10)
- (modified) lld/wasm/SymbolTable.cpp (+14-14)
- (modified) lld/wasm/Symbols.cpp (+3-3)
- (modified) lld/wasm/Symbols.h (+1-1)
- (modified) lld/wasm/SyntheticSections.cpp (+28-28)
- (modified) lld/wasm/SyntheticSections.h (+7-7)
- (modified) lld/wasm/Writer.cpp (+91-91)
``diff
diff --git a/lld/wasm/Driver.cpp b/lld/wasm/Driver.cpp
index 02471950fb5196..7b56bf90af3c1c 100644
--- a/lld/wasm/Driver.cpp
+++ b/lld/wasm/Driver.cpp
@@ -48,7 +48,7 @@ ConfigWrapper config;
Ctx ctx;
void errorOrWarn(const llvm::Twine &msg) {
- if (config->noinhibitExec)
+ if (ctx.arg.noinhibitExec)
warn(msg);
else
error(msg);
@@ -268,7 +268,7 @@ opt::InputArgList WasmOptTable::parse(ArrayRef argv) {
static void readImportFile(StringRef filename) {
if (std::optional buf = readFile(filename))
for (StringRef sym : args::getLines(*buf))
- config->allowUndefinedSymbols.insert(sym);
+ ctx.arg.allowUndefinedSymbols.insert(sym);
}
// Returns slices of MB by parsing MB as an archive file.
@@ -345,7 +345,7 @@ void LinkerDriver::addFile(StringRef path) {
case file_magic::bitcode:
case file_magic::wasm_object: {
auto obj = createObjectFile(mbref, "", 0, inLib);
-if (config->isStatic && isa(obj)) {
+if (ctx.arg.isStatic && isa(obj)) {
error("attempted static link of dynamic object " + path);
break;
}
@@ -364,7 +364,7 @@ void LinkerDriver::addFile(StringRef path) {
}
static std::optional findFromSearchPaths(StringRef path) {
- for (StringRef dir : config->searchPaths)
+ for (StringRef dir : ctx.arg.searchPaths)
if (std::optional s = findFile(dir, path))
return s;
return std::nullopt;
@@ -373,8 +373,8 @@ static std::optional
findFromSearchPaths(StringRef path) {
// This is for -l. We'll look for lib.a from
// search paths.
static std::optional searchLibraryBaseName(StringRef name) {
- for (StringRef dir : config->searchPaths) {
-if (!config->isStatic)
+ for (StringRef dir : ctx.arg.searchPaths) {
+if (!ctx.arg.isStatic)
if (std::optional s = findFile(dir, "lib" + name + ".so"))
return s;
if (std::optional s = findFile(dir, "lib" + name + ".a"))
@@ -408,10 +408,10 @@ void LinkerDriver::createFiles(opt::InputArgList &args) {
addFile(arg->getValue());
break;
case OPT_Bstatic:
- config->isStatic = true;
+ ctx.arg.isStatic = true;
break;
case OPT_Bdynamic:
- config->isStatic = false;
+ ctx.arg.isStatic = false;
break;
case OPT_whole_archive:
inWholeArchive = true;
@@ -527,99 +527,98 @@ getBuildId(opt::InputArgList &args) {
// Initializes Config members by the command line options.
static void readConfigs(opt::InputArgList &args) {
- config->allowMultipleDefinition =
+ ctx.arg.allowMultipleDefinition =
hasZOption(args, "muldefs") ||
args.hasFlag(OPT_allow_multiple_definition,
OPT_no_allow_multiple_definition, false);
- config->bsymbolic = args.hasArg(OPT_Bsymbolic);
- config->checkFeatures =
+ ctx.arg.bsymbolic = args.hasArg(OPT_Bsymbolic);
+ ctx.arg.checkFeatures =
args.hasFlag(OPT_check_features, OPT_no_check_features, true);
- config->compressRelocations = args.hasArg(OPT_compress_relocations);
- config->demangle = args.hasFlag(OPT_demangle, OPT_no_demangle, true);
- config->disableVerify = args.hasArg(OPT_disable_verify);
- config->emitRelocs = args.hasArg(OPT_emit_relocs);
- config->experimentalPic = args.hasArg(OPT_experimental_pic);
- config->entry = getEntry(args);
- config->exportAll = args.hasArg(OPT_export_all);
- config->exportTable = args.hasArg(OPT_export_table);
- config->growableTable = args.hasArg(OPT_growable_table);
- config->noinhibitExec = args.hasArg(OPT_noinhibit_exec);
+ ctx.arg.compressRelocations = args.hasArg(OPT_compress_relocations);
+ ctx.arg.demangle = args.hasFlag(OPT_demangle, OPT_no_demangle, true);
+ ctx.arg.disableVerify = args.hasArg(OPT_disable_verify);
+ ctx.arg.emitRelocs = args.hasArg(OPT_emit_relocs);
+ ctx.arg.experimentalPic = args.hasArg(OPT_experimental_pic);
+ ctx.arg.entry = getEntry(args);
+ ctx.arg.exportAll = args.hasArg(OPT_export_all);
+ ctx.arg.exportTable = args.hasArg(OPT_export_table);
+ ctx.arg.gro
[llvm-branch-commits] [lld, wasm] Replace config-> with ctx.arg. (PR #119835)
https://github.com/MaskRay created https://github.com/llvm/llvm-project/pull/119835 None ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-doc] Use QualName in Markdown output (PR #119815)
https://github.com/petrhosek approved this pull request. https://github.com/llvm/llvm-project/pull/119815 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-doc][NFC] Make test resilient to line changes (PR #119811)
https://github.com/petrhosek approved this pull request. https://github.com/llvm/llvm-project/pull/119811 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-doc] Precommit test case for functions with templated parameters and return (PR #119814)
https://github.com/petrhosek approved this pull request. https://github.com/llvm/llvm-project/pull/119814 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-doc] Add tests for Markdown output with C++ templates (PR #119813)
https://github.com/petrhosek approved this pull request. https://github.com/llvm/llvm-project/pull/119813 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-doc] Add tests for Markdown output with C++ templates (PR #119813)
@@ -75,3 +89,8 @@ void function(bool x) {}
// YAML-NEXT: - Contents:'0'
// YAML-NEXT: ...
+// MD: ### function
+// MD: *void function(_Bool x)*
+// MD: *Defined at {{.*}}templates.cpp#[[# @LINE - 27]]*
+
+
petrhosek wrote:
Nit: These extra empty lines shouldn't be needed.
```suggestion
```
https://github.com/llvm/llvm-project/pull/119813
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] AMDGPU: Fix libcall recognition of image array types (PR #119832)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/119832
Add tests with get_image_width as a sample for all of the non-extension
image types. The transform doesn't do anything, but this runs through
all the mangled libfunc parsing and shows it does not crash. It would
probably be smarter to check for exact match of the types, rather than
checking the prefix.
>From 7543aca2d3c6fd6e8debc6035899699efa532d01 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 13 Dec 2024 14:55:55 +0900
Subject: [PATCH] AMDGPU: Fix libcall recognition of image array types
Add tests with get_image_width as a sample for all of the non-extension
image types. The transform doesn't do anything, but this runs through
all the mangled libfunc parsing and shows it does not crash. It would
probably be smarter to check for exact match of the types, rather than
checking the prefix.
---
clang/test/CodeGenOpenCL/opencl_types.cl | 78
llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp | 6 +-
...plify-libcall-image-function-signatures.ll | 356 --
3 files changed, 397 insertions(+), 43 deletions(-)
diff --git a/clang/test/CodeGenOpenCL/opencl_types.cl
b/clang/test/CodeGenOpenCL/opencl_types.cl
index eb68ab850744a4..aac3492b7a9e8d 100644
--- a/clang/test/CodeGenOpenCL/opencl_types.cl
+++ b/clang/test/CodeGenOpenCL/opencl_types.cl
@@ -73,3 +73,81 @@ kernel void foo_wo_pipe(write_only pipe int p) {}
void __attribute__((overloadable)) bad1(image1d_t b, image2d_t c, image2d_t d)
{}
// CHECK-SPIR-LABEL:
@{{_Z4bad114ocl_image1d_ro14ocl_image2d_roS0_|"\\01\?bad1@@\$\$J0YAXPAUocl_image1d_ro@@PAUocl_image2d_ro@@1@Z"}}
// CHECK-AMDGCN-LABEL:
@{{_Z4bad114ocl_image1d_ro14ocl_image2d_roS0_|"\\01\?bad1@@\$\$J0YAXPAUocl_image1d_ro@@PAUocl_image2d_ro@@1@Z"}}(ptr
addrspace(4){{.*}}ptr addrspace(4){{.*}}ptr addrspace(4){{.*}})
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image1d_array_ro(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_only image1d_array_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image1d_array_wo(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(write_only image1d_array_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image1d_array_rw(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_write image1d_array_t img) {}
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test21ocl_image1d_buffer_ro(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_only image1d_buffer_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test21ocl_image1d_buffer_wo(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(write_only image1d_buffer_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test21ocl_image1d_buffer_rw(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_write image1d_buffer_t img) {}
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image2d_array_ro(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_only image2d_array_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image2d_array_wo(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(write_only image2d_array_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image2d_array_rw(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_write image2d_array_t img) {}
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image1d_ro(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_only image1d_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image1d_wo(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(write_only image1d_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image1d_rw(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_write image1d_t img) {}
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image2d_ro(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_only image2d_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image2d_wo(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(write_only image2d_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image2d_rw(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_write image2d_t img) {}
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image
[llvm-branch-commits] [clang] [llvm] AMDGPU: Fix libcall recognition of image array types (PR #119832)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
Add tests with get_image_width as a sample for all of the non-extension
image types. The transform doesn't do anything, but this runs through
all the mangled libfunc parsing and shows it does not crash. It would
probably be smarter to check for exact match of the types, rather than
checking the prefix.
---
Patch is 22.04 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/119832.diff
3 Files Affected:
- (modified) clang/test/CodeGenOpenCL/opencl_types.cl (+78)
- (modified) llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp (+3-3)
- (modified)
llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-image-function-signatures.ll
(+316-40)
``diff
diff --git a/clang/test/CodeGenOpenCL/opencl_types.cl
b/clang/test/CodeGenOpenCL/opencl_types.cl
index eb68ab850744a4..aac3492b7a9e8d 100644
--- a/clang/test/CodeGenOpenCL/opencl_types.cl
+++ b/clang/test/CodeGenOpenCL/opencl_types.cl
@@ -73,3 +73,81 @@ kernel void foo_wo_pipe(write_only pipe int p) {}
void __attribute__((overloadable)) bad1(image1d_t b, image2d_t c, image2d_t d)
{}
// CHECK-SPIR-LABEL:
@{{_Z4bad114ocl_image1d_ro14ocl_image2d_roS0_|"\\01\?bad1@@\$\$J0YAXPAUocl_image1d_ro@@PAUocl_image2d_ro@@1@Z"}}
// CHECK-AMDGCN-LABEL:
@{{_Z4bad114ocl_image1d_ro14ocl_image2d_roS0_|"\\01\?bad1@@\$\$J0YAXPAUocl_image1d_ro@@PAUocl_image2d_ro@@1@Z"}}(ptr
addrspace(4){{.*}}ptr addrspace(4){{.*}}ptr addrspace(4){{.*}})
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image1d_array_ro(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_only image1d_array_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image1d_array_wo(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(write_only image1d_array_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image1d_array_rw(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_write image1d_array_t img) {}
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test21ocl_image1d_buffer_ro(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_only image1d_buffer_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test21ocl_image1d_buffer_wo(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(write_only image1d_buffer_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test21ocl_image1d_buffer_rw(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_write image1d_buffer_t img) {}
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image2d_array_ro(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_only image2d_array_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image2d_array_wo(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(write_only image2d_array_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test20ocl_image2d_array_rw(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_write image2d_array_t img) {}
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image1d_ro(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_only image1d_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image1d_wo(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(write_only image1d_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image1d_rw(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_write image1d_t img) {}
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image2d_ro(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_only image2d_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image2d_wo(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(write_only image2d_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image2d_rw(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_write image2d_t img) {}
+
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image3d_ro(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(read_only image3d_t img) {}
+
+// CHECK-AMDGCN: define dso_local void
@_Z20img_type_mangle_test14ocl_image3d_wo(ptr addrspace(4) %img)
+__attribute__((overloadable))
+void img_type_mangle_test(write_only image3d_t img) {}
+
+// CHECK-AMDGCN: define dso_local v
[llvm-branch-commits] [clang] [llvm] AMDGPU: Fix libcall recognition of image array types (PR #119832)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/119832 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] AMDGPU: Fix libcall recognition of image array types (PR #119832)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/119832?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#119832** https://app.graphite.dev/github/pr/llvm/llvm-project/119832?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/119832?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#119043** https://app.graphite.dev/github/pr/llvm/llvm-project/119043?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/119832 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CI][Github] Add linux premerge workflow (PR #119635)
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/119635
>From 19f4098c0934f242ed5b332533dfe03c44e82de8 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:31:07 +
Subject: [PATCH 01/29] [CI][Github] Add linux premerge workflow
This patch adds a Github Actions workflow for Linux premerge. This currently
just calls into the existing CI scripts as a starting point.
---
.github/workflows/premerge.yaml | 20
1 file changed, 20 insertions(+)
create mode 100644 .github/workflows/premerge.yaml
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
new file mode 100644
index 00..33a5b57ab3548f
--- /dev/null
+++ b/.github/workflows/premerge.yaml
@@ -0,0 +1,20 @@
+name: LLVM Premerge Checks
+
+permissions:
+ contents: read
+
+on:
+ pull_request:
+paths:
+ - .github/workflows/premerge.yaml
+
+jobs:
+ premerge-checks-linux:
+if: github.repository_owner == 'llvm'
+runs-on: ubuntu-latest
+steps:
+ - name: Checkout LLVM
+uses: actions/checkout@v4
+ - name: Build and Test
+run: |
+ echo test
>From 9c8661960efcbfee9164dcc74bca22c5e30adbc9 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:44:30 +
Subject: [PATCH 02/29] Modification stuff
---
.github/workflows/premerge.yaml | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
index 33a5b57ab3548f..e471f0d3aa256c 100644
--- a/.github/workflows/premerge.yaml
+++ b/.github/workflows/premerge.yaml
@@ -17,4 +17,8 @@ jobs:
uses: actions/checkout@v4
- name: Build and Test
run: |
- echo test
+ ${MODIFIED_FILES:=$(git diff --name-only HEAD~1...HEAD)}
+ echo $MODIFIED_FILES
+ modified_dirs=$(echo "$MODIFIED_FILES" | cut -d'/' -f1 | sort -u)
+ echo "$modified_dirs" >&2
+
>From 60c621205f3994c7a0b4e34d087bb11f6dbda7f4 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:51:04 +
Subject: [PATCH 03/29] Adjust depth
---
.github/workflows/premerge.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
index e471f0d3aa256c..632c5ca38a1784 100644
--- a/.github/workflows/premerge.yaml
+++ b/.github/workflows/premerge.yaml
@@ -15,6 +15,8 @@ jobs:
steps:
- name: Checkout LLVM
uses: actions/checkout@v4
+with:
+ fetch-depth: 2
- name: Build and Test
run: |
${MODIFIED_FILES:=$(git diff --name-only HEAD~1...HEAD)}
>From 49b3859a055e7aa788c74e09a438001602fc00c1 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:53:31 +
Subject: [PATCH 04/29] maybe
---
.github/workflows/premerge.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
index 632c5ca38a1784..1964085cbf0cfc 100644
--- a/.github/workflows/premerge.yaml
+++ b/.github/workflows/premerge.yaml
@@ -22,5 +22,5 @@ jobs:
${MODIFIED_FILES:=$(git diff --name-only HEAD~1...HEAD)}
echo $MODIFIED_FILES
modified_dirs=$(echo "$MODIFIED_FILES" | cut -d'/' -f1 | sort -u)
- echo "$modified_dirs" >&2
+ echo "$modified_dirs"
>From 41efe71d08fe063f1ee96731ea32f313e6422a1d Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:54:41 +
Subject: [PATCH 05/29] fix thing
---
.github/workflows/premerge.yaml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
index 1964085cbf0cfc..17094574499281 100644
--- a/.github/workflows/premerge.yaml
+++ b/.github/workflows/premerge.yaml
@@ -19,8 +19,8 @@ jobs:
fetch-depth: 2
- name: Build and Test
run: |
- ${MODIFIED_FILES:=$(git diff --name-only HEAD~1...HEAD)}
- echo $MODIFIED_FILES
- modified_dirs=$(echo "$MODIFIED_FILES" | cut -d'/' -f1 | sort -u)
+ modified_files=$(git diff --name-only HEAD~1...HEAD)
+ echo $modified_files
+ modified_dirs=$(echo "$modified_files" | cut -d'/' -f1 | sort -u)
echo "$modified_dirs"
>From cb5cf35c20e40ba461fb0f6f75f0409ce14ec7ad Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:59:54 +
Subject: [PATCH 06/29] incremental testing
---
.github/workflows/premerge.yaml | 13 +
1 file changed, 13 insertions(+)
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
index 17094574499281..94b0f97ba49509 100644
--- a/.github/workflows/premerge.yaml
+++ b/.github/workflows/premerge.yaml
@@ -24,3 +24,16 @@ jobs:
modified_dirs=$(echo "$modified_files" | cut -d'/' -f1 | sort -u)
echo "$modified_dirs"
+ . ./.ci/compute-project
[llvm-branch-commits] [llvm] [CI][Github] Add linux premerge workflow (PR #119635)
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/119635
>From 19f4098c0934f242ed5b332533dfe03c44e82de8 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:31:07 +
Subject: [PATCH 01/29] [CI][Github] Add linux premerge workflow
This patch adds a Github Actions workflow for Linux premerge. This currently
just calls into the existing CI scripts as a starting point.
---
.github/workflows/premerge.yaml | 20
1 file changed, 20 insertions(+)
create mode 100644 .github/workflows/premerge.yaml
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
new file mode 100644
index 00..33a5b57ab3548f
--- /dev/null
+++ b/.github/workflows/premerge.yaml
@@ -0,0 +1,20 @@
+name: LLVM Premerge Checks
+
+permissions:
+ contents: read
+
+on:
+ pull_request:
+paths:
+ - .github/workflows/premerge.yaml
+
+jobs:
+ premerge-checks-linux:
+if: github.repository_owner == 'llvm'
+runs-on: ubuntu-latest
+steps:
+ - name: Checkout LLVM
+uses: actions/checkout@v4
+ - name: Build and Test
+run: |
+ echo test
>From 9c8661960efcbfee9164dcc74bca22c5e30adbc9 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:44:30 +
Subject: [PATCH 02/29] Modification stuff
---
.github/workflows/premerge.yaml | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
index 33a5b57ab3548f..e471f0d3aa256c 100644
--- a/.github/workflows/premerge.yaml
+++ b/.github/workflows/premerge.yaml
@@ -17,4 +17,8 @@ jobs:
uses: actions/checkout@v4
- name: Build and Test
run: |
- echo test
+ ${MODIFIED_FILES:=$(git diff --name-only HEAD~1...HEAD)}
+ echo $MODIFIED_FILES
+ modified_dirs=$(echo "$MODIFIED_FILES" | cut -d'/' -f1 | sort -u)
+ echo "$modified_dirs" >&2
+
>From 60c621205f3994c7a0b4e34d087bb11f6dbda7f4 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:51:04 +
Subject: [PATCH 03/29] Adjust depth
---
.github/workflows/premerge.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
index e471f0d3aa256c..632c5ca38a1784 100644
--- a/.github/workflows/premerge.yaml
+++ b/.github/workflows/premerge.yaml
@@ -15,6 +15,8 @@ jobs:
steps:
- name: Checkout LLVM
uses: actions/checkout@v4
+with:
+ fetch-depth: 2
- name: Build and Test
run: |
${MODIFIED_FILES:=$(git diff --name-only HEAD~1...HEAD)}
>From 49b3859a055e7aa788c74e09a438001602fc00c1 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:53:31 +
Subject: [PATCH 04/29] maybe
---
.github/workflows/premerge.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
index 632c5ca38a1784..1964085cbf0cfc 100644
--- a/.github/workflows/premerge.yaml
+++ b/.github/workflows/premerge.yaml
@@ -22,5 +22,5 @@ jobs:
${MODIFIED_FILES:=$(git diff --name-only HEAD~1...HEAD)}
echo $MODIFIED_FILES
modified_dirs=$(echo "$MODIFIED_FILES" | cut -d'/' -f1 | sort -u)
- echo "$modified_dirs" >&2
+ echo "$modified_dirs"
>From 41efe71d08fe063f1ee96731ea32f313e6422a1d Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:54:41 +
Subject: [PATCH 05/29] fix thing
---
.github/workflows/premerge.yaml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
index 1964085cbf0cfc..17094574499281 100644
--- a/.github/workflows/premerge.yaml
+++ b/.github/workflows/premerge.yaml
@@ -19,8 +19,8 @@ jobs:
fetch-depth: 2
- name: Build and Test
run: |
- ${MODIFIED_FILES:=$(git diff --name-only HEAD~1...HEAD)}
- echo $MODIFIED_FILES
- modified_dirs=$(echo "$MODIFIED_FILES" | cut -d'/' -f1 | sort -u)
+ modified_files=$(git diff --name-only HEAD~1...HEAD)
+ echo $modified_files
+ modified_dirs=$(echo "$modified_files" | cut -d'/' -f1 | sort -u)
echo "$modified_dirs"
>From cb5cf35c20e40ba461fb0f6f75f0409ce14ec7ad Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Wed, 11 Dec 2024 23:59:54 +
Subject: [PATCH 06/29] incremental testing
---
.github/workflows/premerge.yaml | 13 +
1 file changed, 13 insertions(+)
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
index 17094574499281..94b0f97ba49509 100644
--- a/.github/workflows/premerge.yaml
+++ b/.github/workflows/premerge.yaml
@@ -24,3 +24,16 @@ jobs:
modified_dirs=$(echo "$modified_files" | cut -d'/' -f1 | sort -u)
echo "$modified_dirs"
+ . ./.ci/compute-project
[llvm-branch-commits] [llvm] [DirectX] Introduce the DXILResourceAccess pass (PR #116726)
@@ -10,10 +10,11 @@ ; CHECK-NEXT: DXIL Intrinsic Expansion ; CHECK-NEXT: DXIL Data Scalarization ; CHECK-NEXT: DXIL Array Flattener +; CHECK-NEXT: DXIL Resource analysis bogner wrote: This is no longer relevant after splitting the analysis passes https://github.com/llvm/llvm-project/pull/116726 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Delete spills of undef values (PR #119684)
arsenm wrote: > Currently, regalloc won't do subreg spilling. But it will be fixed in the > foreseeable future. What will happen if you write a test that spills the > `undef` subreg of a tuple? Do you want to cover it anyway? There's no change in interpretation of an undef use with subregisters. The register is just unused, it doesn't matter what the subregister index is. https://github.com/llvm/llvm-project/pull/119684 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RegAlloc: Do not fatal error if there are no registers in the alloc order (PR #119640)
https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/119640 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] RegAlloc: Do not fatal error if there are no registers in the alloc order (PR #119640)
@@ -192,3 +177,50 @@ void RegAllocBase::enqueue(const LiveInterval *LI) {
<< " in skipped register class\n");
}
}
+
+MCPhysReg RegAllocBase::getErrorAssignment(const TargetRegisterClass &RC,
+ const MachineInstr *CtxMI) {
+ MachineFunction &MF = VRM->getMachineFunction();
+
+ // Avoid printing the error for every single instance of the register. It
+ // would be better if this were per register class.
+ bool EmitError = !MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::FailedRegAlloc);
+ if (EmitError)
+
MF.getProperties().set(MachineFunctionProperties::Property::FailedRegAlloc);
+
+ const Function &Fn = MF.getFunction();
+ LLVMContext &Context = Fn.getContext();
+
+ ArrayRef AllocOrder = RegClassInfo.getOrder(&RC);
+ if (AllocOrder.empty()) {
+// If the allocation order is empty, it likely means all registers in the
+// class are reserved. We still to need to pick something, so look at the
+// underlying class.
+ArrayRef RawRegs = RC.getRegisters();
+
+if (EmitError) {
+ DiagnosticInfoRegAllocFailure DI(
+ "no registers from class available to allocate", Fn,
+ CtxMI ? CtxMI->getDebugLoc() : DiagnosticLocation());
+ Context.diagnose(DI);
+}
+
+assert(!RawRegs.empty() && "register classes cannot have no registers");
+return RawRegs.front();
+ }
+
+ if (EmitError) {
arsenm wrote:
Yes. report_fatal_error is not an acceptable end user error experience. We
should produce proper LLVMContext diagnostics for the frontend to intercept,
with line locations pointing at the failing instruction.
AMDGPU has attributes to control the register budget, which can be used to make
certain operations uncompilable. It is nicer to have a proper error pointing at
the failing instruction
https://github.com/llvm/llvm-project/pull/119640
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] TargetParser: AArch64: Add part numbers for Apple CPUs. (PR #119777)
https://github.com/pcc created https://github.com/llvm/llvm-project/pull/119777 Part numbers taken from: https://github.com/AsahiLinux/m1n1/blob/main/src/chickens.c ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [DirectX] Split resource info into type and binding info. NFC (PR #119773)
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Justin Bogner (bogner)
Changes
This splits the DXILResourceAnalysis pass into TypeAnalysis and BindingAnalysis
passes. The type analysis pass is made immutable and populated lazily so that
it can be used earlier in the pipeline without needing to carefully maintain
the invariants of the binding analysis.
Fixes #118400
---
Patch is 93.11 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/119773.diff
19 Files Affected:
- (modified) llvm/include/llvm/Analysis/DXILResource.h (+161-58)
- (modified) llvm/include/llvm/InitializePasses.h (+2-1)
- (modified) llvm/include/llvm/LinkAllPasses.h (+2-1)
- (modified) llvm/lib/Analysis/Analysis.cpp (+2-1)
- (modified) llvm/lib/Analysis/DXILResource.cpp (+225-158)
- (modified) llvm/lib/Passes/PassRegistry.def (+4-2)
- (modified) llvm/lib/Target/DirectX/DXContainerGlobals.cpp (+17-11)
- (modified) llvm/lib/Target/DirectX/DXILDataScalarization.cpp (-7)
- (modified) llvm/lib/Target/DirectX/DXILFinalizeLinkage.cpp (-5)
- (modified) llvm/lib/Target/DirectX/DXILFinalizeLinkage.h (-1)
- (modified) llvm/lib/Target/DirectX/DXILFlattenArrays.cpp (-7)
- (modified) llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp (-6)
- (modified) llvm/lib/Target/DirectX/DXILOpLowering.cpp (+33-22)
- (modified) llvm/lib/Target/DirectX/DXILPrepare.cpp (+1-1)
- (modified) llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp (+47-32)
- (modified) llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp (+27-20)
- (modified) llvm/test/Analysis/DXILResource/buffer-frombinding.ll (+2-14)
- (modified) llvm/test/CodeGen/DirectX/llc-pipeline.ll (+2-2)
- (modified) llvm/unittests/Analysis/DXILResourceTest.cpp (+197-195)
``diff
diff --git a/llvm/include/llvm/Analysis/DXILResource.h
b/llvm/include/llvm/Analysis/DXILResource.h
index 0205356af54443..2f5dded46538ea 100644
--- a/llvm/include/llvm/Analysis/DXILResource.h
+++ b/llvm/include/llvm/Analysis/DXILResource.h
@@ -25,6 +25,8 @@ class MDTuple;
class TargetExtType;
class Value;
+class DXILResourceTypeMap;
+
namespace dxil {
/// The dx.RawBuffer target extension type
@@ -196,27 +198,8 @@ class SamplerExtType : public TargetExtType {
//===--===//
-class ResourceInfo {
+class ResourceTypeInfo {
public:
- struct ResourceBinding {
-uint32_t RecordID;
-uint32_t Space;
-uint32_t LowerBound;
-uint32_t Size;
-
-bool operator==(const ResourceBinding &RHS) const {
- return std::tie(RecordID, Space, LowerBound, Size) ==
- std::tie(RHS.RecordID, RHS.Space, RHS.LowerBound, RHS.Size);
-}
-bool operator!=(const ResourceBinding &RHS) const {
- return !(*this == RHS);
-}
-bool operator<(const ResourceBinding &RHS) const {
- return std::tie(RecordID, Space, LowerBound, Size) <
- std::tie(RHS.RecordID, RHS.Space, RHS.LowerBound, RHS.Size);
-}
- };
-
struct UAVInfo {
bool GloballyCoherent;
bool HasCounter;
@@ -266,12 +249,11 @@ class ResourceInfo {
};
private:
- ResourceBinding Binding;
TargetExtType *HandleTy;
// GloballyCoherent and HasCounter aren't really part of the type and need to
- // be determined by analysis, so they're just provided directly when we
- // construct these.
+ // be determined by analysis, so they're just provided directly by the
+ // DXILResourceTypeMap when we construct these.
bool GloballyCoherent;
bool HasCounter;
@@ -279,9 +261,13 @@ class ResourceInfo {
dxil::ResourceKind Kind;
public:
- ResourceInfo(uint32_t RecordID, uint32_t Space, uint32_t LowerBound,
- uint32_t Size, TargetExtType *HandleTy,
- bool GloballyCoherent = false, bool HasCounter = false);
+ ResourceTypeInfo(TargetExtType *HandleTy, const dxil::ResourceClass RC,
+ const dxil::ResourceKind Kind, bool GloballyCoherent =
false,
+ bool HasCounter = false);
+ ResourceTypeInfo(TargetExtType *HandleTy, bool GloballyCoherent = false,
+ bool HasCounter = false)
+ : ResourceTypeInfo(HandleTy, {}, dxil::ResourceKind::Invalid,
+ GloballyCoherent, HasCounter) {}
TargetExtType *getHandleTy() const { return HandleTy; }
@@ -303,44 +289,157 @@ class ResourceInfo {
dxil::SamplerFeedbackType getFeedbackType() const;
uint32_t getMultiSampleCount() const;
- StringRef getName() const {
-// TODO: Get the name from the symbol once we include one here.
-return "";
- }
dxil::ResourceClass getResourceClass() const { return RC; }
dxil::ResourceKind getResourceKind() const { return Kind; }
+ bool operator==(const ResourceTypeInfo &RHS) const;
+ bool operator!=(const ResourceTypeInfo &RHS) const { return !(*this == RHS);
}
+ bool operator<(const ResourceTypeInfo &RHS) const;
+
+ void print(raw_ostream &OS, const DataLayout &DL)
[llvm-branch-commits] [llvm] [DirectX] Split resource info into type and binding info. NFC (PR #119773)
llvmbot wrote:
@llvm/pr-subscribers-llvm-analysis
Author: Justin Bogner (bogner)
Changes
This splits the DXILResourceAnalysis pass into TypeAnalysis and BindingAnalysis
passes. The type analysis pass is made immutable and populated lazily so that
it can be used earlier in the pipeline without needing to carefully maintain
the invariants of the binding analysis.
Fixes #118400
---
Patch is 93.11 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/119773.diff
19 Files Affected:
- (modified) llvm/include/llvm/Analysis/DXILResource.h (+161-58)
- (modified) llvm/include/llvm/InitializePasses.h (+2-1)
- (modified) llvm/include/llvm/LinkAllPasses.h (+2-1)
- (modified) llvm/lib/Analysis/Analysis.cpp (+2-1)
- (modified) llvm/lib/Analysis/DXILResource.cpp (+225-158)
- (modified) llvm/lib/Passes/PassRegistry.def (+4-2)
- (modified) llvm/lib/Target/DirectX/DXContainerGlobals.cpp (+17-11)
- (modified) llvm/lib/Target/DirectX/DXILDataScalarization.cpp (-7)
- (modified) llvm/lib/Target/DirectX/DXILFinalizeLinkage.cpp (-5)
- (modified) llvm/lib/Target/DirectX/DXILFinalizeLinkage.h (-1)
- (modified) llvm/lib/Target/DirectX/DXILFlattenArrays.cpp (-7)
- (modified) llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp (-6)
- (modified) llvm/lib/Target/DirectX/DXILOpLowering.cpp (+33-22)
- (modified) llvm/lib/Target/DirectX/DXILPrepare.cpp (+1-1)
- (modified) llvm/lib/Target/DirectX/DXILPrettyPrinter.cpp (+47-32)
- (modified) llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp (+27-20)
- (modified) llvm/test/Analysis/DXILResource/buffer-frombinding.ll (+2-14)
- (modified) llvm/test/CodeGen/DirectX/llc-pipeline.ll (+2-2)
- (modified) llvm/unittests/Analysis/DXILResourceTest.cpp (+197-195)
``diff
diff --git a/llvm/include/llvm/Analysis/DXILResource.h
b/llvm/include/llvm/Analysis/DXILResource.h
index 0205356af54443..2f5dded46538ea 100644
--- a/llvm/include/llvm/Analysis/DXILResource.h
+++ b/llvm/include/llvm/Analysis/DXILResource.h
@@ -25,6 +25,8 @@ class MDTuple;
class TargetExtType;
class Value;
+class DXILResourceTypeMap;
+
namespace dxil {
/// The dx.RawBuffer target extension type
@@ -196,27 +198,8 @@ class SamplerExtType : public TargetExtType {
//===--===//
-class ResourceInfo {
+class ResourceTypeInfo {
public:
- struct ResourceBinding {
-uint32_t RecordID;
-uint32_t Space;
-uint32_t LowerBound;
-uint32_t Size;
-
-bool operator==(const ResourceBinding &RHS) const {
- return std::tie(RecordID, Space, LowerBound, Size) ==
- std::tie(RHS.RecordID, RHS.Space, RHS.LowerBound, RHS.Size);
-}
-bool operator!=(const ResourceBinding &RHS) const {
- return !(*this == RHS);
-}
-bool operator<(const ResourceBinding &RHS) const {
- return std::tie(RecordID, Space, LowerBound, Size) <
- std::tie(RHS.RecordID, RHS.Space, RHS.LowerBound, RHS.Size);
-}
- };
-
struct UAVInfo {
bool GloballyCoherent;
bool HasCounter;
@@ -266,12 +249,11 @@ class ResourceInfo {
};
private:
- ResourceBinding Binding;
TargetExtType *HandleTy;
// GloballyCoherent and HasCounter aren't really part of the type and need to
- // be determined by analysis, so they're just provided directly when we
- // construct these.
+ // be determined by analysis, so they're just provided directly by the
+ // DXILResourceTypeMap when we construct these.
bool GloballyCoherent;
bool HasCounter;
@@ -279,9 +261,13 @@ class ResourceInfo {
dxil::ResourceKind Kind;
public:
- ResourceInfo(uint32_t RecordID, uint32_t Space, uint32_t LowerBound,
- uint32_t Size, TargetExtType *HandleTy,
- bool GloballyCoherent = false, bool HasCounter = false);
+ ResourceTypeInfo(TargetExtType *HandleTy, const dxil::ResourceClass RC,
+ const dxil::ResourceKind Kind, bool GloballyCoherent =
false,
+ bool HasCounter = false);
+ ResourceTypeInfo(TargetExtType *HandleTy, bool GloballyCoherent = false,
+ bool HasCounter = false)
+ : ResourceTypeInfo(HandleTy, {}, dxil::ResourceKind::Invalid,
+ GloballyCoherent, HasCounter) {}
TargetExtType *getHandleTy() const { return HandleTy; }
@@ -303,44 +289,157 @@ class ResourceInfo {
dxil::SamplerFeedbackType getFeedbackType() const;
uint32_t getMultiSampleCount() const;
- StringRef getName() const {
-// TODO: Get the name from the symbol once we include one here.
-return "";
- }
dxil::ResourceClass getResourceClass() const { return RC; }
dxil::ResourceKind getResourceKind() const { return Kind; }
+ bool operator==(const ResourceTypeInfo &RHS) const;
+ bool operator!=(const ResourceTypeInfo &RHS) const { return !(*this == RHS);
}
+ bool operator<(const ResourceTypeInfo &RHS) const;
+
+ void print(raw_ostream &OS, const DataLayout &DL) c
[llvm-branch-commits] [llvm] [DirectX] Create symbols for resource handles (PR #119775)
llvmbot wrote:
@llvm/pr-subscribers-backend-directx
Author: Justin Bogner (bogner)
Changes
We need to create symbols with "the original shape of resource and element
type" to put in the resource metadata in order to generate valid DXIL.
Note that DXC generally doesn't emit an actual symbol outside of library
shaders (it emits an undef of a pointer to the type), but since we have to deal
with opaque pointers we would need a way to smuggle the type through to match
that. Instead, we simply emit symbols for now.
Fixed #116849
---
Patch is 21.43 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/119775.diff
5 Files Affected:
- (modified) llvm/include/llvm/Analysis/DXILResource.h (+11-7)
- (modified) llvm/lib/Analysis/DXILResource.cpp (+93-7)
- (modified) llvm/lib/Target/DirectX/DXILTranslateMetadata.cpp (+4)
- (added) llvm/test/CodeGen/DirectX/Metadata/resource-symbols.ll (+48)
- (modified) llvm/unittests/Analysis/DXILResourceTest.cpp (+38-22)
``diff
diff --git a/llvm/include/llvm/Analysis/DXILResource.h
b/llvm/include/llvm/Analysis/DXILResource.h
index 2f5dded46538ea..b59798a3d64a47 100644
--- a/llvm/include/llvm/Analysis/DXILResource.h
+++ b/llvm/include/llvm/Analysis/DXILResource.h
@@ -270,6 +270,7 @@ class ResourceTypeInfo {
GloballyCoherent, HasCounter) {}
TargetExtType *getHandleTy() const { return HandleTy; }
+ StructType *createElementStruct();
// Conditions to check before accessing specific views.
bool isUAV() const;
@@ -325,21 +326,23 @@ class ResourceBindingInfo {
private:
ResourceBinding Binding;
TargetExtType *HandleTy;
+ GlobalVariable *Symbol = nullptr;
public:
ResourceBindingInfo(uint32_t RecordID, uint32_t Space, uint32_t LowerBound,
- uint32_t Size, TargetExtType *HandleTy)
- : Binding{RecordID, Space, LowerBound, Size}, HandleTy(HandleTy) {}
+ uint32_t Size, TargetExtType *HandleTy,
+ GlobalVariable *Symbol = nullptr)
+ : Binding{RecordID, Space, LowerBound, Size}, HandleTy(HandleTy),
+Symbol(Symbol) {}
void setBindingID(unsigned ID) { Binding.RecordID = ID; }
const ResourceBinding &getBinding() const { return Binding; }
TargetExtType *getHandleTy() const { return HandleTy; }
- const StringRef getName() const {
-// TODO: Get the name from the symbol once we include one here.
-return "";
- }
+ const StringRef getName() const { return Symbol ? Symbol->getName() : ""; }
+ bool hasSymbol() const { return Symbol; }
+ GlobalVariable *createSymbol(Module &M, StructType *Ty, StringRef Name = "");
MDTuple *getAsMetadata(Module &M, DXILResourceTypeMap &DRTM) const;
MDTuple *getAsMetadata(Module &M, dxil::ResourceTypeInfo RTI) const;
@@ -349,7 +352,8 @@ class ResourceBindingInfo {
getAnnotateProps(Module &M, dxil::ResourceTypeInfo RTI) const;
bool operator==(const ResourceBindingInfo &RHS) const {
-return std::tie(Binding, HandleTy) == std::tie(RHS.Binding, RHS.HandleTy);
+return std::tie(Binding, HandleTy, Symbol) ==
+ std::tie(RHS.Binding, RHS.HandleTy, RHS.Symbol);
}
bool operator!=(const ResourceBindingInfo &RHS) const {
return !(*this == RHS);
diff --git a/llvm/lib/Analysis/DXILResource.cpp
b/llvm/lib/Analysis/DXILResource.cpp
index e1942a0c4930cd..793929e0e40dfa 100644
--- a/llvm/lib/Analysis/DXILResource.cpp
+++ b/llvm/lib/Analysis/DXILResource.cpp
@@ -216,6 +216,81 @@ ResourceTypeInfo::ResourceTypeInfo(TargetExtType *HandleTy,
llvm_unreachable("Unknown handle type");
}
+static void formatTypeName(SmallString<64> &Dest, StringRef Name,
+ bool isWriteable, bool isROV) {
+ Dest = isWriteable ? (isROV ? "RasterizerOrdered" : "RW") : "";
+ Dest += Name;
+}
+
+StructType *ResourceTypeInfo::createElementStruct() {
+ SmallString<64> TypeName;
+
+ switch (Kind) {
+ case ResourceKind::Texture1D:
+ case ResourceKind::Texture2D:
+ case ResourceKind::Texture3D:
+ case ResourceKind::TextureCube:
+ case ResourceKind::Texture1DArray:
+ case ResourceKind::Texture2DArray:
+ case ResourceKind::TextureCubeArray: {
+auto *RTy = cast(HandleTy);
+formatTypeName(TypeName, getResourceKindName(Kind), RTy->isWriteable(),
+ RTy->isROV());
+return StructType::create(RTy->getResourceType(), TypeName);
+ }
+ case ResourceKind::Texture2DMS:
+ case ResourceKind::Texture2DMSArray: {
+auto *RTy = cast(HandleTy);
+formatTypeName(TypeName, getResourceKindName(Kind), RTy->isWriteable(),
+ /*IsROV=*/false);
+return StructType::create(RTy->getResourceType(), TypeName);
+ }
+ case ResourceKind::TypedBuffer: {
+auto *RTy = cast(HandleTy);
+formatTypeName(TypeName, getResourceKindName(Kind), RTy->isWriteable(),
+ RTy->isROV());
+return StructType::create(RTy->getResourceType(), TypeName);
+ }
+ case ResourceKind::Ra
