================ @@ -982,16 +982,23 @@ void RegAllocFastImpl::allocVirtRegUndef(MachineOperand &MO) { if (!shouldAllocateRegister(VirtReg)) return; - LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg); + LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); MCPhysReg PhysReg; if (LRI != LiveVirtRegs.end() && LRI->PhysReg) { PhysReg = LRI->PhysReg; } else { const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); - // FIXME: This can happen, and should fall back to a reserved entry in RC. - assert(!AllocationOrder.empty() && "Allocation order must not be empty"); - PhysReg = AllocationOrder[0]; + if (AllocationOrder.empty()) { + // All registers in the class were reserved. + // + // It might be OK to take any entry from the class as this is an undef + // use, but accepting this would give different behavior than greedy and + // basic. + PhysReg = getErrorAssignment(*LRI, *MO.getParent(), RC); + LRI->Error = true; + } else + PhysReg = AllocationOrder[0]; ---------------- ilovepi wrote:
Up the stack you're using `AllocationOrder.front()`. Either way is fine, but I think we should try to keep them consistent. https://github.com/llvm/llvm-project/pull/119647 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits