[llvm-branch-commits] [lldb] 84633d7 - Revert "[LLDB] Add a target.launch-working-dir setting (#113521)"
Author: Walter Erquinigo
Date: 2024-11-05T07:11:32-05:00
New Revision: 84633d7ccc926abff46c6480dbe7ccc7e48247ce
URL:
https://github.com/llvm/llvm-project/commit/84633d7ccc926abff46c6480dbe7ccc7e48247ce
DIFF:
https://github.com/llvm/llvm-project/commit/84633d7ccc926abff46c6480dbe7ccc7e48247ce.diff
LOG: Revert "[LLDB] Add a target.launch-working-dir setting (#113521)"
This reverts commit 6620cd25234a42ca4b51490627afcb93fa443dc3.
Added:
Modified:
lldb/include/lldb/Target/Target.h
lldb/source/Commands/CommandObjectProcess.cpp
lldb/source/Commands/Options.td
lldb/source/Target/Target.cpp
lldb/source/Target/TargetProperties.td
lldb/test/API/commands/process/launch/TestProcessLaunch.py
llvm/docs/ReleaseNotes.md
Removed:
diff --git a/lldb/include/lldb/Target/Target.h
b/lldb/include/lldb/Target/Target.h
index cab21c29a7486f..e4848f19e64d62 100644
--- a/lldb/include/lldb/Target/Target.h
+++ b/lldb/include/lldb/Target/Target.h
@@ -37,7 +37,6 @@
#include "lldb/Utility/RealpathPrefixes.h"
#include "lldb/Utility/Timeout.h"
#include "lldb/lldb-public.h"
-#include "llvm/ADT/StringRef.h"
namespace lldb_private {
@@ -115,8 +114,6 @@ class TargetProperties : public Properties {
void SetDisableSTDIO(bool b);
- llvm::StringRef GetLaunchWorkingDirectory() const;
-
const char *GetDisassemblyFlavor() const;
InlineStrategy GetInlineStrategy() const;
diff --git a/lldb/source/Commands/CommandObjectProcess.cpp
b/lldb/source/Commands/CommandObjectProcess.cpp
index 7444e46aa729e7..e7c7d07ad47722 100644
--- a/lldb/source/Commands/CommandObjectProcess.cpp
+++ b/lldb/source/Commands/CommandObjectProcess.cpp
@@ -201,13 +201,6 @@ class CommandObjectProcessLaunch : public
CommandObjectProcessLaunchOrAttach {
if (target->GetDisableSTDIO())
m_options.launch_info.GetFlags().Set(eLaunchFlagDisableSTDIO);
-if (!m_options.launch_info.GetWorkingDirectory()) {
- if (llvm::StringRef wd = target->GetLaunchWorkingDirectory();
- !wd.empty()) {
-m_options.launch_info.SetWorkingDirectory(FileSpec(wd));
- }
-}
-
// Merge the launch info environment with the target environment.
Environment target_env = target->GetEnvironment();
m_options.launch_info.GetEnvironment().insert(target_env.begin(),
diff --git a/lldb/source/Commands/Options.td b/lldb/source/Commands/Options.td
index 9d8d45d083eca4..4276d9e7f9c8b0 100644
--- a/lldb/source/Commands/Options.td
+++ b/lldb/source/Commands/Options.td
@@ -691,10 +691,7 @@ let Command = "process launch" in {
def process_launch_plugin : Option<"plugin", "P">, Arg<"Plugin">,
Desc<"Name of the process plugin you want to use.">;
def process_launch_working_dir : Option<"working-dir", "w">,
Arg<"DirectoryName">,
-Desc<"Set the current working directory to when running the
inferior. This option "
- "applies only to the current `process launch` invocation. If "
- "`target.launch-working-dir` is set and this option is given, the
value of this "
- "option will be used instead of the setting.">;
+Desc<"Set the current working directory to when running the
inferior.">;
def process_launch_arch : Option<"arch", "a">, Arg<"Architecture">,
Desc<"Set the architecture for the process to launch when ambiguous.">;
def process_launch_environment : Option<"environment", "E">,
diff --git a/lldb/source/Target/Target.cpp b/lldb/source/Target/Target.cpp
index 242d2eaec2a15a..8cd3fa8af6bae1 100644
--- a/lldb/source/Target/Target.cpp
+++ b/lldb/source/Target/Target.cpp
@@ -4471,11 +4471,6 @@ void TargetProperties::SetDisableSTDIO(bool b) {
const uint32_t idx = ePropertyDisableSTDIO;
SetPropertyAtIndex(idx, b);
}
-llvm::StringRef TargetProperties::GetLaunchWorkingDirectory() const {
- const uint32_t idx = ePropertyLaunchWorkingDir;
- return GetPropertyAtIndexAs(
- idx, g_target_properties[idx].default_cstr_value);
-}
const char *TargetProperties::GetDisassemblyFlavor() const {
const uint32_t idx = ePropertyDisassemblyFlavor;
diff --git a/lldb/source/Target/TargetProperties.td
b/lldb/source/Target/TargetProperties.td
index 00ad8dd2a9f7f9..fb61478fb752dc 100644
--- a/lldb/source/Target/TargetProperties.td
+++ b/lldb/source/Target/TargetProperties.td
@@ -201,13 +201,6 @@ let Definition = "target" in {
def DebugUtilityExpression: Property<"debug-utility-expression", "Boolean">,
DefaultFalse,
Desc<"Enable debugging of LLDB-internal utility expressions.">;
- def LaunchWorkingDir: Property<"launch-working-dir", "String">,
-DefaultStringValue<"">,
-Desc<"A default value for the working directory to use when launching
processes. "
- "It is ignored when empty. This setting is only used when the target
is "
- "launched. If you change this setting, the new value will only apply
to "
- "subsequent launches.
[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/114971
>From 3fd27bd1405a8b2c068786a200d610b9cacb65ef Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 5 Nov 2024 20:38:44 +0800
Subject: [PATCH] Set max bytes
Created using spr 1.3.6-beta.1
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c65feb9755633c..a1c5f76bae0099 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2508,7 +2508,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool
IsZeroCmp) const {
Options.LoadSizes = {4, 2, 1};
if (IsZeroCmp && ST->hasVInstructions()) {
unsigned VLenB = ST->getRealMinVLen() / 8;
-for (unsigned Size = ST->getXLen() / 8 + 1;
+// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
+// and `XLen + 8`.
+unsigned MinSize = std::max(VLenB / 8, ST->getXLen() / 8 + 1);
+for (unsigned Size = MinSize;
Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
}
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
Changes
We can convert non-power-of-2 types into extended value types
and then they will be widen.
---
Patch is 253.31 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/114971.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2-6)
- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+4-14)
- (modified) llvm/test/CodeGen/RISCV/memcmp-optsize.ll (+462-760)
- (modified) llvm/test/CodeGen/RISCV/memcmp.ll (+460-3282)
``diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 72d85491a6f77d..e67515c24e8341 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14492,10 +14492,6 @@ combineVectorSizedSetCCEquality(EVT VT, SDValue X,
SDValue Y, ISD::CondCode CC,
return SDValue();
unsigned OpSize = OpVT.getSizeInBits();
- // TODO: Support non-power-of-2 types.
- if (!isPowerOf2_32(OpSize))
-return SDValue();
-
// The size should be larger than XLen and smaller than the maximum vector
// size.
if (OpSize <= Subtarget.getXLen() ||
@@ -14517,8 +14513,8 @@ combineVectorSizedSetCCEquality(EVT VT, SDValue X,
SDValue Y, ISD::CondCode CC,
return SDValue();
unsigned VecSize = OpSize / 8;
- EVT VecVT = MVT::getVectorVT(MVT::i8, VecSize);
- EVT CmpVT = MVT::getVectorVT(MVT::i1, VecSize);
+ EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, VecSize);
+ EVT CmpVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, VecSize);
SDValue VecX = DAG.getBitcast(VecVT, X);
SDValue VecY = DAG.getBitcast(VecVT, Y);
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 637b670cf041a5..c65feb9755633c 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2507,20 +2507,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool
IsZeroCmp) const {
else
Options.LoadSizes = {4, 2, 1};
if (IsZeroCmp && ST->hasVInstructions()) {
-unsigned RealMinVLen = ST->getRealMinVLen();
-// Support Fractional LMULs if the lengths are larger than XLen.
-// TODO: Support non-power-of-2 types.
-for (unsigned LMUL = 8; LMUL >= 2; LMUL /= 2) {
- unsigned Len = RealMinVLen / LMUL;
- if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
-for (unsigned LMUL = 1; LMUL <= ST->getMaxLMULForFixedLengthVectors();
- LMUL *= 2) {
- unsigned Len = RealMinVLen * LMUL;
- if (Len > ST->getXLen())
-Options.LoadSizes.insert(Options.LoadSizes.begin(), Len / 8);
-}
+unsigned VLenB = ST->getRealMinVLen() / 8;
+for (unsigned Size = ST->getXLen() / 8 + 1;
+ Size <= VLenB * ST->getMaxLMULForFixedLengthVectors(); Size++)
+ Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
}
return Options;
}
diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
index b39e6a425d702f..800b5a80fdf160 100644
--- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
+++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll
@@ -739,31 +739,14 @@ define i32 @bcmp_size_5(ptr %s1, ptr %s2) nounwind
optsize {
;
; CHECK-ALIGNED-RV32-V-LABEL: bcmp_size_5:
; CHECK-ALIGNED-RV32-V: # %bb.0: # %entry
-; CHECK-ALIGNED-RV32-V-NEXT:lbu a2, 1(a0)
-; CHECK-ALIGNED-RV32-V-NEXT:lbu a3, 0(a0)
-; CHECK-ALIGNED-RV32-V-NEXT:lbu a4, 2(a0)
-; CHECK-ALIGNED-RV32-V-NEXT:lbu a5, 3(a0)
-; CHECK-ALIGNED-RV32-V-NEXT:slli a2, a2, 8
-; CHECK-ALIGNED-RV32-V-NEXT:or a2, a2, a3
-; CHECK-ALIGNED-RV32-V-NEXT:slli a4, a4, 16
-; CHECK-ALIGNED-RV32-V-NEXT:slli a5, a5, 24
-; CHECK-ALIGNED-RV32-V-NEXT:or a4, a5, a4
-; CHECK-ALIGNED-RV32-V-NEXT:lbu a3, 0(a1)
-; CHECK-ALIGNED-RV32-V-NEXT:lbu a5, 1(a1)
-; CHECK-ALIGNED-RV32-V-NEXT:or a2, a4, a2
-; CHECK-ALIGNED-RV32-V-NEXT:lbu a4, 2(a1)
-; CHECK-ALIGNED-RV32-V-NEXT:lbu a6, 3(a1)
-; CHECK-ALIGNED-RV32-V-NEXT:slli a5, a5, 8
-; CHECK-ALIGNED-RV32-V-NEXT:or a3, a5, a3
-; CHECK-ALIGNED-RV32-V-NEXT:slli a4, a4, 16
-; CHECK-ALIGNED-RV32-V-NEXT:slli a6, a6, 24
-; CHECK-ALIGNED-RV32-V-NEXT:lbu a0, 4(a0)
-; CHECK-ALIGNED-RV32-V-NEXT:lbu a1, 4(a1)
-; CHECK-ALIGNED-RV32-V-NEXT:or a4, a6, a4
-; CHECK-ALIGNED-RV32-V-NEXT:or a3, a4, a3
-; CHECK-ALIGNED-RV32-V-NEXT:xor a2, a2, a3
-; CHECK-ALIGNED-RV32-V-NEXT:xor a0, a0, a1
-; CHECK-ALIGNED-RV32-V-NEXT:or a0, a2, a0
+; CHECK-ALIGNED-RV32-V-NEXT:vsetivli zero, 5, e8, mf2, ta, ma
+; CHECK-ALIGNED-RV32-V-NEXT:vle8.v v8, (a0)
+; CHECK-ALIGNED-RV32-V-NEXT:vle8.v v9, (a1)
+; CHECK-ALIGNED-RV32-V-NEXT:vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-ALIGNED-RV32-V-NEXT:vmset.m v
[llvm-branch-commits] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)
https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/114971 We can convert non-power-of-2 types into extended value types and then they will be widen. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Clang] Consider outer instantiation scopes for constraint normalization (PR #114951)
https://github.com/erichkeane approved this pull request. https://github.com/llvm/llvm-project/pull/114951 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] Add documentation for Multilib custom flags (PR #114998)
https://github.com/vhscampos created https://github.com/llvm/llvm-project/pull/114998 None >From 02161c1c4754b15450ae81538c22b77501a809ca Mon Sep 17 00:00:00 2001 From: Victor Campos Date: Tue, 5 Nov 2024 14:22:06 + Subject: [PATCH] Add documentation for Multilib custom flags --- clang/docs/Multilib.rst | 116 1 file changed, 116 insertions(+) diff --git a/clang/docs/Multilib.rst b/clang/docs/Multilib.rst index 7637d0db9565b8..7c165d149d7a4c 100644 --- a/clang/docs/Multilib.rst +++ b/clang/docs/Multilib.rst @@ -122,6 +122,104 @@ subclass and a suitable base multilib variant is present then the It is the responsibility of layered multilib authors to ensure that headers and libraries in each layer are complete enough to mask any incompatibilities. +Multilib custom flags += + +Introduction + + +The multilib mechanism supports library variants that correspond to target, +code generation or language command-line flags. Examples include ``--target``, +``-mcpu``, ``-mfpu``, ``-mbranch-protection``, ``-fno-rtti``. However, some library +variants are particular to features that do not correspond to any command-line +option. Multithreading and semihosting, for instance, have no associated +compiler option. + +In order to support the selection of variants for which no compiler option +exists, the multilib specification includes the concept of *custom flags*. +These flags have no impact on code generation and are only used in the multilib +processing. + +Multilib custom flags follow this format in the driver invocation: + +:: + + -fmultilib-flag= + +They are fed into the multilib system alongside the remaining flags. + +Custom flag declarations + + +Custom flags can be declared in the YAML file under the *Flags* section. + +.. code-block:: yaml + + Flags: + - Name: multithreaded +Values: +- Name: no-multithreaded + ExtraBuildArgs: [-D__SINGLE_THREAD__] +- Name: multithreaded +Default: no-multithreaded + +* Name: the name to categorize a flag. +* Values: a list of flag *Value*s (defined below). +* Default: it specifies the name of the value this flag should take if not + specified in the command-line invocation. It must be one value from the Values + field. + +A Default value is useful to save users from specifying custom flags that have a +most commonly used value. + +Each flag *Value* is defined as: + +* Name: name of the value. This is the string to be used in + ``-fmultilib-flag=``. +* ExtraBuildArgs: a list of strings corresponding to the extra build arguments + used to build a library variant that's in accordance to this specific custom + flag value. + +The namespace of flag values is common across all flags. This means that flag +value names must be unique. + +Usage of custom flags in the *Variants* specifications +-- + +Library variants should list their requirement on one or more custom flags like +they do for any other flag. Each requirement must be listed as +``-fmultilib-flag=``. + +A variant that does not specify a requirement on one particular flag can be +matched against any value of that flag. + +Use of ``-print-multi-lib`` by build systems + + +Some library build systems use the ``-print-multi-lib`` command-line option to +query what library variants are shipped or supported by the target compiler and +what command-line options should be used to build the variants. + +In this use case, a build system queries the target toolchain about what library +variants should be built. With this information in hand, the build system may +launch the build of each variant using the collected command-line arguments. + +For example, in *newlib*, multithreading is enabled by default and can be +disabled by defining the ``__SINGLE_THREAD__`` macro. Therefore a multilib YAML +file that is used to drive a *newlib* build must encode this information in the +output of ``-print-multi-lib``. + +To account for this use case, custom flag values may specify the +*ExtraBuildArgs* field. This optional field is a list of strings to be printed +alongside the other command-line arguments in the output of +``-print-multi-lib``. In the example of *newlib* and its multithreading support, +a variant specific for single threaded execution should list +``-D__SINGLE_THREAD__`` in its corresponding flag value's *ExtraBuildArgs* +field. + +Since this information is specific for users of ``-print-multi-lib``, that is, +for *builders* of library variants, it has no relevance in library *selection*. + Stability = @@ -222,6 +320,24 @@ For a more comprehensive example see # Flags is a list of one or more strings. Flags: [--target=thumbv7m-none-eabi] + # Custom flag declarations. Each item is a different declaration. + Flags: +# Name of the flag + - Name: multithreaded +# Li
[llvm-branch-commits] [compiler-rt] release/19.x: [compiler-rt] Stop using x86 builtin on AArch64 with GCC (#93890) (PR #115006)
llvmbot wrote: @statham-arm What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/115006 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/19.x: [compiler-rt] Stop using x86 builtin on AArch64 with GCC (#93890) (PR #115006)
https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/115006 Backport 8aa9d6206ce55bdaaf422839c351fbd63f033b89 Requested by: @XrXr >From aebbc1f67998ef1646f023ced799d921098ab6bc Mon Sep 17 00:00:00 2001 From: Alan Wu Date: Fri, 16 Aug 2024 08:16:17 -0400 Subject: [PATCH] [compiler-rt] Stop using x86 builtin on AArch64 with GCC (#93890) Previously, building `multc3.c` on A64 with GCC 7 or up but 9 and lower will attempt to reference `__builtin_copysignq`, an [x86-specific intrinsic][1]: ``` $ gcc -c multc3.c In file included from fp_lib.h:24, from multc3.c:14: multc3.c: In function '__multc3': int_math.h:71:32: warning: implicit declaration of function '__builtin_copysignq'; did you mean '__builtin_copysign'? [-Wimplicit-function-declaration] #define crt_copysignf128(x, y) __builtin_copysignq((x), (y)) ^~~ ``` This is because `__has_builtin` is from GCC 10, and defined to 0 at the top of int_math.h for affected GCC versions, so the fallback definition is used. But `__builtin_copysignq` is unavailable on A64. Use version detection to find `__builtin_copysignf128` instead. It's available since GCC 7 and [available][2] on both x86 and A64, given this macro is only used when `CRT_HAS_IEEE_TF`. --- I realize this is fixing a problem for an out-of-tree build configuration, but help would be greatly appreciated. Rust [builds](https://github.com/rust-lang/compiler-builtins) `multc3.c` with GCC 8 and this mis-selection is causing [build issues](https://github.com/rust-lang/rust/issues/125619) way downstream. ref: d2ce3e9621411f3391def327f89e3a650918989f [1]: https://gcc.gnu.org/onlinedocs/gcc/x86-Built-in-Functions.html [2]: https://gcc.gnu.org/gcc-7/changes.html (cherry picked from commit 8aa9d6206ce55bdaaf422839c351fbd63f033b89) --- compiler-rt/lib/builtins/int_math.h | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/compiler-rt/lib/builtins/int_math.h b/compiler-rt/lib/builtins/int_math.h index 74d3e311db5e71..08bfe922ffa13b 100644 --- a/compiler-rt/lib/builtins/int_math.h +++ b/compiler-rt/lib/builtins/int_math.h @@ -65,9 +65,12 @@ #define crt_copysign(x, y) __builtin_copysign((x), (y)) #define crt_copysignf(x, y) __builtin_copysignf((x), (y)) #define crt_copysignl(x, y) __builtin_copysignl((x), (y)) -#if __has_builtin(__builtin_copysignf128) +// We define __has_builtin to always return 0 for GCC versions below 10, +// but __builtin_copysignf128 is available since version 7. +#if __has_builtin(__builtin_copysignf128) || \ +(defined(__GNUC__) && __GNUC__ >= 7) #define crt_copysignf128(x, y) __builtin_copysignf128((x), (y)) -#elif __has_builtin(__builtin_copysignq) || (defined(__GNUC__) && __GNUC__ >= 7) +#elif __has_builtin(__builtin_copysignq) #define crt_copysignf128(x, y) __builtin_copysignq((x), (y)) #endif #endif @@ -80,9 +83,11 @@ #define crt_fabs(x) __builtin_fabs((x)) #define crt_fabsf(x) __builtin_fabsf((x)) #define crt_fabsl(x) __builtin_fabsl((x)) -#if __has_builtin(__builtin_fabsf128) +// We define __has_builtin to always return 0 for GCC versions below 10, +// but __builtin_fabsf128 is available since version 7. +#if __has_builtin(__builtin_fabsf128) || (defined(__GNUC__) && __GNUC__ >= 7) #define crt_fabsf128(x) __builtin_fabsf128((x)) -#elif __has_builtin(__builtin_fabsq) || (defined(__GNUC__) && __GNUC__ >= 7) +#elif __has_builtin(__builtin_fabsq) #define crt_fabsf128(x) __builtin_fabsq((x)) #endif #endif ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/19.x: [compiler-rt] Stop using x86 builtin on AArch64 with GCC (#93890) (PR #115006)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/115006 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/19.x: [compiler-rt] Stop using x86 builtin on AArch64 with GCC (#93890) (PR #115006)
github-actions[bot] wrote: ⚠️ We detected that you are using a GitHub private e-mail address to contribute to the repo. Please turn off [Keep my email addresses private](https://github.com/settings/emails) setting in your account. See [LLVM Discourse](https://discourse.llvm.org/t/hidden-emails-on-github-should-we-do-something-about-it) for more information. https://github.com/llvm/llvm-project/pull/115006 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)
https://github.com/vhscampos updated
https://github.com/llvm/llvm-project/pull/110659
>From f2525efdd1f70c59923220b787be005903bdced5 Mon Sep 17 00:00:00 2001
From: Victor Campos
Date: Thu, 26 Sep 2024 14:44:33 +0100
Subject: [PATCH 1/3] [Multilib] Custom flags processing for library selection
Select library variants in the multilib system using the flags passed
following the '-fmultilib-flag=' format.
Multilib flags that were not passed in the command-line have their
default value fed into the library selection mechanism.
A warning is shown if the flag's value name is invalid. If the wrong
name is close enough to any valid one, according to edit distance, the
closest valid value name is suggested.
Details about this change can be found in this thread:
https://discourse.llvm.org/t/rfc-multilib-custom-flags/81058
---
.../clang/Basic/DiagnosticDriverKinds.td | 6 +
clang/include/clang/Driver/Multilib.h | 3 +
clang/lib/Driver/Driver.cpp | 4 +-
clang/lib/Driver/Multilib.cpp | 137 +-
.../baremetal-multilib-custom-flags.yaml | 57
5 files changed, 201 insertions(+), 6 deletions(-)
create mode 100644 clang/test/Driver/baremetal-multilib-custom-flags.yaml
diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td
b/clang/include/clang/Basic/DiagnosticDriverKinds.td
index 65551bd7761a9d..6874614557f837 100644
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -14,6 +14,12 @@ def err_drv_no_such_file_with_suggestion : Error<
def err_drv_unsupported_opt : Error<"unsupported option '%0'">;
def err_drv_unsupported_opt_with_suggestion : Error<
"unsupported option '%0'; did you mean '%1'?">;
+def warn_drv_unsupported_opt : Warning<
+ "unsupported option '%0'">,
+ InGroup;
+def warn_drv_unsupported_opt_with_suggestion : Warning<
+ "unsupported option '%0'; did you mean '%1'?">,
+ InGroup;
def err_drv_unsupported_opt_for_target : Error<
"unsupported option '%0' for target '%1'">;
def err_drv_unsupported_opt_for_language_mode : Error<
diff --git a/clang/include/clang/Driver/Multilib.h
b/clang/include/clang/Driver/Multilib.h
index 0662feb114c796..d0a3dd827e3531 100644
--- a/clang/include/clang/Driver/Multilib.h
+++ b/clang/include/clang/Driver/Multilib.h
@@ -163,6 +163,9 @@ class MultilibSet {
const_iterator begin() const { return Multilibs.begin(); }
const_iterator end() const { return Multilibs.end(); }
+ Multilib::flags_list
+ processCustomFlags(const Driver &D, const Multilib::flags_list &Flags) const;
+
/// Select compatible variants, \returns false if none are compatible
bool select(const Driver &D, const Multilib::flags_list &Flags,
llvm::SmallVectorImpl &) const;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 9878a9dad78d40..cee10d36070616 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -2324,9 +2324,7 @@ bool Driver::HandleImmediateArgs(Compilation &C) {
}
if (C.getArgs().hasArg(options::OPT_print_multi_lib)) {
-for (const Multilib &Multilib : TC.getMultilibs())
- if (!Multilib.isError())
-llvm::outs() << Multilib << "\n";
+llvm::outs() << TC.getMultilibs();
return false;
}
diff --git a/clang/lib/Driver/Multilib.cpp b/clang/lib/Driver/Multilib.cpp
index 236074478e7d84..adabf21057eb35 100644
--- a/clang/lib/Driver/Multilib.cpp
+++ b/clang/lib/Driver/Multilib.cpp
@@ -12,6 +12,7 @@
#include "clang/Driver/Driver.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Error.h"
@@ -95,9 +96,113 @@ MultilibSet &MultilibSet::FilterOut(FilterCallback F) {
void MultilibSet::push_back(const Multilib &M) { Multilibs.push_back(M); }
+static void WarnUnclaimedMultilibCustomFlags(
+const Driver &D, const SmallVector &UnclaimedCustomFlagValues,
+const SmallVector &CustomFlagDecls)
{
+ struct EditDistanceInfo {
+StringRef FlagValue;
+unsigned EditDistance;
+ };
+ const unsigned MaxEditDistance = 5;
+
+ for (StringRef Unclaimed : UnclaimedCustomFlagValues) {
+std::optional BestCandidate;
+for (const auto &Decl : CustomFlagDecls) {
+ for (const auto &Value : Decl->ValueList) {
+const std::string &FlagValueName = Value.Name;
+unsigned EditDistance =
+Unclaimed.edit_distance(FlagValueName, /*AllowReplacements=*/true,
+/*MaxEditDistance=*/MaxEditDistance);
+if (!BestCandidate || (EditDistance <= MaxEditDistance &&
+ EditDistance < BestCandidate->EditDistance)) {
+ BestCandidate = {FlagValueName, EditDistance};
+}
+ }
+}
+if (!BestCandidate)
+ D.Diag(clang::diag::warn_drv_unsupported_opt)
+ << (custom_flag::Pref
[llvm-branch-commits] [clang] [Multilib] Custom flags processing for library selection (PR #110659)
vhscampos wrote: FYI I added a test for `-print-multi-lib` and its interaction with `ExtraBuildArgs`. https://github.com/llvm/llvm-project/pull/110659 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/19.x: [compiler-rt] Stop using x86 builtin on AArch64 with GCC (#93890) (PR #115006)
https://github.com/statham-arm approved this pull request. Sounds like a good idea to me! https://github.com/llvm/llvm-project/pull/115006 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: RegBankLegalize rules for load (PR #112882)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112882
>From 74a1970b576cb6943271614cfe616459cd73956c Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Wed, 30 Oct 2024 15:37:59 +0100
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for load
Add IDs for bit width that cover multiple LLTs: B32 B64 etc.
"Predicate" wrapper class for bool predicate functions used to
write pretty rules. Predicates can be combined using &&, || and !.
Lowering for splitting and widening loads.
Write rules for loads to not change existing mir tests from old
regbankselect.
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp| 284 +++-
.../AMDGPU/AMDGPURegBankLegalizeHelper.h | 5 +
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 309 -
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 65 +++-
.../AMDGPU/GlobalISel/regbankselect-load.mir | 320 +++---
.../GlobalISel/regbankselect-zextload.mir | 9 +-
6 files changed, 927 insertions(+), 65 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 916140e2bbcd68..86be855d730305 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -38,6 +38,83 @@ void
RegBankLegalizeHelper::findRuleAndApplyMapping(MachineInstr &MI) {
lower(MI, Mapping, WaterfallSgprs);
}
+void RegBankLegalizeHelper::splitLoad(MachineInstr &MI,
+ ArrayRef LLTBreakdown, LLT MergeTy)
{
+ MachineFunction &MF = B.getMF();
+ assert(MI.getNumMemOperands() == 1);
+ MachineMemOperand &BaseMMO = **MI.memoperands_begin();
+ Register Dst = MI.getOperand(0).getReg();
+ const RegisterBank *DstRB = MRI.getRegBankOrNull(Dst);
+ Register Base = MI.getOperand(1).getReg();
+ LLT PtrTy = MRI.getType(Base);
+ const RegisterBank *PtrRB = MRI.getRegBankOrNull(Base);
+ LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits());
+ SmallVector LoadPartRegs;
+
+ unsigned ByteOffset = 0;
+ for (LLT PartTy : LLTBreakdown) {
+Register BasePlusOffset;
+if (ByteOffset == 0) {
+ BasePlusOffset = Base;
+} else {
+ auto Offset = B.buildConstant({PtrRB, OffsetTy}, ByteOffset);
+ BasePlusOffset = B.buildPtrAdd({PtrRB, PtrTy}, Base, Offset).getReg(0);
+}
+auto *OffsetMMO = MF.getMachineMemOperand(&BaseMMO, ByteOffset, PartTy);
+auto LoadPart = B.buildLoad({DstRB, PartTy}, BasePlusOffset, *OffsetMMO);
+LoadPartRegs.push_back(LoadPart.getReg(0));
+ByteOffset += PartTy.getSizeInBytes();
+ }
+
+ if (!MergeTy.isValid()) {
+// Loads are of same size, concat or merge them together.
+B.buildMergeLikeInstr(Dst, LoadPartRegs);
+ } else {
+// Loads are not all of same size, need to unmerge them to smaller pieces
+// of MergeTy type, then merge pieces to Dst.
+SmallVector MergeTyParts;
+for (Register Reg : LoadPartRegs) {
+ if (MRI.getType(Reg) == MergeTy) {
+MergeTyParts.push_back(Reg);
+ } else {
+auto Unmerge = B.buildUnmerge({DstRB, MergeTy}, Reg);
+for (unsigned i = 0; i < Unmerge->getNumOperands() - 1; ++i)
+ MergeTyParts.push_back(Unmerge.getReg(i));
+ }
+}
+B.buildMergeLikeInstr(Dst, MergeTyParts);
+ }
+ MI.eraseFromParent();
+}
+
+void RegBankLegalizeHelper::widenLoad(MachineInstr &MI, LLT WideTy,
+ LLT MergeTy) {
+ MachineFunction &MF = B.getMF();
+ assert(MI.getNumMemOperands() == 1);
+ MachineMemOperand &BaseMMO = **MI.memoperands_begin();
+ Register Dst = MI.getOperand(0).getReg();
+ const RegisterBank *DstRB = MRI.getRegBankOrNull(Dst);
+ Register Base = MI.getOperand(1).getReg();
+
+ MachineMemOperand *WideMMO = MF.getMachineMemOperand(&BaseMMO, 0, WideTy);
+ auto WideLoad = B.buildLoad({DstRB, WideTy}, Base, *WideMMO);
+
+ if (WideTy.isScalar()) {
+B.buildTrunc(Dst, WideLoad);
+ } else {
+SmallVector MergeTyParts;
+auto Unmerge = B.buildUnmerge({DstRB, MergeTy}, WideLoad);
+
+LLT DstTy = MRI.getType(Dst);
+unsigned NumElts = DstTy.getSizeInBits() / MergeTy.getSizeInBits();
+for (unsigned i = 0; i < NumElts; ++i) {
+ MergeTyParts.push_back(Unmerge.getReg(i));
+}
+B.buildMergeLikeInstr(Dst, MergeTyParts);
+ }
+ MI.eraseFromParent();
+}
+
void RegBankLegalizeHelper::lower(MachineInstr &MI,
const RegBankLLTMapping &Mapping,
SmallSet &WaterfallSgprs) {
@@ -116,6 +193,50 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
MI.eraseFromParent();
break;
}
+ case SplitLoad: {
+LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
+unsigned Size = DstTy.getSizeInBits();
+// Even split to 128-bit loads
+if (Size > 128) {
+ LLT B128;
+ if (DstTy.isVector()) {
+LLT EltTy = DstTy.getElementType();
+B128 = LLT:
[llvm-branch-commits] [llvm] MachineUniformityAnalysis: Improve isConstantOrUndefValuePhi (PR #112866)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/112866
>From a8d15f3f4854a364fc0b905544840112283b41a3 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 31 Oct 2024 14:10:57 +0100
Subject: [PATCH] MachineUniformityAnalysis: Improve isConstantOrUndefValuePhi
Change existing code for G_PHI to match what LLVM-IR version is doing
via PHINode::hasConstantOrUndefValue. This is not safe for regular PHI
since it may appear with an undef operand and getVRegDef can fail.
Most notably this improves number of values that can be allocated
to sgpr register bank in AMDGPURegBankSelect.
Common case here are phis that appear in structurize-cfg lowering
for cycles with multiple exits:
Undef incoming value is coming from block that reached cycle exit
condition, if other incoming is uniform keep the phi uniform despite
the fact it is joining values from pair of blocks that are entered
via divergent condition branch.
---
llvm/lib/CodeGen/MachineSSAContext.cpp| 27 +-
.../AMDGPU/MIR/hidden-diverge-gmir.mir| 28 +++
.../AMDGPU/MIR/hidden-loop-diverge.mir| 4 +-
.../AMDGPU/MIR/uses-value-from-cycle.mir | 8 +-
.../GlobalISel/divergence-structurizer.mir| 80 --
.../regbankselect-mui-regbanklegalize.mir | 69 ---
.../regbankselect-mui-regbankselect.mir | 18 ++--
.../AMDGPU/GlobalISel/regbankselect-mui.ll| 84 ++-
.../AMDGPU/GlobalISel/regbankselect-mui.mir | 51 ++-
9 files changed, 191 insertions(+), 178 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineSSAContext.cpp
b/llvm/lib/CodeGen/MachineSSAContext.cpp
index e384187b6e8593..8e13c0916dd9e1 100644
--- a/llvm/lib/CodeGen/MachineSSAContext.cpp
+++ b/llvm/lib/CodeGen/MachineSSAContext.cpp
@@ -54,9 +54,34 @@ const MachineBasicBlock
*MachineSSAContext::getDefBlock(Register value) const {
return F->getRegInfo().getVRegDef(value)->getParent();
}
+static bool isUndef(const MachineInstr &MI) {
+ return MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+ MI.getOpcode() == TargetOpcode::IMPLICIT_DEF;
+}
+
+/// MachineInstr equivalent of PHINode::hasConstantOrUndefValue() for G_PHI.
template <>
bool MachineSSAContext::isConstantOrUndefValuePhi(const MachineInstr &Phi) {
- return Phi.isConstantValuePHI();
+ if (!Phi.isPHI())
+return false;
+
+ // In later passes PHI may appear with an undef operand, getVRegDef can fail.
+ if (Phi.getOpcode() == TargetOpcode::PHI)
+return Phi.isConstantValuePHI();
+
+ // For G_PHI we do equivalent of PHINode::hasConstantOrUndefValue().
+ const MachineRegisterInfo &MRI = Phi.getMF()->getRegInfo();
+ Register This = Phi.getOperand(0).getReg();
+ Register ConstantValue;
+ for (unsigned i = 1, e = Phi.getNumOperands(); i < e; i += 2) {
+Register Incoming = Phi.getOperand(i).getReg();
+if (Incoming != This && !isUndef(*MRI.getVRegDef(Incoming))) {
+ if (ConstantValue && ConstantValue != Incoming)
+return false;
+ ConstantValue = Incoming;
+}
+ }
+ return true;
}
template <>
diff --git
a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
index ce00edf3363f77..9694a340b5e906 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
@@ -1,24 +1,24 @@
# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 |
FileCheck %s
# CHECK-LABEL: MachineUniformityInfo for function: hidden_diverge
# CHECK-LABEL: BLOCK bb.0
-# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_INTRINSIC
intrinsic(@llvm.amdgcn.workitem.id.x)
-# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s1) = G_ICMP intpred(slt)
-# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s1) = G_XOR %{{[0-9]*}}:_,
%{{[0-9]*}}:_
-# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s1), %{{[0-9]*}}:_(s64) =
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if)
-# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s1), %{{[0-9]*}}:_(s64) =
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if)
-# CHECK: DIVERGENT: G_BRCOND %{{[0-9]*}}:_(s1), %bb.1
-# CHECK: DIVERGENT: G_BR %bb.2
+# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_INTRINSIC
intrinsic(@llvm.amdgcn.workitem.id.x)
+# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s1) = G_ICMP intpred(slt)
+# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s1) = G_XOR %{{[0-9]*}}:_,
%{{[0-9]*}}:_
+# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s1), %{{[0-9]*}}:_(s64) =
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if)
+# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s1), %{{[0-9]*}}:_(s64) =
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if)
+# CHECK: DIVERGENT: G_BRCOND %{{[0-9]*}}:_(s1), %bb.1
+# CHECK: DIVERGENT: G_BR %bb.2
# CHECK-LABEL: BLOCK bb.1
# CHECK-LABEL: BLOCK bb.2
-# CHECK: D
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: AMDGPURegBankSelect (PR #112863)
@@ -66,9 +81,232 @@ FunctionPass *llvm::createAMDGPURegBankSelectPass() {
return new AMDGPURegBankSelect();
}
+class RegBankSelectHelper {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA;
+ const MachineUniformityInfo &MUI;
+ const SIRegisterInfo &TRI;
+ const RegisterBank *SgprRB;
+ const RegisterBank *VgprRB;
+ const RegisterBank *VccRB;
+
+public:
+ RegBankSelectHelper(MachineIRBuilder &B,
+ AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA,
+ const MachineUniformityInfo &MUI,
+ const SIRegisterInfo &TRI, const RegisterBankInfo &RBI)
+ : B(B), MRI(*B.getMRI()), ILMA(ILMA), MUI(MUI), TRI(TRI),
+SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)),
+VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
+VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {}
+
+ bool shouldRegBankSelect(MachineInstr &MI) {
+return MI.isPreISelOpcode() || MI.isCopy();
+ }
+
+ // Temporal divergence copy: COPY to vgpr with implicit use of $exec inside
of
+ // the cycle
+ // Note: uniformity analysis does not consider that registers with vgpr def
+ // are divergent (you can have uniform value in vgpr).
+ // - TODO: implicit use of $exec could be implemented as indicator that
+ // instruction is divergent
+ bool isTemporalDivergenceCopy(Register Reg) {
+MachineInstr *MI = MRI.getVRegDef(Reg);
+if (!MI->isCopy())
+ return false;
+
+for (auto Op : MI->implicit_operands()) {
petar-avramovic wrote:
There is nothing useful in real operands, it is a simple sgpr to vgpr COPY
which is quite common. What makes that COPY special is implicit exec, for
example:
`%21:vgpr_32(s32) = COPY %8:sgpr(s32), implicit $exec_lo`
implicit exec is there to stop other passes from moving the COPY outside of the
loop.
https://github.com/llvm/llvm-project/pull/112863
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] clang/AMDGPU: Emit grid size builtins with range metadata (PR #113038)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/113038
>From 6981d5ad80130130d373b8c879a88b7d727b0115 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:39:06 +0400
Subject: [PATCH] clang/AMDGPU: Emit grid size builtins with range metadata
These cannot be 0.
---
clang/lib/CodeGen/CGBuiltin.cpp | 6 ++
clang/test/CodeGenOpenCL/builtins-amdgcn.cl | 3 ++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 34fedd67114751..3e627667cf4da0 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18671,6 +18671,12 @@ Value *EmitAMDGPUGridSize(CodeGenFunction &CGF,
unsigned Index) {
auto *GEP = CGF.Builder.CreateGEP(CGF.Int8Ty, DP, Offset);
auto *LD = CGF.Builder.CreateLoad(
Address(GEP, CGF.Int32Ty, CharUnits::fromQuantity(4)));
+
+ llvm::MDBuilder MDB(CGF.getLLVMContext());
+
+ // Known non-zero.
+ LD->setMetadata(llvm::LLVMContext::MD_range,
+ MDB.createRange(APInt(32, 1), APInt::getZero(32)));
LD->setMetadata(llvm::LLVMContext::MD_invariant_load,
llvm::MDNode::get(CGF.getLLVMContext(), {}));
return LD;
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl
index 9132cc8a717e0f..3bc6107b7fd40d 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl
@@ -639,7 +639,7 @@ void test_get_workgroup_size(int d, global int *out)
// CHECK-LABEL: @test_get_grid_size(
// CHECK: {{.*}}call align 4 dereferenceable(64){{.*}} ptr addrspace(4)
@llvm.amdgcn.dispatch.ptr()
// CHECK: getelementptr inbounds i8, ptr addrspace(4) %{{.*}}, i64 %{{.+}}
-// CHECK: load i32, ptr addrspace(4) %{{.*}}, align 4, !invariant.load
+// CHECK: load i32, ptr addrspace(4) %{{.*}}, align 4, !range
[[$GRID_RANGE:![0-9]+]], !invariant.load
void test_get_grid_size(int d, global int *out)
{
switch (d) {
@@ -896,5 +896,6 @@ void test_set_fpenv(unsigned long env) {
__builtin_amdgcn_set_fpenv(env);
}
+// CHECK-DAG: [[$GRID_RANGE]] = !{i32 1, i32 0}
// CHECK-DAG: [[$WS_RANGE]] = !{i16 1, i16 1025}
// CHECK-DAG: attributes #[[$NOUNWIND_READONLY]] = { convergent mustprogress
nocallback nofree nounwind willreturn memory(none) }
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: AMDGPURegBankLegalize (PR #112864)
@@ -69,11 +82,297 @@ FunctionPass *llvm::createAMDGPURegBankLegalizePass() {
return new AMDGPURegBankLegalize();
}
-using namespace AMDGPU;
+const RegBankLegalizeRules &getRules(const GCNSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ static std::mutex GlobalMutex;
+ static SmallDenseMap>
+ CacheForRuleSet;
+ std::lock_guard Lock(GlobalMutex);
+ if (!CacheForRuleSet.contains(ST.getGeneration())) {
+auto Rules = std::make_unique(ST, MRI);
+CacheForRuleSet[ST.getGeneration()] = std::move(Rules);
+ } else {
+CacheForRuleSet[ST.getGeneration()]->refreshRefs(ST, MRI);
+ }
+ return *CacheForRuleSet[ST.getGeneration()];
+}
+
+class AMDGPURegBankLegalizeCombiner {
+ MachineIRBuilder &B;
+ MachineRegisterInfo &MRI;
+ const SIRegisterInfo &TRI;
+ const RegisterBank *SgprRB;
+ const RegisterBank *VgprRB;
+ const RegisterBank *VccRB;
+
+ static constexpr LLT S1 = LLT::scalar(1);
+ static constexpr LLT S16 = LLT::scalar(16);
+ static constexpr LLT S32 = LLT::scalar(32);
+ static constexpr LLT S64 = LLT::scalar(64);
+
+public:
+ AMDGPURegBankLegalizeCombiner(MachineIRBuilder &B, const SIRegisterInfo &TRI,
+const RegisterBankInfo &RBI)
+ : B(B), MRI(*B.getMRI()), TRI(TRI),
+SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)),
+VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
+VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
+
+ bool isLaneMask(Register Reg) {
+const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
+if (RB && RB->getID() == AMDGPU::VCCRegBankID)
+ return true;
+
+const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
+return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1);
+ }
+
+ void cleanUpAfterCombine(MachineInstr &MI, MachineInstr *Optional0) {
+MI.eraseFromParent();
+if (Optional0 && isTriviallyDead(*Optional0, MRI))
+ Optional0->eraseFromParent();
+ }
+
+ std::pair tryMatch(Register Src, unsigned Opcode) {
+MachineInstr *MatchMI = MRI.getVRegDef(Src);
+if (MatchMI->getOpcode() != Opcode)
+ return {nullptr, Register()};
+return {MatchMI, MatchMI->getOperand(1).getReg()};
+ }
+
+ void tryCombineCopy(MachineInstr &MI) {
+using namespace llvm::MIPatternMatch;
+Register Dst = MI.getOperand(0).getReg();
+Register Src = MI.getOperand(1).getReg();
+// Skip copies of physical registers.
+if (!Dst.isVirtual() || !Src.isVirtual())
+ return;
+
+// This is a cross bank copy, sgpr S1 to lane mask.
+//
+// %Src:sgpr(s1) = G_TRUNC %TruncS32Src:sgpr(s32)
+// %Dst:lane-mask(s1) = COPY %Src:sgpr(s1)
+// ->
+// %Dst:lane-mask(s1) = G_COPY_VCC_SCC %TruncS32Src:sgpr(s32)
+if (isLaneMask(Dst) && MRI.getRegBankOrNull(Src) == SgprRB) {
+ auto [Trunc, TruncS32Src] = tryMatch(Src, AMDGPU::G_TRUNC);
+ assert(Trunc && MRI.getType(TruncS32Src) == S32 &&
+ "sgpr S1 must be result of G_TRUNC of sgpr S32");
+
+ B.setInstr(MI);
+ // Ensure that truncated bits in BoolSrc are 0.
+ auto One = B.buildConstant({SgprRB, S32}, 1);
+ auto BoolSrc = B.buildAnd({SgprRB, S32}, TruncS32Src, One);
+ B.buildInstr(AMDGPU::G_COPY_VCC_SCC, {Dst}, {BoolSrc});
+ cleanUpAfterCombine(MI, Trunc);
+ return;
+}
+
+// Src = G_READANYLANE RALSrc
+// Dst = COPY Src
+// ->
+// Dst = RALSrc
+if (MRI.getRegBankOrNull(Dst) == VgprRB &&
+MRI.getRegBankOrNull(Src) == SgprRB) {
+ auto [RAL, RALSrc] = tryMatch(Src, AMDGPU::G_READANYLANE);
+ if (!RAL)
+return;
+
+ assert(MRI.getRegBank(RALSrc) == VgprRB);
+ MRI.replaceRegWith(Dst, RALSrc);
+ cleanUpAfterCombine(MI, RAL);
+ return;
+}
+ }
+
+ void tryCombineS1AnyExt(MachineInstr &MI) {
+// %Src:sgpr(S1) = G_TRUNC %TruncSrc
+// %Dst = G_ANYEXT %Src:sgpr(S1)
+// ->
+// %Dst = G_... %TruncSrc
+Register Dst = MI.getOperand(0).getReg();
+Register Src = MI.getOperand(1).getReg();
+if (MRI.getType(Src) != S1)
+ return;
+
+auto [Trunc, TruncSrc] = tryMatch(Src, AMDGPU::G_TRUNC);
+if (!Trunc)
+ return;
+
+LLT DstTy = MRI.getType(Dst);
+LLT TruncSrcTy = MRI.getType(TruncSrc);
+
+if (DstTy == TruncSrcTy) {
+ MRI.replaceRegWith(Dst, TruncSrc);
+ cleanUpAfterCombine(MI, Trunc);
+ return;
+}
+
+B.setInstr(MI);
+
+if (DstTy == S32 && TruncSrcTy == S64) {
+ auto Unmerge = B.buildUnmerge({SgprRB, S32}, TruncSrc);
+ MRI.replaceRegWith(Dst, Unmerge.getReg(0));
+ cleanUpAfterCombine(MI, Trunc);
+ return;
+}
+
+if (DstTy == S32 && TruncSrcTy == S16) {
+ B.buildAnyExt(Dst, TruncSrc);
+ cleanUpAfterCombine(MI, Trunc);
+ return;
+}
+
+if (DstTy == S16 && TruncSrcTy == S32) {
+ B.buildTrunc(Dst, TruncSrc);
+ cleanUpAfterCombine(MI, Trunc);
+ return;
+}
+
+llvm_unreachable("missing an
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: AMDGPURegBankLegalize (PR #112864)
@@ -697,6 +697,15 @@ MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
}
+MachineInstrBuilder
+MachineIRBuilder::buildUnmerge(MachineRegisterInfo::VRegAttrs Attrs,
+ const SrcOp &Op) {
+ LLT OpTy = Op.getLLTTy(*getMRI());
+ unsigned NumRegs = OpTy.getSizeInBits() / Attrs.Ty.getSizeInBits();
petar-avramovic wrote:
divideCoefficientBy works only for vectors, we need to unmerge scalars also.
Don't know about scalable vectors, they seem to only be used to say something
is legal, don't know if there is actual lowering done for them. Other places in
builder don't check for them.
https://github.com/llvm/llvm-project/pull/112864
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Propagate amdgpu-max-num-workgroups attribute (PR #113018)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/113018
>From 27426a189d748ea66ad4c16f3fbee445ad1643e5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 18 Oct 2024 23:05:51 +0400
Subject: [PATCH 1/4] AMDGPU: Propagate amdgpu-max-num-workgroups attribute
I'm not sure what the interpretation of 0 is supposed to be,
AMDGPUUsage doesn't say.
---
llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp | 154 +++-
...ttr-amdgpu-max-num-workgroups-propagate.ll | 228 ++
2 files changed, 380 insertions(+), 2 deletions(-)
create mode 100644
llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups-propagate.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
index 2ae34636005eac..d7a7db5b556dd2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
@@ -179,6 +179,11 @@ class AMDGPUInformationCache : public InformationCache {
return {ST.getMinFlatWorkGroupSize(), ST.getMaxFlatWorkGroupSize()};
}
+ SmallVector getMaxNumWorkGroups(const Function &F) {
+const GCNSubtarget &ST = TM.getSubtarget(F);
+return ST.getMaxNumWorkGroups(F);
+ }
+
/// Get code object version.
unsigned getCodeObjectVersion() const { return CodeObjectVersion; }
@@ -821,6 +826,150 @@ AAAMDFlatWorkGroupSize::createForPosition(const
IRPosition &IRP,
"AAAMDFlatWorkGroupSize is only valid for function position");
}
+struct TupleDecIntegerRangeState : public AbstractState {
+ DecIntegerState X, Y, Z;
+
+ bool isValidState() const override {
+return X.isValidState() && Y.isValidState() && Z.isValidState();
+ }
+
+ bool isAtFixpoint() const override {
+return X.isAtFixpoint() && Y.isAtFixpoint() && Z.isAtFixpoint();
+ }
+
+ ChangeStatus indicateOptimisticFixpoint() override {
+return X.indicateOptimisticFixpoint() | Y.indicateOptimisticFixpoint() |
+ Z.indicateOptimisticFixpoint();
+ }
+
+ ChangeStatus indicatePessimisticFixpoint() override {
+return X.indicatePessimisticFixpoint() | Y.indicatePessimisticFixpoint() |
+ Z.indicatePessimisticFixpoint();
+ }
+
+ TupleDecIntegerRangeState operator^=(const TupleDecIntegerRangeState &Other)
{
+X ^= Other.X;
+Y ^= Other.Y;
+Z ^= Other.Z;
+return *this;
+ }
+
+ bool operator==(const TupleDecIntegerRangeState &Other) const {
+return X == Other.X && Y == Other.Y && Z == Other.Z;
+ }
+
+ TupleDecIntegerRangeState &getAssumed() { return *this; }
+ const TupleDecIntegerRangeState &getAssumed() const { return *this; }
+};
+
+using AAAMDMaxNumWorkgroupsState =
+StateWrapper;
+
+/// Propagate amdgpu-max-num-workgroups attribute.
+struct AAAMDMaxNumWorkgroups
+: public StateWrapper {
+ using Base = StateWrapper;
+
+ AAAMDMaxNumWorkgroups(const IRPosition &IRP, Attributor &A) : Base(IRP) {}
+
+ void initialize(Attributor &A) override {
+Function *F = getAssociatedFunction();
+auto &InfoCache = static_cast(A.getInfoCache());
+
+SmallVector MaxNumWorkgroups = InfoCache.getMaxNumWorkGroups(*F);
+
+// FIXME: What is the interpretation of 0?
+for (unsigned &Entry : MaxNumWorkgroups) {
+ if (Entry == 0)
+Entry = std::numeric_limits::max();
+}
+
+X.takeKnownMinimum(MaxNumWorkgroups[0]);
+Y.takeKnownMinimum(MaxNumWorkgroups[1]);
+Z.takeKnownMinimum(MaxNumWorkgroups[2]);
+
+if (AMDGPU::isEntryFunctionCC(F->getCallingConv()))
+ indicatePessimisticFixpoint();
+ }
+
+ ChangeStatus updateImpl(Attributor &A) override {
+ChangeStatus Change = ChangeStatus::UNCHANGED;
+
+auto CheckCallSite = [&](AbstractCallSite CS) {
+ Function *Caller = CS.getInstruction()->getFunction();
+ LLVM_DEBUG(dbgs() << "[AAAMDMaxNumWorkgroups] Call " << Caller->getName()
+<< "->" << getAssociatedFunction()->getName() << '\n');
+
+ const auto *CallerInfo = A.getAAFor(
+ *this, IRPosition::function(*Caller), DepClassTy::REQUIRED);
+ if (!CallerInfo)
+return false;
+
+ Change |=
+ clampStateAndIndicateChange(this->getState(),
CallerInfo->getState());
+ return true;
+};
+
+bool AllCallSitesKnown = true;
+if (!A.checkForAllCallSites(CheckCallSite, *this, true, AllCallSitesKnown))
+ return indicatePessimisticFixpoint();
+
+return Change;
+ }
+
+ /// Create an abstract attribute view for the position \p IRP.
+ static AAAMDMaxNumWorkgroups &createForPosition(const IRPosition &IRP,
+ Attributor &A);
+
+ ChangeStatus manifest(Attributor &A) override {
+Function *F = getAssociatedFunction();
+// TODO: Skip adding if worst case?
+LLVMContext &Ctx = F->getContext();
+SmallString<32> Buffer;
+raw_svector_ostream OS(Buffer);
+OS << X.getAssumed() << ',' << Y.getAssumed() << ',' << Z.getAssumed();
+
+// TODO: Should annotate loads of the group size fo
[llvm-branch-commits] [llvm] AMDGPU: Mark grid size loads with range metadata (PR #113019)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/113019
>From 8c4d57e8f1039101b380d13c69986870365a2d4e Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:18:45 +0400
Subject: [PATCH] AMDGPU: Mark grid size loads with range metadata
Only handles the v5 case.
---
.../AMDGPU/AMDGPULowerKernelAttributes.cpp| 33 -
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp| 1 +
...amdgpu-max-num-workgroups-load-annotate.ll | 124 ++
3 files changed, 154 insertions(+), 4 deletions(-)
create mode 100644
llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
index 1bb5e794da7dd6..5fc0c36359b6f5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
@@ -23,6 +23,7 @@
#include "llvm/IR/InstIterator.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
+#include "llvm/IR/MDBuilder.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Pass.h"
@@ -83,6 +84,20 @@ Function *getBasePtrIntrinsic(Module &M, bool IsV5OrAbove) {
} // end anonymous namespace
+static void annotateGridSizeLoadWithRangeMD(LoadInst *Load,
+uint32_t MaxNumGroups) {
+ if (MaxNumGroups == 0 || MaxNumGroups ==
std::numeric_limits::max())
+return;
+
+ if (!Load->getType()->isIntegerTy(32))
+return;
+
+ // TODO: If there is existing range metadata, preserve it if it is stricter.
+ MDBuilder MDB(Load->getContext());
+ MDNode *Range = MDB.createRange(APInt(32, 1), APInt(32, MaxNumGroups + 1));
+ Load->setMetadata(LLVMContext::MD_range, Range);
+}
+
static bool processUse(CallInst *CI, bool IsV5OrAbove) {
Function *F = CI->getParent()->getParent();
@@ -92,7 +107,11 @@ static bool processUse(CallInst *CI, bool IsV5OrAbove) {
const bool HasUniformWorkGroupSize =
F->getFnAttribute("uniform-work-group-size").getValueAsBool();
- if (!HasReqdWorkGroupSize && !HasUniformWorkGroupSize)
+ SmallVector MaxNumWorkgroups =
+ AMDGPU::getIntegerVecAttribute(*F, "amdgpu-max-num-workgroups", 3);
+
+ if (!HasReqdWorkGroupSize && !HasUniformWorkGroupSize &&
+ none_of(MaxNumWorkgroups, [](unsigned X) { return X != 0; }))
return false;
Value *BlockCounts[3] = {nullptr, nullptr, nullptr};
@@ -133,16 +152,22 @@ static bool processUse(CallInst *CI, bool IsV5OrAbove) {
if (IsV5OrAbove) { // Base is ImplicitArgPtr.
switch (Offset) {
case HIDDEN_BLOCK_COUNT_X:
-if (LoadSize == 4)
+if (LoadSize == 4) {
BlockCounts[0] = Load;
+ annotateGridSizeLoadWithRangeMD(Load, MaxNumWorkgroups[0]);
+}
break;
case HIDDEN_BLOCK_COUNT_Y:
-if (LoadSize == 4)
+if (LoadSize == 4) {
BlockCounts[1] = Load;
+ annotateGridSizeLoadWithRangeMD(Load, MaxNumWorkgroups[1]);
+}
break;
case HIDDEN_BLOCK_COUNT_Z:
-if (LoadSize == 4)
+if (LoadSize == 4) {
BlockCounts[2] = Load;
+ annotateGridSizeLoadWithRangeMD(Load, MaxNumWorkgroups[2]);
+}
break;
case HIDDEN_GROUP_SIZE_X:
if (LoadSize == 2)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
index 54b17ca2cffb15..b18ce90cf45dba 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -369,6 +369,7 @@ const AMDGPUSubtarget &AMDGPUSubtarget::get(const
TargetMachine &TM, const Funct
TM.getSubtarget(F));
}
+// FIXME: This has no reason to be in subtarget
SmallVector
AMDGPUSubtarget::getMaxNumWorkGroups(const Function &F) const {
return AMDGPU::getIntegerVecAttribute(F, "amdgpu-max-num-workgroups", 3,
diff --git
a/llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
b/llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
new file mode 100644
index 00..9064292129928f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
@@ -0,0 +1,124 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa
-passes=amdgpu-lower-kernel-attributes %s | FileCheck %s
+
+define i32 @use_grid_size_x_max_num_workgroups() #0 {
+; CHECK-LABEL: define i32 @use_grid_size_x_max_num_workgroups(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:[[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4)
@llvm.amdgcn.implicitarg.ptr()
+; CHECK-NEXT:[[GRID_SIZE_X:%.*]] = load i32, ptr addrspace(4)
[[IMPLICITARG_PTR]], align 4, !range [[RNG0:![0-9]+]]
+; CHECK-NEXT:ret i32 [[GRID_SIZE_X]]
+;
+ %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+ %grid.size.x = load i32,
[llvm-branch-commits] [llvm] AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups (PR #113751)
https://github.com/arsenm edited https://github.com/llvm/llvm-project/pull/113751 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: AMDGPURegBankLegalize (PR #112864)
@@ -217,6 +217,74 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr
&I) const {
return true;
}
+bool AMDGPUInstructionSelector::selectCOPY_SCC_VCC(MachineInstr &I) const {
petar-avramovic wrote:
This allows for more registers to be allocated to sgpr.
Avoiding them could be done later in some optimization pass when we can decide
if we want to do global-isel equivalent of moveToVALU, but we don't do it for
correctness but to influence register allocation to sgpr or vgpr.
Why would we want to avoid vcc to scc copy? Question for @nhaehnle also.
https://github.com/llvm/llvm-project/pull/112864
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: AMDGPURegBankLegalize (PR #112864)
petar-avramovic wrote: Added LLVM_DEBUG around dumps, RB->RegBank rename for methods and class names https://github.com/llvm/llvm-project/pull/112864 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Clang] Consider outer instantiation scopes for constraint normalization (PR #114951)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Younan Zhang (zyn0217)
Changes
Backport 227afac3
---
Full diff: https://github.com/llvm/llvm-project/pull/114951.diff
2 Files Affected:
- (modified) clang/lib/Sema/SemaConcept.cpp (+1-1)
- (modified) clang/test/SemaTemplate/concepts-out-of-line-def.cpp (+16)
``diff
diff --git a/clang/lib/Sema/SemaConcept.cpp b/clang/lib/Sema/SemaConcept.cpp
index 244f6ef2f53faa..c45443d76e6bad 100644
--- a/clang/lib/Sema/SemaConcept.cpp
+++ b/clang/lib/Sema/SemaConcept.cpp
@@ -967,7 +967,7 @@ static const Expr
*SubstituteConstraintExpressionWithoutSatisfaction(
// parameters that the surrounding function hasn't been instantiated yet.
Note
// this may happen while we're comparing two templates' constraint
// equivalence.
- LocalInstantiationScope ScopeForParameters(S);
+ LocalInstantiationScope ScopeForParameters(S,
/*CombineWithOuterScope=*/true);
if (auto *FD = DeclInfo.getDecl()->getAsFunction())
for (auto *PVD : FD->parameters()) {
if (!PVD->isParameterPack()) {
diff --git a/clang/test/SemaTemplate/concepts-out-of-line-def.cpp
b/clang/test/SemaTemplate/concepts-out-of-line-def.cpp
index 333187b0d74ad6..c5dd855f0c000b 100644
--- a/clang/test/SemaTemplate/concepts-out-of-line-def.cpp
+++ b/clang/test/SemaTemplate/concepts-out-of-line-def.cpp
@@ -622,3 +622,19 @@ void A::method(Ts&... ts)
} {}
}
+
+namespace GH114685 {
+
+template struct ptr {
+ template
+ friend ptr make_item(auto &&args)
+requires(sizeof(args) > 1);
+};
+
+template
+ptr make_item(auto &&args)
+ requires(sizeof(args) > 1) {}
+
+ptr p;
+
+} // namespace GH114685
``
https://github.com/llvm/llvm-project/pull/114951
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Clang] Consider outer instantiation scopes for constraint normalization (PR #114951)
https://github.com/zyn0217 edited https://github.com/llvm/llvm-project/pull/114951 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Clang] Consider outer instantiation scopes for constraint normalization (PR #114951)
https://github.com/zyn0217 milestoned https://github.com/llvm/llvm-project/pull/114951 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/19.x: [Clang] Consider outer instantiation scopes for constraint normalization (PR #114951)
https://github.com/zyn0217 created
https://github.com/llvm/llvm-project/pull/114951
Backport 227afac3
>From ee31957b09ee5cb03d36b15fcc59cff5754aa553 Mon Sep 17 00:00:00 2001
From: Younan Zhang
Date: Tue, 5 Nov 2024 16:25:35 +0800
Subject: [PATCH] release/19.x: [Clang] Consider outer instantiation scopes for
constraint normalization
Backport 227afac3
---
clang/lib/Sema/SemaConcept.cpp | 2 +-
.../SemaTemplate/concepts-out-of-line-def.cpp| 16
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Sema/SemaConcept.cpp b/clang/lib/Sema/SemaConcept.cpp
index 244f6ef2f53faa..c45443d76e6bad 100644
--- a/clang/lib/Sema/SemaConcept.cpp
+++ b/clang/lib/Sema/SemaConcept.cpp
@@ -967,7 +967,7 @@ static const Expr
*SubstituteConstraintExpressionWithoutSatisfaction(
// parameters that the surrounding function hasn't been instantiated yet.
Note
// this may happen while we're comparing two templates' constraint
// equivalence.
- LocalInstantiationScope ScopeForParameters(S);
+ LocalInstantiationScope ScopeForParameters(S,
/*CombineWithOuterScope=*/true);
if (auto *FD = DeclInfo.getDecl()->getAsFunction())
for (auto *PVD : FD->parameters()) {
if (!PVD->isParameterPack()) {
diff --git a/clang/test/SemaTemplate/concepts-out-of-line-def.cpp
b/clang/test/SemaTemplate/concepts-out-of-line-def.cpp
index 333187b0d74ad6..c5dd855f0c000b 100644
--- a/clang/test/SemaTemplate/concepts-out-of-line-def.cpp
+++ b/clang/test/SemaTemplate/concepts-out-of-line-def.cpp
@@ -622,3 +622,19 @@ void A::method(Ts&... ts)
} {}
}
+
+namespace GH114685 {
+
+template struct ptr {
+ template
+ friend ptr make_item(auto &&args)
+requires(sizeof(args) > 1);
+};
+
+template
+ptr make_item(auto &&args)
+ requires(sizeof(args) > 1) {}
+
+ptr p;
+
+} // namespace GH114685
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [DataLayout][LangRef] Split non-integral and unstable pointer properties (PR #105735)
nikic wrote: I think this change would benefit from an RFC on discourse, for wider visibility. Something that's not super clear to me is how to reconcile the statements about pointer/integer casts and in-memory type punning. I'd expect that ptrtoint returns an i128 value and if you cast back that value to a pointer, you preserve capabilities. If you truncate the i128 value to i64 and then cast it back, then you obviously don't -- but LLVM should already know that truncation is not a value preserving operation :) Or does ptrtoint actually directly return an i64 value? If it does, then I think you must have additional changes for that, because I don't think that LLVM supports that directly. And if you do, then that may be sufficient? https://github.com/llvm/llvm-project/pull/105735 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] Add documentation for Multilib custom flags (PR #114998)
llvmbot wrote: @llvm/pr-subscribers-clang Author: Victor Campos (vhscampos) Changes --- Full diff: https://github.com/llvm/llvm-project/pull/114998.diff 1 Files Affected: - (modified) clang/docs/Multilib.rst (+116) ``diff diff --git a/clang/docs/Multilib.rst b/clang/docs/Multilib.rst index 7637d0db9565b8..7c165d149d7a4c 100644 --- a/clang/docs/Multilib.rst +++ b/clang/docs/Multilib.rst @@ -122,6 +122,104 @@ subclass and a suitable base multilib variant is present then the It is the responsibility of layered multilib authors to ensure that headers and libraries in each layer are complete enough to mask any incompatibilities. +Multilib custom flags += + +Introduction + + +The multilib mechanism supports library variants that correspond to target, +code generation or language command-line flags. Examples include ``--target``, +``-mcpu``, ``-mfpu``, ``-mbranch-protection``, ``-fno-rtti``. However, some library +variants are particular to features that do not correspond to any command-line +option. Multithreading and semihosting, for instance, have no associated +compiler option. + +In order to support the selection of variants for which no compiler option +exists, the multilib specification includes the concept of *custom flags*. +These flags have no impact on code generation and are only used in the multilib +processing. + +Multilib custom flags follow this format in the driver invocation: + +:: + + -fmultilib-flag= + +They are fed into the multilib system alongside the remaining flags. + +Custom flag declarations + + +Custom flags can be declared in the YAML file under the *Flags* section. + +.. code-block:: yaml + + Flags: + - Name: multithreaded +Values: +- Name: no-multithreaded + ExtraBuildArgs: [-D__SINGLE_THREAD__] +- Name: multithreaded +Default: no-multithreaded + +* Name: the name to categorize a flag. +* Values: a list of flag *Value*s (defined below). +* Default: it specifies the name of the value this flag should take if not + specified in the command-line invocation. It must be one value from the Values + field. + +A Default value is useful to save users from specifying custom flags that have a +most commonly used value. + +Each flag *Value* is defined as: + +* Name: name of the value. This is the string to be used in + ``-fmultilib-flag=``. +* ExtraBuildArgs: a list of strings corresponding to the extra build arguments + used to build a library variant that's in accordance to this specific custom + flag value. + +The namespace of flag values is common across all flags. This means that flag +value names must be unique. + +Usage of custom flags in the *Variants* specifications +-- + +Library variants should list their requirement on one or more custom flags like +they do for any other flag. Each requirement must be listed as +``-fmultilib-flag=``. + +A variant that does not specify a requirement on one particular flag can be +matched against any value of that flag. + +Use of ``-print-multi-lib`` by build systems + + +Some library build systems use the ``-print-multi-lib`` command-line option to +query what library variants are shipped or supported by the target compiler and +what command-line options should be used to build the variants. + +In this use case, a build system queries the target toolchain about what library +variants should be built. With this information in hand, the build system may +launch the build of each variant using the collected command-line arguments. + +For example, in *newlib*, multithreading is enabled by default and can be +disabled by defining the ``__SINGLE_THREAD__`` macro. Therefore a multilib YAML +file that is used to drive a *newlib* build must encode this information in the +output of ``-print-multi-lib``. + +To account for this use case, custom flag values may specify the +*ExtraBuildArgs* field. This optional field is a list of strings to be printed +alongside the other command-line arguments in the output of +``-print-multi-lib``. In the example of *newlib* and its multithreading support, +a variant specific for single threaded execution should list +``-D__SINGLE_THREAD__`` in its corresponding flag value's *ExtraBuildArgs* +field. + +Since this information is specific for users of ``-print-multi-lib``, that is, +for *builders* of library variants, it has no relevance in library *selection*. + Stability = @@ -222,6 +320,24 @@ For a more comprehensive example see # Flags is a list of one or more strings. Flags: [--target=thumbv7m-none-eabi] + # Custom flag declarations. Each item is a different declaration. + Flags: +# Name of the flag + - Name: multithreaded +# List of custom flag values +Values: + # Name of the custom flag value. To be used in -fmultilib-flag=. +- Name: no-multithreaded + # Ext
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
optimisan wrote: The default value is false, but two targets are setting it to true. Currently MachineSink is added by generic TargetPassConfig. Can add the option to `CGPassBuilderOptions` so targets can set it there instead. https://github.com/llvm/llvm-project/pull/114746 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen] Move EnableSinkAndFold to TargetOptions (PR #114746)
https://github.com/optimisan closed https://github.com/llvm/llvm-project/pull/114746 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM (PR #113874)
@@ -1,5 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s + +; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=irtranslator -o - %s \ arsenm wrote: It seems to just be a general analysis print. Can we get rid of the flag and use a general mechanism? https://github.com/llvm/llvm-project/pull/113874 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] d560dca - Revert "[XRay][AArch64] Support -fxray-shared (#114431)"
Author: Felipe de Azevedo Piovezan
Date: 2024-11-05T08:43:16-08:00
New Revision: d560dcabad287952024ffb0014cfcce1f4672535
URL:
https://github.com/llvm/llvm-project/commit/d560dcabad287952024ffb0014cfcce1f4672535
DIFF:
https://github.com/llvm/llvm-project/commit/d560dcabad287952024ffb0014cfcce1f4672535.diff
LOG: Revert "[XRay][AArch64] Support -fxray-shared (#114431)"
This reverts commit 7767aa45abf9706fa5ec9a2b182f3ccde92a93f0.
Added:
Modified:
clang/lib/Driver/XRayArgs.cpp
clang/test/Driver/XRay/xray-shared.cpp
compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
compiler-rt/lib/xray/CMakeLists.txt
compiler-rt/lib/xray/xray_trampoline_AArch64.S
compiler-rt/test/xray/TestCases/Posix/basic-mode-dso.cpp
compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp
compiler-rt/test/xray/TestCases/Posix/dlopen.cpp
compiler-rt/test/xray/TestCases/Posix/dso-dep-chains.cpp
compiler-rt/test/xray/TestCases/Posix/patch-premain-dso.cpp
compiler-rt/test/xray/TestCases/Posix/patching-unpatching-dso.cpp
Removed:
diff --git a/clang/lib/Driver/XRayArgs.cpp b/clang/lib/Driver/XRayArgs.cpp
index c270a94f216ebd..d0bb5d4887c184 100644
--- a/clang/lib/Driver/XRayArgs.cpp
+++ b/clang/lib/Driver/XRayArgs.cpp
@@ -67,12 +67,8 @@ XRayArgs::XRayArgs(const ToolChain &TC, const ArgList &Args)
{
false)) {
XRayShared = true;
-// Certain targets support DSO instrumentation
-switch (Triple.getArch()) {
-case llvm::Triple::aarch64:
-case llvm::Triple::x86_64:
- break;
-default:
+// DSO instrumentation is currently limited to x86_64
+if (Triple.getArch() != llvm::Triple::x86_64) {
D.Diag(diag::err_drv_unsupported_opt_for_target)
<< "-fxray-shared" << Triple.str();
}
diff --git a/clang/test/Driver/XRay/xray-shared.cpp
b/clang/test/Driver/XRay/xray-shared.cpp
index 820c5b363d2c62..e331fefed1e0c9 100644
--- a/clang/test/Driver/XRay/xray-shared.cpp
+++ b/clang/test/Driver/XRay/xray-shared.cpp
@@ -1,21 +1,15 @@
-// Check supported targets
// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fPIC -fxray-instrument
-fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -### --target=aarch64-unknown-linux-gnu -fPIC -fxray-instrument
-fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s
-
-// Check unsupported targets
-// RUN: not %clang -### --target=arm-unknown-linux-gnu -fPIC -fxray-instrument
-fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR-TARGET
-// RUN: not %clang -### --target=mips-unknown-linux-gnu -fPIC
-fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s
--check-prefix=ERR-TARGET
-// RUN: not %clang -### --target=loongarch64-unknown-linux-gnu -fPIC
-fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s
--check-prefix=ERR-TARGET
-// RUN: not %clang -### --target=hexagon-unknown-linux-gnu -fPIC
-fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s
--check-prefix=ERR-TARGET
-// RUN: not %clang -### --target=powerpc64le-unknown-linux-gnu -fPIC
-fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s
--check-prefix=ERR-TARGET
-
-// Check PIC requirement
// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fpic -fxray-instrument
-fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s
// RUN: not %clang -### --target=x86_64-unknown-linux-gnu -fno-PIC
-fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s
--check-prefix=ERR-PIC
// RUN: not %clang -### --target=x86_64-unknown-linux-gnu -fno-pic
-fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s
--check-prefix=ERR-PIC
+
// On 64 bit darwin, PIC is always enabled
// RUN: %clang -### --target=x86_64-apple-darwin -fxray-instrument
-fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s
+// Check unsupported targets
+// RUN: not %clang -### --target=aarch64-pc-freebsd -fPIC -fxray-instrument
-fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR-TARGET
+// RUN: not %clang -### --target=arm64-apple-macos -fPIC -fxray-instrument
-fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR-TARGET
+
// CHECK: "-cc1" {{.*}}"-fxray-instrument" {{.*}}"-fxray-shared"
// ERR-TARGET: error: unsupported option '-fxray-shared' for target
// ERR-PIC: error: option '-fxray-shared' cannot be specified without '-fPIC'
diff --git a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
index b29ae179c2b4f4..fb4dfa7bd09dfe 100644
--- a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
+++ b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
@@ -104,7 +104,7 @@ else()
set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64}
powerpc64le ${HEXAGON} ${LOONGARCH64})
endif()
-set(ALL_XRAY_DSO_SUPPORTED_ARC
[llvm-branch-commits] Revert "[nfc][tsan] Move out `morder` params from __VA_ARGS__ (#114916)" (PR #115030)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/115030 This reverts commit a9f829a3d7556593e0814080c8e33eca09e3a51e. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Revert "[nfc][tsan] Move out `morder` params from __VA_ARGS__ (#114916)" (PR #115030)
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
This reverts commit a9f829a3d7556593e0814080c8e33eca09e3a51e.
---
Patch is 25.32 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/115030.diff
1 Files Affected:
- (modified) compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp (+126-126)
``diff
diff --git a/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
b/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
index 67106f59f6e7f5..6190e315f72c34 100644
--- a/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
+++ b/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
@@ -248,30 +248,30 @@ static T AtomicRMW(ThreadState *thr, uptr pc, volatile T
*a, T v, morder mo) {
struct OpLoad {
template
- static T NoTsanAtomic(morder mo, const volatile T *a) {
+ static T NoTsanAtomic(const volatile T *a, morder mo) {
return atomic_load(to_atomic(a), to_mo(mo));
}
#if __TSAN_HAS_INT128 && !SANITIZER_GO
- static a128 NoTsanAtomic(morder mo, const volatile a128 *a) {
+ static a128 NoTsanAtomic(const volatile a128 *a, morder mo) {
SpinMutexLock lock(&mutex128);
return *a;
}
#endif
template
- static T Atomic(ThreadState *thr, uptr pc, morder mo, const volatile T *a) {
+ static T Atomic(ThreadState *thr, uptr pc, const volatile T *a, morder mo) {
DCHECK(IsLoadOrder(mo));
// This fast-path is critical for performance.
// Assume the access is atomic.
if (!IsAcquireOrder(mo)) {
MemoryAccess(thr, pc, (uptr)a, AccessSize(),
kAccessRead | kAccessAtomic);
- return NoTsanAtomic(mo, a);
+ return NoTsanAtomic(a, mo);
}
// Don't create sync object if it does not exist yet. For example, an
atomic
// pointer is initialized to nullptr and then periodically acquire-loaded.
-T v = NoTsanAtomic(mo, a);
+T v = NoTsanAtomic(a, mo);
SyncVar *s = ctx->metamap.GetSyncIfExists((uptr)a);
if (s) {
SlotLocker locker(thr);
@@ -279,7 +279,7 @@ struct OpLoad {
thr->clock.Acquire(s->clock);
// Re-read under sync mutex because we need a consistent snapshot
// of the value and the clock we acquire.
- v = NoTsanAtomic(mo, a);
+ v = NoTsanAtomic(a, mo);
}
MemoryAccess(thr, pc, (uptr)a, AccessSize(),
kAccessRead | kAccessAtomic);
@@ -289,19 +289,19 @@ struct OpLoad {
struct OpStore {
template
- static void NoTsanAtomic(morder mo, volatile T *a, T v) {
+ static void NoTsanAtomic(volatile T *a, T v, morder mo) {
atomic_store(to_atomic(a), v, to_mo(mo));
}
#if __TSAN_HAS_INT128 && !SANITIZER_GO
- static void NoTsanAtomic(morder mo, volatile a128 *a, a128 v) {
+ static void NoTsanAtomic(volatile a128 *a, a128 v, morder mo) {
SpinMutexLock lock(&mutex128);
*a = v;
}
#endif
template
- static void Atomic(ThreadState *thr, uptr pc, morder mo, volatile T *a, T v)
{
+ static void Atomic(ThreadState *thr, uptr pc, volatile T *a, T v, morder mo)
{
DCHECK(IsStoreOrder(mo));
MemoryAccess(thr, pc, (uptr)a, AccessSize(),
kAccessWrite | kAccessAtomic);
@@ -310,7 +310,7 @@ struct OpStore {
// Strictly saying even relaxed store cuts off release sequence,
// so must reset the clock.
if (!IsReleaseOrder(mo)) {
- NoTsanAtomic(mo, a, v);
+ NoTsanAtomic(a, v, mo);
return;
}
SlotLocker locker(thr);
@@ -318,7 +318,7 @@ struct OpStore {
auto s = ctx->metamap.GetSyncOrCreate(thr, pc, (uptr)a, false);
Lock lock(&s->mtx);
thr->clock.ReleaseStore(&s->clock);
- NoTsanAtomic(mo, a, v);
+ NoTsanAtomic(a, v, mo);
}
IncrementEpoch(thr);
}
@@ -326,96 +326,96 @@ struct OpStore {
struct OpExchange {
template
- static T NoTsanAtomic(morder mo, volatile T *a, T v) {
+ static T NoTsanAtomic(volatile T *a, T v, morder mo) {
return func_xchg(a, v);
}
template
- static T Atomic(ThreadState *thr, uptr pc, morder mo, volatile T *a, T v) {
+ static T Atomic(ThreadState *thr, uptr pc, volatile T *a, T v, morder mo) {
return AtomicRMW(thr, pc, a, v, mo);
}
};
struct OpFetchAdd {
template
- static T NoTsanAtomic(morder mo, volatile T *a, T v) {
+ static T NoTsanAtomic(volatile T *a, T v, morder mo) {
return func_add(a, v);
}
template
- static T Atomic(ThreadState *thr, uptr pc, morder mo, volatile T *a, T v) {
+ static T Atomic(ThreadState *thr, uptr pc, volatile T *a, T v, morder mo) {
return AtomicRMW(thr, pc, a, v, mo);
}
};
struct OpFetchSub {
template
- static T NoTsanAtomic(morder mo, volatile T *a, T v) {
+ static T NoTsanAtomic(volatile T *a, T v, morder mo) {
return func_sub(a, v);
}
template
- static T Atomic(ThreadState *thr, uptr pc, morder mo, volatile T *a, T v) {
+ static T Atomic(ThreadState *thr, uptr pc, volatile T *a, T v, morder mo) {
[llvm-branch-commits] Reapply "[nfc][tsan] Move out `morder` params from __VA_ARGS__ (#114916)" (PR #115031)
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
This reverts commit dd6f380c8837c7df135a871250f8a10ee0abb101.
---
Patch is 25.32 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/115031.diff
1 Files Affected:
- (modified) compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp (+126-126)
``diff
diff --git a/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
b/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
index 6190e315f72c34..67106f59f6e7f5 100644
--- a/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
+++ b/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
@@ -248,30 +248,30 @@ static T AtomicRMW(ThreadState *thr, uptr pc, volatile T
*a, T v, morder mo) {
struct OpLoad {
template
- static T NoTsanAtomic(const volatile T *a, morder mo) {
+ static T NoTsanAtomic(morder mo, const volatile T *a) {
return atomic_load(to_atomic(a), to_mo(mo));
}
#if __TSAN_HAS_INT128 && !SANITIZER_GO
- static a128 NoTsanAtomic(const volatile a128 *a, morder mo) {
+ static a128 NoTsanAtomic(morder mo, const volatile a128 *a) {
SpinMutexLock lock(&mutex128);
return *a;
}
#endif
template
- static T Atomic(ThreadState *thr, uptr pc, const volatile T *a, morder mo) {
+ static T Atomic(ThreadState *thr, uptr pc, morder mo, const volatile T *a) {
DCHECK(IsLoadOrder(mo));
// This fast-path is critical for performance.
// Assume the access is atomic.
if (!IsAcquireOrder(mo)) {
MemoryAccess(thr, pc, (uptr)a, AccessSize(),
kAccessRead | kAccessAtomic);
- return NoTsanAtomic(a, mo);
+ return NoTsanAtomic(mo, a);
}
// Don't create sync object if it does not exist yet. For example, an
atomic
// pointer is initialized to nullptr and then periodically acquire-loaded.
-T v = NoTsanAtomic(a, mo);
+T v = NoTsanAtomic(mo, a);
SyncVar *s = ctx->metamap.GetSyncIfExists((uptr)a);
if (s) {
SlotLocker locker(thr);
@@ -279,7 +279,7 @@ struct OpLoad {
thr->clock.Acquire(s->clock);
// Re-read under sync mutex because we need a consistent snapshot
// of the value and the clock we acquire.
- v = NoTsanAtomic(a, mo);
+ v = NoTsanAtomic(mo, a);
}
MemoryAccess(thr, pc, (uptr)a, AccessSize(),
kAccessRead | kAccessAtomic);
@@ -289,19 +289,19 @@ struct OpLoad {
struct OpStore {
template
- static void NoTsanAtomic(volatile T *a, T v, morder mo) {
+ static void NoTsanAtomic(morder mo, volatile T *a, T v) {
atomic_store(to_atomic(a), v, to_mo(mo));
}
#if __TSAN_HAS_INT128 && !SANITIZER_GO
- static void NoTsanAtomic(volatile a128 *a, a128 v, morder mo) {
+ static void NoTsanAtomic(morder mo, volatile a128 *a, a128 v) {
SpinMutexLock lock(&mutex128);
*a = v;
}
#endif
template
- static void Atomic(ThreadState *thr, uptr pc, volatile T *a, T v, morder mo)
{
+ static void Atomic(ThreadState *thr, uptr pc, morder mo, volatile T *a, T v)
{
DCHECK(IsStoreOrder(mo));
MemoryAccess(thr, pc, (uptr)a, AccessSize(),
kAccessWrite | kAccessAtomic);
@@ -310,7 +310,7 @@ struct OpStore {
// Strictly saying even relaxed store cuts off release sequence,
// so must reset the clock.
if (!IsReleaseOrder(mo)) {
- NoTsanAtomic(a, v, mo);
+ NoTsanAtomic(mo, a, v);
return;
}
SlotLocker locker(thr);
@@ -318,7 +318,7 @@ struct OpStore {
auto s = ctx->metamap.GetSyncOrCreate(thr, pc, (uptr)a, false);
Lock lock(&s->mtx);
thr->clock.ReleaseStore(&s->clock);
- NoTsanAtomic(a, v, mo);
+ NoTsanAtomic(mo, a, v);
}
IncrementEpoch(thr);
}
@@ -326,96 +326,96 @@ struct OpStore {
struct OpExchange {
template
- static T NoTsanAtomic(volatile T *a, T v, morder mo) {
+ static T NoTsanAtomic(morder mo, volatile T *a, T v) {
return func_xchg(a, v);
}
template
- static T Atomic(ThreadState *thr, uptr pc, volatile T *a, T v, morder mo) {
+ static T Atomic(ThreadState *thr, uptr pc, morder mo, volatile T *a, T v) {
return AtomicRMW(thr, pc, a, v, mo);
}
};
struct OpFetchAdd {
template
- static T NoTsanAtomic(volatile T *a, T v, morder mo) {
+ static T NoTsanAtomic(morder mo, volatile T *a, T v) {
return func_add(a, v);
}
template
- static T Atomic(ThreadState *thr, uptr pc, volatile T *a, T v, morder mo) {
+ static T Atomic(ThreadState *thr, uptr pc, morder mo, volatile T *a, T v) {
return AtomicRMW(thr, pc, a, v, mo);
}
};
struct OpFetchSub {
template
- static T NoTsanAtomic(volatile T *a, T v, morder mo) {
+ static T NoTsanAtomic(morder mo, volatile T *a, T v) {
return func_sub(a, v);
}
template
- static T Atomic(ThreadState *thr, uptr pc, volatile T *a, T v, morder mo) {
+ static T Atomic(ThreadState *thr, uptr pc, morder mo, volatile T *a, T v) {
[llvm-branch-commits] Revert "[nfc][tsan] Eliminate a few macros" (PR #115028)
llvmbot wrote:
@llvm/pr-subscribers-compiler-rt-sanitizer
Author: Vitaly Buka (vitalybuka)
Changes
This reverts commit 67edb0ebbd5bb1139dc0dac9bf1ba6f1aa56c7ce.
---
Patch is 23.28 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/115028.diff
1 Files Affected:
- (modified) compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp (+110-131)
``diff
diff --git a/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
b/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
index 5b1fc8982d95a8..283eaee3b8ba7a 100644
--- a/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
+++ b/compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
@@ -519,373 +519,357 @@ static morder convert_morder(morder mo) {
return static_cast(static_cast(mo) & 0x7fff);
}
-template
-ALWAYS_INLINE auto AtomicImpl(morder mo, Types... args) {
- ThreadState *const thr = cur_thread();
- ProcessPendingSignals(thr);
- if (UNLIKELY(thr->ignore_sync || thr->ignore_interceptors))
-return Op::NoTsanAtomic(mo, args...);
- return Op::Atomic(thr, GET_CALLER_PC(), convert_morder(mo), args...);
-}
+# define ATOMIC_IMPL(func, mo, ...) \
+ThreadState *const thr = cur_thread();\
+ProcessPendingSignals(thr); \
+if (UNLIKELY(thr->ignore_sync || thr->ignore_interceptors)) \
+ return Op##func::NoTsanAtomic(mo, ##__VA_ARGS__); \
+return Op##func::Atomic(thr, GET_CALLER_PC(), convert_morder(mo), \
+##__VA_ARGS__);
extern "C" {
SANITIZER_INTERFACE_ATTRIBUTE
a8 __tsan_atomic8_load(const volatile a8 *a, int mo) {
- return AtomicImpl(static_cast(mo), a);
+ ATOMIC_IMPL(Load, static_cast(mo), a);
}
SANITIZER_INTERFACE_ATTRIBUTE
a16 __tsan_atomic16_load(const volatile a16 *a, int mo) {
- return AtomicImpl(static_cast(mo), a);
+ ATOMIC_IMPL(Load, static_cast(mo), a);
}
SANITIZER_INTERFACE_ATTRIBUTE
a32 __tsan_atomic32_load(const volatile a32 *a, int mo) {
- return AtomicImpl(static_cast(mo), a);
+ ATOMIC_IMPL(Load, static_cast(mo), a);
}
SANITIZER_INTERFACE_ATTRIBUTE
a64 __tsan_atomic64_load(const volatile a64 *a, int mo) {
- return AtomicImpl(static_cast(mo), a);
+ ATOMIC_IMPL(Load, static_cast(mo), a);
}
# if __TSAN_HAS_INT128
SANITIZER_INTERFACE_ATTRIBUTE
a128 __tsan_atomic128_load(const volatile a128 *a, int mo) {
- return AtomicImpl(static_cast(mo), a);
+ ATOMIC_IMPL(Load, static_cast(mo), a);
}
# endif
SANITIZER_INTERFACE_ATTRIBUTE
void __tsan_atomic8_store(volatile a8 *a, a8 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(Store, static_cast(mo), a, v);
}
SANITIZER_INTERFACE_ATTRIBUTE
void __tsan_atomic16_store(volatile a16 *a, a16 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(Store, static_cast(mo), a, v);
}
SANITIZER_INTERFACE_ATTRIBUTE
void __tsan_atomic32_store(volatile a32 *a, a32 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(Store, static_cast(mo), a, v);
}
SANITIZER_INTERFACE_ATTRIBUTE
void __tsan_atomic64_store(volatile a64 *a, a64 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(Store, static_cast(mo), a, v);
}
# if __TSAN_HAS_INT128
SANITIZER_INTERFACE_ATTRIBUTE
void __tsan_atomic128_store(volatile a128 *a, a128 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(Store, static_cast(mo), a, v);
}
# endif
SANITIZER_INTERFACE_ATTRIBUTE
a8 __tsan_atomic8_exchange(volatile a8 *a, a8 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(Exchange, static_cast(mo), a, v);
}
SANITIZER_INTERFACE_ATTRIBUTE
a16 __tsan_atomic16_exchange(volatile a16 *a, a16 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(Exchange, static_cast(mo), a, v);
}
SANITIZER_INTERFACE_ATTRIBUTE
a32 __tsan_atomic32_exchange(volatile a32 *a, a32 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(Exchange, static_cast(mo), a, v);
}
SANITIZER_INTERFACE_ATTRIBUTE
a64 __tsan_atomic64_exchange(volatile a64 *a, a64 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(Exchange, static_cast(mo), a, v);
}
# if __TSAN_HAS_INT128
SANITIZER_INTERFACE_ATTRIBUTE
a128 __tsan_atomic128_exchange(volatile a128 *a, a128 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(Exchange, static_cast(mo), a, v);
}
# endif
SANITIZER_INTERFACE_ATTRIBUTE
a8 __tsan_atomic8_fetch_add(volatile a8 *a, a8 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(FetchAdd, static_cast(mo), a, v);
}
SANITIZER_INTERFACE_ATTRIBUTE
a16 __tsan_atomic16_fetch_add(volatile a16 *a, a16 v, int mo) {
- return AtomicImpl(static_cast(mo), a, v);
+ ATOMIC_IMPL(FetchAdd, static_cast(mo), a, v);
}
SANITIZER_INTERFACE_ATTRIBUTE
a32 __tsan_atomic32_fetch_add(volati
[llvm-branch-commits] Revert "[nfc][tsan] Eliminate a few macros" (PR #115028)
vitalybuka wrote: Uploaded by mistake. https://github.com/llvm/llvm-project/pull/115028 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Revert "[nfc][tsan] Eliminate a few macros" (PR #115028)
https://github.com/vitalybuka closed https://github.com/llvm/llvm-project/pull/115028 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Reapply "[nfc][tsan] Move out `morder` params from __VA_ARGS__ (#114916)" (PR #115031)
vitalybuka wrote: Uploaded by mistake. https://github.com/llvm/llvm-project/pull/115031 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Revert "[nfc][tsan] Move out `morder` params from __VA_ARGS__ (#114916)" (PR #115030)
https://github.com/vitalybuka closed https://github.com/llvm/llvm-project/pull/115030 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoCollector pass to NPM (PR #113874)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/113874 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Reapply "[nfc][tsan] Move out `morder` params from __VA_ARGS__ (#114916)" (PR #115031)
https://github.com/vitalybuka closed https://github.com/llvm/llvm-project/pull/115031 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind
optsize {
; CHECK-RV32: # %bb.0: # %entry
; CHECK-RV32-NEXT:addi sp, sp, -16
; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill
-; CHECK-RV32-NEXT:li a2, 31
+; CHECK-RV32-NEXT:li a2, 31
+; CHECK-RV32-NEXT:call bcmp
+; CHECK-RV32-NEXT:lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK-RV32-NEXT:addi sp, sp, 16
+; CHECK-RV32-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-ZBB-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64-ZBB: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-ZBB-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-ZBB-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-ZBB-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-ZBB-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-ZBB-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-ZBB-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-ZBB-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-ZBKB-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64-ZBKB: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-ZBKB-NEXT:ret
+;
+; CHECK-ALIGNED-RV64-V-LABEL: bcmp_size_31:
+; CHECK-ALIGNED-RV64-V: # %bb.0: # %entry
+; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, -16
+; CHECK-ALIGNED-RV64-V-NEXT:sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ALIGNED-RV64-V-NEXT:li a2, 31
+; CHECK-ALIGNED-RV64-V-NEXT:call bcmp
+; CHECK-ALIGNED-RV64-V-NEXT:ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ALIGNED-RV64-V-NEXT:addi sp, sp, 16
+; CHECK-ALIGNED-RV64-V-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-LABEL: bcmp_size_31:
+; CHECK-UNALIGNED-RV64: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-NEXT:ld a2, 0(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a3, 8(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a4, 16(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a0, 23(a0)
+; CHECK-UNALIGNED-RV64-NEXT:ld a5, 0(a1)
+; CHECK-UNALIGNED-RV64-NEXT:ld a6, 8(a1)
+; CHECK-UNALIGNED-RV64-NEXT:ld a7, 16(a1)
+; CHECK-UNALIGNED-RV64-NEXT:ld a1, 23(a1)
+; CHECK-UNALIGNED-RV64-NEXT:xor a2, a2, a5
+; CHECK-UNALIGNED-RV64-NEXT:xor a3, a3, a6
+; CHECK-UNALIGNED-RV64-NEXT:xor a4, a4, a7
+; CHECK-UNALIGNED-RV64-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-NEXT:or a2, a2, a3
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a4, a0
+; CHECK-UNALIGNED-RV64-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-ZBB-LABEL: bcmp_size_31:
+; CHECK-UNALIGNED-RV64-ZBB: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a2, 0(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a3, 8(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a4, 16(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a0, 23(a0)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a5, 0(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a6, 8(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a7, 16(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ld a1, 23(a1)
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a2, a2, a5
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a3, a3, a6
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a4, a4, a7
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:or a2, a2, a3
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:or a0, a4, a0
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:or a0, a2, a0
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:snez a0, a0
+; CHECK-UNALIGNED-RV64-ZBB-NEXT:ret
+;
+; CHECK-UNALIGNED-RV64-ZBKB-LABEL: bcmp_size_31:
+; CHECK-UNALIGNED-RV64-ZBKB: # %bb.0: # %entry
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a2, 0(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a3, 8(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a4, 16(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a0, 23(a0)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a5, 0(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a6, 8(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a7, 16(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:ld a1, 23(a1)
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a2, a2, a5
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a3, a3, a6
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a4, a4, a7
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:xor a0, a0, a1
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:or a2, a2, a3
+; CHECK-UNALIGNED-RV64-ZBKB-NEXT:or a0, a4, a
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
wangleiat wrote:
Thanks, it's done.
https://github.com/llvm/llvm-project/pull/114742
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,664 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(str_name),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12, nullptr),
+ DEFINE_REGISTER_STUB(r13, nullptr),
+ DEFINE_REGISTER_STUB(r14, nullptr),
+ DEFINE_REGISTER_STUB(r15, nullptr),
+ DEFINE_REGISTER_STUB(r16, nullptr),
+ DEFINE_REGISTER_STUB(r17, nullptr),
+ DEFINE_REGISTER_STUB(r18, nullptr),
+ DEFINE_REGISTER_STUB(r19, nullptr),
+ DEFINE_REGISTER_STUB(r20, nullptr),
+ DEFINE_REGISTER_STUB(r21, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23, nullptr),
+ DEFINE_REGISTER_STUB(r24, nullptr),
+ DEFINE_REGISTER_STUB(r25, nullptr),
+ DEFINE_REGISTER_STUB(r26, nullptr),
+ DEFINE_REGISTER_STUB(r27, nullptr),
+ DEFINE_REGISTER_STUB(r28, nullptr),
+ DEFINE_REGISTER_STUB(r29, nullptr),
+ DEFINE_REGISTER_STUB(r30, nullptr),
+ DEFINE_REGISTER_STUB(r31, nullptr),
+ DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+/
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
https://github.com/wangleiat updated
https://github.com/llvm/llvm-project/pull/114742
>From f390561ee9c49dd10f0b13b79b713624664d7da2 Mon Sep 17 00:00:00 2001
From: wanglei
Date: Mon, 4 Nov 2024 17:12:03 +0800
Subject: [PATCH 1/2] comply with code style
Created using spr 1.3.5-bogner
---
lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
index 6e57b0806e54f5..5069bc48bbfba2 100644
--- a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
+++ b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.h
@@ -6,8 +6,8 @@
//
//===--===//
-#ifndef liblldb_ABISysV_loongarch_h_
-#define liblldb_ABISysV_loongarch_h_
+#ifndef LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+#define LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
// Other libraries and framework includes
#include "llvm/TargetParser/Triple.h"
@@ -101,4 +101,4 @@ class ABISysV_loongarch : public
lldb_private::RegInfoBasedABI {
// loongarch32
};
-#endif // liblldb_ABISysV_loongarch_h_
+#endif // LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
>From 8363707da351b6f2c10f1e945514402c5ceea65d Mon Sep 17 00:00:00 2001
From: wanglei
Date: Tue, 5 Nov 2024 18:28:25 +0800
Subject: [PATCH 2/2] Address @DavidSpickett's comments
Created using spr 1.3.5-bogner
---
.../ABI/LoongArch/ABISysV_loongarch.cpp | 200 +-
.../Plugins/ABI/LoongArch/ABISysV_loongarch.h | 6 +-
2 files changed, 107 insertions(+), 99 deletions(-)
diff --git a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
index cd8270c01113f7..1624af4fd6f6e8 100644
--- a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
+++ b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
@@ -30,10 +30,10 @@
// The ABI is not a source of such information as size, offset, encoding, etc.
// of a register. Just provides correct dwarf and eh_frame numbers.
-#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, generic_num)
\
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)
\
{
\
DEFINE_REG_NAME(dwarf_num),
\
- DEFINE_REG_NAME_STR(str_name),
\
+ DEFINE_REG_NAME_STR(nullptr),
\
0,
\
0,
\
eEncodingInvalid,
\
@@ -44,8 +44,8 @@
nullptr,
\
}
-#define DEFINE_REGISTER_STUB(dwarf_num, str_name)
\
- DEFINE_GENERIC_REGISTER_STUB(dwarf_num, str_name, LLDB_INVALID_REGNUM)
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
using namespace lldb;
using namespace lldb_private;
@@ -94,39 +94,39 @@ enum regnums {
};
static const std::array g_register_infos = {
-{DEFINE_REGISTER_STUB(r0, nullptr),
- DEFINE_GENERIC_REGISTER_STUB(r1, nullptr, LLDB_REGNUM_GENERIC_RA),
- DEFINE_REGISTER_STUB(r2, nullptr),
- DEFINE_GENERIC_REGISTER_STUB(r3, nullptr, LLDB_REGNUM_GENERIC_SP),
- DEFINE_GENERIC_REGISTER_STUB(r4, nullptr, LLDB_REGNUM_GENERIC_ARG1),
- DEFINE_GENERIC_REGISTER_STUB(r5, nullptr, LLDB_REGNUM_GENERIC_ARG2),
- DEFINE_GENERIC_REGISTER_STUB(r6, nullptr, LLDB_REGNUM_GENERIC_ARG3),
- DEFINE_GENERIC_REGISTER_STUB(r7, nullptr, LLDB_REGNUM_GENERIC_ARG4),
- DEFINE_GENERIC_REGISTER_STUB(r8, nullptr, LLDB_REGNUM_GENERIC_ARG5),
- DEFINE_GENERIC_REGISTER_STUB(r9, nullptr, LLDB_REGNUM_GENERIC_ARG6),
- DEFINE_GENERIC_REGISTER_STUB(r10, nullptr, LLDB_REGNUM_GENERIC_ARG7),
- DEFINE_GENERIC_REGISTER_STUB(r11, nullptr, LLDB_REGNUM_GENERIC_ARG8),
- DEFINE_REGISTER_STUB(r12, nullptr),
- DEFINE_REGISTER_STUB(r13, nullptr),
- DEFINE_REGISTER_STUB(r14, nullptr),
- DEFINE_REGISTER_STUB(r15, nullptr),
- DEFINE_REGISTER_STUB(r16, nullptr),
- DEFINE_REGISTER_STUB(r17, nullptr),
- DEFINE_REGISTER_STUB(r18, nullptr),
- DEFINE_REGISTER_STUB(r19, nullptr),
- DEFINE_REGISTER_STUB(r20, nullptr),
- DEFINE_REGISTER_STUB(r21, nullptr),
- DEFINE_GENERIC_REGISTER_STUB(r22, nullptr, LLDB_REGNUM_GENERIC_FP),
- DEFINE_REGISTER_STUB(r23, nullptr),
- DEFINE_REGISTER_STUB(r24, nullptr),
- DEFINE_REGISTER_STUB(r25, nullptr),
- DEFINE_REGISTER_STUB(r26, nullptr),
- DEFINE_REGISTER
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
https://github.com/DavidSpickett commented: LGTM but a LoongArch expert should give the final approval. https://github.com/llvm/llvm-project/pull/114742 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,104 @@
+//===-- ABISysV_loongarch.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+#define LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+
+// Other libraries and framework includes
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_loongarch : public lldb_private::RegInfoBasedABI {
+public:
+ ~ABISysV_loongarch() override = default;
+
+ size_t GetRedZoneSize() const override { return 0; }
+
+ bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+ lldb::addr_t functionAddress,
+ lldb::addr_t returnAddress,
+ llvm::ArrayRef args) const override;
+
+ bool GetArgumentValues(lldb_private::Thread &thread,
+ lldb_private::ValueList &values) const override;
+
+ lldb_private::Status
+ SetReturnValueObject(lldb::StackFrameSP &frame_sp,
+ lldb::ValueObjectSP &new_value) override;
+
+ lldb::ValueObjectSP
+ GetReturnValueObjectImpl(lldb_private::Thread &thread,
+ lldb_private::CompilerType &type) const override;
+
+ bool
+ CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan &unwind_plan)
override;
+
+ bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override;
+
+ bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+ bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 128 bit aligned.
+return (cfa & 0xfull) == 0;
+ }
+
+ void SetIsLA64(bool is_la64) { m_is_la64 = is_la64; }
+
+ bool CodeAddressIsValid(lldb::addr_t pc) override {
+if (pc & (4ull - 1ull))
+ return false; // Not 4 byte aligned
+
+// Anything else if fair game..
wangleiat wrote:
Thank you very much for your comments, everything is completed.
https://github.com/llvm/llvm-project/pull/114742
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,104 @@
+//===-- ABISysV_loongarch.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+#define LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+
+// Other libraries and framework includes
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_loongarch : public lldb_private::RegInfoBasedABI {
+public:
+ ~ABISysV_loongarch() override = default;
+
+ size_t GetRedZoneSize() const override { return 0; }
+
+ bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+ lldb::addr_t functionAddress,
+ lldb::addr_t returnAddress,
+ llvm::ArrayRef args) const override;
+
+ bool GetArgumentValues(lldb_private::Thread &thread,
+ lldb_private::ValueList &values) const override;
+
+ lldb_private::Status
+ SetReturnValueObject(lldb::StackFrameSP &frame_sp,
+ lldb::ValueObjectSP &new_value) override;
+
+ lldb::ValueObjectSP
+ GetReturnValueObjectImpl(lldb_private::Thread &thread,
+ lldb_private::CompilerType &type) const override;
+
+ bool
+ CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan &unwind_plan)
override;
+
+ bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override;
+
+ bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+ bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 128 bit aligned.
wangleiat wrote:
It is indeed 128-bit, here it is modified to a more general `byte`.
https://github.com/llvm/llvm-project/pull/114742
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [SLP]Check that operand of abs does not overflow before making it part of minbitwidth transformation (PR #113146)
@@ -15440,9 +15440,25 @@ bool BoUpSLP::collectValuesToDemote(
MaskedValueIsZero(I->getOperand(1), Mask, SimplifyQuery(*DL)));
});
};
+auto AbsChecker = [&](unsigned BitWidth, unsigned OrigBitWidth) {
+ assert(BitWidth <= OrigBitWidth && "Unexpected bitwidths!");
+ return all_of(E.Scalars, [&](Value *V) {
+auto *I = cast(V);
+unsigned SignBits = OrigBitWidth - BitWidth;
+APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, BitWidth - 1);
+unsigned Op0SignBits =
+ComputeNumSignBits(I->getOperand(0), *DL, 0, AC, nullptr, DT);
+return SignBits <= Op0SignBits &&
+ ((SignBits != Op0SignBits &&
+ !isKnownNonNegative(I->getOperand(0), SimplifyQuery(*DL))) ||
nikic wrote:
I don't understand this part of the condition. What is the meaning of `SignBits
!= Op0SignBits && !isKnownNonNegative`? Should this be `SignBits != Op0SignBits
|| isKnownNonNegative`?
Though I'm not really sure why we'd be interested in handling the case where
the abs is known non-negative (including also the MaskedValueIsZero check
below): If it's non-negative, wouldn't we expect the abs to fold away anyway?
https://github.com/llvm/llvm-project/pull/113146
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/19.x: [SLP]Check that operand of abs does not overflow before making it part of minbitwidth transformation (PR #113146)
@@ -15440,9 +15440,25 @@ bool BoUpSLP::collectValuesToDemote(
MaskedValueIsZero(I->getOperand(1), Mask, SimplifyQuery(*DL)));
});
};
+auto AbsChecker = [&](unsigned BitWidth, unsigned OrigBitWidth) {
+ assert(BitWidth <= OrigBitWidth && "Unexpected bitwidths!");
+ return all_of(E.Scalars, [&](Value *V) {
+auto *I = cast(V);
+unsigned SignBits = OrigBitWidth - BitWidth;
+APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, BitWidth - 1);
+unsigned Op0SignBits =
+ComputeNumSignBits(I->getOperand(0), *DL, 0, AC, nullptr, DT);
+return SignBits <= Op0SignBits &&
+ ((SignBits != Op0SignBits &&
+ !isKnownNonNegative(I->getOperand(0), SimplifyQuery(*DL))) ||
alexey-bataev wrote:
Right, isKnownNonNegative is meaningless here. Instead we check that the value
is negative and SignBits < Op0SignBits, i.e. we do not lose signedness info
when trying to truncate the operand value
https://github.com/llvm/llvm-project/pull/113146
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][Attributor] Make `AAAMDWavesPerEU` honor existing attribute (PR #114438)
shiltian wrote: bump https://github.com/llvm/llvm-project/pull/114438 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][Attributor] Skip update if an AA is at its initial state (PR #114726)
shiltian wrote: bump https://github.com/llvm/llvm-project/pull/114726 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Revert "[nfc][tsan] Move out `morder` params from __VA_ARGS__ (#114916)" (PR #115030)
vitalybuka wrote: Uploaded by mistake. https://github.com/llvm/llvm-project/pull/115030 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups (PR #113751)
https://github.com/shiltian approved this pull request. https://github.com/llvm/llvm-project/pull/113751 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ValueTracking: Allow getUnderlyingObject to look at vectors (PR #114311)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/114311
>From e518d75b613f843747bc39ba35c95076caa37c75 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 29 Oct 2024 15:30:51 -0700
Subject: [PATCH] ValueTracking: Allow getUnderlyingObject to look at vectors
We can identify some easy vector of pointer cases, such as
a getelementptr with a scalar base.
---
llvm/lib/Analysis/ValueTracking.cpp | 4 +--
.../AMDGPU/promote-alloca-vector-gep.ll | 27 ++-
2 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Analysis/ValueTracking.cpp
b/llvm/lib/Analysis/ValueTracking.cpp
index 5c20c24d0ae00a..dfaa019e4c9fe5 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -6714,11 +6714,11 @@ static bool isSameUnderlyingObjectInLoop(const PHINode
*PN,
}
const Value *llvm::getUnderlyingObject(const Value *V, unsigned MaxLookup) {
- if (!V->getType()->isPointerTy())
-return V;
for (unsigned Count = 0; MaxLookup == 0 || Count < MaxLookup; ++Count) {
if (auto *GEP = dyn_cast(V)) {
V = GEP->getPointerOperand();
+ if (!V->getType()->isPointerTy()) // Only handle scalar pointer base.
+return nullptr;
} else if (Operator::getOpcode(V) == Instruction::BitCast ||
Operator::getOpcode(V) == Instruction::AddrSpaceCast) {
Value *NewV = cast(V)->getOperand(0);
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
index 355a2b8796b24d..76e1868b3c4b9e 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-gep.ll
@@ -35,17 +35,30 @@ bb:
ret void
}
-; TODO: Should be able to promote this
define amdgpu_kernel void @scalar_alloca_ptr_with_vector_gep_offset_select(i1
%cond) {
; CHECK-LABEL: define amdgpu_kernel void
@scalar_alloca_ptr_with_vector_gep_offset_select(
; CHECK-SAME: i1 [[COND:%.*]]) {
; CHECK-NEXT: [[BB:.*:]]
-; CHECK-NEXT:[[ALLOCA:%.*]] = alloca [4 x i32], align 4, addrspace(5)
-; CHECK-NEXT:[[GETELEMENTPTR0:%.*]] = getelementptr inbounds i8, ptr
addrspace(5) [[ALLOCA]], <4 x i64>
-; CHECK-NEXT:[[GETELEMENTPTR1:%.*]] = getelementptr inbounds i8, ptr
addrspace(5) [[ALLOCA]], <4 x i64>
-; CHECK-NEXT:[[SELECT:%.*]] = select i1 [[COND]], <4 x ptr addrspace(5)>
[[GETELEMENTPTR0]], <4 x ptr addrspace(5)> [[GETELEMENTPTR1]]
-; CHECK-NEXT:[[EXTRACTELEMENT:%.*]] = extractelement <4 x ptr
addrspace(5)> [[SELECT]], i64 1
-; CHECK-NEXT:store i32 0, ptr addrspace(5) [[EXTRACTELEMENT]], align 4
+; CHECK-NEXT:[[TMP0:%.*]] = call noalias nonnull dereferenceable(64) ptr
addrspace(4) @llvm.amdgcn.dispatch.ptr()
+; CHECK-NEXT:[[TMP1:%.*]] = getelementptr inbounds i32, ptr addrspace(4)
[[TMP0]], i64 1
+; CHECK-NEXT:[[TMP2:%.*]] = load i32, ptr addrspace(4) [[TMP1]], align 4,
!invariant.load [[META0]]
+; CHECK-NEXT:[[TMP3:%.*]] = getelementptr inbounds i32, ptr addrspace(4)
[[TMP0]], i64 2
+; CHECK-NEXT:[[TMP4:%.*]] = load i32, ptr addrspace(4) [[TMP3]], align 4,
!range [[RNG1]], !invariant.load [[META0]]
+; CHECK-NEXT:[[TMP5:%.*]] = lshr i32 [[TMP2]], 16
+; CHECK-NEXT:[[TMP6:%.*]] = call range(i32 0, 1024) i32
@llvm.amdgcn.workitem.id.x()
+; CHECK-NEXT:[[TMP7:%.*]] = call range(i32 0, 1024) i32
@llvm.amdgcn.workitem.id.y()
+; CHECK-NEXT:[[TMP8:%.*]] = call range(i32 0, 1024) i32
@llvm.amdgcn.workitem.id.z()
+; CHECK-NEXT:[[TMP9:%.*]] = mul nuw nsw i32 [[TMP5]], [[TMP4]]
+; CHECK-NEXT:[[TMP10:%.*]] = mul i32 [[TMP9]], [[TMP6]]
+; CHECK-NEXT:[[TMP11:%.*]] = mul nuw nsw i32 [[TMP7]], [[TMP4]]
+; CHECK-NEXT:[[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]]
+; CHECK-NEXT:[[TMP13:%.*]] = add i32 [[TMP12]], [[TMP8]]
+; CHECK-NEXT:[[TMP14:%.*]] = getelementptr inbounds [1024 x [4 x i32]],
ptr addrspace(3) @scalar_alloca_ptr_with_vector_gep_offset_select.alloca, i32
0, i32 [[TMP13]]
+; CHECK-NEXT:[[GETELEMENTPTR0:%.*]] = getelementptr inbounds i8, ptr
addrspace(3) [[TMP14]], <4 x i64>
+; CHECK-NEXT:[[GETELEMENTPTR1:%.*]] = getelementptr inbounds i8, ptr
addrspace(3) [[TMP14]], <4 x i64>
+; CHECK-NEXT:[[SELECT:%.*]] = select i1 [[COND]], <4 x ptr addrspace(3)>
[[GETELEMENTPTR0]], <4 x ptr addrspace(3)> [[GETELEMENTPTR1]]
+; CHECK-NEXT:[[EXTRACTELEMENT:%.*]] = extractelement <4 x ptr
addrspace(3)> [[SELECT]], i64 1
+; CHECK-NEXT:store i32 0, ptr addrspace(3) [[EXTRACTELEMENT]], align 4
; CHECK-NEXT:ret void
;
bb:
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegUsageInfoPropagation pass to NPM (PR #114010)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/114010 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [PAC][lld][AArch64][ELF] Support signed TLSDESC (PR #113817)
https://github.com/smithp35 commented: A few small suggestions from me. https://github.com/llvm/llvm-project/pull/113817 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [PAC][lld][AArch64][ELF] Support signed TLSDESC (PR #113817)
https://github.com/smithp35 edited https://github.com/llvm/llvm-project/pull/113817 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [PAC][lld][AArch64][ELF] Support signed TLSDESC (PR #113817)
@@ -1352,6 +1352,36 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr
expr, RelType type,
return 1;
}
+ auto fatalBothAuthAndNonAuth = [&sym]() {
+fatal("both AUTH and non-AUTH TLSDESC entries for '" + sym.getName() +
smithp35 wrote:
Can you add getLocation to the error message so that a user can find the source
of at least one of the relocations?
I also recommend not using fatal but use error so that a user can get
diagnostics like the map file out of the link.
https://github.com/llvm/llvm-project/pull/113817
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [PAC][lld][AArch64][ELF] Support signed TLSDESC (PR #113817)
@@ -0,0 +1,134 @@ +// REQUIRES: aarch64 +// RUN: rm -rf %t && split-file %s %t && cd %t + +//--- a.s + +.section .tbss,"awT",@nobits +.global a +a: +.xword 0 + +//--- ok.s + +// RUN: llvm-mc -filetype=obj -triple=aarch64-pc-linux -mattr=+pauth ok.s -o ok.o +// RUN: ld.lld -shared ok.o -o ok.so +// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn ok.so | \ +// RUN: FileCheck -DP=20 -DA=896 -DB=912 -DC=928 %s +// RUN: llvm-readobj -r -x .got ok.so | FileCheck --check-prefix=REL \ +// RUN: -DP1=20 -DA1=380 -DB1=390 -DC1=3A0 -DP2=020 -DA2=380 -DB2=390 -DC2=3a0 %s + +// RUN: llvm-mc -filetype=obj -triple=aarch64-pc-linux -mattr=+pauth a.s -o a.so.o +// RUN: ld.lld -shared a.so.o -soname=so -o a.so +// RUN: ld.lld ok.o a.so -o ok +// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn ok | \ +// RUN: FileCheck -DP=220 -DA=936 -DB=952 -DC=968 %s +// RUN: llvm-readobj -r -x .got ok | FileCheck --check-prefix=REL \ +// RUN: -DP1=220 -DA1=3A8 -DB1=3B8 -DC1=3C8 -DP2=220 -DA2=3a8 -DB2=3b8 -DC2=3c8 %s + +.text +adrpx0, :tlsdesc_auth:a +ldr x16, [x0, :tlsdesc_auth_lo12:a] +add x0, x0, :tlsdesc_auth_lo12:a +.tlsdesccall a +blraa x16, x0 + +// CHECK: adrpx0, 0x[[P]]000 +// CHECK-NEXT: ldr x16, [x0, #[[A]]] +// CHECK-NEXT: add x0, x0, #[[A]] +// CHECK-NEXT: blraa x16, x0 + +// Create relocation against local TLS symbols where linker should smithp35 wrote: I think LLD has a convention to put an additional comment character for lines that are not RUN or FileCheck comments. For example: /// Create relocation ... https://github.com/llvm/llvm-project/pull/113817 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [PAC][lld][AArch64][ELF] Support signed TLSDESC (PR #113817)
@@ -92,6 +92,10 @@ enum RelExpr {
R_AARCH64_PAGE_PC,
R_AARCH64_RELAX_TLS_GD_TO_IE_PAGE_PC,
R_AARCH64_TLSDESC_PAGE,
+ R_AARCH64_AUTH_TLSDESC_PAGE,
+ // TODO: maybe it's better to rename this expression
+ // to avoid name conflict with dynamic reloc
+ R_AARCH64_AUTH_TLSDESC,
smithp35 wrote:
Could be `R_AARCH64_AUTH_TLSDESC_STATIC`?
https://github.com/llvm/llvm-project/pull/113817
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Reapply "[nfc][tsan] Move out `morder` params from __VA_ARGS__ (#114916)" (PR #115031)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/115031 This reverts commit dd6f380c8837c7df135a871250f8a10ee0abb101. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] Revert "[nfc][tsan] Eliminate a few macros" (PR #115028)
https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/115028 This reverts commit 67edb0ebbd5bb1139dc0dac9bf1ba6f1aa56c7ce. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] a3efa16 - Revert "Revert "[tsan] Don't use `enum __tsan_memory_order` in tsan interface…"
Author: Vitaly Buka
Date: 2024-11-05T09:44:36-08:00
New Revision: a3efa16d8fd2efc5d1ed8bc984e58c908202b048
URL:
https://github.com/llvm/llvm-project/commit/a3efa16d8fd2efc5d1ed8bc984e58c908202b048
DIFF:
https://github.com/llvm/llvm-project/commit/a3efa16d8fd2efc5d1ed8bc984e58c908202b048.diff
LOG: Revert "Revert "[tsan] Don't use `enum __tsan_memory_order` in tsan
interface…"
This reverts commit b14c436311e3ff78f61dd59c90486432d13bf38e.
Added:
Modified:
compiler-rt/include/sanitizer/tsan_interface_atomic.h
compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
compiler-rt/lib/tsan/rtl/tsan_interface.h
compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Removed:
diff --git a/compiler-rt/include/sanitizer/tsan_interface_atomic.h
b/compiler-rt/include/sanitizer/tsan_interface_atomic.h
index de3a1c3936097d..74ed91efade040 100644
--- a/compiler-rt/include/sanitizer/tsan_interface_atomic.h
+++ b/compiler-rt/include/sanitizer/tsan_interface_atomic.h
@@ -43,183 +43,178 @@ typedef enum {
} __tsan_memory_order;
__tsan_atomic8 SANITIZER_CDECL
-__tsan_atomic8_load(const volatile __tsan_atomic8 *a, __tsan_memory_order mo);
+__tsan_atomic8_load(const volatile __tsan_atomic8 *a, int mo);
__tsan_atomic16 SANITIZER_CDECL
-__tsan_atomic16_load(const volatile __tsan_atomic16 *a, __tsan_memory_order
mo);
+__tsan_atomic16_load(const volatile __tsan_atomic16 *a, int mo);
__tsan_atomic32 SANITIZER_CDECL
-__tsan_atomic32_load(const volatile __tsan_atomic32 *a, __tsan_memory_order
mo);
+__tsan_atomic32_load(const volatile __tsan_atomic32 *a, int mo);
__tsan_atomic64 SANITIZER_CDECL
-__tsan_atomic64_load(const volatile __tsan_atomic64 *a, __tsan_memory_order
mo);
+__tsan_atomic64_load(const volatile __tsan_atomic64 *a, int mo);
#if __TSAN_HAS_INT128
-__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_load(
-const volatile __tsan_atomic128 *a, __tsan_memory_order mo);
+__tsan_atomic128 SANITIZER_CDECL
+__tsan_atomic128_load(const volatile __tsan_atomic128 *a, int mo);
#endif
void SANITIZER_CDECL __tsan_atomic8_store(volatile __tsan_atomic8 *a,
- __tsan_atomic8 v,
- __tsan_memory_order mo);
+ __tsan_atomic8 v, int mo);
void SANITIZER_CDECL __tsan_atomic16_store(volatile __tsan_atomic16 *a,
- __tsan_atomic16 v,
- __tsan_memory_order mo);
+ __tsan_atomic16 v, int mo);
void SANITIZER_CDECL __tsan_atomic32_store(volatile __tsan_atomic32 *a,
- __tsan_atomic32 v,
- __tsan_memory_order mo);
+ __tsan_atomic32 v, int mo);
void SANITIZER_CDECL __tsan_atomic64_store(volatile __tsan_atomic64 *a,
- __tsan_atomic64 v,
- __tsan_memory_order mo);
+ __tsan_atomic64 v, int mo);
#if __TSAN_HAS_INT128
void SANITIZER_CDECL __tsan_atomic128_store(volatile __tsan_atomic128 *a,
-__tsan_atomic128 v,
-__tsan_memory_order mo);
+__tsan_atomic128 v, int mo);
#endif
-__tsan_atomic8 SANITIZER_CDECL __tsan_atomic8_exchange(
-volatile __tsan_atomic8 *a, __tsan_atomic8 v, __tsan_memory_order mo);
+__tsan_atomic8 SANITIZER_CDECL
+__tsan_atomic8_exchange(volatile __tsan_atomic8 *a, __tsan_atomic8 v, int mo);
__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_exchange(
-volatile __tsan_atomic16 *a, __tsan_atomic16 v, __tsan_memory_order mo);
+volatile __tsan_atomic16 *a, __tsan_atomic16 v, int mo);
__tsan_atomic32 SANITIZER_CDECL __tsan_atomic32_exchange(
-volatile __tsan_atomic32 *a, __tsan_atomic32 v, __tsan_memory_order mo);
+volatile __tsan_atomic32 *a, __tsan_atomic32 v, int mo);
__tsan_atomic64 SANITIZER_CDECL __tsan_atomic64_exchange(
-volatile __tsan_atomic64 *a, __tsan_atomic64 v, __tsan_memory_order mo);
+volatile __tsan_atomic64 *a, __tsan_atomic64 v, int mo);
#if __TSAN_HAS_INT128
__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_exchange(
-volatile __tsan_atomic128 *a, __tsan_atomic128 v, __tsan_memory_order mo);
+volatile __tsan_atomic128 *a, __tsan_atomic128 v, int mo);
#endif
-__tsan_atomic8 SANITIZER_CDECL __tsan_atomic8_fetch_add(
-volatile __tsan_atomic8 *a, __tsan_atomic8 v, __tsan_memory_order mo);
+__tsan_atomic8 SANITIZER_CDECL
+__tsan_atomic8_fetch_add(volatile __tsan_atomic8 *a, __tsan_atomic8 v, int mo);
__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_fetch_add(
-volatile __tsan_atomic16 *a, __tsan_atomic16 v, __tsan_memory_order mo)
[llvm-branch-commits] [compiler-rt] 106d54b - Revert "[tsan] Don't use `enum __tsan_memory_order` in tsan interface (#114724)"
Author: Vitaly Buka
Date: 2024-11-05T09:38:28-08:00
New Revision: 106d54be69070e26c1b68f3f62ff4fa6c53d23b9
URL:
https://github.com/llvm/llvm-project/commit/106d54be69070e26c1b68f3f62ff4fa6c53d23b9
DIFF:
https://github.com/llvm/llvm-project/commit/106d54be69070e26c1b68f3f62ff4fa6c53d23b9.diff
LOG: Revert "[tsan] Don't use `enum __tsan_memory_order` in tsan interface
(#114724)"
This reverts commit 1e50958399e0bb2a558a5d5806a61da9b2ef9e74.
Added:
Modified:
compiler-rt/include/sanitizer/tsan_interface_atomic.h
compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
compiler-rt/lib/tsan/rtl/tsan_interface.h
compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
Removed:
diff --git a/compiler-rt/include/sanitizer/tsan_interface_atomic.h
b/compiler-rt/include/sanitizer/tsan_interface_atomic.h
index 74ed91efade040..de3a1c3936097d 100644
--- a/compiler-rt/include/sanitizer/tsan_interface_atomic.h
+++ b/compiler-rt/include/sanitizer/tsan_interface_atomic.h
@@ -43,178 +43,183 @@ typedef enum {
} __tsan_memory_order;
__tsan_atomic8 SANITIZER_CDECL
-__tsan_atomic8_load(const volatile __tsan_atomic8 *a, int mo);
+__tsan_atomic8_load(const volatile __tsan_atomic8 *a, __tsan_memory_order mo);
__tsan_atomic16 SANITIZER_CDECL
-__tsan_atomic16_load(const volatile __tsan_atomic16 *a, int mo);
+__tsan_atomic16_load(const volatile __tsan_atomic16 *a, __tsan_memory_order
mo);
__tsan_atomic32 SANITIZER_CDECL
-__tsan_atomic32_load(const volatile __tsan_atomic32 *a, int mo);
+__tsan_atomic32_load(const volatile __tsan_atomic32 *a, __tsan_memory_order
mo);
__tsan_atomic64 SANITIZER_CDECL
-__tsan_atomic64_load(const volatile __tsan_atomic64 *a, int mo);
+__tsan_atomic64_load(const volatile __tsan_atomic64 *a, __tsan_memory_order
mo);
#if __TSAN_HAS_INT128
-__tsan_atomic128 SANITIZER_CDECL
-__tsan_atomic128_load(const volatile __tsan_atomic128 *a, int mo);
+__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_load(
+const volatile __tsan_atomic128 *a, __tsan_memory_order mo);
#endif
void SANITIZER_CDECL __tsan_atomic8_store(volatile __tsan_atomic8 *a,
- __tsan_atomic8 v, int mo);
+ __tsan_atomic8 v,
+ __tsan_memory_order mo);
void SANITIZER_CDECL __tsan_atomic16_store(volatile __tsan_atomic16 *a,
- __tsan_atomic16 v, int mo);
+ __tsan_atomic16 v,
+ __tsan_memory_order mo);
void SANITIZER_CDECL __tsan_atomic32_store(volatile __tsan_atomic32 *a,
- __tsan_atomic32 v, int mo);
+ __tsan_atomic32 v,
+ __tsan_memory_order mo);
void SANITIZER_CDECL __tsan_atomic64_store(volatile __tsan_atomic64 *a,
- __tsan_atomic64 v, int mo);
+ __tsan_atomic64 v,
+ __tsan_memory_order mo);
#if __TSAN_HAS_INT128
void SANITIZER_CDECL __tsan_atomic128_store(volatile __tsan_atomic128 *a,
-__tsan_atomic128 v, int mo);
+__tsan_atomic128 v,
+__tsan_memory_order mo);
#endif
-__tsan_atomic8 SANITIZER_CDECL
-__tsan_atomic8_exchange(volatile __tsan_atomic8 *a, __tsan_atomic8 v, int mo);
+__tsan_atomic8 SANITIZER_CDECL __tsan_atomic8_exchange(
+volatile __tsan_atomic8 *a, __tsan_atomic8 v, __tsan_memory_order mo);
__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_exchange(
-volatile __tsan_atomic16 *a, __tsan_atomic16 v, int mo);
+volatile __tsan_atomic16 *a, __tsan_atomic16 v, __tsan_memory_order mo);
__tsan_atomic32 SANITIZER_CDECL __tsan_atomic32_exchange(
-volatile __tsan_atomic32 *a, __tsan_atomic32 v, int mo);
+volatile __tsan_atomic32 *a, __tsan_atomic32 v, __tsan_memory_order mo);
__tsan_atomic64 SANITIZER_CDECL __tsan_atomic64_exchange(
-volatile __tsan_atomic64 *a, __tsan_atomic64 v, int mo);
+volatile __tsan_atomic64 *a, __tsan_atomic64 v, __tsan_memory_order mo);
#if __TSAN_HAS_INT128
__tsan_atomic128 SANITIZER_CDECL __tsan_atomic128_exchange(
-volatile __tsan_atomic128 *a, __tsan_atomic128 v, int mo);
+volatile __tsan_atomic128 *a, __tsan_atomic128 v, __tsan_memory_order mo);
#endif
-__tsan_atomic8 SANITIZER_CDECL
-__tsan_atomic8_fetch_add(volatile __tsan_atomic8 *a, __tsan_atomic8 v, int mo);
+__tsan_atomic8 SANITIZER_CDECL __tsan_atomic8_fetch_add(
+volatile __tsan_atomic8 *a, __tsan_atomic8 v, __tsan_memory_order mo);
__tsan_atomic16 SANITIZER_CDECL __tsan_atomic16_fetch_add(
-volatile __tsan_atomic16 *a, __tsan_atomic16 v, int mo);
+volatile
[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)
topperc wrote: > > > Can we break the enabling down into more manageable pieces? I think > > > `enableUnalignedScalarMem() && (Subtarget->hasStdExtZbb() || > > > Subtarget->hasStdExtZbkb() || IsZeroCmp)` might be a good starting point. > > > > > > I'd be fine with this type of approach. > > Thanks! I have applied this suggestion. For `ExpandMemcmp` issue, I will try > to fix it later. I meant we should start with only doing inline memcmp expansion under those conditions. Not just the overlapping loads part. https://github.com/llvm/llvm-project/pull/107548 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [DataLayout][LangRef] Split non-integral and unstable pointer properties (PR #105735)
arichardson wrote: > I think this change would benefit from an RFC on discourse, for wider > visibility. > > Something that's not super clear to me is how to reconcile the statements > about pointer/integer casts and in-memory type punning. I'd expect that > ptrtoint returns an i128 value and if you cast back that value to a pointer, > you preserve capabilities. If you truncate the i128 value to i64 and then > cast it back, then you obviously don't -- but LLVM should already know that > truncation is not a value preserving operation :) Or does ptrtoint actually > directly return an i64 value? If it does, then I think you must have > additional changes for that, because I don't think that LLVM supports that > directly. And if you do, then that may be sufficient? That is a good suggestion - I will post a RFC soon. The CHERI downstream ensures that ptrtoint for capabilities only returns the address part of the capability (i.e. i32 for 64-bit capabilities and i64 for 128-bit ones). We added additional helpers to query that width which I attempted to cleanup+upsteream in https://reviews.llvm.org/D135158 and https://reviews.llvm.org/D99660. Storing via memory preserves capabilities (as long as the load+store are correctly sized and aligned - there is one additional out-of-band bit that is only preserved for capability-typed loads+stores), but casting via same-size integers does not. This also means that the C (u)intptr_t is lowered to `ptr addrspace(200)` instead of `i128` in IR to preserve capability data. https://github.com/llvm/llvm-project/pull/105735 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Fold more scalar operations on frame index to VALU (PR #115059)
https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/115059
Further extend workaround for the lack of proper regbankselect
for frame indexes.
>From 493a45c9a65aca2402c950bae122bad477e0e5b0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 1 Nov 2024 12:24:37 -0700
Subject: [PATCH] AMDGPU: Fold more scalar operations on frame index to VALU
Further extend workaround for the lack of proper regbankselect
for frame indexes.
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 121 -
.../fold-operands-s-add-copy-to-vgpr.mir | 167 --
2 files changed, 229 insertions(+), 59 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 28bcbd58dc0376..de7dec8831daec 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -78,9 +78,25 @@ class SIFoldOperandsImpl {
bool frameIndexMayFold(const MachineInstr &UseMI, int OpNo,
const MachineOperand &OpToFold) const;
- /// Fold %vgpr = COPY (S_ADD_I32 x, frameindex)
- ///
- /// => %vgpr = V_ADD_U32 x, frameindex
+ // TODO: Just use TII::getVALUOp
+ unsigned convertToVALUOp(unsigned Opc, bool UseVOP3 = false) const {
+switch (Opc) {
+case AMDGPU::S_ADD_I32: {
+ if (ST->hasAddNoCarry())
+return UseVOP3 ? AMDGPU::V_ADD_U32_e64 : AMDGPU::V_ADD_U32_e32;
+ return UseVOP3 ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_ADD_CO_U32_e32;
+}
+case AMDGPU::S_OR_B32:
+ return UseVOP3 ? AMDGPU::V_OR_B32_e64 : AMDGPU::V_OR_B32_e32;
+case AMDGPU::S_AND_B32:
+ return UseVOP3 ? AMDGPU::V_AND_B32_e64 : AMDGPU::V_AND_B32_e32;
+case AMDGPU::S_MUL_I32:
+ return AMDGPU::V_MUL_LO_U32_e64;
+default:
+ return AMDGPU::INSTRUCTION_LIST_END;
+}
+ }
+
bool foldCopyToVGPROfScalarAddOfFrameIndex(Register DstReg, Register SrcReg,
MachineInstr &MI) const;
@@ -202,6 +218,8 @@ bool SIFoldOperandsImpl::frameIndexMayFold(
const unsigned Opc = UseMI.getOpcode();
switch (Opc) {
case AMDGPU::S_ADD_I32:
+ case AMDGPU::S_OR_B32:
+ case AMDGPU::S_AND_B32:
case AMDGPU::V_ADD_U32_e32:
case AMDGPU::V_ADD_CO_U32_e32:
// TODO: Possibly relax hasOneUse. It matters more for mubuf, since we have
@@ -238,53 +256,62 @@ bool
SIFoldOperandsImpl::foldCopyToVGPROfScalarAddOfFrameIndex(
if (TRI->isVGPR(*MRI, DstReg) && TRI->isSGPRReg(*MRI, SrcReg) &&
MRI->hasOneNonDBGUse(SrcReg)) {
MachineInstr *Def = MRI->getVRegDef(SrcReg);
-if (Def && Def->getOpcode() == AMDGPU::S_ADD_I32 &&
-Def->getOperand(3).isDead()) {
- MachineOperand *Src0 = &Def->getOperand(1);
- MachineOperand *Src1 = &Def->getOperand(2);
-
- // TODO: This is profitable with more operand types, and for more
- // opcodes. But ultimately this is working around poor / nonexistent
- // regbankselect.
- if (!Src0->isFI() && !Src1->isFI())
-return false;
+if (!Def || Def->getNumOperands() != 4)
+ return false;
- if (Src0->isFI())
-std::swap(Src0, Src1);
-
- MachineBasicBlock *MBB = Def->getParent();
- const DebugLoc &DL = Def->getDebugLoc();
- if (ST->hasAddNoCarry()) {
-bool UseVOP3 = !Src0->isImm() || TII->isInlineConstant(*Src0);
-MachineInstrBuilder Add =
-BuildMI(*MBB, *Def, DL,
-TII->get(UseVOP3 ? AMDGPU::V_ADD_U32_e64
- : AMDGPU::V_ADD_U32_e32),
-DstReg)
-.add(*Src0)
-.add(*Src1)
-.setMIFlags(Def->getFlags());
-if (UseVOP3)
- Add.addImm(0);
-
-Def->eraseFromParent();
-MI.eraseFromParent();
-return true;
- }
+MachineOperand *Src0 = &Def->getOperand(1);
+MachineOperand *Src1 = &Def->getOperand(2);
- MachineBasicBlock::LivenessQueryResult Liveness =
- MBB->computeRegisterLiveness(TRI, AMDGPU::VCC, *Def, 16);
- if (Liveness == MachineBasicBlock::LQR_Dead) {
-// TODO: If src1 satisfies operand constraints, use vop3 version.
-BuildMI(*MBB, *Def, DL, TII->get(AMDGPU::V_ADD_CO_U32_e32), DstReg)
-.add(*Src0)
-.add(*Src1)
-.setOperandDead(3) // implicit-def $vcc
-.setMIFlags(Def->getFlags());
-Def->eraseFromParent();
-MI.eraseFromParent();
-return true;
+// TODO: This is profitable with more operand types, and for more
+// opcodes. But ultimately this is working around poor / nonexistent
+// regbankselect.
+if (!Src0->isFI() && !Src1->isFI())
+ return false;
+
+if (Src0->isFI())
+ std::swap(Src0, Src1);
+
+const bool UseVOP3 = !Src0->isImm() || TII->isInlineConstant(*Src0);
+unsigned NewOp = convertToVALUOp(Def->getOpcode(), UseVOP3);
+if (NewOp == AMDGPU::INSTRUCTION_LIST_END ||
+
[llvm-branch-commits] [llvm] AMDGPU: Fold more scalar operations on frame index to VALU (PR #115059)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
Further extend workaround for the lack of proper regbankselect
for frame indexes.
---
Full diff: https://github.com/llvm/llvm-project/pull/115059.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIFoldOperands.cpp (+74-47)
- (modified) llvm/test/CodeGen/AMDGPU/fold-operands-s-add-copy-to-vgpr.mir
(+155-12)
``diff
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 28bcbd58dc0376..de7dec8831daec 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -78,9 +78,25 @@ class SIFoldOperandsImpl {
bool frameIndexMayFold(const MachineInstr &UseMI, int OpNo,
const MachineOperand &OpToFold) const;
- /// Fold %vgpr = COPY (S_ADD_I32 x, frameindex)
- ///
- /// => %vgpr = V_ADD_U32 x, frameindex
+ // TODO: Just use TII::getVALUOp
+ unsigned convertToVALUOp(unsigned Opc, bool UseVOP3 = false) const {
+switch (Opc) {
+case AMDGPU::S_ADD_I32: {
+ if (ST->hasAddNoCarry())
+return UseVOP3 ? AMDGPU::V_ADD_U32_e64 : AMDGPU::V_ADD_U32_e32;
+ return UseVOP3 ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_ADD_CO_U32_e32;
+}
+case AMDGPU::S_OR_B32:
+ return UseVOP3 ? AMDGPU::V_OR_B32_e64 : AMDGPU::V_OR_B32_e32;
+case AMDGPU::S_AND_B32:
+ return UseVOP3 ? AMDGPU::V_AND_B32_e64 : AMDGPU::V_AND_B32_e32;
+case AMDGPU::S_MUL_I32:
+ return AMDGPU::V_MUL_LO_U32_e64;
+default:
+ return AMDGPU::INSTRUCTION_LIST_END;
+}
+ }
+
bool foldCopyToVGPROfScalarAddOfFrameIndex(Register DstReg, Register SrcReg,
MachineInstr &MI) const;
@@ -202,6 +218,8 @@ bool SIFoldOperandsImpl::frameIndexMayFold(
const unsigned Opc = UseMI.getOpcode();
switch (Opc) {
case AMDGPU::S_ADD_I32:
+ case AMDGPU::S_OR_B32:
+ case AMDGPU::S_AND_B32:
case AMDGPU::V_ADD_U32_e32:
case AMDGPU::V_ADD_CO_U32_e32:
// TODO: Possibly relax hasOneUse. It matters more for mubuf, since we have
@@ -238,53 +256,62 @@ bool
SIFoldOperandsImpl::foldCopyToVGPROfScalarAddOfFrameIndex(
if (TRI->isVGPR(*MRI, DstReg) && TRI->isSGPRReg(*MRI, SrcReg) &&
MRI->hasOneNonDBGUse(SrcReg)) {
MachineInstr *Def = MRI->getVRegDef(SrcReg);
-if (Def && Def->getOpcode() == AMDGPU::S_ADD_I32 &&
-Def->getOperand(3).isDead()) {
- MachineOperand *Src0 = &Def->getOperand(1);
- MachineOperand *Src1 = &Def->getOperand(2);
-
- // TODO: This is profitable with more operand types, and for more
- // opcodes. But ultimately this is working around poor / nonexistent
- // regbankselect.
- if (!Src0->isFI() && !Src1->isFI())
-return false;
+if (!Def || Def->getNumOperands() != 4)
+ return false;
- if (Src0->isFI())
-std::swap(Src0, Src1);
-
- MachineBasicBlock *MBB = Def->getParent();
- const DebugLoc &DL = Def->getDebugLoc();
- if (ST->hasAddNoCarry()) {
-bool UseVOP3 = !Src0->isImm() || TII->isInlineConstant(*Src0);
-MachineInstrBuilder Add =
-BuildMI(*MBB, *Def, DL,
-TII->get(UseVOP3 ? AMDGPU::V_ADD_U32_e64
- : AMDGPU::V_ADD_U32_e32),
-DstReg)
-.add(*Src0)
-.add(*Src1)
-.setMIFlags(Def->getFlags());
-if (UseVOP3)
- Add.addImm(0);
-
-Def->eraseFromParent();
-MI.eraseFromParent();
-return true;
- }
+MachineOperand *Src0 = &Def->getOperand(1);
+MachineOperand *Src1 = &Def->getOperand(2);
- MachineBasicBlock::LivenessQueryResult Liveness =
- MBB->computeRegisterLiveness(TRI, AMDGPU::VCC, *Def, 16);
- if (Liveness == MachineBasicBlock::LQR_Dead) {
-// TODO: If src1 satisfies operand constraints, use vop3 version.
-BuildMI(*MBB, *Def, DL, TII->get(AMDGPU::V_ADD_CO_U32_e32), DstReg)
-.add(*Src0)
-.add(*Src1)
-.setOperandDead(3) // implicit-def $vcc
-.setMIFlags(Def->getFlags());
-Def->eraseFromParent();
-MI.eraseFromParent();
-return true;
+// TODO: This is profitable with more operand types, and for more
+// opcodes. But ultimately this is working around poor / nonexistent
+// regbankselect.
+if (!Src0->isFI() && !Src1->isFI())
+ return false;
+
+if (Src0->isFI())
+ std::swap(Src0, Src1);
+
+const bool UseVOP3 = !Src0->isImm() || TII->isInlineConstant(*Src0);
+unsigned NewOp = convertToVALUOp(Def->getOpcode(), UseVOP3);
+if (NewOp == AMDGPU::INSTRUCTION_LIST_END ||
+!Def->getOperand(3).isDead()) // Check if scc is dead
+ return false;
+
+MachineBasicBlock *MBB = Def->getParent();
+const DebugLoc &DL = Def->getDebugLoc();
+if (NewOp != AMDGPU::V_ADD_CO_
[llvm-branch-commits] [llvm] AMDGPU: Default to selecting frame indexes to SGPRs (PR #115060)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/115060?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#115060** https://app.graphite.dev/github/pr/llvm/llvm-project/115060?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 * **#115059** https://app.graphite.dev/github/pr/llvm/llvm-project/115059?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#115058** https://app.graphite.dev/github/pr/llvm/llvm-project/115058?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by Graphite. https://stacking.dev/?utm_source=stack-comment";>Learn more about stacking. Join @arsenm and the rest of your teammates on https://graphite.dev?utm-source=stack-comment";>https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="11px" height="11px"/> Graphite https://github.com/llvm/llvm-project/pull/115060 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Fold more scalar operations on frame index to VALU (PR #115059)
arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/115059?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#115060** https://app.graphite.dev/github/pr/llvm/llvm-project/115060?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#115059** https://app.graphite.dev/github/pr/llvm/llvm-project/115059?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 * **#115058** https://app.graphite.dev/github/pr/llvm/llvm-project/115058?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by Graphite. https://stacking.dev/?utm_source=stack-comment";>Learn more about stacking. Join @arsenm and the rest of your teammates on https://graphite.dev?utm-source=stack-comment";>https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="11px" height="11px"/> Graphite https://github.com/llvm/llvm-project/pull/115059 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Default to selecting frame indexes to SGPRs (PR #115060)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
Changes
Only select to a VGPR if it's trivally used in VGPR only contexts.
This fixes mishandling frame indexes used in SGPR only contexts,
like inline assembly constraints.
This is suboptimal in the common case where the frame index
is transitively used by only VALU ops. We make up for this by later
folding the copy to VALU plus scalar op in SIFoldOperands.
---
Patch is 147.55 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/115060.diff
19 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+4-1)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll (+3-2)
- (modified) llvm/test/CodeGen/AMDGPU/captured-frame-index.ll (+31-41)
- (modified) llvm/test/CodeGen/AMDGPU/commute-compares.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll (+55-67)
- (modified) llvm/test/CodeGen/AMDGPU/flat-scratch.ll (+95-60)
- (modified) llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll (+21-26)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll (+36-36)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll (+36-36)
- (modified) llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll (+12-12)
- (modified) llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
(+6-8)
- (modified) llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
(+50-40)
- (modified) llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.gfx10.ll
(+111-133)
- (modified) llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll
(+390-501)
- (modified) llvm/test/CodeGen/AMDGPU/memcpy-fixed-align.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/required-export-priority.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/scratch-buffer.ll (+9-5)
- (modified) llvm/test/CodeGen/AMDGPU/scratch-simple.ll (+16-11)
``diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td
b/llvm/lib/Target/AMDGPU/SIInstructions.td
index c8a46217190a1d..423d63931a4755 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2175,8 +2175,11 @@ foreach vt = [i32, p3, p5, p6, p2] in {
>;
}
+// FIXME: The register bank of the frame index should depend on the
+// users, and transitive users of the add. We may require an
+// unnecessary copy from SGPR to VGPR.
def : GCNPat <
- (p5 frameindex:$fi),
+ (VGPRImm<(p5 frameindex)>:$fi),
(V_MOV_B32_e32 (p5 (frameindex_to_targetframeindex $fi)))
>;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
b/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
index 5889af70a8f092..c1a957dec3e867 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
@@ -364,9 +364,10 @@ entry:
; FUNC-LABEL: ptrtoint:
; SI-NOT: ds_write
+; SI: s_add_i32 [[S_ADD_OFFSET:s[0-9]+]], s{{[0-9]+}}, 5
; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0
offen
-; SI: v_add_{{[iu]}}32_e32 [[ADD_OFFSET:v[0-9]+]], vcc, 5,
-; SI: buffer_load_dword v{{[0-9]+}}, [[ADD_OFFSET:v[0-9]+]],
s[{{[0-9]+:[0-9]+}}], 0 offen ;
+; SI: v_mov_b32_e32 [[V_ADD_OFFSET:v[0-9]+]], [[S_ADD_OFFSET]]
+; SI: buffer_load_dword v{{[0-9]+}}, [[V_ADD_OFFSET:v[0-9]+]],
s[{{[0-9]+:[0-9]+}}], 0 offen ;
define amdgpu_kernel void @ptrtoint(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
%alloca = alloca [16 x i32], addrspace(5)
%tmp0 = getelementptr [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %a
diff --git a/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
b/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
index ca0c669056ee33..2ec4c074a892dc 100644
--- a/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
+++ b/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
@@ -147,19 +147,14 @@ define amdgpu_kernel void
@stored_fi_to_global_2_small_objects(ptr addrspace(1)
; GCN-LABEL: {{^}}kernel_stored_fi_to_global_huge_frame_offset:
; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
-; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0
offset:4{{$}}
-; FIXME: Re-initialize
-; GCN: v_mov_b32_e32 [[BASE_0_1:v[0-9]+]], 4{{$}}
+; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0
offset:4{{$}}
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
-; GCN-DAG: v_add_i32_e32 [[BASE_1_OFF_1:v[0-9]+]], vcc, 0x3ffc, [[BASE_0_1]]
-
+; GCN-DAG: v_mov_b32_e32 [[V_BASE_1_OFF:v[0-9]+]], 0x4000{{$}}
+; GCN: buffer_store_dword [[K]], [[V_BASE_1_OFF]], s{{\[[0-9]+:[0-9]+\]}}, 0
offen{{$}}
-; GCN: v_add_i32_e32 [[BASE_1_OFF_2:v[0-9]+]], vcc, 56, [[BASE_0_1]]
-; GCN: buffer_store_dword [[K]], [[BASE_1_OFF_1]], s{{\[[0-9]+:[0-9]+\]}}, 0
offen{{$}}
-
-; GCN: buffer_store_dword [[BASE_1_OFF_2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
+; GCN: buffer_store_dword [[V_BASE_1_OFF]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
define am
[llvm-branch-commits] [llvm] AMDGPU: Mark grid size loads with range metadata (PR #113019)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/113019
>From 64d530b7c139da8aec7ede71fd201cb751a4072d Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:18:45 +0400
Subject: [PATCH] AMDGPU: Mark grid size loads with range metadata
Only handles the v5 case.
---
.../AMDGPU/AMDGPULowerKernelAttributes.cpp| 33 -
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp| 1 +
...amdgpu-max-num-workgroups-load-annotate.ll | 124 ++
3 files changed, 154 insertions(+), 4 deletions(-)
create mode 100644
llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
index 1bb5e794da7dd6..5fc0c36359b6f5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
@@ -23,6 +23,7 @@
#include "llvm/IR/InstIterator.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
+#include "llvm/IR/MDBuilder.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Pass.h"
@@ -83,6 +84,20 @@ Function *getBasePtrIntrinsic(Module &M, bool IsV5OrAbove) {
} // end anonymous namespace
+static void annotateGridSizeLoadWithRangeMD(LoadInst *Load,
+uint32_t MaxNumGroups) {
+ if (MaxNumGroups == 0 || MaxNumGroups ==
std::numeric_limits::max())
+return;
+
+ if (!Load->getType()->isIntegerTy(32))
+return;
+
+ // TODO: If there is existing range metadata, preserve it if it is stricter.
+ MDBuilder MDB(Load->getContext());
+ MDNode *Range = MDB.createRange(APInt(32, 1), APInt(32, MaxNumGroups + 1));
+ Load->setMetadata(LLVMContext::MD_range, Range);
+}
+
static bool processUse(CallInst *CI, bool IsV5OrAbove) {
Function *F = CI->getParent()->getParent();
@@ -92,7 +107,11 @@ static bool processUse(CallInst *CI, bool IsV5OrAbove) {
const bool HasUniformWorkGroupSize =
F->getFnAttribute("uniform-work-group-size").getValueAsBool();
- if (!HasReqdWorkGroupSize && !HasUniformWorkGroupSize)
+ SmallVector MaxNumWorkgroups =
+ AMDGPU::getIntegerVecAttribute(*F, "amdgpu-max-num-workgroups", 3);
+
+ if (!HasReqdWorkGroupSize && !HasUniformWorkGroupSize &&
+ none_of(MaxNumWorkgroups, [](unsigned X) { return X != 0; }))
return false;
Value *BlockCounts[3] = {nullptr, nullptr, nullptr};
@@ -133,16 +152,22 @@ static bool processUse(CallInst *CI, bool IsV5OrAbove) {
if (IsV5OrAbove) { // Base is ImplicitArgPtr.
switch (Offset) {
case HIDDEN_BLOCK_COUNT_X:
-if (LoadSize == 4)
+if (LoadSize == 4) {
BlockCounts[0] = Load;
+ annotateGridSizeLoadWithRangeMD(Load, MaxNumWorkgroups[0]);
+}
break;
case HIDDEN_BLOCK_COUNT_Y:
-if (LoadSize == 4)
+if (LoadSize == 4) {
BlockCounts[1] = Load;
+ annotateGridSizeLoadWithRangeMD(Load, MaxNumWorkgroups[1]);
+}
break;
case HIDDEN_BLOCK_COUNT_Z:
-if (LoadSize == 4)
+if (LoadSize == 4) {
BlockCounts[2] = Load;
+ annotateGridSizeLoadWithRangeMD(Load, MaxNumWorkgroups[2]);
+}
break;
case HIDDEN_GROUP_SIZE_X:
if (LoadSize == 2)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
index 54b17ca2cffb15..b18ce90cf45dba 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -369,6 +369,7 @@ const AMDGPUSubtarget &AMDGPUSubtarget::get(const
TargetMachine &TM, const Funct
TM.getSubtarget(F));
}
+// FIXME: This has no reason to be in subtarget
SmallVector
AMDGPUSubtarget::getMaxNumWorkGroups(const Function &F) const {
return AMDGPU::getIntegerVecAttribute(F, "amdgpu-max-num-workgroups", 3,
diff --git
a/llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
b/llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
new file mode 100644
index 00..9064292129928f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
@@ -0,0 +1,124 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa
-passes=amdgpu-lower-kernel-attributes %s | FileCheck %s
+
+define i32 @use_grid_size_x_max_num_workgroups() #0 {
+; CHECK-LABEL: define i32 @use_grid_size_x_max_num_workgroups(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:[[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4)
@llvm.amdgcn.implicitarg.ptr()
+; CHECK-NEXT:[[GRID_SIZE_X:%.*]] = load i32, ptr addrspace(4)
[[IMPLICITARG_PTR]], align 4, !range [[RNG0:![0-9]+]]
+; CHECK-NEXT:ret i32 [[GRID_SIZE_X]]
+;
+ %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+ %grid.size.x = load i32,
[llvm-branch-commits] [llvm] AMDGPU: Fold more scalar operations on frame index to VALU (PR #115059)
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/115059 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [NVPTX] Promote v2i8 to v2i16 (#111189) (PR #115081)
https://github.com/Artem-B edited https://github.com/llvm/llvm-project/pull/115081 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] clang/HIP: Remove requires system-linux from some driver tests (PR #112842)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/112842
>From a5e5b2c05c6026e855f1534b040c353ee638c178 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Fri, 18 Oct 2024 09:40:34 +0400
Subject: [PATCH] clang/HIP: Remove requires system-linux from some driver
tests
---
clang/test/Driver/hip-partial-link.hip | 2 +-
clang/test/Driver/linker-wrapper.c | 10 --
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/clang/test/Driver/hip-partial-link.hip
b/clang/test/Driver/hip-partial-link.hip
index 8b27f78f3bdd12..5580e569780194 100644
--- a/clang/test/Driver/hip-partial-link.hip
+++ b/clang/test/Driver/hip-partial-link.hip
@@ -1,4 +1,4 @@
-// REQUIRES: x86-registered-target, amdgpu-registered-target, lld, system-linux
+// REQUIRES: x86-registered-target, amdgpu-registered-target, lld
// RUN: %clang -x hip --target=x86_64-unknown-linux-gnu
--no-offload-new-driver \
// RUN: --offload-arch=gfx906 -c -nostdinc -nogpuinc -nohipwrapperinc \
diff --git a/clang/test/Driver/linker-wrapper.c
b/clang/test/Driver/linker-wrapper.c
index 470af4d5d70cac..fac4331e51f694 100644
--- a/clang/test/Driver/linker-wrapper.c
+++ b/clang/test/Driver/linker-wrapper.c
@@ -2,8 +2,6 @@
// REQUIRES: nvptx-registered-target
// REQUIRES: amdgpu-registered-target
-// REQUIRES: system-linux
-
// An externally visible variable so static libraries extract.
__attribute__((visibility("protected"), used)) int x;
@@ -30,7 +28,7 @@ __attribute__((visibility("protected"), used)) int x;
// RUN: clang-linker-wrapper --host-triple=x86_64-unknown-linux-gnu --dry-run
--device-debug -O0 \
// RUN: --linker-path=/usr/bin/ld %t.o -o a.out 2>&1 | FileCheck %s
--check-prefix=NVPTX-LINK-DEBUG
-// NVPTX-LINK-DEBUG: clang{{.*}} -o {{.*}}.img --target=nvptx64-nvidia-cuda
-march=sm_70 -O2 -flto {{.*}}.o {{.*}}.o -g
+// NVPTX-LINK-DEBUG: clang{{.*}} -o {{.*}}.img --target=nvptx64-nvidia-cuda
-march=sm_70 -O2 -flto {{.*}}.o {{.*}}.o -g
// RUN: clang-offload-packager -o %t.out \
// RUN:
--image=file=%t.elf.o,kind=openmp,triple=amdgcn-amd-amdhsa,arch=gfx908 \
@@ -93,7 +91,7 @@ __attribute__((visibility("protected"), used)) int x;
// CUDA: clang{{.*}} -o [[IMG_SM70:.+]] --target=nvptx64-nvidia-cuda
-march=sm_70
// CUDA: clang{{.*}} -o [[IMG_SM52:.+]] --target=nvptx64-nvidia-cuda
-march=sm_52
-// CUDA: fatbinary{{.*}}-64 --create {{.*}}.fatbin
--image=profile=sm_70,file=[[IMG_SM70]] --image=profile=sm_52,file=[[IMG_SM52]]
+// CUDA: fatbinary{{.*}}-64 --create {{.*}}.fatbin
--image=profile=sm_70,file=[[IMG_SM70]] --image=profile=sm_52,file=[[IMG_SM52]]
// CUDA: usr/bin/ld{{.*}} {{.*}}.openmp.image.{{.*}}.o
{{.*}}.cuda.image.{{.*}}.o
// RUN: clang-offload-packager -o %t.out \
@@ -120,7 +118,7 @@ __attribute__((visibility("protected"), used)) int x;
// HIP: clang{{.*}} -o [[IMG_GFX90A:.+]] --target=amdgcn-amd-amdhsa
-mcpu=gfx90a
// HIP: clang{{.*}} -o [[IMG_GFX908:.+]] --target=amdgcn-amd-amdhsa
-mcpu=gfx908
-// HIP: clang-offload-bundler{{.*}}-type=o -bundle-align=4096 -compress
-compression-level=6
-targets=host-x86_64-unknown-linux,hip-amdgcn-amd-amdhsa--gfx90a,hip-amdgcn-amd-amdhsa--gfx908
-input=/dev/null -input=[[IMG_GFX90A]] -input=[[IMG_GFX908]]
-output={{.*}}.hipfb
+// HIP: clang-offload-bundler{{.*}}-type=o -bundle-align=4096 -compress
-compression-level=6
-targets=host-x86_64-unknown-linux,hip-amdgcn-amd-amdhsa--gfx90a,hip-amdgcn-amd-amdhsa--gfx908
-input={{/dev/null|NUL}} -input=[[IMG_GFX90A]] -input=[[IMG_GFX908]]
-output={{.*}}.hipfb
// RUN: clang-offload-packager -o %t.out \
// RUN:
--image=file=%t.elf.o,kind=openmp,triple=amdgcn-amd-amdhsa,arch=gfx908 \
@@ -211,7 +209,7 @@ __attribute__((visibility("protected"), used)) int x;
// RUN: %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=RELOCATABLE-LINK-HIP
// RELOCATABLE-LINK-HIP: clang{{.*}} -o {{.*}}.img --target=amdgcn-amd-amdhsa
-// RELOCATABLE-LINK-HIP: clang-offload-bundler{{.*}} -type=o
-bundle-align=4096
-targets=host-x86_64-unknown-linux,hip-amdgcn-amd-amdhsa--gfx90a
-input=/dev/null -input={{.*}} -output={{.*}}
+// RELOCATABLE-LINK-HIP: clang-offload-bundler{{.*}} -type=o
-bundle-align=4096
-targets=host-x86_64-unknown-linux,hip-amdgcn-amd-amdhsa--gfx90a
-input={{/dev/null|NUL}} -input={{.*}} -output={{.*}}
// RELOCATABLE-LINK-HIP: /usr/bin/ld.lld{{.*}}-r
// RELOCATABLE-LINK-HIP: llvm-objcopy{{.*}}a.out --remove-section
.llvm.offloading
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Default to selecting frame indexes to SGPRs (PR #115060)
https://github.com/rampitec approved this pull request. https://github.com/llvm/llvm-project/pull/115060 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Fold more scalar operations on frame index to VALU (PR #115059)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/115059 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Default to selecting frame indexes to SGPRs (PR #115060)
https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/115060 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups (PR #113751)
arsenm wrote: ### Merge activity * **Nov 5, 3:43 PM EST**: A user started a stack merge that includes this pull request via [Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/113751). https://github.com/llvm/llvm-project/pull/113751 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU: Mark grid size loads with range metadata (PR #113019)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/113019
>From 63a199325b085599e1d66c241c7a9beca667dfb3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sat, 19 Oct 2024 02:18:45 +0400
Subject: [PATCH] AMDGPU: Mark grid size loads with range metadata
Only handles the v5 case.
---
.../AMDGPU/AMDGPULowerKernelAttributes.cpp| 33 -
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp| 1 +
...amdgpu-max-num-workgroups-load-annotate.ll | 124 ++
3 files changed, 154 insertions(+), 4 deletions(-)
create mode 100644
llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
index 1bb5e794da7dd6..5fc0c36359b6f5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp
@@ -23,6 +23,7 @@
#include "llvm/IR/InstIterator.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
+#include "llvm/IR/MDBuilder.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Pass.h"
@@ -83,6 +84,20 @@ Function *getBasePtrIntrinsic(Module &M, bool IsV5OrAbove) {
} // end anonymous namespace
+static void annotateGridSizeLoadWithRangeMD(LoadInst *Load,
+uint32_t MaxNumGroups) {
+ if (MaxNumGroups == 0 || MaxNumGroups ==
std::numeric_limits::max())
+return;
+
+ if (!Load->getType()->isIntegerTy(32))
+return;
+
+ // TODO: If there is existing range metadata, preserve it if it is stricter.
+ MDBuilder MDB(Load->getContext());
+ MDNode *Range = MDB.createRange(APInt(32, 1), APInt(32, MaxNumGroups + 1));
+ Load->setMetadata(LLVMContext::MD_range, Range);
+}
+
static bool processUse(CallInst *CI, bool IsV5OrAbove) {
Function *F = CI->getParent()->getParent();
@@ -92,7 +107,11 @@ static bool processUse(CallInst *CI, bool IsV5OrAbove) {
const bool HasUniformWorkGroupSize =
F->getFnAttribute("uniform-work-group-size").getValueAsBool();
- if (!HasReqdWorkGroupSize && !HasUniformWorkGroupSize)
+ SmallVector MaxNumWorkgroups =
+ AMDGPU::getIntegerVecAttribute(*F, "amdgpu-max-num-workgroups", 3);
+
+ if (!HasReqdWorkGroupSize && !HasUniformWorkGroupSize &&
+ none_of(MaxNumWorkgroups, [](unsigned X) { return X != 0; }))
return false;
Value *BlockCounts[3] = {nullptr, nullptr, nullptr};
@@ -133,16 +152,22 @@ static bool processUse(CallInst *CI, bool IsV5OrAbove) {
if (IsV5OrAbove) { // Base is ImplicitArgPtr.
switch (Offset) {
case HIDDEN_BLOCK_COUNT_X:
-if (LoadSize == 4)
+if (LoadSize == 4) {
BlockCounts[0] = Load;
+ annotateGridSizeLoadWithRangeMD(Load, MaxNumWorkgroups[0]);
+}
break;
case HIDDEN_BLOCK_COUNT_Y:
-if (LoadSize == 4)
+if (LoadSize == 4) {
BlockCounts[1] = Load;
+ annotateGridSizeLoadWithRangeMD(Load, MaxNumWorkgroups[1]);
+}
break;
case HIDDEN_BLOCK_COUNT_Z:
-if (LoadSize == 4)
+if (LoadSize == 4) {
BlockCounts[2] = Load;
+ annotateGridSizeLoadWithRangeMD(Load, MaxNumWorkgroups[2]);
+}
break;
case HIDDEN_GROUP_SIZE_X:
if (LoadSize == 2)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
index 54b17ca2cffb15..b18ce90cf45dba 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -369,6 +369,7 @@ const AMDGPUSubtarget &AMDGPUSubtarget::get(const
TargetMachine &TM, const Funct
TM.getSubtarget(F));
}
+// FIXME: This has no reason to be in subtarget
SmallVector
AMDGPUSubtarget::getMaxNumWorkGroups(const Function &F) const {
return AMDGPU::getIntegerVecAttribute(F, "amdgpu-max-num-workgroups", 3,
diff --git
a/llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
b/llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
new file mode 100644
index 00..9064292129928f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-max-num-workgroups-load-annotate.ll
@@ -0,0 +1,124 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa
-passes=amdgpu-lower-kernel-attributes %s | FileCheck %s
+
+define i32 @use_grid_size_x_max_num_workgroups() #0 {
+; CHECK-LABEL: define i32 @use_grid_size_x_max_num_workgroups(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:[[IMPLICITARG_PTR:%.*]] = call ptr addrspace(4)
@llvm.amdgcn.implicitarg.ptr()
+; CHECK-NEXT:[[GRID_SIZE_X:%.*]] = load i32, ptr addrspace(4)
[[IMPLICITARG_PTR]], align 4, !range [[RNG0:![0-9]+]]
+; CHECK-NEXT:ret i32 [[GRID_SIZE_X]]
+;
+ %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
+ %grid.size.x = load i32,
[llvm-branch-commits] [clang] [AMDGPU] Simplify dpp builtin handling (PR #115090)
https://github.com/rampitec edited https://github.com/llvm/llvm-project/pull/115090 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(nullptr),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0),
+ DEFINE_GENERIC_REGISTER_STUB(r1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2),
+ DEFINE_GENERIC_REGISTER_STUB(r3, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12),
+ DEFINE_REGISTER_STUB(r13),
+ DEFINE_REGISTER_STUB(r14),
+ DEFINE_REGISTER_STUB(r15),
+ DEFINE_REGISTER_STUB(r16),
+ DEFINE_REGISTER_STUB(r17),
+ DEFINE_REGISTER_STUB(r18),
+ DEFINE_REGISTER_STUB(r19),
+ DEFINE_REGISTER_STUB(r20),
+ DEFINE_REGISTER_STUB(r21),
+ DEFINE_GENERIC_REGISTER_STUB(r22, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23),
+ DEFINE_REGISTER_STUB(r24),
+ DEFINE_REGISTER_STUB(r25),
+ DEFINE_REGISTER_STUB(r26),
+ DEFINE_REGISTER_STUB(r27),
+ DEFINE_REGISTER_STUB(r28),
+ DEFINE_REGISTER_STUB(r29),
+ DEFINE_REGISTER_STUB(r30),
+ DEFINE_REGISTER_STUB(r31),
+ DEFINE_GENERIC_REGISTER_STUB(pc, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+//--
+// Static Functions
+//--
+
+ABISP
+ABISysV_loongarch::CreateInstance(ProcessSP process_sp, const ArchSpec &arch) {
+ llvm::Triple::ArchType machine = arch.GetTriple().getAr
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(nullptr),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0),
+ DEFINE_GENERIC_REGISTER_STUB(r1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2),
+ DEFINE_GENERIC_REGISTER_STUB(r3, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12),
+ DEFINE_REGISTER_STUB(r13),
+ DEFINE_REGISTER_STUB(r14),
+ DEFINE_REGISTER_STUB(r15),
+ DEFINE_REGISTER_STUB(r16),
+ DEFINE_REGISTER_STUB(r17),
+ DEFINE_REGISTER_STUB(r18),
+ DEFINE_REGISTER_STUB(r19),
+ DEFINE_REGISTER_STUB(r20),
+ DEFINE_REGISTER_STUB(r21),
+ DEFINE_GENERIC_REGISTER_STUB(r22, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23),
+ DEFINE_REGISTER_STUB(r24),
+ DEFINE_REGISTER_STUB(r25),
+ DEFINE_REGISTER_STUB(r26),
+ DEFINE_REGISTER_STUB(r27),
+ DEFINE_REGISTER_STUB(r28),
+ DEFINE_REGISTER_STUB(r29),
+ DEFINE_REGISTER_STUB(r30),
+ DEFINE_REGISTER_STUB(r31),
+ DEFINE_GENERIC_REGISTER_STUB(pc, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+//--
+// Static Functions
+//--
+
+ABISP
+ABISysV_loongarch::CreateInstance(ProcessSP process_sp, const ArchSpec &arch) {
+ llvm::Triple::ArchType machine = arch.GetTriple().getAr
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(nullptr),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0),
+ DEFINE_GENERIC_REGISTER_STUB(r1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2),
+ DEFINE_GENERIC_REGISTER_STUB(r3, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12),
+ DEFINE_REGISTER_STUB(r13),
+ DEFINE_REGISTER_STUB(r14),
+ DEFINE_REGISTER_STUB(r15),
+ DEFINE_REGISTER_STUB(r16),
+ DEFINE_REGISTER_STUB(r17),
+ DEFINE_REGISTER_STUB(r18),
+ DEFINE_REGISTER_STUB(r19),
+ DEFINE_REGISTER_STUB(r20),
+ DEFINE_REGISTER_STUB(r21),
+ DEFINE_GENERIC_REGISTER_STUB(r22, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23),
+ DEFINE_REGISTER_STUB(r24),
+ DEFINE_REGISTER_STUB(r25),
+ DEFINE_REGISTER_STUB(r26),
+ DEFINE_REGISTER_STUB(r27),
+ DEFINE_REGISTER_STUB(r28),
+ DEFINE_REGISTER_STUB(r29),
+ DEFINE_REGISTER_STUB(r30),
+ DEFINE_REGISTER_STUB(r31),
+ DEFINE_GENERIC_REGISTER_STUB(pc, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+//--
+// Static Functions
+//--
+
+ABISP
+ABISysV_loongarch::CreateInstance(ProcessSP process_sp, const ArchSpec &arch) {
+ llvm::Triple::ArchType machine = arch.GetTriple().getAr
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(nullptr),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0),
+ DEFINE_GENERIC_REGISTER_STUB(r1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2),
+ DEFINE_GENERIC_REGISTER_STUB(r3, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12),
+ DEFINE_REGISTER_STUB(r13),
+ DEFINE_REGISTER_STUB(r14),
+ DEFINE_REGISTER_STUB(r15),
+ DEFINE_REGISTER_STUB(r16),
+ DEFINE_REGISTER_STUB(r17),
+ DEFINE_REGISTER_STUB(r18),
+ DEFINE_REGISTER_STUB(r19),
+ DEFINE_REGISTER_STUB(r20),
+ DEFINE_REGISTER_STUB(r21),
+ DEFINE_GENERIC_REGISTER_STUB(r22, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23),
+ DEFINE_REGISTER_STUB(r24),
+ DEFINE_REGISTER_STUB(r25),
+ DEFINE_REGISTER_STUB(r26),
+ DEFINE_REGISTER_STUB(r27),
+ DEFINE_REGISTER_STUB(r28),
+ DEFINE_REGISTER_STUB(r29),
+ DEFINE_REGISTER_STUB(r30),
+ DEFINE_REGISTER_STUB(r31),
+ DEFINE_GENERIC_REGISTER_STUB(pc, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
+
+const RegisterInfo *ABISysV_loongarch::GetRegisterInfoArray(uint32_t &count) {
+ count = dwarf::g_register_infos.size();
+ return dwarf::g_register_infos.data();
+}
+
+//--
+// Static Functions
+//--
+
+ABISP
+ABISysV_loongarch::CreateInstance(ProcessSP process_sp, const ArchSpec &arch) {
+ llvm::Triple::ArchType machine = arch.GetTriple().getAr
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,672 @@
+//===--
ABISysV_loongarch.cpp--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "ABISysV_loongarch.h"
+
+#include
+#include
+#include
+
+#include "llvm/IR/DerivedTypes.h"
+
+#include "Utility/LoongArch_DWARF_Registers.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Core/Value.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Target/StackFrame.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/ValueObject/ValueObjectConstResult.h"
+
+#define DEFINE_REG_NAME(reg_num) ConstString(#reg_num).GetCString()
+#define DEFINE_REG_NAME_STR(reg_name) ConstString(reg_name).GetCString()
+
+// The ABI is not a source of such information as size, offset, encoding, etc.
+// of a register. Just provides correct dwarf and eh_frame numbers.
+
+#define DEFINE_GENERIC_REGISTER_STUB(dwarf_num, generic_num)
\
+ {
\
+ DEFINE_REG_NAME(dwarf_num),
\
+ DEFINE_REG_NAME_STR(nullptr),
\
+ 0,
\
+ 0,
\
+ eEncodingInvalid,
\
+ eFormatDefault,
\
+ {dwarf_num, dwarf_num, generic_num, LLDB_INVALID_REGNUM, dwarf_num},
\
+ nullptr,
\
+ nullptr,
\
+ nullptr,
\
+ }
+
+#define DEFINE_REGISTER_STUB(dwarf_num)
\
+ DEFINE_GENERIC_REGISTER_STUB(dwarf_num, LLDB_INVALID_REGNUM)
+
+using namespace lldb;
+using namespace lldb_private;
+
+LLDB_PLUGIN_DEFINE_ADV(ABISysV_loongarch, ABILoongArch)
+
+namespace {
+namespace dwarf {
+enum regnums {
+ r0,
+ ra,
+ r1 = ra,
+ r2,
+ sp,
+ r3 = sp,
+ r4,
+ r5,
+ r6,
+ r7,
+ r8,
+ r9,
+ r10,
+ r11,
+ r12,
+ r13,
+ r14,
+ r15,
+ r16,
+ r17,
+ r18,
+ r19,
+ r20,
+ r21,
+ fp,
+ r22 = fp,
+ r23,
+ r24,
+ r25,
+ r26,
+ r27,
+ r28,
+ r29,
+ r30,
+ r31,
+ pc
+};
+
+static const std::array g_register_infos = {
+{DEFINE_REGISTER_STUB(r0),
+ DEFINE_GENERIC_REGISTER_STUB(r1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_REGISTER_STUB(r2),
+ DEFINE_GENERIC_REGISTER_STUB(r3, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GENERIC_REGISTER_STUB(r4, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GENERIC_REGISTER_STUB(r5, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GENERIC_REGISTER_STUB(r6, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GENERIC_REGISTER_STUB(r7, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GENERIC_REGISTER_STUB(r8, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GENERIC_REGISTER_STUB(r9, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GENERIC_REGISTER_STUB(r10, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GENERIC_REGISTER_STUB(r11, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_REGISTER_STUB(r12),
+ DEFINE_REGISTER_STUB(r13),
+ DEFINE_REGISTER_STUB(r14),
+ DEFINE_REGISTER_STUB(r15),
+ DEFINE_REGISTER_STUB(r16),
+ DEFINE_REGISTER_STUB(r17),
+ DEFINE_REGISTER_STUB(r18),
+ DEFINE_REGISTER_STUB(r19),
+ DEFINE_REGISTER_STUB(r20),
+ DEFINE_REGISTER_STUB(r21),
+ DEFINE_GENERIC_REGISTER_STUB(r22, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_REGISTER_STUB(r23),
+ DEFINE_REGISTER_STUB(r24),
+ DEFINE_REGISTER_STUB(r25),
+ DEFINE_REGISTER_STUB(r26),
+ DEFINE_REGISTER_STUB(r27),
+ DEFINE_REGISTER_STUB(r28),
+ DEFINE_REGISTER_STUB(r29),
+ DEFINE_REGISTER_STUB(r30),
+ DEFINE_REGISTER_STUB(r31),
+ DEFINE_GENERIC_REGISTER_STUB(pc, LLDB_REGNUM_GENERIC_PC)}};
+} // namespace dwarf
+} // namespace
+
+// Number of argument registers (the base integer calling convention
+// provides 8 argument registers, a0-a7)
+static constexpr size_t g_regs_for_args_count = 8U;
SixWeining wrote:
Should we take floating point registers into account? Or we should mention
somewhere that only GPRs are supported currently.
https://github.com/llvm/llvm-project/pull/114742
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lldb] [lldb][LoongArch] Function calls support in lldb expressions (PR #114742)
@@ -0,0 +1,104 @@
+//===-- ABISysV_loongarch.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+#define LLDB_SOURCE_PLUGINS_ABI_LOONGARCH_ABISYSV_LOONGARCH_H
+
+// Other libraries and framework includes
+#include "llvm/TargetParser/Triple.h"
+
+// Project includes
+#include "lldb/Target/ABI.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+class ABISysV_loongarch : public lldb_private::RegInfoBasedABI {
+public:
+ ~ABISysV_loongarch() override = default;
+
+ size_t GetRedZoneSize() const override { return 0; }
+
+ bool PrepareTrivialCall(lldb_private::Thread &thread, lldb::addr_t sp,
+ lldb::addr_t functionAddress,
+ lldb::addr_t returnAddress,
+ llvm::ArrayRef args) const override;
+
+ bool GetArgumentValues(lldb_private::Thread &thread,
+ lldb_private::ValueList &values) const override;
+
+ lldb_private::Status
+ SetReturnValueObject(lldb::StackFrameSP &frame_sp,
+ lldb::ValueObjectSP &new_value) override;
+
+ lldb::ValueObjectSP
+ GetReturnValueObjectImpl(lldb_private::Thread &thread,
+ lldb_private::CompilerType &type) const override;
+
+ bool
+ CreateFunctionEntryUnwindPlan(lldb_private::UnwindPlan &unwind_plan)
override;
+
+ bool CreateDefaultUnwindPlan(lldb_private::UnwindPlan &unwind_plan) override;
+
+ bool RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
+
+ bool CallFrameAddressIsValid(lldb::addr_t cfa) override {
+// The CFA must be 16 byte aligned.
+return (cfa & 0xfull) == 0;
+ }
+
+ void SetIsLA64(bool is_la64) { m_is_la64 = is_la64; }
+
+ bool CodeAddressIsValid(lldb::addr_t pc) override {
+// Code address must be 4 byte aligned.
+if (pc & (4ull - 1ull))
+ return false;
+
+return true;
+ }
+
+ const lldb_private::RegisterInfo *
+ GetRegisterInfoArray(uint32_t &count) override;
+
+ //--
+ // Static Functions
+ //--
+
+ static void Initialize();
+
+ static void Terminate();
+
+ static lldb::ABISP CreateInstance(lldb::ProcessSP process_sp,
+const lldb_private::ArchSpec &arch);
+
+ static llvm::StringRef GetPluginNameStatic() { return "sysv-loongarch"; }
+
+ //--
+ // PluginInterface protocol
+ //--
+
+ llvm::StringRef GetPluginName() override { return GetPluginNameStatic(); }
+
+protected:
+ void AugmentRegisterInfo(
+ std::vector ®s) override;
+
+ bool RegisterIsCalleeSaved(const lldb_private::RegisterInfo *reg_info);
+
+private:
+ lldb::ValueObjectSP
+ GetReturnValueObjectSimple(lldb_private::Thread &thread,
+ lldb_private::CompilerType &ast_type) const;
+
+ using lldb_private::RegInfoBasedABI::RegInfoBasedABI; // Call CreateInstance
+// instead.
+ bool m_is_la64; // true if target is loongarch64; false if target is
SixWeining wrote:
Seems the comments are redundant.
https://github.com/llvm/llvm-project/pull/114742
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
