[llvm-branch-commits] [llvm] Local: Handle noalias.addrspace in copyMetadataForLoad (PR #103939)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/103939
>From b655b4c3d3be5f8347ff4bc8fa37c1553f1fd980 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 16:51:08 +0400
Subject: [PATCH] Local: Handle noalias.addrspace in copyMetadataForLoad
---
llvm/lib/Transforms/Utils/Local.cpp| 1 +
llvm/test/Transforms/InstCombine/loadstore-metadata.ll | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Transforms/Utils/Local.cpp
b/llvm/lib/Transforms/Utils/Local.cpp
index 564e5f47024d40..49c5030357aacc 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -3474,6 +3474,7 @@ void llvm::copyMetadataForLoad(LoadInst &Dest, const
LoadInst &Source) {
case LLVMContext::MD_mem_parallel_loop_access:
case LLVMContext::MD_access_group:
case LLVMContext::MD_noundef:
+case LLVMContext::MD_noalias_addrspace:
// All of these directly apply.
Dest.setMetadata(ID, N);
break;
diff --git a/llvm/test/Transforms/InstCombine/loadstore-metadata.ll
b/llvm/test/Transforms/InstCombine/loadstore-metadata.ll
index 247a02f0bcc14a..dccbfbd13f73d0 100644
--- a/llvm/test/Transforms/InstCombine/loadstore-metadata.ll
+++ b/llvm/test/Transforms/InstCombine/loadstore-metadata.ll
@@ -177,7 +177,7 @@ define i32 @test_load_cast_combine_noalias_addrspace(ptr
%ptr) {
; Ensure (cast (load (...))) -> (load (cast (...))) preserves TBAA.
; CHECK-LABEL: @test_load_cast_combine_noalias_addrspace(
; CHECK-NEXT: entry:
-; CHECK-NEXT:[[L1:%.*]] = load i32, ptr [[PTR:%.*]], align 4
+; CHECK-NEXT:[[L1:%.*]] = load i32, ptr [[PTR:%.*]], align 4,
!noalias.addrspace [[META10:![0-9]+]]
; CHECK-NEXT:ret i32 [[L1]]
;
entry:
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[llvm-branch-commits] [flang] [llvm] [Flang] Move runtime library files to FortranRuntime. NFC (PR #110298)
clementval wrote: How recent is your latest rebase? They are missing files in this PR. https://github.com/llvm/llvm-project/pull/110298 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][PAC] Move emission of LR checks in tail calls to AsmPrinter (PR #110705)
https://github.com/kovdan01 commented: With latest update, test-suite passes, thanks! https://github.com/llvm/llvm-project/pull/110705 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AArch64][PAC] Move emission of LR checks in tail calls to AsmPrinter (PR #110705)
https://github.com/kovdan01 dismissed https://github.com/llvm/llvm-project/pull/110705 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC] [MTE] simplify tagp logic (PR #110337)
https://github.com/vitalybuka approved this pull request. https://github.com/llvm/llvm-project/pull/110337 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
Akshat-Oke wrote: ping https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/111634 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/110229 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -1716,6 +1716,19 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (uint8_t Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
arsenm wrote:
Might as well just inline this and duplicate the code, the loop is trivial
enough
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -3851,3 +3851,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
arsenm wrote:
```suggestion
if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG))
RegFlags.push_back("WWM_REG");
```
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] Update correct dependency (PR #109937)
arsenm wrote: > ping Fix the description https://github.com/llvm/llvm-project/pull/109937 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/111634
>From 8e7f36627516a76d76ac7bb1d8c756261b6bbc5c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/2] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
>From bf5cc39e294bd6ff1b3361872e6d76a5e45100a8 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 06:22:10 +
Subject: [PATCH 2/2] unrename RegInfo: doesn't belong here
---
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index f10a480f7e6160..10d3cdcf0c1ce1 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &MRI = MF.getRegInfo();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-MRI.invalidateLiveness();
+RegInfo.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,7 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
-MRI.noteNewVirtualRegister(Info.VReg);
+RegInfo.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -721,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-MRI.addLiveIn(Reg, VReg);
+RegInfo.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -734,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-MRI.setCalleeSavedRegs(CalleeSavedRegisters);
+RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back(SmallString<8>("WWM_REG"));
+ }
arsenm wrote:
I mean the interface could change from SmallString to StringLiteral
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [clang] [flang] [lld] [llvm] [Flang] LLVM_ENABLE_RUNTIMES=FortranRuntime (PR #110217)
@@ -171,145 +76,88 @@ set(sources
unit-map.cpp
unit.cpp
utf.cpp
- ${FORTRAN_MODULE_OBJECTS}
)
-include(AddFlangOffloadRuntime)
-
-# List of files that are buildable for all devices.
-set(supported_files
- ISO_Fortran_binding.cpp
- allocatable.cpp
- allocator-registry.cpp
- array-constructor.cpp
- assign.cpp
- buffer.cpp
- character.cpp
- connection.cpp
- copy.cpp
- derived-api.cpp
- derived.cpp
- descriptor.cpp
- descriptor-io.cpp
- dot-product.cpp
- edit-input.cpp
- edit-output.cpp
- environment.cpp
- extrema.cpp
- external-unit.cpp
- file.cpp
- findloc.cpp
- format.cpp
- inquiry.cpp
- internal-unit.cpp
- io-api.cpp
- io-api-minimal.cpp
- io-error.cpp
- io-stmt.cpp
- iostat.cpp
- matmul-transpose.cpp
- matmul.cpp
- memory.cpp
- misc-intrinsic.cpp
- namelist.cpp
- non-tbp-dio.cpp
- numeric.cpp
- pointer.cpp
- product.cpp
- pseudo-unit.cpp
- ragged.cpp
- stat.cpp
- sum.cpp
- support.cpp
- terminator.cpp
- tools.cpp
- transformational.cpp
- type-code.cpp
- type-info.cpp
- unit.cpp
- utf.cpp
+set(public_headers "")
+file(GLOB_RECURSE public_headers
+ "${FLANGRUNTIME_SOURCE_DIR}/include/flang/Runtime/*.h"
+ "${FLANGRUNTIME_SOURCE_DIR}/include/flang/Common/*.h"
)
-enable_cuda_compilation(FortranRuntime "${supported_files}")
-enable_omp_offload_compilation("${supported_files}")
vzakhari wrote:
Is this just removed or moved somewhere?
https://github.com/llvm/llvm-project/pull/110217
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[llvm-branch-commits] [llvm] DAG: Preserve more flags when expanding gep (PR #110815)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/110815
>From 078f5f02502edadcc9c86f3e45f69e9fac918656 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 2 Oct 2024 11:20:23 +0400
Subject: [PATCH 1/3] DAG: Preserve more flags when expanding gep
This allows selecting the addressing mode for stack instructions
in cases where we need to prove the sign bit is zero.
---
.../SelectionDAG/SelectionDAGBuilder.cpp | 41 +++
.../CodeGen/AMDGPU/gep-flags-stack-offsets.ll | 6 +--
.../pointer-add-unknown-offset-debug-info.ll | 2 +-
3 files changed, 36 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 25213f587116d5..6838c0b530a363 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4386,6 +4386,17 @@ void SelectionDAGBuilder::visitGetElementPtr(const User
&I) {
// it.
IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
+ SDNodeFlags ScaleFlags;
+ // The multiplication of an index by the type size does not wrap the
+ // pointer index type in a signed sense (mul nsw).
+ if (NW.hasNoUnsignedSignedWrap())
+ScaleFlags.setNoSignedWrap(true);
+
+ // The multiplication of an index by the type size does not wrap the
+ // pointer index type in an unsigned sense (mul nuw).
+ if (NW.hasNoUnsignedWrap())
+ScaleFlags.setNoUnsignedWrap(true);
+
if (ElementScalable) {
EVT VScaleTy = N.getValueType().getScalarType();
SDValue VScale = DAG.getNode(
@@ -4393,27 +4404,41 @@ void SelectionDAGBuilder::visitGetElementPtr(const User
&I) {
DAG.getConstant(ElementMul.getZExtValue(), dl, VScaleTy));
if (IsVectorGEP)
VScale = DAG.getSplatVector(N.getValueType(), dl, VScale);
-IdxN = DAG.getNode(ISD::MUL, dl, N.getValueType(), IdxN, VScale);
+IdxN = DAG.getNode(ISD::MUL, dl, N.getValueType(), IdxN, VScale,
+ ScaleFlags);
} else {
// If this is a multiply by a power of two, turn it into a shl
// immediately. This is a very common case.
if (ElementMul != 1) {
if (ElementMul.isPowerOf2()) {
unsigned Amt = ElementMul.logBase2();
-IdxN = DAG.getNode(ISD::SHL, dl,
- N.getValueType(), IdxN,
- DAG.getConstant(Amt, dl, IdxN.getValueType()));
+IdxN = DAG.getNode(ISD::SHL, dl, N.getValueType(), IdxN,
+ DAG.getConstant(Amt, dl, IdxN.getValueType()),
+ ScaleFlags);
} else {
SDValue Scale = DAG.getConstant(ElementMul.getZExtValue(), dl,
IdxN.getValueType());
-IdxN = DAG.getNode(ISD::MUL, dl,
- N.getValueType(), IdxN, Scale);
+IdxN = DAG.getNode(ISD::MUL, dl, N.getValueType(), IdxN, Scale,
+ ScaleFlags);
}
}
}
- N = DAG.getNode(ISD::ADD, dl,
- N.getValueType(), N, IdxN);
+ SDNodeFlags AddFlags;
+
+ // The successive addition of each offset (without adding the base
+ // address) does not wrap the pointer index type in a signed sense (add
+ // nsw).
+ if (NW.hasNoUnsignedSignedWrap())
+AddFlags.setNoSignedWrap(true);
+
+ // The successive addition of each offset (without adding the base
+ // address) does not wrap the pointer index type in an unsigned sense
(add
+ // nuw).
+ if (NW.hasNoUnsignedWrap())
+AddFlags.setNoUnsignedWrap(true);
+
+ N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, IdxN, AddFlags);
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/gep-flags-stack-offsets.ll
b/llvm/test/CodeGen/AMDGPU/gep-flags-stack-offsets.ll
index 782894976c711c..a39afa6f609c7e 100644
--- a/llvm/test/CodeGen/AMDGPU/gep-flags-stack-offsets.ll
+++ b/llvm/test/CodeGen/AMDGPU/gep-flags-stack-offsets.ll
@@ -118,8 +118,7 @@ define void @gep_inbounds_nuw_alloca(i32 %idx, i32 %val) #0
{
; GFX8-NEXT:v_lshlrev_b32_e32 v0, 2, v0
; GFX8-NEXT:v_lshrrev_b32_e64 v2, 6, s32
; GFX8-NEXT:v_add_u32_e32 v0, vcc, v2, v0
-; GFX8-NEXT:v_add_u32_e32 v0, vcc, 16, v0
-; GFX8-NEXT:buffer_store_dword v1, v0, s[0:3], 0 offen
+; GFX8-NEXT:buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX8-NEXT:s_waitcnt vmcnt(0)
; GFX8-NEXT:s_setpc_b64 s[30:31]
;
@@ -145,8 +144,7 @@ define void @gep_nusw_nuw_alloca(i32 %idx, i32 %val) #0 {
; GFX8-NEXT:v_lshlrev_b32_e32 v0, 2, v0
; GFX8-NEXT:v_lshrrev_b32_e64 v2, 6, s32
; GFX8-NEXT:v_add_u32_e32 v0, vcc, v2, v0
-; GFX8-NEXT:v_add_u32_e32 v0, vcc, 16, v0
-; GFX8-NEXT:buffer_store_dword v1, v0, s[0:3], 0 offe
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/Akshat-Oke edited https://github.com/llvm/llvm-project/pull/111634 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/Akshat-Oke ready_for_review https://github.com/llvm/llvm-project/pull/111634 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Local: Handle noalias.addrspace in copyMetadataForLoad (PR #103939)
arsenm wrote: ping https://github.com/llvm/llvm-project/pull/103939 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
Akshat-Oke wrote:
I think Register info is an avenue for noting new virtual registers so I've put
it here https://github.com/llvm/llvm-project/pull/111634
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/Akshat-Oke edited https://github.com/llvm/llvm-project/pull/110229 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From 2b877142d7a9346033d02e5a977d2dcaa440258c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH 1/7] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
>From 553d5139960f0a26a5d3014fe36179c4ae0cf49d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 2/7] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 2c84cdac76d027..b23fea33183354 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1716,6 +1716,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..ec09a2803ed09c 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -696,8 +696,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGP
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/Akshat-Oke created
https://github.com/llvm/llvm-project/pull/111634
None
>From 2b877142d7a9346033d02e5a977d2dcaa440258c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
___
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[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
Akshat-Oke wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/111634?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#110229** https://app.graphite.dev/github/pr/llvm/llvm-project/110229?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#111634** https://app.graphite.dev/github/pr/llvm/llvm-project/111634?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 * **#110228** https://app.graphite.dev/github/pr/llvm/llvm-project/110228?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by Graphite. https://stacking.dev/?utm_source=stack-comment";>Learn more about stacking. Join @Akshat-Oke and the rest of your teammates on https://graphite.dev?utm-source=stack-comment";>https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="11px" height="11px"/> Graphite https://github.com/llvm/llvm-project/pull/111634 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/cdevadas commented: The changes you made in llvm/lib/CodeGen/MIRParser/MIRParser.cpp are not related to this PR. Create a separate NFC patch for it. https://github.com/llvm/llvm-project/pull/111634 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [MIR] Add missing noteNewVirtualRegister callbacks (PR #111634)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/111634
>From 8e7f36627516a76d76ac7bb1d8c756261b6bbc5c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 9 Oct 2024 05:01:22 +
Subject: [PATCH] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast(nullptr));
MRI.setType(Reg, Ty);
+MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
-RegInfo.invalidateLiveness();
+MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
-RegInfo.addLiveIn(Reg, VReg);
+MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
-RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From f4a65dea10cd581aada8cbdf33dae5a66518ddcf Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/7] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 2c84cdac76d027..b23fea33183354 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1716,6 +1716,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..ec09a2803ed09c 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -696,8 +696,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index de9cbe403ab618..6b6750af1d86cb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3851,3 +3851,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 99fa632c0300be..fe3bbe839e9373 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -457,6 +457,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From f9a79de1ee2907baa3673ec504efb687bc4b8576 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/7] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterI
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
Akshat-Oke wrote:
It doesn't take effect here.
Might be better to move it to a separate commit.
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
cdevadas wrote:
This change doesn't make sense to me. What will happen to the regular flow when
it reaches from MRI createVirtualRegister? Isn't duplicating the size?
https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/MachineRegisterInfo.cpp#L166
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [OpenMP][MLIR] Descriptor explicit member map lowering changes (PR #111191)
@@ -2468,51 +2468,45 @@ static int getMapDataMemberIdx(MapInfoData &mapData,
omp::MapInfoOp memberOp) {
return std::distance(mapData.MapClause.begin(), res);
}
-static omp::MapInfoOp getFirstOrLastMappedMemberPtr(omp::MapInfoOp mapInfo,
-bool first) {
- DenseIntElementsAttr indexAttr = mapInfo.getMembersIndexAttr();
-
+static mlir::omp::MapInfoOp
+getFirstOrLastMappedMemberPtr(mlir::omp::MapInfoOp mapInfo, bool first) {
+ mlir::ArrayAttr indexAttr = mapInfo.getMembersIndexAttr();
// Only 1 member has been mapped, we can return it.
if (indexAttr.size() == 1)
-if (auto mapOp =
-dyn_cast(mapInfo.getMembers()[0].getDefiningOp()))
+if (auto mapOp = mlir::dyn_cast(
TIFitis wrote:
Is there a scenario where the definingOp can be anything other than a
MapInfoOp? If not, you can take get rid of the if statement and replace the
`dyn_cast` with a `cast`.
https://github.com/llvm/llvm-project/pull/91
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[llvm-branch-commits] [OpenMP][MLIR] Descriptor explicit member map lowering changes (PR #111191)
@@ -2663,6 +2657,8 @@ static llvm::omp::OpenMPOffloadMappingFlags mapParentWithMembers( auto mapOp = dyn_cast(mapData.MapClause[mapDataIndex]); int firstMemberIdx = getMapDataMemberIdx( mapData, getFirstOrLastMappedMemberPtr(mapOp, true)); +// NOTE/TODO: Should perhaps use OriginalValue here instead of Pointers to TIFitis wrote: Is it possible to determine this definitively in this patch itself? https://github.com/llvm/llvm-project/pull/91 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [OpenMP][MLIR] Descriptor explicit member map lowering changes (PR #111191)
https://github.com/TIFitis approved this pull request. Added couple of nit comments. Otherwise happy with the patch. Thank you for the amazing work :) https://github.com/llvm/llvm-project/pull/91 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [OpenMP][MLIR] Descriptor explicit member map lowering changes (PR #111191)
https://github.com/TIFitis edited https://github.com/llvm/llvm-project/pull/91 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libc] [libc][math][c23] Add tanhf16 C23 math function (PR #106006)
nickdesaulniers wrote: ping @lntue for review here. https://github.com/llvm/llvm-project/pull/106006 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -49,38 +51,95 @@ using DeclareTargetCapturePair =
// and index data when lowering OpenMP map clauses. Keeps track of the
// placement of the component in the derived type hierarchy it rests within,
// alongside the generated mlir::omp::MapInfoOp for the mapped component.
-struct OmpMapMemberIndicesData {
+//
+// As an example of what the contents of this data structure may be like,
+// when provided the following derived type and map of that type:
+//
+// type :: bottom_layer
+// real(8) :: i2
+// real(4) :: array_i2(10)
+// real(4) :: array_j2(10)
+// end type bottom_layer
+//
+// type :: top_layer
+// real(4) :: i
+// integer(4) :: array_i(10)
+// real(4) :: j
+// type(bottom_layer) :: nested
+// integer, allocatable :: array_j(:)
+// integer(4) :: k
+// end type top_layer
+//
+// type(top_layer) :: top_dtype
+//
+// map(tofrom: top_dtype%nested%i2, top_dtype%k, top_dtype%nested%array_i2)
+//
+// We would end up with an OmpMapParentAndMemberData populated like below:
+//
+// memberPlacementIndices:
+// Vector 1: 3, 0
+// Vector 2: 5
+// Vector 3: 3, 1
+//
+// memberMap:
+// Entry 1: omp.map.info for "top_dtype%nested%i2"
+// Entry 2: omp.map.info for "top_dtype%k"
+// Entry 3: omp.map.info for "top_dtype%nested%array_i2"
+//
+// And this OmpMapParentAndMemberData would be accessed via the parent
+// symbol for top_dtype. Other parent derived type instances that have
+// members mapped would have there own OmpMapParentAndMemberData entry
+// accessed via their own symbol.
+struct OmpMapParentAndMemberData {
ergawy wrote:
Could this be something like this:
```suggestion
struct OmpMapParentAndMemberData {
struct MemberMappingData {
llvm::SmallVector placementIndices;
mlir::omp::MapInfo memberMap;
};
llvm::SmallVector allMembersData;
};
```
The reason I think this is better is that it ties all the mapping data for a
single member in one structure which makes easier to understand what
`OmpMapParentAndMemberData` encapsulates.
https://github.com/llvm/llvm-project/pull/92
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[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -145,11 +146,174 @@ createMapInfoOp(fir::FirOpBuilder &builder,
mlir::Location loc,
builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(mapCaptureType),
builder.getStringAttr(name), builder.getBoolAttr(partialMap));
-
return op;
}
-static int
+omp::ObjectList gatherObjects(omp::Object obj,
+ semantics::SemanticsContext &semaCtx) {
+ omp::ObjectList objList;
+ std::optional baseObj = obj;
+ while (baseObj.has_value()) {
+objList.push_back(baseObj.value());
+baseObj = getBaseObject(baseObj.value(), semaCtx);
+ }
+ return omp::ObjectList{llvm::reverse(objList)};
+}
+
+bool isDuplicateMemberMapInfo(OmpMapParentAndMemberData &parentMembers,
ergawy wrote:
Can this be a method in `OmpMapParentAndMemberData`?
https://github.com/llvm/llvm-project/pull/92
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[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -183,99 +347,69 @@ getComponentObject(std::optional object,
return getComponentObject(baseObj.value(), semaCtx);
}
-static void
-generateMemberPlacementIndices(const Object &object,
- llvm::SmallVectorImpl &indices,
- semantics::SemanticsContext &semaCtx) {
+void generateMemberPlacementIndices(const Object &object,
+llvm::SmallVectorImpl &indices,
+semantics::SemanticsContext &semaCtx) {
+ indices.clear();
auto compObj = getComponentObject(object, semaCtx);
+
while (compObj) {
-indices.push_back(getComponentPlacementInParent(compObj->sym()));
+int64_t index = getComponentPlacementInParent(compObj->sym());
+assert(index >= 0);
+indices.push_back(index);
compObj =
getComponentObject(getBaseObject(compObj.value(), semaCtx), semaCtx);
}
- indices = llvm::SmallVector{llvm::reverse(indices)};
+ indices = llvm::SmallVector{llvm::reverse(indices)};
}
-void addChildIndexAndMapToParent(
-const omp::Object &object,
-std::map> &parentMemberIndices,
-mlir::omp::MapInfoOp &mapOp, semantics::SemanticsContext &semaCtx) {
- std::optional dataRef = ExtractDataRef(object.ref());
- assert(dataRef.has_value() &&
- "DataRef could not be extracted during mapping of derived type "
- "cannot proceed");
- const semantics::Symbol *parentSym = &dataRef->GetFirstSymbol();
- assert(parentSym && "Could not find parent symbol during lower of "
- "a component member in OpenMP map clause");
- llvm::SmallVector indices;
+void addChildIndexAndMapToParent(const omp::Object &object,
+ OmpMapParentAndMemberData
&parentMemberIndices,
+ mlir::omp::MapInfoOp &mapOp,
+ semantics::SemanticsContext &semaCtx) {
+ llvm::SmallVector indices;
generateMemberPlacementIndices(object, indices, semaCtx);
- parentMemberIndices[parentSym].push_back({indices, mapOp});
+ parentMemberIndices.memberPlacementIndices.push_back(indices);
+ parentMemberIndices.memberMap.push_back(mapOp);
}
-static void calculateShapeAndFillIndices(
-llvm::SmallVectorImpl &shape,
-llvm::SmallVectorImpl &memberPlacementData) {
- shape.push_back(memberPlacementData.size());
- size_t largestIndicesSize =
- std::max_element(memberPlacementData.begin(), memberPlacementData.end(),
- [](auto a, auto b) {
- return a.memberPlacementIndices.size() <
-b.memberPlacementIndices.size();
- })
- ->memberPlacementIndices.size();
- shape.push_back(largestIndicesSize);
-
- // DenseElementsAttr expects a rectangular shape for the data, so all
- // index lists have to be of the same length, this emplaces -1 as filler.
- for (auto &v : memberPlacementData) {
-if (v.memberPlacementIndices.size() < largestIndicesSize) {
- auto *prevEnd = v.memberPlacementIndices.end();
- v.memberPlacementIndices.resize(largestIndicesSize);
- std::fill(prevEnd, v.memberPlacementIndices.end(), -1);
-}
+bool isMemberOrParentAllocatableOrPointer(
+const Object &object, semantics::SemanticsContext &semaCtx) {
+ if (semantics::IsAllocatableOrObjectPointer(object.sym()))
+return true;
+
+ auto compObj = getBaseObject(object, semaCtx);
+ while (compObj) {
+if (compObj.has_value() &&
+semantics::IsAllocatableOrObjectPointer(compObj.value().sym()))
ergawy wrote:
```suggestion
if (semantics::IsAllocatableOrObjectPointer(compObj.value().sym()))
```
https://github.com/llvm/llvm-project/pull/92
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[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
https://github.com/ergawy commented: Reviewed `Utils.h/.cpp`, submitting the current state of the review to prevent double-reviews when possible. https://github.com/llvm/llvm-project/pull/92 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -145,11 +146,174 @@ createMapInfoOp(fir::FirOpBuilder &builder, mlir::Location loc, builder.getIntegerAttr(builder.getIntegerType(64, false), mapType), builder.getAttr(mapCaptureType), builder.getStringAttr(name), builder.getBoolAttr(partialMap)); - return op; } -static int +omp::ObjectList gatherObjects(omp::Object obj, ergawy wrote: ```suggestion omp::ObjectList gatherParentObjectsOf(omp::Object derivedTypeMember, ``` https://github.com/llvm/llvm-project/pull/92 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -145,11 +146,174 @@ createMapInfoOp(fir::FirOpBuilder &builder,
mlir::Location loc,
builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(mapCaptureType),
builder.getStringAttr(name), builder.getBoolAttr(partialMap));
-
return op;
}
-static int
+omp::ObjectList gatherObjects(omp::Object obj,
+ semantics::SemanticsContext &semaCtx) {
+ omp::ObjectList objList;
+ std::optional baseObj = obj;
+ while (baseObj.has_value()) {
+objList.push_back(baseObj.value());
+baseObj = getBaseObject(baseObj.value(), semaCtx);
+ }
+ return omp::ObjectList{llvm::reverse(objList)};
+}
+
+bool isDuplicateMemberMapInfo(OmpMapParentAndMemberData &parentMembers,
+ llvm::SmallVectorImpl &memberIndices) {
+ for (auto memberData : parentMembers.memberPlacementIndices)
+if (std::equal(memberIndices.begin(), memberIndices.end(),
+ memberData.begin()))
+ return true;
+ return false;
+}
+
+static void generateArrayIndices(lower::AbstractConverter &converter,
ergawy wrote:
Please add docs with an example.
https://github.com/llvm/llvm-project/pull/92
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[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -49,38 +51,95 @@ using DeclareTargetCapturePair =
// and index data when lowering OpenMP map clauses. Keeps track of the
// placement of the component in the derived type hierarchy it rests within,
// alongside the generated mlir::omp::MapInfoOp for the mapped component.
-struct OmpMapMemberIndicesData {
+//
+// As an example of what the contents of this data structure may be like,
+// when provided the following derived type and map of that type:
+//
+// type :: bottom_layer
+// real(8) :: i2
+// real(4) :: array_i2(10)
+// real(4) :: array_j2(10)
+// end type bottom_layer
+//
+// type :: top_layer
+// real(4) :: i
+// integer(4) :: array_i(10)
+// real(4) :: j
+// type(bottom_layer) :: nested
+// integer, allocatable :: array_j(:)
+// integer(4) :: k
+// end type top_layer
+//
+// type(top_layer) :: top_dtype
+//
+// map(tofrom: top_dtype%nested%i2, top_dtype%k, top_dtype%nested%array_i2)
+//
+// We would end up with an OmpMapParentAndMemberData populated like below:
+//
+// memberPlacementIndices:
+// Vector 1: 3, 0
+// Vector 2: 5
+// Vector 3: 3, 1
+//
+// memberMap:
+// Entry 1: omp.map.info for "top_dtype%nested%i2"
+// Entry 2: omp.map.info for "top_dtype%k"
+// Entry 3: omp.map.info for "top_dtype%nested%array_i2"
+//
+// And this OmpMapParentAndMemberData would be accessed via the parent
+// symbol for top_dtype. Other parent derived type instances that have
+// members mapped would have there own OmpMapParentAndMemberData entry
+// accessed via their own symbol.
+struct OmpMapParentAndMemberData {
// The indices representing the component members placement in its derived
// type parents hierarchy.
- llvm::SmallVector memberPlacementIndices;
+ llvm::SmallVector> memberPlacementIndices;
// Placement of the member in the member vector.
- mlir::omp::MapInfoOp memberMap;
+ llvm::SmallVector memberMap;
};
-mlir::omp::MapInfoOp
-createMapInfoOp(fir::FirOpBuilder &builder, mlir::Location loc,
-mlir::Value baseAddr, mlir::Value varPtrPtr, std::string name,
-mlir::ArrayRef bounds,
-mlir::ArrayRef members,
-mlir::DenseIntElementsAttr membersIndex, uint64_t mapType,
-mlir::omp::VariableCaptureKind mapCaptureType, mlir::Type
retTy,
-bool partialMap = false);
-
-void addChildIndexAndMapToParent(
-const omp::Object &object,
-std::map> &parentMemberIndices,
-mlir::omp::MapInfoOp &mapOp, semantics::SemanticsContext &semaCtx);
+mlir::omp::MapInfoOp createMapInfoOp(
+fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value baseAddr,
+mlir::Value varPtrPtr, std::string name, mlir::ArrayRef
bounds,
+mlir::ArrayRef members, mlir::ArrayAttr membersIndex,
+uint64_t mapType, mlir::omp::VariableCaptureKind mapCaptureType,
+mlir::Type retTy, bool partialMap = false);
+
+void addChildIndexAndMapToParent(const omp::Object &object,
ergawy wrote:
Can we have this as a member method inside `OmpMapParentAndMemberData`?
https://github.com/llvm/llvm-project/pull/92
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[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -183,99 +347,69 @@ getComponentObject(std::optional object,
return getComponentObject(baseObj.value(), semaCtx);
}
-static void
-generateMemberPlacementIndices(const Object &object,
- llvm::SmallVectorImpl &indices,
- semantics::SemanticsContext &semaCtx) {
+void generateMemberPlacementIndices(const Object &object,
+llvm::SmallVectorImpl &indices,
+semantics::SemanticsContext &semaCtx) {
+ indices.clear();
ergawy wrote:
I think it would be better to assert the list is emtpy here.
https://github.com/llvm/llvm-project/pull/92
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[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -0,0 +1,161 @@
+!RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s
+
+!CHECK: %[[ALLOCA:.*]] = fir.alloca
!fir.type<_QFtest_derived_type_allocatable_map_operand_and_block_additionTone_layer{i:f32,scalar:!fir.box>,array_i:!fir.array<10xi32>,j:f32,array_j:!fir.box>>,k:i32}>
{bindc_name = "one_l", uniq_name =
"_QFtest_derived_type_allocatable_map_operand_and_block_additionEone_l"}
+!CHECK: %[[DECLARE:.*]]:2 = hlfir.declare %[[ALLOCA]] {uniq_name =
"_QFtest_derived_type_allocatable_map_operand_and_block_additionEone_l"} :
(!fir.ref>,array_i:!fir.array<10xi32>,j:f32,array_j:!fir.box>>,k:i32}>>)
->
(!fir.ref>,array_i:!fir.array<10xi32>,j:f32,array_j:!fir.box>>,k:i32}>>,
!fir.ref>,array_i:!fir.array<10xi32>,j:f32,array_j:!fir.box>>,k:i32}>>)
+!CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound({{.*}})
upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}})
{stride_in_bytes = true}
+!CHECK: %[[MEMBER_INDEX:.*]] = arith.constant 4 : index
+!CHECK: %[[MEMBER_COORD:.*]] = fir.coordinate_of %[[DECLARE]]#0,
%[[MEMBER_INDEX]] :
(!fir.ref>,array_i:!fir.array<10xi32>,j:f32,array_j:!fir.box>>,k:i32}>>,
index) -> !fir.ref>>>
ergawy wrote:
@agozillon Here is what I meant, nothing fancy, just making sure the test it
more readable by reusing short names for complicated types.
```suggestion
!CHECK: %[[ALLOCA:.*]] = fir.alloca
!fir.type<[[ONE_LAYER_TY:_QFtest_derived_type_allocatable_map_operand_and_block_additionTone_layer{i:f32,scalar:!fir.box>,array_i:!fir.array<10xi32>,j:f32,array_j:!fir.box>>,k:i32}]]>
{bindc_name = "one_l", uniq_name =
"_QFtest_derived_type_allocatable_map_operand_and_block_additionEone_l"}
!CHECK: %[[DECLARE:.*]]:2 = hlfir.declare %[[ALLOCA]] {uniq_name =
"_QFtest_derived_type_allocatable_map_operand_and_block_additionEone_l"} :
(!fir.ref>) ->
(!fir.ref>, !fir.ref>)
!CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}})
extent({{.*}}) stride({{.*}}) start_idx({{.*}}) {stride_in_bytes = true}
!CHECK: %[[MEMBER_INDEX:.*]] = arith.constant 4 : index
!CHECK: %[[MEMBER_COORD:.*]] = fir.coordinate_of %[[DECLARE]]#0,
%[[MEMBER_INDEX]] : (!fir.ref>, index) ->
!fir.ref>>>
```
https://github.com/llvm/llvm-project/pull/92
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[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -183,99 +347,69 @@ getComponentObject(std::optional object,
return getComponentObject(baseObj.value(), semaCtx);
}
-static void
-generateMemberPlacementIndices(const Object &object,
- llvm::SmallVectorImpl &indices,
- semantics::SemanticsContext &semaCtx) {
+void generateMemberPlacementIndices(const Object &object,
+llvm::SmallVectorImpl &indices,
+semantics::SemanticsContext &semaCtx) {
+ indices.clear();
auto compObj = getComponentObject(object, semaCtx);
+
while (compObj) {
-indices.push_back(getComponentPlacementInParent(compObj->sym()));
+int64_t index = getComponentPlacementInParent(compObj->sym());
+assert(index >= 0);
+indices.push_back(index);
compObj =
getComponentObject(getBaseObject(compObj.value(), semaCtx), semaCtx);
}
- indices = llvm::SmallVector{llvm::reverse(indices)};
+ indices = llvm::SmallVector{llvm::reverse(indices)};
}
-void addChildIndexAndMapToParent(
-const omp::Object &object,
-std::map> &parentMemberIndices,
-mlir::omp::MapInfoOp &mapOp, semantics::SemanticsContext &semaCtx) {
- std::optional dataRef = ExtractDataRef(object.ref());
- assert(dataRef.has_value() &&
- "DataRef could not be extracted during mapping of derived type "
- "cannot proceed");
- const semantics::Symbol *parentSym = &dataRef->GetFirstSymbol();
- assert(parentSym && "Could not find parent symbol during lower of "
- "a component member in OpenMP map clause");
- llvm::SmallVector indices;
+void addChildIndexAndMapToParent(const omp::Object &object,
+ OmpMapParentAndMemberData
&parentMemberIndices,
+ mlir::omp::MapInfoOp &mapOp,
+ semantics::SemanticsContext &semaCtx) {
+ llvm::SmallVector indices;
generateMemberPlacementIndices(object, indices, semaCtx);
- parentMemberIndices[parentSym].push_back({indices, mapOp});
+ parentMemberIndices.memberPlacementIndices.push_back(indices);
+ parentMemberIndices.memberMap.push_back(mapOp);
}
-static void calculateShapeAndFillIndices(
-llvm::SmallVectorImpl &shape,
-llvm::SmallVectorImpl &memberPlacementData) {
- shape.push_back(memberPlacementData.size());
- size_t largestIndicesSize =
- std::max_element(memberPlacementData.begin(), memberPlacementData.end(),
- [](auto a, auto b) {
- return a.memberPlacementIndices.size() <
-b.memberPlacementIndices.size();
- })
- ->memberPlacementIndices.size();
- shape.push_back(largestIndicesSize);
-
- // DenseElementsAttr expects a rectangular shape for the data, so all
- // index lists have to be of the same length, this emplaces -1 as filler.
- for (auto &v : memberPlacementData) {
-if (v.memberPlacementIndices.size() < largestIndicesSize) {
- auto *prevEnd = v.memberPlacementIndices.end();
- v.memberPlacementIndices.resize(largestIndicesSize);
- std::fill(prevEnd, v.memberPlacementIndices.end(), -1);
-}
+bool isMemberOrParentAllocatableOrPointer(
+const Object &object, semantics::SemanticsContext &semaCtx) {
+ if (semantics::IsAllocatableOrObjectPointer(object.sym()))
+return true;
+
+ auto compObj = getBaseObject(object, semaCtx);
+ while (compObj) {
+if (compObj.has_value() &&
+semantics::IsAllocatableOrObjectPointer(compObj.value().sym()))
+ return true;
+compObj = getBaseObject(compObj.value(), semaCtx);
}
-}
-static mlir::DenseIntElementsAttr createDenseElementsAttrFromIndices(
-llvm::SmallVectorImpl &memberPlacementData,
-fir::FirOpBuilder &builder) {
- llvm::SmallVector shape;
- calculateShapeAndFillIndices(shape, memberPlacementData);
-
- llvm::SmallVector indicesFlattened =
- std::accumulate(memberPlacementData.begin(), memberPlacementData.end(),
- llvm::SmallVector(),
- [](llvm::SmallVector &x, OmpMapMemberIndicesData y)
{
-x.insert(x.end(), y.memberPlacementIndices.begin(),
- y.memberPlacementIndices.end());
-return x;
- });
-
- return mlir::DenseIntElementsAttr::get(
- mlir::VectorType::get(shape,
-mlir::IntegerType::get(builder.getContext(), 32)),
- indicesFlattened);
+ return false;
}
void insertChildMapInfoIntoParent(
-lower::AbstractConverter &converter,
-std::map> &parentMemberIndices,
+lower::AbstractConverter &converter, semantics::SemanticsContext &semaCtx,
+lower::StatementContext &stmtCtx,
+std::map &parentMemberIndices,
llvm::SmallVectorImpl &mapOperands,
-llvm::SmallVectorImpl &mapSyms,
llvm::SmallVectorImpl *mapSymTypes,
-ll
[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -183,99 +347,69 @@ getComponentObject(std::optional object,
return getComponentObject(baseObj.value(), semaCtx);
}
-static void
-generateMemberPlacementIndices(const Object &object,
- llvm::SmallVectorImpl &indices,
- semantics::SemanticsContext &semaCtx) {
+void generateMemberPlacementIndices(const Object &object,
+llvm::SmallVectorImpl &indices,
ergawy wrote:
Just curious why the change from `int` to `int64_t` in particular?
https://github.com/llvm/llvm-project/pull/92
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[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
https://github.com/ergawy edited https://github.com/llvm/llvm-project/pull/92 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -145,11 +146,174 @@ createMapInfoOp(fir::FirOpBuilder &builder,
mlir::Location loc,
builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(mapCaptureType),
builder.getStringAttr(name), builder.getBoolAttr(partialMap));
-
return op;
}
-static int
+omp::ObjectList gatherObjects(omp::Object obj,
+ semantics::SemanticsContext &semaCtx) {
+ omp::ObjectList objList;
+ std::optional baseObj = obj;
+ while (baseObj.has_value()) {
+objList.push_back(baseObj.value());
+baseObj = getBaseObject(baseObj.value(), semaCtx);
+ }
+ return omp::ObjectList{llvm::reverse(objList)};
+}
+
+bool isDuplicateMemberMapInfo(OmpMapParentAndMemberData &parentMembers,
+ llvm::SmallVectorImpl &memberIndices) {
+ for (auto memberData : parentMembers.memberPlacementIndices)
+if (std::equal(memberIndices.begin(), memberIndices.end(),
+ memberData.begin()))
+ return true;
+ return false;
+}
+
+static void generateArrayIndices(lower::AbstractConverter &converter,
+ fir::FirOpBuilder &firOpBuilder,
+ lower::StatementContext &stmtCtx,
+ mlir::Location clauseLocation,
+ llvm::SmallVectorImpl &indices,
+ omp::Object object) {
+ if (auto maybeRef = evaluate::ExtractDataRef(*object.ref())) {
+evaluate::DataRef ref = *maybeRef;
+if (auto *arr = std::get_if(&ref.u)) {
+ for (auto v : arr->subscript()) {
+if (std::holds_alternative(v.u)) {
+ llvm_unreachable("Triplet indexing in map clause is unsupported");
+} else {
+ auto expr =
+ std::get(v.u);
+ mlir::Value subscript = fir::getBase(
+ converter.genExprValue(toEvExpr(expr.value()), stmtCtx));
+ mlir::Value one = firOpBuilder.createIntegerConstant(
+ clauseLocation, firOpBuilder.getIndexType(), 1);
+ subscript = firOpBuilder.createConvert(
+ clauseLocation, firOpBuilder.getIndexType(), subscript);
+ indices.push_back(firOpBuilder.create(
+ clauseLocation, subscript, one));
+}
+ }
+}
+ }
+}
+
+// When mapping members of derived types, there is a chance that one of the
+// members along the way to a mapped member is an descriptor. In which case
+// we have to make sure we generate a map for those along the way otherwise
+// we will be missing a chunk of data required to actually map the member
+// type to device. This function effectively generates these maps and the
+// appropriate data accesses required to generate these maps. It will avoid
+// creating duplicate maps, as duplicates are just as bad as unmapped
+// descriptor data in a lot of cases for the runtime (and unnecessary
+// data movement should be avoided where possible)
+mlir::Value createParentSymAndGenIntermediateMaps(
ergawy wrote:
It is difficult for me to understand what this function does. Can you please
document the paramemters (the ones specific to the function, no need to
document `converter` and other usual parameters.
Can you also add some pseudo-MLIR guiding examples to the comments to help
clarify the behavior of the function?
https://github.com/llvm/llvm-project/pull/92
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[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -145,11 +146,174 @@ createMapInfoOp(fir::FirOpBuilder &builder,
mlir::Location loc,
builder.getIntegerAttr(builder.getIntegerType(64, false), mapType),
builder.getAttr(mapCaptureType),
builder.getStringAttr(name), builder.getBoolAttr(partialMap));
-
return op;
}
-static int
+omp::ObjectList gatherObjects(omp::Object obj,
+ semantics::SemanticsContext &semaCtx) {
+ omp::ObjectList objList;
+ std::optional baseObj = obj;
+ while (baseObj.has_value()) {
+objList.push_back(baseObj.value());
+baseObj = getBaseObject(baseObj.value(), semaCtx);
+ }
+ return omp::ObjectList{llvm::reverse(objList)};
+}
+
+bool isDuplicateMemberMapInfo(OmpMapParentAndMemberData &parentMembers,
+ llvm::SmallVectorImpl &memberIndices) {
+ for (auto memberData : parentMembers.memberPlacementIndices)
+if (std::equal(memberIndices.begin(), memberIndices.end(),
+ memberData.begin()))
+ return true;
+ return false;
+}
+
+static void generateArrayIndices(lower::AbstractConverter &converter,
+ fir::FirOpBuilder &firOpBuilder,
+ lower::StatementContext &stmtCtx,
+ mlir::Location clauseLocation,
+ llvm::SmallVectorImpl &indices,
+ omp::Object object) {
+ if (auto maybeRef = evaluate::ExtractDataRef(*object.ref())) {
+evaluate::DataRef ref = *maybeRef;
+if (auto *arr = std::get_if(&ref.u)) {
+ for (auto v : arr->subscript()) {
+if (std::holds_alternative(v.u)) {
+ llvm_unreachable("Triplet indexing in map clause is unsupported");
+} else {
+ auto expr =
+ std::get(v.u);
+ mlir::Value subscript = fir::getBase(
+ converter.genExprValue(toEvExpr(expr.value()), stmtCtx));
+ mlir::Value one = firOpBuilder.createIntegerConstant(
+ clauseLocation, firOpBuilder.getIndexType(), 1);
+ subscript = firOpBuilder.createConvert(
+ clauseLocation, firOpBuilder.getIndexType(), subscript);
+ indices.push_back(firOpBuilder.create(
+ clauseLocation, subscript, one));
+}
+ }
+}
+ }
+}
+
+// When mapping members of derived types, there is a chance that one of the
+// members along the way to a mapped member is an descriptor. In which case
+// we have to make sure we generate a map for those along the way otherwise
+// we will be missing a chunk of data required to actually map the member
+// type to device. This function effectively generates these maps and the
+// appropriate data accesses required to generate these maps. It will avoid
+// creating duplicate maps, as duplicates are just as bad as unmapped
+// descriptor data in a lot of cases for the runtime (and unnecessary
+// data movement should be avoided where possible)
+mlir::Value createParentSymAndGenIntermediateMaps(
+mlir::Location clauseLocation, lower::AbstractConverter &converter,
+semantics::SemanticsContext &semaCtx, lower::StatementContext &stmtCtx,
+omp::ObjectList &objectList, llvm::SmallVector &indices,
+OmpMapParentAndMemberData &parentMemberIndices, std::string asFortran,
+llvm::omp::OpenMPOffloadMappingFlags mapTypeBits) {
+
+ auto arrayExprWithSubscript = [](omp::Object obj) {
+if (auto maybeRef = evaluate::ExtractDataRef(*obj.ref())) {
+ evaluate::DataRef ref = *maybeRef;
+ if (auto *arr = std::get_if(&ref.u))
+return !arr->subscript().empty();
+}
+return false;
+ };
+
+ fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder();
+ lower::AddrAndBoundsInfo parentBaseAddr = lower::getDataOperandBaseAddr(
+ converter, firOpBuilder, *objectList[0].sym(), clauseLocation);
+ mlir::Value curValue = parentBaseAddr.addr;
+
+ // Iterate over all objects in the objectList, this should consist of all
+ // record types between the parent and the member being mapped (including
+ // the parent). The object list may also contain array objects as well,
+ // this can occur when specifying bounds or a specific element access
+ // within a member map, we skip these.
+ size_t currentIndex = 0;
+ for (size_t i = 0; i < objectList.size(); ++i) {
ergawy wrote:
We can use a range-based loop here.
https://github.com/llvm/llvm-project/pull/92
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[llvm-branch-commits] [clang] [clang-format] Handle template closer followed by empty paretheses (PR #111245)
https://github.com/kadircet approved this pull request. https://github.com/llvm/llvm-project/pull/111245 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [llvm] [Flang] Move runtime library files to FortranRuntime. NFC (PR #110298)
https://github.com/tblah approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/110298 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] [llvm] [Flang] Move runtime library files to FortranRuntime. NFC (PR #110298)
@@ -1,15 +0,0 @@ -if (FLANG_CUF_RUNTIME) Meinersbur wrote: File has been moved to FortranRuntime/unittests/Runtime/CUDA/CMakeLists.txt (https://github.com/llvm/llvm-project/pull/110298/files/8b984fea71966e325e8e1306ab1da34be47ff746#diff-c6d68be4180e8ba3884bdd150b807e61c7b058d3a8a15683c916634b8e3dbca7). A copyright header has been added, which is apparently enough of a change that GitHub doesn't recognize the rename. https://github.com/llvm/llvm-project/pull/110298 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back(SmallString<8>("WWM_REG"));
+ }
Akshat-Oke wrote:
Should I change this to a const char* instead?
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back(SmallString<8>("WWM_REG"));
+ }
arsenm wrote:
I expect only literals, so could use StringRef or StringLiteral
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] AMDGPU: Custom expand flat cmpxchg which may access private (PR #109410)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109410
>From b695265d5a72bf3c6ebe137df4d730fb92df08c5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 14 Aug 2024 13:57:14 +0400
Subject: [PATCH 1/2] AMDGPU: Custom expand flat cmpxchg which may access
private
64-bit flat cmpxchg instructions do not work correctly for scratch
addresses, and need to be expanded as non-atomic.
Allow custom expansion of cmpxchg in AtomicExpand, as is
already the case for atomicrmw.
---
llvm/include/llvm/CodeGen/TargetLowering.h|5 +
.../llvm/Transforms/Utils/LowerAtomic.h |7 +
llvm/lib/CodeGen/AtomicExpandPass.cpp |4 +
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 146 ++-
llvm/lib/Target/AMDGPU/SIISelLowering.h |3 +
llvm/lib/Transforms/Utils/LowerAtomic.cpp | 21 +-
llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll | 1019 +++--
...expand-atomicrmw-flat-noalias-addrspace.ll |6 +-
...expand-atomicrmw-integer-ops-0-to-add-0.ll |6 +-
.../expand-cmpxchg-flat-maybe-private.ll | 104 +-
10 files changed, 1157 insertions(+), 164 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index 4c76592c42e1eb..a4be39d43e38e7 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -2204,6 +2204,11 @@ class TargetLoweringBase {
"Generic atomicrmw expansion unimplemented on this target");
}
+ /// Perform a cmpxchg expansion using a target-specific method.
+ virtual void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const {
+llvm_unreachable("Generic cmpxchg expansion unimplemented on this target");
+ }
+
/// Perform a bit test atomicrmw using a target-specific intrinsic. This
/// represents the combined bit test intrinsic which will be lowered at a
late
/// stage by the backend.
diff --git a/llvm/include/llvm/Transforms/Utils/LowerAtomic.h
b/llvm/include/llvm/Transforms/Utils/LowerAtomic.h
index b25b281667f9cb..295c2bd2b4b47e 100644
--- a/llvm/include/llvm/Transforms/Utils/LowerAtomic.h
+++ b/llvm/include/llvm/Transforms/Utils/LowerAtomic.h
@@ -23,6 +23,13 @@ class IRBuilderBase;
/// Convert the given Cmpxchg into primitive load and compare.
bool lowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI);
+/// Emit IR to implement the given cmpxchg operation on values in registers,
+/// returning the new value.
+std::pair buildAtomicCmpXchgValue(IRBuilderBase &Builder,
+Value *Ptr, Value *Cmp,
+Value *Val,
+Align Alignment);
+
/// Convert the given RMWI into primitive load and stores,
/// assuming that doing so is legal. Return true if the lowering
/// succeeds.
diff --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp
b/llvm/lib/CodeGen/AtomicExpandPass.cpp
index b5eca44cb611a3..71e0fd2b7167a2 100644
--- a/llvm/lib/CodeGen/AtomicExpandPass.cpp
+++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp
@@ -1672,6 +1672,10 @@ bool
AtomicExpandImpl::tryExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) {
return true;
case TargetLoweringBase::AtomicExpansionKind::NotAtomic:
return lowerAtomicCmpXchgInst(CI);
+ case TargetLoweringBase::AtomicExpansionKind::Expand: {
+TLI->emitExpandAtomicCmpXchg(CI);
+return true;
+ }
}
}
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 5e72c1bb82be63..9d1e807da1b233 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -16588,9 +16588,21 @@
SITargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
TargetLowering::AtomicExpansionKind
SITargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CmpX) const
{
- return CmpX->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS
- ? AtomicExpansionKind::NotAtomic
- : AtomicExpansionKind::None;
+ unsigned AddrSpace = CmpX->getPointerAddressSpace();
+ if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS)
+return AtomicExpansionKind::NotAtomic;
+
+ if (AddrSpace != AMDGPUAS::FLAT_ADDRESS || !flatInstrMayAccessPrivate(CmpX))
+return AtomicExpansionKind::None;
+
+ const DataLayout &DL = CmpX->getDataLayout();
+
+ Type *ValTy = CmpX->getNewValOperand()->getType();
+
+ // If a 64-bit flat atomic may alias private, we need to avoid using the
+ // atomic in the private case.
+ return DL.getTypeSizeInBits(ValTy) == 64 ? AtomicExpansionKind::Expand
+ : AtomicExpansionKind::None;
}
const TargetRegisterClass *
@@ -16754,40 +16766,8 @@ bool SITargetLowering::checkForPhysRegDependency(
return false;
}
-void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
- AtomicRMWInst::BinOp Op = AI->getOperation();
-
- if (Op == AtomicRMWInst::Sub || Op ==
[llvm-branch-commits] [llvm] AMDGPU: Add baseline tests for cmpxchg custom expansion (PR #109408)
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/109408
>From fe3d55c18a74cc418315f7b04ae8390a638e2efd Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Thu, 12 Sep 2024 12:44:04 +0400
Subject: [PATCH] AMDGPU: Add baseline tests for cmpxchg custom expansion
We need a non-atomic path if flat may access private.
---
.../AMDGPU/flat_atomics_i64_noprivate.ll | 34 +--
.../AtomicExpand/AMDGPU/expand-atomic-mmra.ll | 12 +-
...and-atomic-rmw-fadd-flat-specialization.ll | 4 +-
...expand-atomicrmw-flat-noalias-addrspace.ll | 149 -
.../expand-cmpxchg-flat-maybe-private.ll | 208 ++
5 files changed, 382 insertions(+), 25 deletions(-)
create mode 100644
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-cmpxchg-flat-maybe-private.ll
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
index e73841e0987800..4072b36e96cf40 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
@@ -5005,7 +5005,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_offset(ptr
%out, i64 %in, i64 %old
; GFX12-NEXT:s_endpgm
entry:
%gep = getelementptr i64, ptr %out, i64 4
- %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst
+ %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst, !noalias.addrspace !0
ret void
}
@@ -5061,7 +5061,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(ptr
%out, i64 %in, i64 %ol
; GFX12-NEXT:s_endpgm
entry:
%gep = getelementptr i64, ptr %out, i64 9000
- %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst
+ %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst, !noalias.addrspace !0
ret void
}
@@ -5121,7 +5121,7 @@ define amdgpu_kernel void
@atomic_cmpxchg_i64_ret_offset(ptr %out, ptr %out2, i6
; GFX12-NEXT:s_endpgm
entry:
%gep = getelementptr i64, ptr %out, i64 4
- %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst
+ %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst, !noalias.addrspace !0
%extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, ptr %out2
ret void
@@ -5184,7 +5184,7 @@ define amdgpu_kernel void
@atomic_cmpxchg_i64_addr64_offset(ptr %out, i64 %in, i
entry:
%ptr = getelementptr i64, ptr %out, i64 %index
%gep = getelementptr i64, ptr %ptr, i64 4
- %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst
+ %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst, !noalias.addrspace !0
ret void
}
@@ -5257,7 +5257,7 @@ define amdgpu_kernel void
@atomic_cmpxchg_i64_ret_addr64_offset(ptr %out, ptr %o
entry:
%ptr = getelementptr i64, ptr %out, i64 %index
%gep = getelementptr i64, ptr %ptr, i64 4
- %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst
+ %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst, !noalias.addrspace !0
%extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, ptr %out2
ret void
@@ -5310,7 +5310,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64(ptr %out,
i64 %in, i64 %old) {
; GFX12-NEXT:global_inv scope:SCOPE_DEV
; GFX12-NEXT:s_endpgm
entry:
- %val = cmpxchg volatile ptr %out, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst
+ %val = cmpxchg volatile ptr %out, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst, !noalias.addrspace !0
ret void
}
@@ -5365,7 +5365,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_ret(ptr
%out, ptr %out2, i64 %in,
; GFX12-NEXT:flat_store_b64 v[2:3], v[0:1]
; GFX12-NEXT:s_endpgm
entry:
- %val = cmpxchg volatile ptr %out, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst
+ %val = cmpxchg volatile ptr %out, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst, !noalias.addrspace !0
%extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, ptr %out2
ret void
@@ -5423,7 +5423,7 @@ define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(ptr
%out, i64 %in, i64 %ind
; GFX12-NEXT:s_endpgm
entry:
%ptr = getelementptr i64, ptr %out, i64 %index
- %val = cmpxchg volatile ptr %ptr, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst
+ %val = cmpxchg volatile ptr %ptr, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst, !noalias.addrspace !0
ret void
}
@@ -5491,7 +5491,7 @@ define amdgpu_kernel void
@atomic_cmpxchg_i64_ret_addr64(ptr %out, ptr %out2, i6
; GFX12-NEXT:s_endpgm
entry:
%ptr = getelementptr i64, ptr %out, i64 %index
- %val = cmpxchg volatile ptr %ptr, i64 %old, i64 %in syncscope("agent")
seq_cst seq_cst
+ %val = cmpxchg volatile ptr %ptr, i64 %old, i64 %in syncscope("agent")
seq_cst se
[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -13,19 +13,22 @@ #include "Utils.h" #include "Clauses.h" +#include + +#include #include +#include TIFitis wrote: Are all of the header file changes necessary? Just making sure we only have the minimal set here. https://github.com/llvm/llvm-project/pull/92 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From 1cbc26fe2de38ae4e174aec128b39c899dab9136 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 27 Sep 2024 08:58:39 +
Subject: [PATCH 1/5] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h| 10 ++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 1f2148c2922de9..28578a875c164c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1712,6 +1712,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+}
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+const VRegInfo &Info = *P.second;
+setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 669f98dd865d61..e28c24bf8f8500 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -693,8 +693,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
+VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 9e1c4941dba283..84569b3f11df67 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 409e5418abc8ec..2c3707e119178a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -454,6 +454,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+}
+return {false, 0};
+ }
+
+ SmallVector
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+%2:sgpr_64 = COPY %1
+%1:sgpr_64 = COPY %0
>From 4c26b4f3b1ad8952767625ba949eaa750aec0652 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 4 Oct 2024 06:31:06 +
Subject: [PATCH 2/5] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterI
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back(SmallString<8>("WWM_REG"));
+ }
Akshat-Oke wrote:
Alright, will keep this.
I have to keep the explicit construct since "WWM_REG" is being refused to be
casted to a SmallString (without creating a StringRef explicitly)
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [flang] [llvm] [Flang] Move runtime library files to FortranRuntime. NFC (PR #110298)
@@ -1,15 +0,0 @@ -if (FLANG_CUF_RUNTIME) tblah wrote: why was this file deleted? https://github.com/llvm/llvm-project/pull/110298 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [NFC] [MTE] simplify tagp logic (PR #110337)
https://github.com/fmayer closed https://github.com/llvm/llvm-project/pull/110337 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -454,6 +454,14 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::optional getVRegFlagValue(StringRef Name) const override {
+return (Name == "WWM_REG") ? AMDGPU::VirtRegFlag::WWM_REG
+ : std::optional{};
arsenm wrote:
```suggestion
return Name == "WWM_REG" ? AMDGPU::VirtRegFlag::WWM_REG
: std::optional{};
```
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back(SmallString<8>("WWM_REG"));
+ }
Akshat-Oke wrote:
Got it
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [flang] [llvm] [Flang] Move runtime library files to FortranRuntime. NFC (PR #110298)
https://github.com/klausler commented: This is a gigantic change and I don't understand why it's being made. Why is so much code moving out of flang/ ? https://github.com/llvm/llvm-project/pull/110298 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] release/19.x: [clang-tidy] Avoid capturing a local variable in a static lambda in UseRangesCheck (#111282) (PR #111318)
https://github.com/hokein approved this pull request. https://github.com/llvm/llvm-project/pull/111318 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [Flang][OpenMP] Derived type explicit allocatable member mapping (PR #111192)
@@ -225,32 +359,79 @@ class MapInfoFinalizationPass
fir::FirOpBuilder &builder,
mlir::Operation *target) {
auto mapClauseOwner =
-llvm::dyn_cast(target);
+llvm::dyn_cast_if_present(
+target);
+// TargetDataOp is technically a MapClauseOwningOpInterface, so we
+// do not need to explicitly check for the extra cases here for use_device
+// addr/ptr
if (!mapClauseOwner)
return;
-llvm::SmallVector newMapOps;
-mlir::OperandRange mapVarsArr = mapClauseOwner.getMapVars();
-auto targetOp = llvm::dyn_cast(target);
-
-for (size_t i = 0; i < mapVarsArr.size(); ++i) {
- if (mapVarsArr[i] == op) {
-for (auto [j, mapMember] : llvm::enumerate(op.getMembers())) {
- newMapOps.push_back(mapMember);
- // for TargetOp's which have IsolatedFromAbove we must align the
- // new additional map operand with an appropriate BlockArgument,
- // as the printing and later processing currently requires a 1:1
- // mapping of BlockArgs to MapInfoOp's at the same placement in
- // each array (BlockArgs and MapVars).
- if (targetOp) {
-targetOp.getRegion().insertArgument(i + j, mapMember.getType(),
-targetOp->getLoc());
+auto addOperands = [&](mlir::OperandRange &mapVarsArr,
+ mlir::MutableOperandRange &mutableOpRange,
+ auto directiveOp) {
+ llvm::SmallVector newMapOps;
+ for (size_t i = 0; i < mapVarsArr.size(); ++i) {
+if (mapVarsArr[i] == op) {
+ for (auto [j, mapMember] : llvm::enumerate(op.getMembers())) {
+newMapOps.push_back(mapMember);
+// for TargetOp's which have IsolatedFromAbove we must align the
+// new additional map operand with an appropriate BlockArgument,
+// as the printing and later processing currently requires a 1:1
+// mapping of BlockArgs to MapInfoOp's at the same placement in
+// each array (BlockArgs and MapVars).
+if (directiveOp) {
+ directiveOp.getRegion().insertArgument(i + j,
mapMember.getType(),
skatrak wrote:
This probably needs rewriting based on the `BlockArgOpenMPOpInterface`, since
this index-based approach easily breaks if other entry block
argument-generating clauses are introduced before `map` (such as
`in_reduction`). This may be a helpful reference:
https://github.com/llvm/llvm-project/blob/db1a76206902e6926464e30cc47249e217405dab/flang/lib/Lower/OpenMP/OpenMP.cpp#L1010-L1014
https://github.com/llvm/llvm-project/pull/92
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -684,8 +684,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
-if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+VRegFlags.grow(Reg);
arsenm wrote:
You changed this though?
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -3839,3 +3839,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector> RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+RegFlags.push_back(SmallString<8>("WWM_REG"));
+ }
arsenm wrote:
```suggestion
if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG))
RegFlags.push_back("WWM_REG");
```
I would hope construct from literal works fine
https://github.com/llvm/llvm-project/pull/110229
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[llvm-branch-commits] [llvm] [AMDGPU] Serialize WWM_REG vreg flag (PR #110229)
@@ -454,6 +454,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::optional getVRegFlagValue(StringRef Name) const override {
+if (Name == "WWM_REG") {
+ return AMDGPU::VirtRegFlag::WWM_REG;
+}
+return {};
arsenm wrote:
```suggestion
return Name == "WWM_REG" ? AMDGPU::VirtRegFlag::WWM_REG : {};
```
https://github.com/llvm/llvm-project/pull/110229
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