[llvm-branch-commits] [clang-tools-extra] [clangd] Add clangd 18 release notes (PR #84436)

[kadir çetinkaya via llvm-branch-commits]

https://github.com/kadircet approved this pull request.

thanks a lot for doing this @HighCommander4 !

https://github.com/llvm/llvm-project/pull/84436
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[llvm-branch-commits] [clang-tools-extra] [clangd] Add clangd 18 release notes (PR #84436)

[kadir çetinkaya via llvm-branch-commits]

https://github.com/kadircet edited 
https://github.com/llvm/llvm-project/pull/84436
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[llvm-branch-commits] [clang-tools-extra] [clangd] Add clangd 18 release notes (PR #84436)

[kadir çetinkaya via llvm-branch-commits]

@@ -51,21 +51,40 @@ Improvements to clangd
 Inlay hints
 ^^^
 
+- Type hints
+* Improved heuristics for showing sugared vs. desguared types
+* Some hints which provide no information (e.g. ) are 
now omitted
+- Parameter hints
+* Parameter hints are now shown for calls through function pointers
+* Parameter hints are now shown for calls to a class's ``operator()``
+* No longer show bogus parameter hints for some builtins like 
``__builtin_dump_struct``
+
 Diagnostics
 ^^^
 
-Semantic Highlighting
-^
+- Improved quality of include-cleaner diagnostics (missing and unused includes)

kadircet wrote:

i'd move this one into include-cleaner release notes (I am also happy to do 
that myself), a more detailed version could look like:

- Support for `--only-headers` flag to limit analysis to headers matching a 
regex
- Recognizes references through `concept`s
- Builtin headers are not analyzed
- Handling of references through `friend` declarations
- Fixes around handling of IWYU pragmas on stdlib headers
- Improved handling around references to/from template specializations

https://github.com/llvm/llvm-project/pull/84436
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[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

[Wang Pengcheng via llvm-branch-commits]

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/84448

The opcode will be determined by LMUL.



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[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-risc-v

Author: Wang Pengcheng (wangpc-pp)


Changes

The opcode will be determined by LMUL.


---
Full diff: https://github.com/llvm/llvm-project/pull/84448.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+26-26) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+1-1) 


``diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 37a8079dcbf10d..fd1b76cd45cde2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -299,36 +299,36 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
&MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg,
MCRegister SrcReg, bool KillSrc,
-   unsigned Opc, unsigned NF) const {
+   RISCVII::VLMUL LMul, unsigned NF) const 
{
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  RISCVII::VLMUL LMul;
+  unsigned Opc;
   unsigned SubRegIdx;
   unsigned VVOpc, VIOpc;
-  switch (Opc) {
+  switch (LMul) {
   default:
 llvm_unreachable("Impossible LMUL for vector register copy.");
-  case RISCV::VMV1R_V:
-LMul = RISCVII::LMUL_1;
+  case RISCVII::LMUL_1:
+Opc = RISCV::VMV1R_V;
 SubRegIdx = RISCV::sub_vrm1_0;
 VVOpc = RISCV::PseudoVMV_V_V_M1;
 VIOpc = RISCV::PseudoVMV_V_I_M1;
 break;
-  case RISCV::VMV2R_V:
-LMul = RISCVII::LMUL_2;
+  case RISCVII::LMUL_2:
+Opc = RISCV::VMV2R_V;
 SubRegIdx = RISCV::sub_vrm2_0;
 VVOpc = RISCV::PseudoVMV_V_V_M2;
 VIOpc = RISCV::PseudoVMV_V_I_M2;
 break;
-  case RISCV::VMV4R_V:
-LMul = RISCVII::LMUL_4;
+  case RISCVII::LMUL_4:
+Opc = RISCV::VMV4R_V;
 SubRegIdx = RISCV::sub_vrm4_0;
 VVOpc = RISCV::PseudoVMV_V_V_M4;
 VIOpc = RISCV::PseudoVMV_V_I_M4;
 break;
-  case RISCV::VMV8R_V:
+  case RISCVII::LMUL_8:
 assert(NF == 1);
-LMul = RISCVII::LMUL_8;
+Opc = RISCV::VMV8R_V;
 SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
 VVOpc = RISCV::PseudoVMV_V_V_M8;
 VIOpc = RISCV::PseudoVMV_V_I_M8;
@@ -505,87 +505,87 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 
   // VR->VR copies.
   if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V);
+copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1);
 return;
   }
 
   if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V);
+copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2);
 return;
   }
 
   if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V);
+copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4);
 return;
   }
 
   if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV8R_V);
+copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_8);
 return;
   }
 
   if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
+copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
   /*NF=*/2);
 return;
   }
 
   if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
+copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
   /*NF=*/2);
 return;
   }
 
   if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V,
+copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4,
   /*NF=*/2);
 return;
   }
 
   if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
+copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
   /*NF=*/3);
 return;
   }
 
   if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
+copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2,
   /*NF=*/3);
 return;
   }
 
   if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
-copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
+copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1,
   /*NF=*/4);
 return;
   }
 
   if (RISCV::VRN4M2RegClass.contai

[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

[Wang Pengcheng via llvm-branch-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/84448


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[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

[Wang Pengcheng via llvm-branch-commits]

https://github.com/wangpc-pp updated 
https://github.com/llvm/llvm-project/pull/84448


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[llvm-branch-commits] [flang] [flang][CodeGen] Fix use-after-free in BoxedProcedurePass (PR #84376)

[via llvm-branch-commits]

https://github.com/jeanPerier commented:

Thanks for identifying the issue

https://github.com/llvm/llvm-project/pull/84376
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[llvm-branch-commits] [flang] [flang][CodeGen] Fix use-after-free in BoxedProcedurePass (PR #84376)

[via llvm-branch-commits]

@@ -208,7 +208,12 @@ class BoxedProcedurePass
   mlir::IRRewriter rewriter(context);
   BoxprocTypeRewriter typeConverter(mlir::UnknownLoc::get(context));
   mlir::Dialect *firDialect = context->getLoadedDialect("fir");
-  getModule().walk([&](mlir::Operation *op) {
+  llvm::SmallVector operations;
+
+  getModule().walk([&](mlir::Operation *op) { operations.push_back(op); });

jeanPerier wrote:

Are you sure it is invalid to erase IR in the walk? I understand why 
`opIsValid` is needed and that it was bad to go through the region of erased 
ops, but I think a walk in post order is supposed to allow erasing operations:  
https://github.com/llvm/llvm-project/blob/881df557501d339c7a14b16d68e43da5c732b424/mlir/include/mlir/IR/Operation.h#L767

Is there still a sanitizer issue when introducing `opIsValid` without creating 
the `operations` vector?

I am a bit concerned with copying the pointer of all the module operations into 
a SmallVector. On big Fortran applications with hundred of thousands of line in 
one file, the module will contain millions of operations (I doubt this go above 
the ~500 millions element capacity of the SmallVector), but it may be overkill 
for a pass that is not expected to modify a lot of IR (procedure pointers and 
dummy procedures are usually not all over the place).

https://github.com/llvm/llvm-project/pull/84376
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[llvm-branch-commits] [flang] [flang][CodeGen] Fix use-after-free in BoxedProcedurePass (PR #84376)

[via llvm-branch-commits]

https://github.com/jeanPerier edited 
https://github.com/llvm/llvm-project/pull/84376
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[llvm-branch-commits] [clang] [llvm] [LV][LAA] Vectorize math lib calls with mem write-only attribute (PR #78432)

[Paschalis Mpeis via llvm-branch-commits]

https://github.com/paschalis-mpeis converted_to_draft 
https://github.com/llvm/llvm-project/pull/78432
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[llvm-branch-commits] [RISCV][NFC] Refactor copyPhysRegVector (PR #84455)

[Wang Pengcheng via llvm-branch-commits]

https://github.com/wangpc-pp created 
https://github.com/llvm/llvm-project/pull/84455

Reduce some duplications and make it easy to follow.

We can optimize segment copies later.



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[llvm-branch-commits] [RISCV][NFC] Refactor copyPhysRegVector (PR #84455)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-risc-v

Author: Wang Pengcheng (wangpc-pp)


Changes

Reduce some duplications and make it easy to follow.

We can optimize segment copies later.


---
Full diff: https://github.com/llvm/llvm-project/pull/84455.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+75-81) 


``diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp 
b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index fd1b76cd45cde2..7895e87702c711 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -302,71 +302,6 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
&MBB,
RISCVII::VLMUL LMul, unsigned NF) const 
{
   const TargetRegisterInfo *TRI = STI.getRegisterInfo();
 
-  unsigned Opc;
-  unsigned SubRegIdx;
-  unsigned VVOpc, VIOpc;
-  switch (LMul) {
-  default:
-llvm_unreachable("Impossible LMUL for vector register copy.");
-  case RISCVII::LMUL_1:
-Opc = RISCV::VMV1R_V;
-SubRegIdx = RISCV::sub_vrm1_0;
-VVOpc = RISCV::PseudoVMV_V_V_M1;
-VIOpc = RISCV::PseudoVMV_V_I_M1;
-break;
-  case RISCVII::LMUL_2:
-Opc = RISCV::VMV2R_V;
-SubRegIdx = RISCV::sub_vrm2_0;
-VVOpc = RISCV::PseudoVMV_V_V_M2;
-VIOpc = RISCV::PseudoVMV_V_I_M2;
-break;
-  case RISCVII::LMUL_4:
-Opc = RISCV::VMV4R_V;
-SubRegIdx = RISCV::sub_vrm4_0;
-VVOpc = RISCV::PseudoVMV_V_V_M4;
-VIOpc = RISCV::PseudoVMV_V_I_M4;
-break;
-  case RISCVII::LMUL_8:
-assert(NF == 1);
-Opc = RISCV::VMV8R_V;
-SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
-VVOpc = RISCV::PseudoVMV_V_V_M8;
-VIOpc = RISCV::PseudoVMV_V_I_M8;
-break;
-  }
-
-  bool UseVMV_V_V = false;
-  bool UseVMV_V_I = false;
-  MachineBasicBlock::const_iterator DefMBBI;
-  if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
-UseVMV_V_V = true;
-Opc = VVOpc;
-
-if (DefMBBI->getOpcode() == VIOpc) {
-  UseVMV_V_I = true;
-  Opc = VIOpc;
-}
-  }
-
-  if (NF == 1) {
-auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg);
-if (UseVMV_V_V)
-  MIB.addReg(DstReg, RegState::Undef);
-if (UseVMV_V_I)
-  MIB = MIB.add(DefMBBI->getOperand(2));
-else
-  MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc));
-if (UseVMV_V_V) {
-  const MCInstrDesc &Desc = DefMBBI->getDesc();
-  MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-  MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-  MIB.addImm(0);// tu, mu
-  MIB.addReg(RISCV::VL, RegState::Implicit);
-  MIB.addReg(RISCV::VTYPE, RegState::Implicit);
-}
-return;
-  }
-
   int I = 0, End = NF, Incr = 1;
   unsigned SrcEncoding = TRI->getEncodingValue(SrcReg);
   unsigned DstEncoding = TRI->getEncodingValue(DstReg);
@@ -381,23 +316,82 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock 
&MBB,
   }
 
   for (; I != End; I += Incr) {
-auto MIB =
-BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx + 
I));
-if (UseVMV_V_V)
-  MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef);
-if (UseVMV_V_I)
-  MIB = MIB.add(DefMBBI->getOperand(2));
-else
-  MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I),
-   getKillRegState(KillSrc));
-if (UseVMV_V_V) {
-  const MCInstrDesc &Desc = DefMBBI->getDesc();
-  MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-  MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
-  MIB.addImm(0);// tu, mu
-  MIB.addReg(RISCV::VL, RegState::Implicit);
-  MIB.addReg(RISCV::VTYPE, RegState::Implicit);
+auto GetCopyInfo =
+[](RISCVII::VLMUL LMul,unsigned NF) -> std::tuple {
+  unsigned Opc;
+  unsigned SubRegIdx;
+  unsigned VVOpc, VIOpc;
+  switch (LMul) {
+  default:
+llvm_unreachable("Impossible LMUL for vector register copy.");
+  case RISCVII::LMUL_1:
+Opc = RISCV::VMV1R_V;
+SubRegIdx = RISCV::sub_vrm1_0;
+VVOpc = RISCV::PseudoVMV_V_V_M1;
+VIOpc = RISCV::PseudoVMV_V_I_M1;
+break;
+  case RISCVII::LMUL_2:
+Opc = RISCV::VMV2R_V;
+SubRegIdx = RISCV::sub_vrm2_0;
+VVOpc = RISCV::PseudoVMV_V_V_M2;
+VIOpc = RISCV::PseudoVMV_V_I_M2;
+break;
+  case RISCVII::LMUL_4:
+Opc = RISCV::VMV4R_V;
+SubRegIdx = RISCV::sub_vrm4_0;
+VVOpc = RISCV::PseudoVMV_V_V_M4;
+VIOpc = RISCV::PseudoVMV_V_I_M4;
+break;
+  case RISCVII::LMUL_8:
+assert(NF == 1);
+Opc = RISCV::VMV8R_V;
+SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0.
+VVOpc = RISCV::PseudoVMV_V_V_M8;
+VIOpc = RISCV::PseudoVMV_V_I_M8;
+break;
+  }
+  return {SubRegIdx, Opc, VVOp

[llvm-branch-commits] [RISCV][NFC] Refactor copyPhysRegVector (PR #84455)

[Wang Pengcheng via llvm-branch-commits]

https://github.com/wangpc-pp converted_to_draft 
https://github.com/llvm/llvm-project/pull/84455
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[llvm-branch-commits] [RISCV] Pass LMUL to copyPhysRegVector (PR #84448)

[Luke Lau via llvm-branch-commits]

https://github.com/lukel97 commented:

Is this NFC?

https://github.com/llvm/llvm-project/pull/84448
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[llvm-branch-commits] [llvm] release 18.x: [ARM] Switch to LiveRegUnits to fix r7 register allocation bug (PR #84475)

[via llvm-branch-commits]

https://github.com/AtariDreams created 
https://github.com/llvm/llvm-project/pull/84475

This fixes a register allocation bug, because while r7 was marked as allowed to 
be used, LivePhysRegs always reported it as unavailable because it is reserved, 
despite this being an exception to the rule.

>From 99f0edf206aa40253db5feb3ea7d37d59ad715b5 Mon Sep 17 00:00:00 2001
From: Rose 
Date: Fri, 8 Mar 2024 07:59:02 -0500
Subject: [PATCH] [ARM] Switch to LiveRegUnits to fix r7 register allocation
 bug

This fixes a register allocation bug, because while r7 was marked as allowed to 
be used, LivePhysRegs always reported it as unavailable because it is reserved, 
despite this being an exception to the rule.
---
 llvm/lib/Target/ARM/Thumb1FrameLowering.cpp |  6 +++---
 llvm/test/CodeGen/Thumb/PR35481.ll  | 14 ++
 2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp 
b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
index 0f4ece64bff532..a8cf036f363cdd 100644
--- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
+++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
@@ -612,11 +612,11 @@ bool Thumb1FrameLowering::needPopSpecialFixUp(const 
MachineFunction &MF) const {
 
 static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
  const BitVector &PopFriendly,
- const LivePhysRegs &UsedRegs, unsigned 
&PopReg,
+ const LiveRegUnits &UsedRegs, unsigned 
&PopReg,
  unsigned &TmpReg, MachineRegisterInfo &MRI) {
   PopReg = TmpReg = 0;
   for (auto Reg : GPRsNoLRSP.set_bits()) {
-if (UsedRegs.available(MRI, Reg)) {
+if (UsedRegs.available(Reg)) {
   // Remember the first pop-friendly register and exit.
   if (PopFriendly.test(Reg)) {
 PopReg = Reg;
@@ -684,7 +684,7 @@ bool 
Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
   // Look for a temporary register to use.
   // First, compute the liveness information.
   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
-  LivePhysRegs UsedRegs(TRI);
+  LiveRegUnits UsedRegs(TRI);
   UsedRegs.addLiveOuts(MBB);
   // The semantic of pristines changed recently and now,
   // the callee-saved registers that are touched in the function
diff --git a/llvm/test/CodeGen/Thumb/PR35481.ll 
b/llvm/test/CodeGen/Thumb/PR35481.ll
index ad3215ecb94952..e48d1547782caf 100644
--- a/llvm/test/CodeGen/Thumb/PR35481.ll
+++ b/llvm/test/CodeGen/Thumb/PR35481.ll
@@ -18,11 +18,10 @@ define <4 x i32> @f() local_unnamed_addr #0 {
 ; CHECK-V4T-NEXT:movs r2, #3
 ; CHECK-V4T-NEXT:movs r3, #4
 ; CHECK-V4T-NEXT:bl g
+; CHECK-V4T-NEXT:ldr r7, [sp, #4]
+; CHECK-V4T-NEXT:mov lr, r7
 ; CHECK-V4T-NEXT:pop {r7}
-; CHECK-V4T-NEXT:mov r12, r0
-; CHECK-V4T-NEXT:pop {r0}
-; CHECK-V4T-NEXT:mov lr, r0
-; CHECK-V4T-NEXT:mov r0, r12
+; CHECK-V4T-NEXT:add sp, #4
 ; CHECK-V4T-NEXT:bx lr
 ;
 ; CHECK-V8M-LABEL: f:
@@ -36,11 +35,10 @@ define <4 x i32> @f() local_unnamed_addr #0 {
 ; CHECK-V8M-NEXT:movs r1, #2
 ; CHECK-V8M-NEXT:movs r2, #3
 ; CHECK-V8M-NEXT:movs r3, #4
+; CHECK-V8M-NEXT:ldr r7, [sp, #4]
+; CHECK-V8M-NEXT:mov lr, r7
 ; CHECK-V8M-NEXT:pop {r7}
-; CHECK-V8M-NEXT:mov r12, r0
-; CHECK-V8M-NEXT:pop {r0}
-; CHECK-V8M-NEXT:mov lr, r0
-; CHECK-V8M-NEXT:mov r0, r12
+; CHECK-V8M-NEXT:add sp, #4
 ; CHECK-V8M-NEXT:b g
 entry:
   %call = tail call i32 @h(i32 1)

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[llvm-branch-commits] [llvm] release/18.x: [ARM] Switch to LiveRegUnits to fix r7 register allocation bug (PR #84475)

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https://github.com/AtariDreams edited 
https://github.com/llvm/llvm-project/pull/84475
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[llvm-branch-commits] [libcxx] release/18.x: [libc++][modules] Fixes naming inconsistency. (#83036) (PR #83156)

[Ben Boeckel via llvm-branch-commits]

mathstuf wrote:

This missed 18.1.0 :( .

https://github.com/llvm/llvm-project/pull/83156
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[llvm-branch-commits] [llvm] release/18.x: [ARM] Switch to LiveRegUnits to fix r7 register allocation bug (PR #84475)

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llvmbot wrote:




@llvm/pr-subscribers-backend-arm

Author: AtariDreams (AtariDreams)


Changes

This fixes a register allocation bug, because while r7 was marked as allowed to 
be used, LivePhysRegs always reported it as unavailable because it is reserved, 
despite this being an exception to the rule.

---
Full diff: https://github.com/llvm/llvm-project/pull/84475.diff


2 Files Affected:

- (modified) llvm/lib/Target/ARM/Thumb1FrameLowering.cpp (+3-3) 
- (modified) llvm/test/CodeGen/Thumb/PR35481.ll (+6-8) 


``diff
diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp 
b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
index 0f4ece64bff532..a8cf036f363cdd 100644
--- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
+++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
@@ -612,11 +612,11 @@ bool Thumb1FrameLowering::needPopSpecialFixUp(const 
MachineFunction &MF) const {
 
 static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
  const BitVector &PopFriendly,
- const LivePhysRegs &UsedRegs, unsigned 
&PopReg,
+ const LiveRegUnits &UsedRegs, unsigned 
&PopReg,
  unsigned &TmpReg, MachineRegisterInfo &MRI) {
   PopReg = TmpReg = 0;
   for (auto Reg : GPRsNoLRSP.set_bits()) {
-if (UsedRegs.available(MRI, Reg)) {
+if (UsedRegs.available(Reg)) {
   // Remember the first pop-friendly register and exit.
   if (PopFriendly.test(Reg)) {
 PopReg = Reg;
@@ -684,7 +684,7 @@ bool 
Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
   // Look for a temporary register to use.
   // First, compute the liveness information.
   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
-  LivePhysRegs UsedRegs(TRI);
+  LiveRegUnits UsedRegs(TRI);
   UsedRegs.addLiveOuts(MBB);
   // The semantic of pristines changed recently and now,
   // the callee-saved registers that are touched in the function
diff --git a/llvm/test/CodeGen/Thumb/PR35481.ll 
b/llvm/test/CodeGen/Thumb/PR35481.ll
index ad3215ecb94952..e48d1547782caf 100644
--- a/llvm/test/CodeGen/Thumb/PR35481.ll
+++ b/llvm/test/CodeGen/Thumb/PR35481.ll
@@ -18,11 +18,10 @@ define <4 x i32> @f() local_unnamed_addr #0 {
 ; CHECK-V4T-NEXT:movs r2, #3
 ; CHECK-V4T-NEXT:movs r3, #4
 ; CHECK-V4T-NEXT:bl g
+; CHECK-V4T-NEXT:ldr r7, [sp, #4]
+; CHECK-V4T-NEXT:mov lr, r7
 ; CHECK-V4T-NEXT:pop {r7}
-; CHECK-V4T-NEXT:mov r12, r0
-; CHECK-V4T-NEXT:pop {r0}
-; CHECK-V4T-NEXT:mov lr, r0
-; CHECK-V4T-NEXT:mov r0, r12
+; CHECK-V4T-NEXT:add sp, #4
 ; CHECK-V4T-NEXT:bx lr
 ;
 ; CHECK-V8M-LABEL: f:
@@ -36,11 +35,10 @@ define <4 x i32> @f() local_unnamed_addr #0 {
 ; CHECK-V8M-NEXT:movs r1, #2
 ; CHECK-V8M-NEXT:movs r2, #3
 ; CHECK-V8M-NEXT:movs r3, #4
+; CHECK-V8M-NEXT:ldr r7, [sp, #4]
+; CHECK-V8M-NEXT:mov lr, r7
 ; CHECK-V8M-NEXT:pop {r7}
-; CHECK-V8M-NEXT:mov r12, r0
-; CHECK-V8M-NEXT:pop {r0}
-; CHECK-V8M-NEXT:mov lr, r0
-; CHECK-V8M-NEXT:mov r0, r12
+; CHECK-V8M-NEXT:add sp, #4
 ; CHECK-V8M-NEXT:b g
 entry:
   %call = tail call i32 @h(i32 1)

``




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[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

[via llvm-branch-commits]

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/84491

Backport ff72c83b017b

Requested by: @johnplatts

>From d7a7ea38a011646ad9dc18f9c045e66df7296c39 Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 4 Mar 2024 10:15:43 +0800
Subject: [PATCH] [X86] Add missing subvector_subreg_lowering for BF16 (#83720)

Fixes: #83358
(cherry picked from commit ff72c83b017ba636be13750c7f96cd87fc22c465)
---
 llvm/lib/Target/X86/X86InstrVecCompiler.td|  3 +++
 .../CodeGen/X86/avx512bf16-vl-intrinsics.ll   | 22 +++
 llvm/test/CodeGen/X86/bfloat.ll   |  7 +++---
 3 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrVecCompiler.td 
b/llvm/lib/Target/X86/X86InstrVecCompiler.td
index bbd19cf8d5b25e..461b2badc13134 100644
--- a/llvm/lib/Target/X86/X86InstrVecCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrVecCompiler.td
@@ -83,6 +83,7 @@ defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
+defm : subvector_subreg_lowering;
 
 // A 128-bit subvector extract from the first 512-bit vector position is a
 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
@@ -95,6 +96,7 @@ defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
+defm : subvector_subreg_lowering;
 
 // A 128-bit subvector extract from the first 512-bit vector position is a
 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
@@ -107,6 +109,7 @@ defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
+defm : subvector_subreg_lowering;
 
 
 // If we're inserting into an all zeros vector, just use a plain move which
diff --git a/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll 
b/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
index 0826faa1071b01..482713e12d15c7 100644
--- a/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
@@ -381,3 +381,25 @@ entry:
   %1 = shufflevector <8 x bfloat> %0, <8 x bfloat> undef, <16 x i32> 
zeroinitializer
   ret <16 x bfloat> %1
 }
+
+define <16 x i32> @pr83358() {
+; X86-LABEL: pr83358:
+; X86:   # %bb.0:
+; X86-NEXT:vcvtneps2bf16y {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # encoding: 
[0x62,0xf2,0x7e,0x28,0x72,0x05,A,A,A,A]
+; X86-NEXT:# fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: 
FK_Data_4
+; X86-NEXT:vshufi64x2 $0, %zmm0, %zmm0, %zmm0 # encoding: 
[0x62,0xf3,0xfd,0x48,0x43,0xc0,0x00]
+; X86-NEXT:# zmm0 = zmm0[0,1,0,1,0,1,0,1]
+; X86-NEXT:retl # encoding: [0xc3]
+;
+; X64-LABEL: pr83358:
+; X64:   # %bb.0:
+; X64-NEXT:vcvtneps2bf16y {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # 
encoding: [0x62,0xf2,0x7e,0x28,0x72,0x05,A,A,A,A]
+; X64-NEXT:# fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: 
reloc_riprel_4byte
+; X64-NEXT:vshufi64x2 $0, %zmm0, %zmm0, %zmm0 # encoding: 
[0x62,0xf3,0xfd,0x48,0x43,0xc0,0x00]
+; X64-NEXT:# zmm0 = zmm0[0,1,0,1,0,1,0,1]
+; X64-NEXT:retq # encoding: [0xc3]
+  %1 = call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> 
)
+  %2 = bitcast <8 x bfloat> %1 to <4 x i32>
+  %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <16 x i32> 
+  ret <16 x i32> %3
+}
diff --git a/llvm/test/CodeGen/X86/bfloat.ll b/llvm/test/CodeGen/X86/bfloat.ll
index f2d3c4fb34199e..0042d477f3b364 100644
--- a/llvm/test/CodeGen/X86/bfloat.ll
+++ b/llvm/test/CodeGen/X86/bfloat.ll
@@ -511,7 +511,7 @@ define void @fold_ext_trunc(ptr %pa, ptr %pc) nounwind {
 define bfloat @fold_ext_trunc2(bfloat %a) nounwind {
 ; X86-LABEL: fold_ext_trunc2:
 ; X86:   # %bb.0:
-; X86-NEXT:vmovsh {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
 ; X86-NEXT:retl
 ;
 ; CHECK-LABEL: fold_ext_trunc2:
@@ -934,8 +934,8 @@ define <8 x bfloat> @addv(<8 x bfloat> %a, <8 x bfloat> %b) 
nounwind {
 define <2 x bfloat> @pr62997(bfloat %a, bfloat %b) {
 ; X86-LABEL: pr62997:
 ; X86:   # %bb.0:
-; X86-NEXT:vmovsh {{[0-9]+}}(%esp), %xmm0
-; X86-NEXT:vmovsh {{[0-9]+}}(%esp), %xmm1
+; X86-NEXT:vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT:vmovsh {{.*#+}} xmm1 = mem[0],zero,zero,zero,zero,zero,zero,zero
 ; X86-NEXT:vpunpcklwd {{.*#+}} xmm0 = 
xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; X86-NEXT:retl
 ;
@@ -2423,7 +2423,6 @@ define <16 x bfloat> @fptrunc_v16f32(<16 x float> %a) 
nounwind {
 ; AVXNC-LABEL: fptrunc_v16f32:
 ; AVXNC:   # %bb.0:
 ; AVXNC-NEXT:{vex} vcvtneps2bf16 %ymm0, %xmm0
-; AVXNC-NEXT:vinsertf128 $0, %xmm0, %ymm0, %ymm0
 ; AVXNC-NEXT:{vex} vcvtneps2bf16 %ymm1, %xmm1
 ; AVXNC-NEXT:vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVXNC-NEXT:retq

___

[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

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https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/84491
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[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

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llvmbot wrote:

@FreddyLeaf What do you think about merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/84491
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[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-x86

Author: None (llvmbot)


Changes

Backport ff72c83b017b

Requested by: @johnplatts

---
Full diff: https://github.com/llvm/llvm-project/pull/84491.diff


3 Files Affected:

- (modified) llvm/lib/Target/X86/X86InstrVecCompiler.td (+3) 
- (modified) llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll (+22) 
- (modified) llvm/test/CodeGen/X86/bfloat.ll (+3-4) 


``diff
diff --git a/llvm/lib/Target/X86/X86InstrVecCompiler.td 
b/llvm/lib/Target/X86/X86InstrVecCompiler.td
index bbd19cf8d5b25e..461b2badc13134 100644
--- a/llvm/lib/Target/X86/X86InstrVecCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrVecCompiler.td
@@ -83,6 +83,7 @@ defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
+defm : subvector_subreg_lowering;
 
 // A 128-bit subvector extract from the first 512-bit vector position is a
 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
@@ -95,6 +96,7 @@ defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
+defm : subvector_subreg_lowering;
 
 // A 128-bit subvector extract from the first 512-bit vector position is a
 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
@@ -107,6 +109,7 @@ defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
+defm : subvector_subreg_lowering;
 
 
 // If we're inserting into an all zeros vector, just use a plain move which
diff --git a/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll 
b/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
index 0826faa1071b01..482713e12d15c7 100644
--- a/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
@@ -381,3 +381,25 @@ entry:
   %1 = shufflevector <8 x bfloat> %0, <8 x bfloat> undef, <16 x i32> 
zeroinitializer
   ret <16 x bfloat> %1
 }
+
+define <16 x i32> @pr83358() {
+; X86-LABEL: pr83358:
+; X86:   # %bb.0:
+; X86-NEXT:vcvtneps2bf16y {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # encoding: 
[0x62,0xf2,0x7e,0x28,0x72,0x05,A,A,A,A]
+; X86-NEXT:# fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: 
FK_Data_4
+; X86-NEXT:vshufi64x2 $0, %zmm0, %zmm0, %zmm0 # encoding: 
[0x62,0xf3,0xfd,0x48,0x43,0xc0,0x00]
+; X86-NEXT:# zmm0 = zmm0[0,1,0,1,0,1,0,1]
+; X86-NEXT:retl # encoding: [0xc3]
+;
+; X64-LABEL: pr83358:
+; X64:   # %bb.0:
+; X64-NEXT:vcvtneps2bf16y {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # 
encoding: [0x62,0xf2,0x7e,0x28,0x72,0x05,A,A,A,A]
+; X64-NEXT:# fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: 
reloc_riprel_4byte
+; X64-NEXT:vshufi64x2 $0, %zmm0, %zmm0, %zmm0 # encoding: 
[0x62,0xf3,0xfd,0x48,0x43,0xc0,0x00]
+; X64-NEXT:# zmm0 = zmm0[0,1,0,1,0,1,0,1]
+; X64-NEXT:retq # encoding: [0xc3]
+  %1 = call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> 
)
+  %2 = bitcast <8 x bfloat> %1 to <4 x i32>
+  %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <16 x i32> 
+  ret <16 x i32> %3
+}
diff --git a/llvm/test/CodeGen/X86/bfloat.ll b/llvm/test/CodeGen/X86/bfloat.ll
index f2d3c4fb34199e..0042d477f3b364 100644
--- a/llvm/test/CodeGen/X86/bfloat.ll
+++ b/llvm/test/CodeGen/X86/bfloat.ll
@@ -511,7 +511,7 @@ define void @fold_ext_trunc(ptr %pa, ptr %pc) nounwind {
 define bfloat @fold_ext_trunc2(bfloat %a) nounwind {
 ; X86-LABEL: fold_ext_trunc2:
 ; X86:   # %bb.0:
-; X86-NEXT:vmovsh {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
 ; X86-NEXT:retl
 ;
 ; CHECK-LABEL: fold_ext_trunc2:
@@ -934,8 +934,8 @@ define <8 x bfloat> @addv(<8 x bfloat> %a, <8 x bfloat> %b) 
nounwind {
 define <2 x bfloat> @pr62997(bfloat %a, bfloat %b) {
 ; X86-LABEL: pr62997:
 ; X86:   # %bb.0:
-; X86-NEXT:vmovsh {{[0-9]+}}(%esp), %xmm0
-; X86-NEXT:vmovsh {{[0-9]+}}(%esp), %xmm1
+; X86-NEXT:vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT:vmovsh {{.*#+}} xmm1 = mem[0],zero,zero,zero,zero,zero,zero,zero
 ; X86-NEXT:vpunpcklwd {{.*#+}} xmm0 = 
xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; X86-NEXT:retl
 ;
@@ -2423,7 +2423,6 @@ define <16 x bfloat> @fptrunc_v16f32(<16 x float> %a) 
nounwind {
 ; AVXNC-LABEL: fptrunc_v16f32:
 ; AVXNC:   # %bb.0:
 ; AVXNC-NEXT:{vex} vcvtneps2bf16 %ymm0, %xmm0
-; AVXNC-NEXT:vinsertf128 $0, %xmm0, %ymm0, %ymm0
 ; AVXNC-NEXT:{vex} vcvtneps2bf16 %ymm1, %xmm1
 ; AVXNC-NEXT:vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVXNC-NEXT:retq

``




https://github.com/llvm/llvm-project/pull/84491
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[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

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https://github.com/llvmbot updated 
https://github.com/llvm/llvm-project/pull/84491

>From 54e01706d1764b689c8eb1ed4b173cca26b5f9ed Mon Sep 17 00:00:00 2001
From: Phoebe Wang 
Date: Mon, 4 Mar 2024 10:15:43 +0800
Subject: [PATCH] [X86] Add missing subvector_subreg_lowering for BF16 (#83720)

Fixes: #83358
(cherry picked from commit ff72c83b017ba636be13750c7f96cd87fc22c465)
---
 llvm/lib/Target/X86/X86InstrVecCompiler.td|  3 +++
 .../CodeGen/X86/avx512bf16-vl-intrinsics.ll   | 22 +++
 llvm/test/CodeGen/X86/bfloat.ll   |  7 +++---
 3 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrVecCompiler.td 
b/llvm/lib/Target/X86/X86InstrVecCompiler.td
index bbd19cf8d5b25e..461b2badc13134 100644
--- a/llvm/lib/Target/X86/X86InstrVecCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrVecCompiler.td
@@ -83,6 +83,7 @@ defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
+defm : subvector_subreg_lowering;
 
 // A 128-bit subvector extract from the first 512-bit vector position is a
 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
@@ -95,6 +96,7 @@ defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
+defm : subvector_subreg_lowering;
 
 // A 128-bit subvector extract from the first 512-bit vector position is a
 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
@@ -107,6 +109,7 @@ defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
 defm : subvector_subreg_lowering;
+defm : subvector_subreg_lowering;
 
 
 // If we're inserting into an all zeros vector, just use a plain move which
diff --git a/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll 
b/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
index 0826faa1071b01..482713e12d15c7 100644
--- a/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll
@@ -381,3 +381,25 @@ entry:
   %1 = shufflevector <8 x bfloat> %0, <8 x bfloat> undef, <16 x i32> 
zeroinitializer
   ret <16 x bfloat> %1
 }
+
+define <16 x i32> @pr83358() {
+; X86-LABEL: pr83358:
+; X86:   # %bb.0:
+; X86-NEXT:vcvtneps2bf16y {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 # encoding: 
[0x62,0xf2,0x7e,0x28,0x72,0x05,A,A,A,A]
+; X86-NEXT:# fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}, kind: 
FK_Data_4
+; X86-NEXT:vshufi64x2 $0, %zmm0, %zmm0, %zmm0 # encoding: 
[0x62,0xf3,0xfd,0x48,0x43,0xc0,0x00]
+; X86-NEXT:# zmm0 = zmm0[0,1,0,1,0,1,0,1]
+; X86-NEXT:retl # encoding: [0xc3]
+;
+; X64-LABEL: pr83358:
+; X64:   # %bb.0:
+; X64-NEXT:vcvtneps2bf16y {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # 
encoding: [0x62,0xf2,0x7e,0x28,0x72,0x05,A,A,A,A]
+; X64-NEXT:# fixup A - offset: 6, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: 
reloc_riprel_4byte
+; X64-NEXT:vshufi64x2 $0, %zmm0, %zmm0, %zmm0 # encoding: 
[0x62,0xf3,0xfd,0x48,0x43,0xc0,0x00]
+; X64-NEXT:# zmm0 = zmm0[0,1,0,1,0,1,0,1]
+; X64-NEXT:retq # encoding: [0xc3]
+  %1 = call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> 
)
+  %2 = bitcast <8 x bfloat> %1 to <4 x i32>
+  %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <16 x i32> 
+  ret <16 x i32> %3
+}
diff --git a/llvm/test/CodeGen/X86/bfloat.ll b/llvm/test/CodeGen/X86/bfloat.ll
index f2d3c4fb34199e..0042d477f3b364 100644
--- a/llvm/test/CodeGen/X86/bfloat.ll
+++ b/llvm/test/CodeGen/X86/bfloat.ll
@@ -511,7 +511,7 @@ define void @fold_ext_trunc(ptr %pa, ptr %pc) nounwind {
 define bfloat @fold_ext_trunc2(bfloat %a) nounwind {
 ; X86-LABEL: fold_ext_trunc2:
 ; X86:   # %bb.0:
-; X86-NEXT:vmovsh {{[0-9]+}}(%esp), %xmm0
+; X86-NEXT:vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
 ; X86-NEXT:retl
 ;
 ; CHECK-LABEL: fold_ext_trunc2:
@@ -934,8 +934,8 @@ define <8 x bfloat> @addv(<8 x bfloat> %a, <8 x bfloat> %b) 
nounwind {
 define <2 x bfloat> @pr62997(bfloat %a, bfloat %b) {
 ; X86-LABEL: pr62997:
 ; X86:   # %bb.0:
-; X86-NEXT:vmovsh {{[0-9]+}}(%esp), %xmm0
-; X86-NEXT:vmovsh {{[0-9]+}}(%esp), %xmm1
+; X86-NEXT:vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT:vmovsh {{.*#+}} xmm1 = mem[0],zero,zero,zero,zero,zero,zero,zero
 ; X86-NEXT:vpunpcklwd {{.*#+}} xmm0 = 
xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; X86-NEXT:retl
 ;
@@ -2423,7 +2423,6 @@ define <16 x bfloat> @fptrunc_v16f32(<16 x float> %a) 
nounwind {
 ; AVXNC-LABEL: fptrunc_v16f32:
 ; AVXNC:   # %bb.0:
 ; AVXNC-NEXT:{vex} vcvtneps2bf16 %ymm0, %xmm0
-; AVXNC-NEXT:vinsertf128 $0, %xmm0, %ymm0, %ymm0
 ; AVXNC-NEXT:{vex} vcvtneps2bf16 %ymm1, %xmm1
 ; AVXNC-NEXT:vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVXNC-NEXT:retq

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[llvm-branch-commits] [libcxx] release/18.x: [libc++][modules] Fixes naming inconsistency. (#83036) (PR #83156)

[Mark de Wever via llvm-branch-commits]

mordante wrote:

I assume it will then be in 18.1.1 in a few weeks.

https://github.com/llvm/llvm-project/pull/83156
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[llvm-branch-commits] [llvm] 9db26e9 - Revert "[IR] Add new Range attribute using new ConstantRange Attribute type (…"

[via llvm-branch-commits]

Author: Florian Mayer
Date: 2024-03-08T11:34:52-08:00
New Revision: 9db26e987297a6406adb5e0c80a6c2a93c59ade6

URL: 
https://github.com/llvm/llvm-project/commit/9db26e987297a6406adb5e0c80a6c2a93c59ade6
DIFF: 
https://github.com/llvm/llvm-project/commit/9db26e987297a6406adb5e0c80a6c2a93c59ade6.diff

LOG: Revert "[IR] Add new Range attribute using new ConstantRange Attribute 
type (…"

This reverts commit e0d49066c1acfa4ae0f0e8ea49b0f0b6bb3f1a25.

Added: 


Modified: 
llvm/docs/LangRef.rst
llvm/include/llvm/ADT/FoldingSet.h
llvm/include/llvm/AsmParser/LLParser.h
llvm/include/llvm/Bitcode/LLVMBitCodes.h
llvm/include/llvm/IR/Attributes.h
llvm/include/llvm/IR/Attributes.td
llvm/lib/AsmParser/LLParser.cpp
llvm/lib/Bitcode/Reader/BitcodeReader.cpp
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
llvm/lib/IR/AttributeImpl.h
llvm/lib/IR/Attributes.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Transforms/Utils/CodeExtractor.cpp
llvm/test/Bitcode/attributes.ll
llvm/utils/TableGen/Attributes.cpp

Removed: 
llvm/test/Assembler/range-attribute-invalid-range.ll
llvm/test/Assembler/range-attribute-invalid-type.ll
llvm/test/Verifier/range-attr.ll



diff  --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index b70220dec92615..a7b77d6f776a7e 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -1635,22 +1635,6 @@ Currently, only the following parameter attributes are 
defined:
 
 This attribute cannot be applied to return values.
 
-``range( , )``
-This attribute expresses the possible range of the parameter or return 
value.
-If the value is not in the specified range, it is converted to poison.
-The arguments passed to ``range`` have the following properties:
-
--  The type must match the scalar type of the parameter or return value.
--  The pair ``a,b`` represents the range ``[a,b)``.
--  Both ``a`` and ``b`` are constants.
--  The range is allowed to wrap.
--  The range should not represent the full or empty set. That is, ``a!=b``.
-
-This attribute may only be applied to parameters or return values with 
integer 
-or vector of integer types.
-
-For vector-typed parameters, the range is applied element-wise.
-
 .. _gc:
 
 Garbage Collector Strategy Names

diff  --git a/llvm/include/llvm/ADT/FoldingSet.h 
b/llvm/include/llvm/ADT/FoldingSet.h
index ddc3e52255d6c0..f82eabd5044b22 100644
--- a/llvm/include/llvm/ADT/FoldingSet.h
+++ b/llvm/include/llvm/ADT/FoldingSet.h
@@ -16,7 +16,6 @@
 #ifndef LLVM_ADT_FOLDINGSET_H
 #define LLVM_ADT_FOLDINGSET_H
 
-#include "llvm/ADT/APInt.h"
 #include "llvm/ADT/Hashing.h"
 #include "llvm/ADT/STLForwardCompat.h"
 #include "llvm/ADT/SmallVector.h"
@@ -355,12 +354,6 @@ class FoldingSetNodeID {
 AddInteger(unsigned(I));
 AddInteger(unsigned(I >> 32));
   }
-  void AddInteger(const APInt &Int) {
-const auto *Parts = Int.getRawData();
-for (int i = 0, N = Int.getNumWords(); i < N; ++i) {
-  AddInteger(Parts[i]);
-}
-  }
 
   void AddBoolean(bool B) { AddInteger(B ? 1U : 0U); }
   void AddString(StringRef String);

diff  --git a/llvm/include/llvm/AsmParser/LLParser.h 
b/llvm/include/llvm/AsmParser/LLParser.h
index e85728aa3c0da0..e5e1ade8b38b36 100644
--- a/llvm/include/llvm/AsmParser/LLParser.h
+++ b/llvm/include/llvm/AsmParser/LLParser.h
@@ -369,7 +369,6 @@ namespace llvm {
 bool parseFnAttributeValuePairs(AttrBuilder &B,
 std::vector &FwdRefAttrGrps,
 bool inAttrGrp, LocTy &BuiltinLoc);
-bool parseRangeAttr(AttrBuilder &B);
 bool parseRequiredTypeAttr(AttrBuilder &B, lltok::Kind AttrToken,
Attribute::AttrKind AttrKind);
 

diff  --git a/llvm/include/llvm/Bitcode/LLVMBitCodes.h 
b/llvm/include/llvm/Bitcode/LLVMBitCodes.h
index c0a52d64a101d0..c6f0ddf29a6da8 100644
--- a/llvm/include/llvm/Bitcode/LLVMBitCodes.h
+++ b/llvm/include/llvm/Bitcode/LLVMBitCodes.h
@@ -724,7 +724,6 @@ enum AttributeKindCodes {
   ATTR_KIND_WRITABLE = 89,
   ATTR_KIND_CORO_ONLY_DESTROY_WHEN_COMPLETE = 90,
   ATTR_KIND_DEAD_ON_UNWIND = 91,
-  ATTR_KIND_RANGE = 92,
 };
 
 enum ComdatSelectionKindCodes {

diff  --git a/llvm/include/llvm/IR/Attributes.h 
b/llvm/include/llvm/IR/Attributes.h
index 0c2a02514ba0e6..a4ebe5d732f568 100644
--- a/llvm/include/llvm/IR/Attributes.h
+++ b/llvm/include/llvm/IR/Attributes.h
@@ -37,7 +37,6 @@ class AttributeMask;
 class AttributeImpl;
 class AttributeListImpl;
 class AttributeSetNode;
-class ConstantRange;
 class FoldingSetNodeID;
 class Function;
 class LLVMContext;
@@ -104,9 +103,6 @@ class Attribute {
   static bool isTypeAttrKind(AttrKind Kind) {
 return Kind >= FirstTypeAttr && Kind <= LastTypeAttr;
   }
-  static bool isConstantRangeAttrKind(AttrKind Kind) {
-return Kind >= FirstConstantRangeAttr && Kind <= LastConstantRangeAt

[llvm-branch-commits] [clang] [lld] [llvm] SystemZ release notes for 18.x. (PR #84560)

[Jonas Paulsson via llvm-branch-commits]

https://github.com/JonPsson1 created 
https://github.com/llvm/llvm-project/pull/84560

None

>From b6bd83cace58517531380eb4e34594bddc973153 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson 
Date: Fri, 8 Mar 2024 15:28:56 -0500
Subject: [PATCH] SystemZ release notes.

---
 clang/docs/ReleaseNotes.rst |  5 +
 lld/docs/ReleaseNotes.rst   |  6 ++
 llvm/docs/ReleaseNotes.rst  | 10 ++
 3 files changed, 21 insertions(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index fc27297aea2d6c..6a038ed4b635c7 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1325,6 +1325,11 @@ AIX Support
   or newer. Similar to the LTO support on AIX, ThinLTO is implemented with
   the libLTO.so plugin.
 
+SystemZ Support
+^^^
+- Properly support 16 byte atomic int/fp types and ops. Atomic __int128 (and
+  long double) variables are now aligned to 16 bytes by default (like gcc 14).
+
 WebAssembly Support
 ^^^
 
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index 56ba3463aeadc0..4de33363d0532b 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -163,5 +163,11 @@ WebAssembly Improvements
   is read from object files within the archive.  This matches the behaviour of
   the ELF linker.
 
+SystemZ
+---
+
+* Add target support for SystemZ (s390x).
+
+
 Fixes
 #
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 5b3210138f2f89..7cfa83fc8b0565 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -215,6 +215,16 @@ Changes to the RISC-V Backend
 * ``-mcpu=sifive-p670`` was added.
 * Support for the Zicond extension is no longer experimental.
 
+Changes to the SystemZ Backend
+--
+
+* Properly support 16 byte atomic int/fp types and ops.
+* Support i128 as legal type in VRs.
+* Add an i128 cost model.
+* Support building individual functions with backchain using the
+  __attribute__((target("backchain"))) syntax.
+* Add exception handling for XPLINK.
+
 Changes to the WebAssembly Backend
 --
 

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[llvm-branch-commits] [clang] [lld] [llvm] SystemZ release notes for 18.x. (PR #84560)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-lld

Author: Jonas Paulsson (JonPsson1)


Changes



---
Full diff: https://github.com/llvm/llvm-project/pull/84560.diff


3 Files Affected:

- (modified) clang/docs/ReleaseNotes.rst (+5) 
- (modified) lld/docs/ReleaseNotes.rst (+6) 
- (modified) llvm/docs/ReleaseNotes.rst (+10) 


``diff
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index fc27297aea2d6c..6a038ed4b635c7 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1325,6 +1325,11 @@ AIX Support
   or newer. Similar to the LTO support on AIX, ThinLTO is implemented with
   the libLTO.so plugin.
 
+SystemZ Support
+^^^
+- Properly support 16 byte atomic int/fp types and ops. Atomic __int128 (and
+  long double) variables are now aligned to 16 bytes by default (like gcc 14).
+
 WebAssembly Support
 ^^^
 
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index 56ba3463aeadc0..4de33363d0532b 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -163,5 +163,11 @@ WebAssembly Improvements
   is read from object files within the archive.  This matches the behaviour of
   the ELF linker.
 
+SystemZ
+---
+
+* Add target support for SystemZ (s390x).
+
+
 Fixes
 #
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 5b3210138f2f89..7cfa83fc8b0565 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -215,6 +215,16 @@ Changes to the RISC-V Backend
 * ``-mcpu=sifive-p670`` was added.
 * Support for the Zicond extension is no longer experimental.
 
+Changes to the SystemZ Backend
+--
+
+* Properly support 16 byte atomic int/fp types and ops.
+* Support i128 as legal type in VRs.
+* Add an i128 cost model.
+* Support building individual functions with backchain using the
+  __attribute__((target("backchain"))) syntax.
+* Add exception handling for XPLINK.
+
 Changes to the WebAssembly Backend
 --
 

``




https://github.com/llvm/llvm-project/pull/84560
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[llvm-branch-commits] [clang] [lld] [llvm] SystemZ release notes for 18.x. (PR #84560)

[Jonas Paulsson via llvm-branch-commits]

https://github.com/JonPsson1 updated 
https://github.com/llvm/llvm-project/pull/84560

>From 639dceb13cf824e3f4e0f627becf8fb8f5ecb29c Mon Sep 17 00:00:00 2001
From: Jonas Paulsson 
Date: Fri, 8 Mar 2024 15:28:56 -0500
Subject: [PATCH] SystemZ release notes.

---
 clang/docs/ReleaseNotes.rst |  5 +
 lld/docs/ReleaseNotes.rst   |  5 +
 llvm/docs/ReleaseNotes.rst  | 10 ++
 3 files changed, 20 insertions(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index fc27297aea2d6c..6a038ed4b635c7 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1325,6 +1325,11 @@ AIX Support
   or newer. Similar to the LTO support on AIX, ThinLTO is implemented with
   the libLTO.so plugin.
 
+SystemZ Support
+^^^
+- Properly support 16 byte atomic int/fp types and ops. Atomic __int128 (and
+  long double) variables are now aligned to 16 bytes by default (like gcc 14).
+
 WebAssembly Support
 ^^^
 
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index 56ba3463aeadc0..6ada711a20a6da 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -163,5 +163,10 @@ WebAssembly Improvements
   is read from object files within the archive.  This matches the behaviour of
   the ELF linker.
 
+SystemZ
+---
+
+* Add target support for SystemZ (s390x).
+
 Fixes
 #
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 5b3210138f2f89..7cfa83fc8b0565 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -215,6 +215,16 @@ Changes to the RISC-V Backend
 * ``-mcpu=sifive-p670`` was added.
 * Support for the Zicond extension is no longer experimental.
 
+Changes to the SystemZ Backend
+--
+
+* Properly support 16 byte atomic int/fp types and ops.
+* Support i128 as legal type in VRs.
+* Add an i128 cost model.
+* Support building individual functions with backchain using the
+  __attribute__((target("backchain"))) syntax.
+* Add exception handling for XPLINK.
+
 Changes to the WebAssembly Backend
 --
 

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[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

[via llvm-branch-commits]

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/84566

Backport 755b439694432d4f68e20e979b479cbc30602bb1

Requested by: @brad0

>From 86b5745e27533404e61912f0233ab38307174025 Mon Sep 17 00:00:00 2001
From: yingopq <115543042+ying...@users.noreply.github.com>
Date: Sat, 9 Mar 2024 04:41:31 +0800
Subject: [PATCH] [Mips] Fix missing sign extension in expansion of sub-word
 atomic max (#77072)

Add sign extension "SEB/SEH" before compare.

Fix #61881

(cherry picked from commit 755b439694432d4f68e20e979b479cbc30602bb1)
---
 llvm/lib/Target/Mips/MipsExpandPseudo.cpp |  51 +-
 llvm/test/CodeGen/Mips/atomic-min-max.ll  | 655 ++
 2 files changed, 577 insertions(+), 129 deletions(-)

diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp 
b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
index 2c2554b5b4bc3b..bded59439a736a 100644
--- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
+++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
@@ -388,18 +388,32 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
 Opcode = Mips::XOR;
 break;
   case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA:
+IsUnsigned = true;
+IsMin = true;
+break;
   case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA:
 IsUnsigned = true;
-[[fallthrough]];
+IsMin = true;
+break;
   case Mips::ATOMIC_LOAD_MIN_I8_POSTRA:
+SEOp = Mips::SEB;
+IsMin = true;
+break;
   case Mips::ATOMIC_LOAD_MIN_I16_POSTRA:
 IsMin = true;
 break;
   case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA:
+IsUnsigned = true;
+IsMax = true;
+break;
   case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA:
 IsUnsigned = true;
-[[fallthrough]];
+IsMax = true;
+break;
   case Mips::ATOMIC_LOAD_MAX_I8_POSTRA:
+SEOp = Mips::SEB;
+IsMax = true;
+break;
   case Mips::ATOMIC_LOAD_MAX_I16_POSTRA:
 IsMax = true;
 break;
@@ -461,14 +475,33 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
 
 // For little endian we need to clear uninterested bits.
 if (STI->isLittle()) {
-  // and OldVal, OldVal, Mask
-  // and Incr, Incr, Mask
-  BuildMI(loopMBB, DL, TII->get(Mips::AND), OldVal)
-  .addReg(OldVal)
-  .addReg(Mask);
-  BuildMI(loopMBB, DL, TII->get(Mips::AND), 
Incr).addReg(Incr).addReg(Mask);
+  if (!IsUnsigned) {
+BuildMI(loopMBB, DL, TII->get(Mips::SRAV), OldVal)
+.addReg(OldVal)
+.addReg(ShiftAmnt);
+BuildMI(loopMBB, DL, TII->get(Mips::SRAV), Incr)
+.addReg(Incr)
+.addReg(ShiftAmnt);
+if (STI->hasMips32r2()) {
+  BuildMI(loopMBB, DL, TII->get(SEOp), OldVal).addReg(OldVal);
+  BuildMI(loopMBB, DL, TII->get(SEOp), Incr).addReg(Incr);
+} else {
+  const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24;
+  BuildMI(loopMBB, DL, TII->get(Mips::SLL), OldVal)
+  .addReg(OldVal, RegState::Kill)
+  .addImm(ShiftImm);
+  BuildMI(loopMBB, DL, TII->get(Mips::SRA), OldVal)
+  .addReg(OldVal, RegState::Kill)
+  .addImm(ShiftImm);
+  BuildMI(loopMBB, DL, TII->get(Mips::SLL), Incr)
+  .addReg(Incr, RegState::Kill)
+  .addImm(ShiftImm);
+  BuildMI(loopMBB, DL, TII->get(Mips::SRA), Incr)
+  .addReg(Incr, RegState::Kill)
+  .addImm(ShiftImm);
+}
+  }
 }
-
 // unsigned: sltu Scratch4, oldVal, Incr
 // signed:   slt Scratch4, oldVal, Incr
 BuildMI(loopMBB, DL, TII->get(SLTScratch4), Scratch4)
diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll 
b/llvm/test/CodeGen/Mips/atomic-min-max.ll
index f953c885ea7345..bc3643f3947a40 100644
--- a/llvm/test/CodeGen/Mips/atomic-min-max.ll
+++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll
@@ -3,6 +3,7 @@
 ; RUN: llc -march=mips -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | 
FileCheck %s --check-prefix=MIPSR6
 ; RUN: llc -march=mips -O0 -mcpu=mips32r2 -mattr=+micromips 
-verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM
 ; RUN: llc -march=mips -O0 -mcpu=mips32r6 -mattr=+micromips 
-verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6
+; RUN: llc -march=mipsel -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | 
FileCheck %s --check-prefix=MIPS32
 ; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | 
FileCheck %s --check-prefix=MIPSEL
 ; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | 
FileCheck %s --check-prefix=MIPSELR6
 ; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -mattr=+micromips 
-verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL
@@ -77,6 +78,23 @@ define i32 @test_max_32(ptr nocapture %ptr, i32 signext 
%val) {
 ; MMR6-NEXT:sync
 ; MMR6-NEXT:jrc $ra
 ;
+; MIPS32-LABEL: test_max_32:
+; MIPS32:   # %bb.0: # %entry
+; MIPS32-NEXT:sync
+; MIPS32-NEXT:  $BB0_1: # %entry
+; MIPS32-NEXT:# =>This Inner Loop Header: Depth=1
+; MIPS32-NEXT:ll $2, 0($4)
+; MIPS32-NEXT:slt $3, $2, $5

[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

[via llvm-branch-commits]

https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/84566
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[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

[via llvm-branch-commits]

llvmbot wrote:

@topperc What do you think about merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/84566
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[llvm-branch-commits] [llvm] b92012c - Remove RC suffix

[Tom Stellard via llvm-branch-commits]

Author: Tobias Hieta
Date: 2024-03-07T21:18:24-08:00
New Revision: b92012c777e602d557124583651313a0afa33484

URL: 
https://github.com/llvm/llvm-project/commit/b92012c777e602d557124583651313a0afa33484
DIFF: 
https://github.com/llvm/llvm-project/commit/b92012c777e602d557124583651313a0afa33484.diff

LOG: Remove RC suffix

Added: 


Modified: 
llvm/CMakeLists.txt

Removed: 




diff  --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index 44f2850b92d522..389bd8b6422da4 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -25,7 +25,7 @@ if(NOT DEFINED LLVM_VERSION_PATCH)
   set(LLVM_VERSION_PATCH 0)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
-  set(LLVM_VERSION_SUFFIX rc)
+  set(LLVM_VERSION_SUFFIX)
 endif()
 
 if (NOT PACKAGE_VERSION)



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[llvm-branch-commits] [llvm] dba2a75 - Bump version to 18.1.1

[Tom Stellard via llvm-branch-commits]

Author: Tom Stellard
Date: 2024-03-07T21:27:31-08:00
New Revision: dba2a75e9c7ef81fe84774ba5eee5e67e01d801a

URL: 
https://github.com/llvm/llvm-project/commit/dba2a75e9c7ef81fe84774ba5eee5e67e01d801a
DIFF: 
https://github.com/llvm/llvm-project/commit/dba2a75e9c7ef81fe84774ba5eee5e67e01d801a.diff

LOG: Bump version to 18.1.1

Added: 


Modified: 
llvm/CMakeLists.txt

Removed: 




diff  --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index 389bd8b6422da4..ddf95cbc6c5175 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -22,7 +22,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR)
   set(LLVM_VERSION_MINOR 1)
 endif()
 if(NOT DEFINED LLVM_VERSION_PATCH)
-  set(LLVM_VERSION_PATCH 0)
+  set(LLVM_VERSION_PATCH 1)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
   set(LLVM_VERSION_SUFFIX)



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[llvm-branch-commits] [llvm] Remove RC suffix (PR #84430)

[Tom Stellard via llvm-branch-commits]

https://github.com/tstellar closed 
https://github.com/llvm/llvm-project/pull/84430
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[llvm-branch-commits] [llvm] Backport ARM64EC variadic args fixes to LLVM 18 (PR #81800)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello updated 
https://github.com/llvm/llvm-project/pull/81800

>From 064dd621c19b3738af5db29afd5b986a6d739ab1 Mon Sep 17 00:00:00 2001
From: Billy Laws 
Date: Wed, 31 Jan 2024 02:32:15 +
Subject: [PATCH 1/3] [AArch64] Fix variadic tail-calls on ARM64EC (#79774)

ARM64EC varargs calls expect that x4 = sp at entry, special handling is
needed to ensure this with tail calls since they occur after the
epilogue and the x4 write happens before.

I tried going through AArch64MachineFrameLowering for this, hoping to
avoid creating the dummy object but this was the best I could do since
the stack info that uses isn't populated at this stage,
CreateFixedObject also explicitly forbids 0 sized objects.
---
 .../Target/AArch64/AArch64ISelLowering.cpp| 10 -
 llvm/test/CodeGen/AArch64/arm64ec-varargs.ll  | 37 +++
 llvm/test/CodeGen/AArch64/vararg-tallcall.ll  |  8 
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 0287856560e91a..196aa50cf4060b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8007,11 +8007,19 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
   }
 
   if (IsVarArg && Subtarget->isWindowsArm64EC()) {
+SDValue ParamPtr = StackPtr;
+if (IsTailCall) {
+  // Create a dummy object at the top of the stack that can be used to get
+  // the SP after the epilogue
+  int FI = MF.getFrameInfo().CreateFixedObject(1, FPDiff, true);
+  ParamPtr = DAG.getFrameIndex(FI, PtrVT);
+}
+
 // For vararg calls, the Arm64EC ABI requires values in x4 and x5
 // describing the argument list.  x4 contains the address of the
 // first stack parameter. x5 contains the size in bytes of all parameters
 // passed on the stack.
-RegsToPass.emplace_back(AArch64::X4, StackPtr);
+RegsToPass.emplace_back(AArch64::X4, ParamPtr);
 RegsToPass.emplace_back(AArch64::X5,
 DAG.getConstant(NumBytes, DL, MVT::i64));
   }
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll 
b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
index dc16b3a1a0f270..844fc52ddade63 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
@@ -100,5 +100,42 @@ define void @varargs_many_argscalleer() nounwind {
   ret void
 }
 
+define void @varargs_caller_tail() nounwind {
+; CHECK-LABEL: varargs_caller_tail:
+; CHECK:// %bb.0:
+; CHECK-NEXT:sub sp, sp, #48
+; CHECK-NEXT:mov x4, sp
+; CHECK-NEXT:add x8, sp, #16
+; CHECK-NEXT:mov x9, #4617315517961601024// 
=0x4014
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #2  // =0x2
+; CHECK-NEXT:mov x2, #4613937818241073152// 
=0x4008
+; CHECK-NEXT:mov w3, #4  // =0x4
+; CHECK-NEXT:mov w5, #16 // =0x10
+; CHECK-NEXT:stp xzr, x30, [sp, #24] // 8-byte Folded 
Spill
+; CHECK-NEXT:stp x9, x8, [sp]
+; CHECK-NEXT:str xzr, [sp, #16]
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:bl  "#varargs_callee"
+; CHECK-NEXT:ldr x30, [sp, #32]  // 8-byte Folded 
Reload
+; CHECK-NEXT:add x4, sp, #48
+; CHECK-NEXT:mov x0, #4607182418800017408// 
=0x3ff0
+; CHECK-NEXT:mov w1, #4  // =0x4
+; CHECK-NEXT:mov w2, #3  // =0x3
+; CHECK-NEXT:mov w3, #2  // =0x2
+; CHECK-NEXT:mov x5, xzr
+; CHECK-NEXT:add sp, sp, #48
+; CHECK-NEXT:.weak_anti_dep  varargs_callee
+; CHECK-NEXT:.set varargs_callee, "#varargs_callee"@WEAKREF
+; CHECK-NEXT:.weak_anti_dep  "#varargs_callee"
+; CHECK-NEXT:.set "#varargs_callee", varargs_callee@WEAKREF
+; CHECK-NEXT:b   "#varargs_callee"
+  call void (double, ...) @varargs_callee(double 1.0, i32 2, double 3.0, i32 
4, double 5.0, <2 x double> )
+  tail call void (double, ...) @varargs_callee(double 1.0, i32 4, i32 3, i32 2)
+  ret void
+}
 
 declare void @llvm.va_start(ptr)
diff --git a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll 
b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
index 2d6db1642247d7..812837639196e6 100644
--- a/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
+++ b/llvm/test/CodeGen/AArch64/vararg-tallcall.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -mtriple=aarch64-windows-msvc %s -o - | FileCheck %s

[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

[Florian Mayer via llvm-branch-commits]

https://github.com/fmayer updated 
https://github.com/llvm/llvm-project/pull/84404


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[llvm-branch-commits] [NFC] [hwasan] factor get[PC|FP] out of HWASan class (PR #84404)

[Florian Mayer via llvm-branch-commits]

https://github.com/fmayer updated 
https://github.com/llvm/llvm-project/pull/84404


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[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[Daniel Paoliello via llvm-branch-commits]

https://github.com/dpaoliello created 
https://github.com/llvm/llvm-project/pull/84590

Backports fixes to be able to generate import libraries for ARM64EC:
* 
* 
* 

>From 8f5a8fc5340687eb6ea943ec8460de56d141ede9 Mon Sep 17 00:00:00 2001
From: Jacek Caban 
Date: Tue, 6 Feb 2024 13:47:58 +0100
Subject: [PATCH 1/3] [llvm-readobj][Object][COFF] Print COFF import library
 symbol export name. (#78769)

getExportName implementation is based on lld-link. In its current form,
it's mostly about convenience, but it will be more useful for EXPORTAS
support, for which export name is not possible to deduce from other
printed properties.
---
 lld/test/COFF/def-export-cpp.s|  1 +
 lld/test/COFF/def-export-stdcall.s| 13 ++
 lld/test/COFF/dllexport.s |  4 +++
 llvm/include/llvm/Object/COFFImportFile.h |  1 +
 llvm/lib/Object/COFFImportFile.cpp| 26 +++
 .../tools/llvm-dlltool/coff-decorated.def |  7 +
 llvm/test/tools/llvm-dlltool/coff-exports.def |  3 +++
 llvm/test/tools/llvm-dlltool/coff-noname.def  |  1 +
 .../llvm-dlltool/no-leading-underscore.def|  2 ++
 llvm/test/tools/llvm-lib/arm64ec-implib.test  |  2 ++
 .../tools/llvm-readobj/COFF/file-headers.test |  1 +
 llvm/tools/llvm-readobj/COFFImportDumper.cpp  |  3 +++
 12 files changed, 64 insertions(+)

diff --git a/lld/test/COFF/def-export-cpp.s b/lld/test/COFF/def-export-cpp.s
index e00b35b1c5b39b..370b8ddba4104b 100644
--- a/lld/test/COFF/def-export-cpp.s
+++ b/lld/test/COFF/def-export-cpp.s
@@ -10,6 +10,7 @@
 
 # IMPLIB: File: foo.dll
 # IMPLIB: Name type: undecorate
+# IMPLIB-NEXT: Export name: GetPathOnDisk
 # IMPLIB-NEXT: Symbol: __imp_?GetPathOnDisk@@YA_NPEA_W@Z
 # IMPLIB-NEXT: Symbol: ?GetPathOnDisk@@YA_NPEA_W@Z
 
diff --git a/lld/test/COFF/def-export-stdcall.s 
b/lld/test/COFF/def-export-stdcall.s
index f015e205c74a33..7e4e04c77cbe7a 100644
--- a/lld/test/COFF/def-export-stdcall.s
+++ b/lld/test/COFF/def-export-stdcall.s
@@ -6,15 +6,19 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
UNDECORATED-EXPORTS %s
 
 # UNDECORATED-IMPLIB: Name type: noprefix
+# UNDECORATED-IMPLIB-NEXT: Export name: _underscored
 # UNDECORATED-IMPLIB-NEXT: __imp___underscored
 # UNDECORATED-IMPLIB-NEXT: __underscored
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: fastcall
 # UNDECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # UNDECORATED-IMPLIB-NEXT: fastcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: stdcall
 # UNDECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # UNDECORATED-IMPLIB-NEXT: _stdcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: vectorcall
 # UNDECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # UNDECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -30,12 +34,15 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-EXPORTS %s
 
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-IMPLIB-NEXT: @fastcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8
 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-IMPLIB-NEXT: _stdcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -51,14 +58,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-MINGW-EXPORTS %s
 
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: fastcall@8
 # DECORATED-MINGW-IMPLIB: Name type: noprefix
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: _stdcall@8
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: vectorcall@@8
 
@@ -75,14 +85,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
MINGW-KILL-AT-EXPORTS %s
 
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB: Export name: fastcall
 # MINGW-KILL-AT-IMPLIB: __imp__fastcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _fastcall
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: Export name: stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: __imp__stdcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _stdcall
 # GNU tools don't support vectorcall, but this test is just to track tha

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-backend-aarch64

Author: Daniel Paoliello (dpaoliello)


Changes

Backports fixes to be able to generate import libraries for ARM64EC:
* ;
* ;
* ;

---

Patch is 32.86 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/84590.diff


19 Files Affected:

- (modified) lld/test/COFF/def-export-cpp.s (+1) 
- (modified) lld/test/COFF/def-export-stdcall.s (+13) 
- (modified) lld/test/COFF/dllexport.s (+4) 
- (modified) llvm/include/llvm/BinaryFormat/COFF.h (+4-1) 
- (modified) llvm/include/llvm/Object/COFF.h (+41) 
- (modified) llvm/include/llvm/Object/COFFImportFile.h (+30-3) 
- (modified) llvm/lib/Object/COFFImportFile.cpp (+86-21) 
- (modified) llvm/lib/Object/COFFModuleDefinition.cpp (+12-1) 
- (modified) llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp (+2) 
- (modified) llvm/lib/Target/AArch64/AArch64MCInstLower.cpp (+2) 
- (modified) llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h (-28) 
- (modified) llvm/test/tools/llvm-dlltool/coff-decorated.def (+7) 
- (modified) llvm/test/tools/llvm-dlltool/coff-exports.def (+3) 
- (modified) llvm/test/tools/llvm-dlltool/coff-noname.def (+1) 
- (modified) llvm/test/tools/llvm-dlltool/no-leading-underscore.def (+2) 
- (modified) llvm/test/tools/llvm-lib/arm64ec-implib.test (+142-1) 
- (added) llvm/test/tools/llvm-lib/exportas.test (+94) 
- (modified) llvm/test/tools/llvm-readobj/COFF/file-headers.test (+1) 
- (modified) llvm/tools/llvm-readobj/COFFImportDumper.cpp (+6) 


``diff
diff --git a/lld/test/COFF/def-export-cpp.s b/lld/test/COFF/def-export-cpp.s
index e00b35b1c5b39b..370b8ddba4104b 100644
--- a/lld/test/COFF/def-export-cpp.s
+++ b/lld/test/COFF/def-export-cpp.s
@@ -10,6 +10,7 @@
 
 # IMPLIB: File: foo.dll
 # IMPLIB: Name type: undecorate
+# IMPLIB-NEXT: Export name: GetPathOnDisk
 # IMPLIB-NEXT: Symbol: __imp_?GetPathOnDisk@@YA_NPEA_W@Z
 # IMPLIB-NEXT: Symbol: ?GetPathOnDisk@@YA_NPEA_W@Z
 
diff --git a/lld/test/COFF/def-export-stdcall.s 
b/lld/test/COFF/def-export-stdcall.s
index f015e205c74a33..7e4e04c77cbe7a 100644
--- a/lld/test/COFF/def-export-stdcall.s
+++ b/lld/test/COFF/def-export-stdcall.s
@@ -6,15 +6,19 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
UNDECORATED-EXPORTS %s
 
 # UNDECORATED-IMPLIB: Name type: noprefix
+# UNDECORATED-IMPLIB-NEXT: Export name: _underscored
 # UNDECORATED-IMPLIB-NEXT: __imp___underscored
 # UNDECORATED-IMPLIB-NEXT: __underscored
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: fastcall
 # UNDECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # UNDECORATED-IMPLIB-NEXT: fastcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: stdcall
 # UNDECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # UNDECORATED-IMPLIB-NEXT: _stdcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: vectorcall
 # UNDECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # UNDECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -30,12 +34,15 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-EXPORTS %s
 
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-IMPLIB-NEXT: @fastcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8
 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-IMPLIB-NEXT: _stdcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -51,14 +58,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-MINGW-EXPORTS %s
 
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: fastcall@8
 # DECORATED-MINGW-IMPLIB: Name type: noprefix
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: _stdcall@8
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: vectorcall@@8
 
@@ -75,14 +85,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
MINGW-KILL-AT-EXPORTS %s
 
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB: Export name: fastcall
 # MINGW-KILL-AT-IMPLIB: __imp__fastcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _fastcall
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: Export

[llvm-branch-commits] [lld] [llvm] Backport fixes for ARM64EC import libraries (PR #84590)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-llvm-binary-utilities

Author: Daniel Paoliello (dpaoliello)


Changes

Backports fixes to be able to generate import libraries for ARM64EC:
* ;
* ;
* ;

---

Patch is 32.86 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/84590.diff


19 Files Affected:

- (modified) lld/test/COFF/def-export-cpp.s (+1) 
- (modified) lld/test/COFF/def-export-stdcall.s (+13) 
- (modified) lld/test/COFF/dllexport.s (+4) 
- (modified) llvm/include/llvm/BinaryFormat/COFF.h (+4-1) 
- (modified) llvm/include/llvm/Object/COFF.h (+41) 
- (modified) llvm/include/llvm/Object/COFFImportFile.h (+30-3) 
- (modified) llvm/lib/Object/COFFImportFile.cpp (+86-21) 
- (modified) llvm/lib/Object/COFFModuleDefinition.cpp (+12-1) 
- (modified) llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp (+2) 
- (modified) llvm/lib/Target/AArch64/AArch64MCInstLower.cpp (+2) 
- (modified) llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h (-28) 
- (modified) llvm/test/tools/llvm-dlltool/coff-decorated.def (+7) 
- (modified) llvm/test/tools/llvm-dlltool/coff-exports.def (+3) 
- (modified) llvm/test/tools/llvm-dlltool/coff-noname.def (+1) 
- (modified) llvm/test/tools/llvm-dlltool/no-leading-underscore.def (+2) 
- (modified) llvm/test/tools/llvm-lib/arm64ec-implib.test (+142-1) 
- (added) llvm/test/tools/llvm-lib/exportas.test (+94) 
- (modified) llvm/test/tools/llvm-readobj/COFF/file-headers.test (+1) 
- (modified) llvm/tools/llvm-readobj/COFFImportDumper.cpp (+6) 


``diff
diff --git a/lld/test/COFF/def-export-cpp.s b/lld/test/COFF/def-export-cpp.s
index e00b35b1c5b39b..370b8ddba4104b 100644
--- a/lld/test/COFF/def-export-cpp.s
+++ b/lld/test/COFF/def-export-cpp.s
@@ -10,6 +10,7 @@
 
 # IMPLIB: File: foo.dll
 # IMPLIB: Name type: undecorate
+# IMPLIB-NEXT: Export name: GetPathOnDisk
 # IMPLIB-NEXT: Symbol: __imp_?GetPathOnDisk@@YA_NPEA_W@Z
 # IMPLIB-NEXT: Symbol: ?GetPathOnDisk@@YA_NPEA_W@Z
 
diff --git a/lld/test/COFF/def-export-stdcall.s 
b/lld/test/COFF/def-export-stdcall.s
index f015e205c74a33..7e4e04c77cbe7a 100644
--- a/lld/test/COFF/def-export-stdcall.s
+++ b/lld/test/COFF/def-export-stdcall.s
@@ -6,15 +6,19 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
UNDECORATED-EXPORTS %s
 
 # UNDECORATED-IMPLIB: Name type: noprefix
+# UNDECORATED-IMPLIB-NEXT: Export name: _underscored
 # UNDECORATED-IMPLIB-NEXT: __imp___underscored
 # UNDECORATED-IMPLIB-NEXT: __underscored
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: fastcall
 # UNDECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # UNDECORATED-IMPLIB-NEXT: fastcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: stdcall
 # UNDECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # UNDECORATED-IMPLIB-NEXT: _stdcall@8
 # UNDECORATED-IMPLIB: Name type: undecorate
+# UNDECORATED-IMPLIB-NEXT: Export name: vectorcall
 # UNDECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # UNDECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -30,12 +34,15 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-EXPORTS %s
 
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-IMPLIB-NEXT: @fastcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8
 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-IMPLIB-NEXT: _stdcall@8
 # DECORATED-IMPLIB: Name type: name
+# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-IMPLIB-NEXT: vectorcall@@8
 
@@ -51,14 +58,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
DECORATED-MINGW-EXPORTS %s
 
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: @fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_@fastcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: fastcall@8
 # DECORATED-MINGW-IMPLIB: Name type: noprefix
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp__stdcall@8
 # DECORATED-MINGW-IMPLIB-NEXT: _stdcall@8
 # GNU tools don't support vectorcall, but this test is just to track that
 # lld's behaviour remains consistent over time.
 # DECORATED-MINGW-IMPLIB: Name type: name
+# DECORATED-MINGW-IMPLIB-NEXT: Export name: vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: __imp_vectorcall@@8
 # DECORATED-MINGW-IMPLIB-NEXT: vectorcall@@8
 
@@ -75,14 +85,17 @@
 # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix 
MINGW-KILL-AT-EXPORTS %s
 
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB: Export name: fastcall
 # MINGW-KILL-AT-IMPLIB: __imp__fastcall
 # MINGW-KILL-AT-IMPLIB-NEXT: _fastcall
 # MINGW-KILL-AT-IMPLIB: Name type: noprefix
+# MINGW-KILL-AT-IMPLIB-NEXT: 

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

[Paul Kirth via llvm-branch-commits]

https://github.com/ilovepi created 
https://github.com/llvm/llvm-project/pull/84598

This patch adds basic support for the Tag_RISCV_x3_reg_usage attribute
specified in:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_x3_reg_usage-16-uleb128value
It adds support for merging the x3_reg_usage attribute in the linker,
and basic support for the attribute in attribute parser.

Enabling this feature will allow targets to avoid challenges with mixing
object files with different expectations for how x3/gp is used.

Merging x3_reg_usage tags with different values is considered an error,
with one exception. The value 0 can merge with 1 or 2 value. After the
merge, the resulting value will be the non-zero one.



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[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

[via llvm-branch-commits]

llvmbot wrote:




@llvm/pr-subscribers-mc

Author: Paul Kirth (ilovepi)


Changes

This patch adds basic support for the Tag_RISCV_x3_reg_usage attribute
specified in:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_x3_reg_usage-16-uleb128value
It adds support for merging the x3_reg_usage attribute in the linker,
and basic support for the attribute in attribute parser.

Enabling this feature will allow targets to avoid challenges with mixing
object files with different expectations for how x3/gp is used.

Merging x3_reg_usage tags with different values is considered an error,
with one exception. The value 0 can merge with 1 or 2 value. After the
merge, the resulting value will be the non-zero one.


---
Full diff: https://github.com/llvm/llvm-project/pull/84598.diff


9 Files Affected:

- (modified) lld/ELF/Arch/RISCV.cpp (+12) 
- (modified) lld/test/ELF/riscv-attributes.s (+51) 
- (modified) llvm/include/llvm/Support/RISCVAttributeParser.h (+1) 
- (modified) llvm/include/llvm/Support/RISCVAttributes.h (+10) 
- (modified) llvm/lib/Support/RISCVAttributeParser.cpp (+7) 
- (modified) llvm/lib/Support/RISCVAttributes.cpp (+1) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+5) 
- (modified) llvm/test/MC/RISCV/attribute.s (+3) 
- (modified) llvm/test/MC/RISCV/invalid-attribute.s (+3) 


``diff
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index e44583fb80fd31..f3b134144b654b 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1224,6 +1224,18 @@ mergeAttributesSection(const 
SmallVector §ions) {
   }
 }
 continue;
+
+  case llvm::RISCVAttrs::AttrType::X3_REG_USAGE:
+if (auto i = parser.getAttributeValue(tag.attr)) {
+  auto r = merged.intAttr.try_emplace(tag.attr, *i);
+  if (r.second) {
+firstX3RegUse = sec;
+  } else {
+mergeX3RegUse(merged.intAttr, firstX3RegUse, sec,
+  r.first->getSecond(), *i);
+  }
+}
+continue;
   }
 
   // Fallback for deprecated priv_spec* and other unknown attributes: 
retain
diff --git a/lld/test/ELF/riscv-attributes.s b/lld/test/ELF/riscv-attributes.s
index 964fec43b52847..43438b238b5d6b 100644
--- a/lld/test/ELF/riscv-attributes.s
+++ b/lld/test/ELF/riscv-attributes.s
@@ -68,6 +68,23 @@
 # RUN: ld.lld atomic_abi_unknown.o atomic_abi_A7.o -o atomic_abi_A7_unknown
 # RUN: llvm-readobj -A atomic_abi_A7_unknown | FileCheck %s 
--check-prefix=UNKNOWN_A7
 
+
+# RUN: llvm-mc -filetype=obj -triple=riscv64  x3_reg_usage_unknown.s -o 
x3_reg_usage_unknown.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64  x3_reg_usage_gp.s -o 
x3_reg_usage_gp.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64  x3_reg_usage_scs.s -o 
x3_reg_usage_scs.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64  x3_reg_usage_tmp.s -o 
x3_reg_usage_tmp.o
+
+# RUN: not ld.lld x3_reg_usage_scs.o x3_reg_usage_gp.o -o /dev/null 2>&1 | 
FileCheck %s --check-prefix=X3_REG_SCS_GP --implicit-check-not=error:
+# X3_REG_SCS_GP: error: x3_reg_usage_scs.o:(.riscv.attributes) has 
x3_reg_usage=2 but x3_reg_usage_gp.o:(.riscv.attributes) has x3_reg_usage=1
+
+# RUN: not ld.lld x3_reg_usage_scs.o x3_reg_usage_tmp.o -o /dev/null 2>&1 | 
FileCheck %s --check-prefix=X3_REG_SCS_TMP --implicit-check-not=error:
+# X3_REG_SCS_TMP: error: x3_reg_usage_scs.o:(.riscv.attributes) has 
x3_reg_usage=2 but x3_reg_usage_tmp.o:(.riscv.attributes) has x3_reg_usage=3
+
+
+# RUN: ld.lld x3_reg_usage_scs.o x3_reg_usage_unknown.o -o 
x3_reg_usage_scs_unknown
+# RUN: llvm-readobj -A x3_reg_usage_scs_unknown | FileCheck %s 
--check-prefix=X3_REG_SCS_UKNOWN
+
+
 ## The deprecated priv_spec is not handled as GNU ld does.
 ## Differing priv_spec attributes lead to an absent attribute.
 # RUN: llvm-mc -filetype=obj -triple=riscv64 diff_priv_spec.s -o 
diff_priv_spec.o
@@ -412,6 +429,40 @@
 # A6S_A7:   }
 # A6S_A7: }
 
+#--- x3_reg_usage_unknown.s
+.attribute x3_reg_usage, 0
+
+#--- x3_reg_usage_gp.s
+.attribute x3_reg_usage, 1
+
+#--- x3_reg_usage_scs.s
+.attribute x3_reg_usage, 2
+
+#--- x3_reg_usage_tmp.s
+.attribute x3_reg_usage, 3
+
+
+# X3_REG_SCS_UKNOWN: BuildAttributes {
+# X3_REG_SCS_UKNOWN:   FormatVersion: 0x41
+# X3_REG_SCS_UKNOWN:   Section 1 {
+# X3_REG_SCS_UKNOWN: SectionLength: 17
+# X3_REG_SCS_UKNOWN: Vendor: riscv
+# X3_REG_SCS_UKNOWN: Tag: Tag_File (0x1)
+# X3_REG_SCS_UKNOWN: Size: 7
+# X3_REG_SCS_UKNOWN: FileAttributes {
+# X3_REG_SCS_UKNOWN:   Attribute {
+# X3_REG_SCS_UKNOWN: Tag: 16
+# X3_REG_SCS_UKNOWN: Value: 2
+# X3_REG_SCS_UKNOWN: TagName: x3_reg_usage
+# X3_REG_SCS_UKNOWN: Description: X3 reg usage is 2
+# X3_REG_SCS_UKNOWN:   }
+# X3_REG_SCS_UKNOWN: }
+# X3_REG_SCS_UKNOWN:   }
+# X3_REG_SCS_UKNOWN: }
+
+
+
+
 #--- unknown13.s
 .attribute 13, "0"
 #--- unknown13a.s
diff --git a/llvm/include/llvm/Support/RISCVAttributeParser.h 
b/llvm/include/llvm/Support/

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

[via llvm-branch-commits]

llvmbot wrote:



@llvm/pr-subscribers-lld-elf

@llvm/pr-subscribers-lld

Author: Paul Kirth (ilovepi)


Changes

This patch adds basic support for the Tag_RISCV_x3_reg_usage attribute
specified in:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_x3_reg_usage-16-uleb128value
It adds support for merging the x3_reg_usage attribute in the linker,
and basic support for the attribute in attribute parser.

Enabling this feature will allow targets to avoid challenges with mixing
object files with different expectations for how x3/gp is used.

Merging x3_reg_usage tags with different values is considered an error,
with one exception. The value 0 can merge with 1 or 2 value. After the
merge, the resulting value will be the non-zero one.


---
Full diff: https://github.com/llvm/llvm-project/pull/84598.diff


9 Files Affected:

- (modified) lld/ELF/Arch/RISCV.cpp (+12) 
- (modified) lld/test/ELF/riscv-attributes.s (+51) 
- (modified) llvm/include/llvm/Support/RISCVAttributeParser.h (+1) 
- (modified) llvm/include/llvm/Support/RISCVAttributes.h (+10) 
- (modified) llvm/lib/Support/RISCVAttributeParser.cpp (+7) 
- (modified) llvm/lib/Support/RISCVAttributes.cpp (+1) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+5) 
- (modified) llvm/test/MC/RISCV/attribute.s (+3) 
- (modified) llvm/test/MC/RISCV/invalid-attribute.s (+3) 


``diff
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index e44583fb80fd31..f3b134144b654b 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -1224,6 +1224,18 @@ mergeAttributesSection(const 
SmallVector §ions) {
   }
 }
 continue;
+
+  case llvm::RISCVAttrs::AttrType::X3_REG_USAGE:
+if (auto i = parser.getAttributeValue(tag.attr)) {
+  auto r = merged.intAttr.try_emplace(tag.attr, *i);
+  if (r.second) {
+firstX3RegUse = sec;
+  } else {
+mergeX3RegUse(merged.intAttr, firstX3RegUse, sec,
+  r.first->getSecond(), *i);
+  }
+}
+continue;
   }
 
   // Fallback for deprecated priv_spec* and other unknown attributes: 
retain
diff --git a/lld/test/ELF/riscv-attributes.s b/lld/test/ELF/riscv-attributes.s
index 964fec43b52847..43438b238b5d6b 100644
--- a/lld/test/ELF/riscv-attributes.s
+++ b/lld/test/ELF/riscv-attributes.s
@@ -68,6 +68,23 @@
 # RUN: ld.lld atomic_abi_unknown.o atomic_abi_A7.o -o atomic_abi_A7_unknown
 # RUN: llvm-readobj -A atomic_abi_A7_unknown | FileCheck %s 
--check-prefix=UNKNOWN_A7
 
+
+# RUN: llvm-mc -filetype=obj -triple=riscv64  x3_reg_usage_unknown.s -o 
x3_reg_usage_unknown.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64  x3_reg_usage_gp.s -o 
x3_reg_usage_gp.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64  x3_reg_usage_scs.s -o 
x3_reg_usage_scs.o
+# RUN: llvm-mc -filetype=obj -triple=riscv64  x3_reg_usage_tmp.s -o 
x3_reg_usage_tmp.o
+
+# RUN: not ld.lld x3_reg_usage_scs.o x3_reg_usage_gp.o -o /dev/null 2>&1 | 
FileCheck %s --check-prefix=X3_REG_SCS_GP --implicit-check-not=error:
+# X3_REG_SCS_GP: error: x3_reg_usage_scs.o:(.riscv.attributes) has 
x3_reg_usage=2 but x3_reg_usage_gp.o:(.riscv.attributes) has x3_reg_usage=1
+
+# RUN: not ld.lld x3_reg_usage_scs.o x3_reg_usage_tmp.o -o /dev/null 2>&1 | 
FileCheck %s --check-prefix=X3_REG_SCS_TMP --implicit-check-not=error:
+# X3_REG_SCS_TMP: error: x3_reg_usage_scs.o:(.riscv.attributes) has 
x3_reg_usage=2 but x3_reg_usage_tmp.o:(.riscv.attributes) has x3_reg_usage=3
+
+
+# RUN: ld.lld x3_reg_usage_scs.o x3_reg_usage_unknown.o -o 
x3_reg_usage_scs_unknown
+# RUN: llvm-readobj -A x3_reg_usage_scs_unknown | FileCheck %s 
--check-prefix=X3_REG_SCS_UKNOWN
+
+
 ## The deprecated priv_spec is not handled as GNU ld does.
 ## Differing priv_spec attributes lead to an absent attribute.
 # RUN: llvm-mc -filetype=obj -triple=riscv64 diff_priv_spec.s -o 
diff_priv_spec.o
@@ -412,6 +429,40 @@
 # A6S_A7:   }
 # A6S_A7: }
 
+#--- x3_reg_usage_unknown.s
+.attribute x3_reg_usage, 0
+
+#--- x3_reg_usage_gp.s
+.attribute x3_reg_usage, 1
+
+#--- x3_reg_usage_scs.s
+.attribute x3_reg_usage, 2
+
+#--- x3_reg_usage_tmp.s
+.attribute x3_reg_usage, 3
+
+
+# X3_REG_SCS_UKNOWN: BuildAttributes {
+# X3_REG_SCS_UKNOWN:   FormatVersion: 0x41
+# X3_REG_SCS_UKNOWN:   Section 1 {
+# X3_REG_SCS_UKNOWN: SectionLength: 17
+# X3_REG_SCS_UKNOWN: Vendor: riscv
+# X3_REG_SCS_UKNOWN: Tag: Tag_File (0x1)
+# X3_REG_SCS_UKNOWN: Size: 7
+# X3_REG_SCS_UKNOWN: FileAttributes {
+# X3_REG_SCS_UKNOWN:   Attribute {
+# X3_REG_SCS_UKNOWN: Tag: 16
+# X3_REG_SCS_UKNOWN: Value: 2
+# X3_REG_SCS_UKNOWN: TagName: x3_reg_usage
+# X3_REG_SCS_UKNOWN: Description: X3 reg usage is 2
+# X3_REG_SCS_UKNOWN:   }
+# X3_REG_SCS_UKNOWN: }
+# X3_REG_SCS_UKNOWN:   }
+# X3_REG_SCS_UKNOWN: }
+
+
+
+
 #--- unknown13.s
 .attribute 13, "0"
 #--- unknown13a.s
diff --git a/llvm/include/llvm/Support/RISCVAttributeParser.h

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

[Paul Kirth via llvm-branch-commits]

https://github.com/ilovepi updated 
https://github.com/llvm/llvm-project/pull/84598


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[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

[Paul Kirth via llvm-branch-commits]

https://github.com/ilovepi updated 
https://github.com/llvm/llvm-project/pull/84598


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[llvm-branch-commits] [llvm] release/18.x: [X86] Add missing subvector_subreg_lowering for BF16 (#83720) (PR #84491)

[Freddy Ye via llvm-branch-commits]

https://github.com/FreddyLeaf approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/84491
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