llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Wang Pengcheng (wangpc-pp) <details> <summary>Changes</summary> Reduce some duplications and make it easy to follow. We can optimize segment copies later. --- Full diff: https://github.com/llvm/llvm-project/pull/84455.diff 1 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+75-81) ``````````diff diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index fd1b76cd45cde2..7895e87702c711 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -302,71 +302,6 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned VVOpc, VIOpc; - switch (LMul) { - default: - llvm_unreachable("Impossible LMUL for vector register copy."); - case RISCVII::LMUL_1: - Opc = RISCV::VMV1R_V; - SubRegIdx = RISCV::sub_vrm1_0; - VVOpc = RISCV::PseudoVMV_V_V_M1; - VIOpc = RISCV::PseudoVMV_V_I_M1; - break; - case RISCVII::LMUL_2: - Opc = RISCV::VMV2R_V; - SubRegIdx = RISCV::sub_vrm2_0; - VVOpc = RISCV::PseudoVMV_V_V_M2; - VIOpc = RISCV::PseudoVMV_V_I_M2; - break; - case RISCVII::LMUL_4: - Opc = RISCV::VMV4R_V; - SubRegIdx = RISCV::sub_vrm4_0; - VVOpc = RISCV::PseudoVMV_V_V_M4; - VIOpc = RISCV::PseudoVMV_V_I_M4; - break; - case RISCVII::LMUL_8: - assert(NF == 1); - Opc = RISCV::VMV8R_V; - SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0. - VVOpc = RISCV::PseudoVMV_V_V_M8; - VIOpc = RISCV::PseudoVMV_V_I_M8; - break; - } - - bool UseVMV_V_V = false; - bool UseVMV_V_I = false; - MachineBasicBlock::const_iterator DefMBBI; - if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) { - UseVMV_V_V = true; - Opc = VVOpc; - - if (DefMBBI->getOpcode() == VIOpc) { - UseVMV_V_I = true; - Opc = VIOpc; - } - } - - if (NF == 1) { - auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg); - if (UseVMV_V_V) - MIB.addReg(DstReg, RegState::Undef); - if (UseVMV_V_I) - MIB = MIB.add(DefMBBI->getOperand(2)); - else - MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc)); - if (UseVMV_V_V) { - const MCInstrDesc &Desc = DefMBBI->getDesc(); - MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL - MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW - MIB.addImm(0); // tu, mu - MIB.addReg(RISCV::VL, RegState::Implicit); - MIB.addReg(RISCV::VTYPE, RegState::Implicit); - } - return; - } - int I = 0, End = NF, Incr = 1; unsigned SrcEncoding = TRI->getEncodingValue(SrcReg); unsigned DstEncoding = TRI->getEncodingValue(DstReg); @@ -381,23 +316,82 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, } for (; I != End; I += Incr) { - auto MIB = - BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx + I)); - if (UseVMV_V_V) - MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef); - if (UseVMV_V_I) - MIB = MIB.add(DefMBBI->getOperand(2)); - else - MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I), - getKillRegState(KillSrc)); - if (UseVMV_V_V) { - const MCInstrDesc &Desc = DefMBBI->getDesc(); - MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL - MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW - MIB.addImm(0); // tu, mu - MIB.addReg(RISCV::VL, RegState::Implicit); - MIB.addReg(RISCV::VTYPE, RegState::Implicit); + auto GetCopyInfo = + [](RISCVII::VLMUL LMul,unsigned NF) -> std::tuple<unsigned, unsigned, unsigned, unsigned> { + unsigned Opc; + unsigned SubRegIdx; + unsigned VVOpc, VIOpc; + switch (LMul) { + default: + llvm_unreachable("Impossible LMUL for vector register copy."); + case RISCVII::LMUL_1: + Opc = RISCV::VMV1R_V; + SubRegIdx = RISCV::sub_vrm1_0; + VVOpc = RISCV::PseudoVMV_V_V_M1; + VIOpc = RISCV::PseudoVMV_V_I_M1; + break; + case RISCVII::LMUL_2: + Opc = RISCV::VMV2R_V; + SubRegIdx = RISCV::sub_vrm2_0; + VVOpc = RISCV::PseudoVMV_V_V_M2; + VIOpc = RISCV::PseudoVMV_V_I_M2; + break; + case RISCVII::LMUL_4: + Opc = RISCV::VMV4R_V; + SubRegIdx = RISCV::sub_vrm4_0; + VVOpc = RISCV::PseudoVMV_V_V_M4; + VIOpc = RISCV::PseudoVMV_V_I_M4; + break; + case RISCVII::LMUL_8: + assert(NF == 1); + Opc = RISCV::VMV8R_V; + SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0. + VVOpc = RISCV::PseudoVMV_V_V_M8; + VIOpc = RISCV::PseudoVMV_V_I_M8; + break; + } + return {SubRegIdx, Opc, VVOpc, VIOpc}; + }; + + auto [SubRegIdx, Opc, VVOpc, VIOpc] = GetCopyInfo(LMul, NF); + + MachineBasicBlock::const_iterator DefMBBI; + if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) { + Opc = VVOpc; + + if (DefMBBI->getOpcode() == VIOpc) { + Opc = VIOpc; + } + } + + auto EmitCopy = [&](MCRegister SrcReg, MCRegister DstReg, unsigned Opcode) { + auto MIB = BuildMI(MBB, MBBI, DL, get(Opcode), DstReg); + bool UseVMV_V_I = RISCV::getRVVMCOpcode(Opcode) == RISCV::VMV_V_I; + bool UseVMV = + UseVMV_V_I || RISCV::getRVVMCOpcode(Opcode) == RISCV::VMV_V_V; + if (UseVMV) + MIB.addReg(DstReg, RegState::Undef); + if (UseVMV_V_I) + MIB = MIB.add(DefMBBI->getOperand(2)); + else + MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc)); + if (UseVMV) { + const MCInstrDesc &Desc = DefMBBI->getDesc(); + MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL + MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW + MIB.addImm(0); // tu, mu + MIB.addReg(RISCV::VL, RegState::Implicit); + MIB.addReg(RISCV::VTYPE, RegState::Implicit); + } + }; + + if (NF == 1) { + EmitCopy(SrcReg, DstReg, Opc); + return; } + + EmitCopy(TRI->getSubReg(SrcReg, SubRegIdx + I), + TRI->getSubReg(DstReg, SubRegIdx + I), Opc); } } `````````` </details> https://github.com/llvm/llvm-project/pull/84455 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
