[llvm-branch-commits] [llvm] cddd3fa - [CSKY] Add visibility macro to fix link error

[Zi Xuan Wu via llvm-branch-commits]

Author: Zi Xuan Wu
Date: 2021-01-11T16:18:01+08:00
New Revision: cddd3faf5debdfd2c09bb5b723f579fa8c8d5027

URL: 
https://github.com/llvm/llvm-project/commit/cddd3faf5debdfd2c09bb5b723f579fa8c8d5027
DIFF: 
https://github.com/llvm/llvm-project/commit/cddd3faf5debdfd2c09bb5b723f579fa8c8d5027.diff

LOG: [CSKY] Add visibility macro to fix link error

Add LLVM_EXTERNAL_VISIBILITY macro to fix link error of
https://reviews.llvm.org/D88466#2476378

Added: 


Modified: 
llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp

Removed: 




diff  --git a/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp 
b/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
index 800b10517aa7..1af2e672ff42 100644
--- a/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
+++ b/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
@@ -15,6 +15,6 @@ Target &llvm::getTheCSKYTarget() {
   return TheCSKYTarget;
 }
 
-extern "C" void LLVMInitializeCSKYTargetInfo() {
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYTargetInfo() {
   RegisterTarget X(getTheCSKYTarget(), "csky", "C-SKY", "CSKY");
 }



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[llvm-branch-commits] [clang] ee27c76 - [clang-format] Skip UTF8 Byte Order Mark while sorting includes

[Marek Kurdej via llvm-branch-commits]

Author: Rafał Jelonek
Date: 2021-01-11T09:32:55+01:00
New Revision: ee27c767bd2062c81f0affc0e8992f60a755f099

URL: 
https://github.com/llvm/llvm-project/commit/ee27c767bd2062c81f0affc0e8992f60a755f099
DIFF: 
https://github.com/llvm/llvm-project/commit/ee27c767bd2062c81f0affc0e8992f60a755f099.diff

LOG: [clang-format] Skip UTF8 Byte Order Mark while sorting includes

If file contain BOM then first instruction (include or clang-format off) is 
ignored

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D94201

Added: 


Modified: 
clang/lib/Format/Format.cpp
clang/unittests/Format/SortIncludesTest.cpp

Removed: 




diff  --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp
index 54424ae190e2..5adfed5f3d32 100644
--- a/clang/lib/Format/Format.cpp
+++ b/clang/lib/Format/Format.cpp
@@ -2253,7 +2253,9 @@ tooling::Replacements sortCppIncludes(const FormatStyle 
&Style, StringRef Code,
   StringRef FileName,
   tooling::Replacements &Replaces,
   unsigned *Cursor) {
-  unsigned Prev = 0;
+  unsigned Prev = llvm::StringSwitch(Code)
+  .StartsWith("\xEF\xBB\xBF", 3) // UTF-8 BOM
+  .Default(0);
   unsigned SearchFrom = 0;
   llvm::Regex IncludeRegex(CppIncludeRegexPattern);
   SmallVector Matches;

diff  --git a/clang/unittests/Format/SortIncludesTest.cpp 
b/clang/unittests/Format/SortIncludesTest.cpp
index d64c97820003..6dc9d9850c59 100644
--- a/clang/unittests/Format/SortIncludesTest.cpp
+++ b/clang/unittests/Format/SortIncludesTest.cpp
@@ -879,6 +879,42 @@ TEST_F(SortIncludesTest, 
DoNotRegroupGroupsInGoogleObjCStyle) {
  "#include \"a.h\""));
 }
 
+TEST_F(SortIncludesTest, skipUTF8ByteOrderMarkMerge) {
+  Style.IncludeBlocks = Style.IBS_Merge;
+  std::string Code = "\xEF\xBB\xBF#include \"d.h\"\r\n"
+ "#include \"b.h\"\r\n"
+ "\r\n"
+ "#include \"c.h\"\r\n"
+ "#include \"a.h\"\r\n"
+ "#include \"e.h\"\r\n";
+
+  std::string Expected = "\xEF\xBB\xBF#include \"e.h\"\r\n"
+ "#include \"a.h\"\r\n"
+ "#include \"b.h\"\r\n"
+ "#include \"c.h\"\r\n"
+ "#include \"d.h\"\r\n";
+
+  EXPECT_EQ(Expected, sort(Code, "e.cpp", 1));
+}
+
+TEST_F(SortIncludesTest, skipUTF8ByteOrderMarkPreserve) {
+  Style.IncludeBlocks = Style.IBS_Preserve;
+  std::string Code = "\xEF\xBB\xBF#include \"d.h\"\r\n"
+ "#include \"b.h\"\r\n"
+ "\r\n"
+ "#include \"c.h\"\r\n"
+ "#include \"a.h\"\r\n"
+ "#include \"e.h\"\r\n";
+
+  std::string Expected = "\xEF\xBB\xBF#include \"b.h\"\r\n"
+ "#include \"d.h\"\r\n"
+ "\r\n"
+ "#include \"a.h\"\r\n"
+ "#include \"c.h\"\r\n"
+ "#include \"e.h\"\r\n";
+
+  EXPECT_EQ(Expected, sort(Code, "e.cpp", 2));
+}
 } // end namespace
 } // end namespace format
 } // end namespace clang



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[llvm-branch-commits] [llvm] 0c8b748 - [ARM] Additional trunc cost tests. NFC

[David Green via llvm-branch-commits]

Author: David Green
Date: 2021-01-11T08:35:16Z
New Revision: 0c8b748f321736d016da0f6d710778f503a89b51

URL: 
https://github.com/llvm/llvm-project/commit/0c8b748f321736d016da0f6d710778f503a89b51
DIFF: 
https://github.com/llvm/llvm-project/commit/0c8b748f321736d016da0f6d710778f503a89b51.diff

LOG: [ARM] Additional trunc cost tests. NFC

Added: 


Modified: 
llvm/test/Analysis/CostModel/ARM/cast.ll

Removed: 




diff  --git a/llvm/test/Analysis/CostModel/ARM/cast.ll 
b/llvm/test/Analysis/CostModel/ARM/cast.ll
index b539dae1585e..3dc55674a131 100644
--- a/llvm/test/Analysis/CostModel/ARM/cast.ll
+++ b/llvm/test/Analysis/CostModel/ARM/cast.ll
@@ -124,8 +124,15 @@ define i32 @casts() {
 ; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 2 for 
instruction: %rext_9 = zext <2 x i16> undef to <2 x i64>
 ; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 1 for 
instruction: %rext_a = sext <2 x i32> undef to <2 x i64>
 ; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 1 for 
instruction: %rext_b = zext <2 x i32> undef to <2 x i64>
-; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 3 for 
instruction: %r74 = trunc <8 x i32> undef to <8 x i8>
-; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 6 for 
instruction: %r75 = trunc <16 x i32> undef to <16 x i8>
+; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 1 for 
instruction: %tv4i32i8 = trunc <4 x i32> undef to <4 x i8>
+; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 1 for 
instruction: %tv4i32i16 = trunc <4 x i32> undef to <4 x i16>
+; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 0 for 
instruction: %tv4i16i8 = trunc <4 x i16> undef to <4 x i8>
+; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 3 for 
instruction: %tv8i32i8 = trunc <8 x i32> undef to <8 x i8>
+; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 3 for 
instruction: %tv8i32i16 = trunc <8 x i32> undef to <8 x i16>
+; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 1 for 
instruction: %tv8i16i8 = trunc <8 x i16> undef to <8 x i8>
+; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 6 for 
instruction: %tv16i32i8 = trunc <16 x i32> undef to <16 x i8>
+; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 6 for 
instruction: %tv16i32i16 = trunc <16 x i32> undef to <16 x i16>
+; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 3 for 
instruction: %tv16i16i8 = trunc <16 x i16> undef to <16 x i8>
 ; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 1 for 
instruction: %r80df = fptrunc double undef to float
 ; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 2 for 
instruction: %r81df = fptrunc <2 x double> undef to <2 x float>
 ; CHECK-NEON-RECIP-NEXT:  Cost Model: Found an estimated cost of 4 for 
instruction: %r82df = fptrunc <4 x double> undef to <4 x float>
@@ -511,8 +518,15 @@ define i32 @casts() {
 ; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 4 for 
instruction: %rext_9 = zext <2 x i16> undef to <2 x i64>
 ; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 16 for 
instruction: %rext_a = sext <2 x i32> undef to <2 x i64>
 ; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 4 for 
instruction: %rext_b = zext <2 x i32> undef to <2 x i64>
-; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 2 for 
instruction: %r74 = trunc <8 x i32> undef to <8 x i8>
-; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 10 for 
instruction: %r75 = trunc <16 x i32> undef to <16 x i8>
+; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 0 for 
instruction: %tv4i32i8 = trunc <4 x i32> undef to <4 x i8>
+; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 0 for 
instruction: %tv4i32i16 = trunc <4 x i32> undef to <4 x i16>
+; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 0 for 
instruction: %tv4i16i8 = trunc <4 x i16> undef to <4 x i8>
+; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 2 for 
instruction: %tv8i32i8 = trunc <8 x i32> undef to <8 x i8>
+; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 2 for 
instruction: %tv8i32i16 = trunc <8 x i32> undef to <8 x i16>
+; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 0 for 
instruction: %tv8i16i8 = trunc <8 x i16> undef to <8 x i8>
+; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 10 for 
instruction: %tv16i32i8 = trunc <16 x i32> undef to <16 x i8>
+; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 8 for 
instruction: %tv16i32i16 = trunc <16 x i32> undef to <16 x i16>
+; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 2 for 
instruction: %tv16i16i8 = trunc <16 x i16> undef to <16 x i8>
 ; CHECK-MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 10 for 
instruction: %

[llvm-branch-commits] [clang] 7473940 - [clang-format] turn on formatting after "clang-format on" while sorting includes

[Marek Kurdej via llvm-branch-commits]

Author: Rafał Jelonek
Date: 2021-01-11T09:41:15+01:00
New Revision: 7473940bae0f263832456d2c99a4bd606ed0d76e

URL: 
https://github.com/llvm/llvm-project/commit/7473940bae0f263832456d2c99a4bd606ed0d76e
DIFF: 
https://github.com/llvm/llvm-project/commit/7473940bae0f263832456d2c99a4bd606ed0d76e.diff

LOG: [clang-format] turn on formatting after "clang-format on" while sorting 
includes

Formatting is not active after "clang-format on" due to merging lines while 
formatting is off. Also, use trimmed line. Behaviour with LF is different than 
with CRLF.

Reviewed By: curdeius, MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D94206

Added: 


Modified: 
clang/lib/Format/Format.cpp
clang/unittests/Format/SortIncludesTest.cpp

Removed: 




diff  --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp
index 5adfed5f3d32..37b6c4c8a20e 100644
--- a/clang/lib/Format/Format.cpp
+++ b/clang/lib/Format/Format.cpp
@@ -2291,7 +2291,8 @@ tooling::Replacements sortCppIncludes(const FormatStyle 
&Style, StringRef Code,
  Style.IncludeStyle.IncludeBlocks ==
  tooling::IncludeStyle::IBS_Regroup);
 
-if (!FormattingOff && !Line.endswith("\\")) {
+bool MergeWithNextLine = Trimmed.endswith("\\");
+if (!FormattingOff && !MergeWithNextLine) {
   if (IncludeRegex.match(Line, &Matches)) {
 StringRef IncludeName = Matches[2];
 int Category = Categories.getIncludePriority(
@@ -2309,10 +2310,12 @@ tooling::Replacements sortCppIncludes(const FormatStyle 
&Style, StringRef Code,
 IncludesInBlock.clear();
 FirstIncludeBlock = false;
   }
-  Prev = Pos + 1;
 }
 if (Pos == StringRef::npos || Pos + 1 == Code.size())
   break;
+
+if (!MergeWithNextLine)
+  Prev = Pos + 1;
 SearchFrom = Pos + 1;
   }
   if (!IncludesInBlock.empty()) {

diff  --git a/clang/unittests/Format/SortIncludesTest.cpp 
b/clang/unittests/Format/SortIncludesTest.cpp
index 6dc9d9850c59..f2f0e9391ece 100644
--- a/clang/unittests/Format/SortIncludesTest.cpp
+++ b/clang/unittests/Format/SortIncludesTest.cpp
@@ -207,6 +207,27 @@ TEST_F(SortIncludesTest, SupportClangFormatOff) {
  "#include \n"
  "#include \n"
  "// clang-format on\n"));
+
+  Style.IncludeBlocks = Style.IBS_Merge;
+  std::string Code = "// clang-format off\r\n"
+ "#include \"d.h\"\r\n"
+ "#include \"b.h\"\r\n"
+ "// clang-format on\r\n"
+ "\r\n"
+ "#include \"c.h\"\r\n"
+ "#include \"a.h\"\r\n"
+ "#include \"e.h\"\r\n";
+
+  std::string Expected = "// clang-format off\r\n"
+ "#include \"d.h\"\r\n"
+ "#include \"b.h\"\r\n"
+ "// clang-format on\r\n"
+ "\r\n"
+ "#include \"e.h\"\r\n"
+ "#include \"a.h\"\r\n"
+ "#include \"c.h\"\r\n";
+
+  EXPECT_EQ(Expected, sort(Code, "e.cpp", 1));
 }
 
 TEST_F(SortIncludesTest, SupportClangFormatOffCStyle) {
@@ -915,6 +936,22 @@ TEST_F(SortIncludesTest, skipUTF8ByteOrderMarkPreserve) {
 
   EXPECT_EQ(Expected, sort(Code, "e.cpp", 2));
 }
+
+TEST_F(SortIncludesTest, MergeLines) {
+  Style.IncludeBlocks = Style.IBS_Merge;
+  std::string Code = "#include \"c.h\"\r\n"
+ "#include \"b\\\r\n"
+ ".h\"\r\n"
+ "#include \"a.h\"\r\n";
+
+  std::string Expected = "#include \"a.h\"\r\n"
+ "#include \"b\\\r\n"
+ ".h\"\r\n"
+ "#include \"c.h\"\r\n";
+
+  EXPECT_EQ(Expected, sort(Code, "a.cpp", 1));
+}
+
 } // end namespace
 } // end namespace format
 } // end namespace clang



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[llvm-branch-commits] [clang] 89878e8 - [clang-format] Find main include after block ended with #pragma hdrstop

[Marek Kurdej via llvm-branch-commits]

Author: Rafał Jelonek
Date: 2021-01-11T09:49:34+01:00
New Revision: 89878e8c966a82ed6b7f0254700017f0a97fb7d7

URL: 
https://github.com/llvm/llvm-project/commit/89878e8c966a82ed6b7f0254700017f0a97fb7d7
DIFF: 
https://github.com/llvm/llvm-project/commit/89878e8c966a82ed6b7f0254700017f0a97fb7d7.diff

LOG: [clang-format] Find main include after block ended with #pragma hdrstop

Find main include in first include block not ended with #pragma hdrstop

Reviewed By: curdeius

Differential Revision: https://reviews.llvm.org/D94217

Added: 


Modified: 
clang/lib/Format/Format.cpp
clang/unittests/Format/SortIncludesTest.cpp

Removed: 




diff  --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp
index 37b6c4c8a20e..fc62a3419d48 100644
--- a/clang/lib/Format/Format.cpp
+++ b/clang/lib/Format/Format.cpp
@@ -2308,7 +2308,10 @@ tooling::Replacements sortCppIncludes(const FormatStyle 
&Style, StringRef Code,
 sortCppIncludes(Style, IncludesInBlock, Ranges, FileName, Code,
 Replaces, Cursor);
 IncludesInBlock.clear();
-FirstIncludeBlock = false;
+if (Trimmed.startswith("#pragma hdrstop")) // Precompiled headers.
+  FirstIncludeBlock = true;
+else
+  FirstIncludeBlock = false;
   }
 }
 if (Pos == StringRef::npos || Pos + 1 == Code.size())

diff  --git a/clang/unittests/Format/SortIncludesTest.cpp 
b/clang/unittests/Format/SortIncludesTest.cpp
index f2f0e9391ece..41ff7afad10e 100644
--- a/clang/unittests/Format/SortIncludesTest.cpp
+++ b/clang/unittests/Format/SortIncludesTest.cpp
@@ -900,6 +900,45 @@ TEST_F(SortIncludesTest, 
DoNotRegroupGroupsInGoogleObjCStyle) {
  "#include \"a.h\""));
 }
 
+TEST_F(SortIncludesTest, DoNotTreatPrecompiledHeadersAsFirstBlock) {
+  Style.IncludeBlocks = Style.IBS_Merge;
+  std::string Code = "#include \"d.h\"\r\n"
+ "#include \"b.h\"\r\n"
+ "#pragma hdrstop\r\n"
+ "\r\n"
+ "#include \"c.h\"\r\n"
+ "#include \"a.h\"\r\n"
+ "#include \"e.h\"\r\n";
+
+  std::string Expected = "#include \"b.h\"\r\n"
+ "#include \"d.h\"\r\n"
+ "#pragma hdrstop\r\n"
+ "\r\n"
+ "#include \"e.h\"\r\n"
+ "#include \"a.h\"\r\n"
+ "#include \"c.h\"\r\n";
+
+  EXPECT_EQ(Expected, sort(Code, "e.cpp", 2));
+
+  Code = "#include \"d.h\"\n"
+ "#include \"b.h\"\n"
+ "#pragma hdrstop( \"c:\\projects\\include\\myinc.pch\" )\n"
+ "\n"
+ "#include \"c.h\"\n"
+ "#include \"a.h\"\n"
+ "#include \"e.h\"\n";
+
+  Expected = "#include \"b.h\"\n"
+ "#include \"d.h\"\n"
+ "#pragma hdrstop(\"c:\\projects\\include\\myinc.pch\")\n"
+ "\n"
+ "#include \"e.h\"\n"
+ "#include \"a.h\"\n"
+ "#include \"c.h\"\n";
+
+  EXPECT_EQ(Expected, sort(Code, "e.cpp", 2));
+}
+
 TEST_F(SortIncludesTest, skipUTF8ByteOrderMarkMerge) {
   Style.IncludeBlocks = Style.IBS_Merge;
   std::string Code = "\xEF\xBB\xBF#include \"d.h\"\r\n"



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[llvm-branch-commits] [llvm] dcefcd5 - [ARM] Update trunc costs

[David Green via llvm-branch-commits]

Author: David Green
Date: 2021-01-11T08:59:28Z
New Revision: dcefcd51e01741c79c9d9a729fe803b13287a372

URL: 
https://github.com/llvm/llvm-project/commit/dcefcd51e01741c79c9d9a729fe803b13287a372
DIFF: 
https://github.com/llvm/llvm-project/commit/dcefcd51e01741c79c9d9a729fe803b13287a372.diff

LOG: [ARM] Update trunc costs

We did not have specific costs for larger than legal truncates that were
not otherwise cheap (where they were next to stores, for example). As
MVE does not have a dedicated instruction for them (and we do not use
loads/stores yet), they should be expensive as they get expanded to a
series of lane moves.

Differential Revision: https://reviews.llvm.org/D94260

Added: 


Modified: 
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/test/Analysis/CostModel/ARM/arith-overflow.ll
llvm/test/Analysis/CostModel/ARM/cast.ll
llvm/test/Analysis/CostModel/ARM/mve-gather-scatter-cost.ll

Removed: 




diff  --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp 
b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
index 0dc0afe271d1..a75c771e66be 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -491,6 +491,7 @@ int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type 
*Dst, Type *Src,
 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i8, 0},
 {ISD::TRUNCATE, MVT::v8i16, MVT::v8i8, 0},
 {ISD::TRUNCATE, MVT::v8i32, MVT::v8i16, 1},
+{ISD::TRUNCATE, MVT::v8i32, MVT::v8i8, 1},
 {ISD::TRUNCATE, MVT::v16i32, MVT::v16i8, 3},
 {ISD::TRUNCATE, MVT::v16i16, MVT::v16i8, 1},
 };
@@ -751,6 +752,18 @@ int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type 
*Dst, Type *Src,
   return Lanes * CallCost;
   }
 
+  if (ISD == ISD::TRUNCATE && ST->hasMVEIntegerOps() &&
+  SrcTy.isFixedLengthVector()) {
+// Treat a truncate with larger than legal source (128bits for MVE) as
+// expensive, 2 instructions per lane.
+if ((SrcTy.getScalarType() == MVT::i8 ||
+ SrcTy.getScalarType() == MVT::i16 ||
+ SrcTy.getScalarType() == MVT::i32) &&
+SrcTy.getSizeInBits() > 128 &&
+SrcTy.getSizeInBits() > DstTy.getSizeInBits())
+  return SrcTy.getVectorNumElements() * 2;
+  }
+
   // Scalar integer conversion costs.
   static const TypeConversionCostTblEntry ARMIntegerConversionTbl[] = {
 // i16 -> i64 requires two dependent operations.

diff  --git a/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll 
b/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll
index 25b268b9b244..172df8600356 100644
--- a/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll
+++ b/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll
@@ -707,13 +707,13 @@ define i32 @smul(i32 %arg) {
 ; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 316 for instruction: 
%V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> 
undef, <8 x i32> undef)
 ; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 1208 for 
instruction: %V16I32 = call { <16 x i32>, <16 x i1> } 
@llvm.smul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef)
 ; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: 
%I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef)
-; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 34 for instruction: 
%V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> 
undef, <8 x i16> undef)
-; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 116 for instruction: 
%V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x 
i16> undef, <16 x i16> undef)
-; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 424 for instruction: 
%V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x 
i16> undef, <32 x i16> undef)
+; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 62 for instruction: 
%V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> 
undef, <8 x i16> undef)
+; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 164 for instruction: 
%V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x 
i16> undef, <16 x i16> undef)
+; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 488 for instruction: 
%V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x 
i16> undef, <32 x i16> undef)
 ; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: 
%I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef)
-; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 34 for instruction: 
%V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> 
undef, <16 x i8> undef)
-; MVE-RECIP-NEXT:  Cost Model: Found an estimated cost of 116 for instruction: 
%V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> 
undef, <3

[llvm-branch-commits] [llvm] b7ccaca - [NFC] Remove min/max functions from InstructionCost

[David Sherwood via llvm-branch-commits]

Author: David Sherwood
Date: 2021-01-11T09:00:12Z
New Revision: b7ccaca53700fce21b0e8e5d7bd2a956bd391fee

URL: 
https://github.com/llvm/llvm-project/commit/b7ccaca53700fce21b0e8e5d7bd2a956bd391fee
DIFF: 
https://github.com/llvm/llvm-project/commit/b7ccaca53700fce21b0e8e5d7bd2a956bd391fee.diff

LOG: [NFC] Remove min/max functions from InstructionCost

Removed the InstructionCost::min/max functions because it's
fine to use std::min/max instead.

Differential Revision: https://reviews.llvm.org/D94301

Added: 


Modified: 
llvm/include/llvm/Support/InstructionCost.h
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/unittests/Support/InstructionCostTest.cpp

Removed: 




diff  --git a/llvm/include/llvm/Support/InstructionCost.h 
b/llvm/include/llvm/Support/InstructionCost.h
index fe56d49b4174..725f8495ac09 100644
--- a/llvm/include/llvm/Support/InstructionCost.h
+++ b/llvm/include/llvm/Support/InstructionCost.h
@@ -196,14 +196,6 @@ class InstructionCost {
 return *this >= RHS2;
   }
 
-  static InstructionCost min(InstructionCost LHS, InstructionCost RHS) {
-return LHS < RHS ? LHS : RHS;
-  }
-
-  static InstructionCost max(InstructionCost LHS, InstructionCost RHS) {
-return LHS > RHS ? LHS : RHS;
-  }
-
   void print(raw_ostream &OS) const;
 };
 

diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp 
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 5b91495bd844..bd673d112b3a 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -6305,7 +6305,7 @@ bool SLPVectorizerPass::tryToVectorizeList(ArrayRef VL, BoUpSLP &R,
 Cost -= UserCost;
   }
 
-  MinCost = InstructionCost::min(MinCost, Cost);
+  MinCost = std::min(MinCost, Cost);
 
   if (Cost.isValid() && Cost < -SLPCostThreshold) {
 LLVM_DEBUG(dbgs() << "SLP: Vectorizing list at cost:" << Cost << 
".\n");

diff  --git a/llvm/unittests/Support/InstructionCostTest.cpp 
b/llvm/unittests/Support/InstructionCostTest.cpp
index da3d3f47a212..8ba9f990f027 100644
--- a/llvm/unittests/Support/InstructionCostTest.cpp
+++ b/llvm/unittests/Support/InstructionCostTest.cpp
@@ -59,6 +59,6 @@ TEST_F(CostTest, Operators) {
   EXPECT_EQ(*(VThree.getValue()), 3);
   EXPECT_EQ(IThreeA.getValue(), None);
 
-  EXPECT_EQ(InstructionCost::min(VThree, VNegTwo), -2);
-  EXPECT_EQ(InstructionCost::max(VThree, VSix), 6);
+  EXPECT_EQ(std::min(VThree, VNegTwo), -2);
+  EXPECT_EQ(std::max(VThree, VSix), 6);
 }



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[llvm-branch-commits] [llvm] 9710064 - Reapply "[clang][cli] Port DiagnosticOpts to new option parsing system"

[Jan Svoboda via llvm-branch-commits]

Author: Jan Svoboda
Date: 2021-01-11T10:05:53+01:00
New Revision: 97100646d1b4526de1eac3aacdb0b098739c6ec9

URL: 
https://github.com/llvm/llvm-project/commit/97100646d1b4526de1eac3aacdb0b098739c6ec9
DIFF: 
https://github.com/llvm/llvm-project/commit/97100646d1b4526de1eac3aacdb0b098739c6ec9.diff

LOG: Reapply "[clang][cli] Port DiagnosticOpts to new option parsing system"

This reverts commit 8e3e148c

This commit fixes two issues with the original patch:
* The sanitizer build bot reported an uninitialized value. This was caused by 
normalizeStringIntegral not returning None on failure.
* Some build bots complained about inaccessible keypaths. To mitigate that, 
"this->" was added back to the keypath to restore the previous behavior.

Added: 


Modified: 
clang/include/clang/Basic/DiagnosticOptions.h
clang/include/clang/Driver/Options.td
clang/lib/Frontend/CompilerInvocation.cpp
clang/unittests/Frontend/CompilerInvocationTest.cpp
llvm/include/llvm/Option/OptParser.td
llvm/utils/TableGen/OptParserEmitter.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/DiagnosticOptions.h 
b/clang/include/clang/Basic/DiagnosticOptions.h
index 7fbe534c5994..17533b38ff5f 100644
--- a/clang/include/clang/Basic/DiagnosticOptions.h
+++ b/clang/include/clang/Basic/DiagnosticOptions.h
@@ -15,7 +15,14 @@
 #include 
 #include 
 
+namespace llvm {
+namespace opt {
+class ArgList;
+} // namespace opt
+} // namespace llvm
+
 namespace clang {
+class DiagnosticsEngine;
 
 /// Specifies which overload candidates to display when overload
 /// resolution fails.
@@ -61,6 +68,11 @@ raw_ostream& operator<<(raw_ostream& Out, 
DiagnosticLevelMask M);
 
 /// Options for controlling the compiler diagnostics engine.
 class DiagnosticOptions : public RefCountedBase{
+  friend bool ParseDiagnosticArgs(DiagnosticOptions &, llvm::opt::ArgList &,
+  clang::DiagnosticsEngine *, bool);
+
+  friend class CompilerInvocation;
+
 public:
   enum TextDiagnosticFormat { Clang, MSVC, Vi };
 

diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 741c28aa1f01..b18c89931cee 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -241,6 +241,8 @@ def mno_mpx : Flag<["-"], "mno-mpx">, 
Group;
 def clang_ignored_gcc_optimization_f_Group : OptionGroup<
   "">, Group, 
Flags<[Ignored]>;
 
+class IsDiag { string MacroPrefix = "DIAG_"; }
+
 // A boolean option which is opt-in in CC1. The positive option exists in CC1 
and
 // Args.hasArg(OPT_ffoo) is used to check that the flag is enabled.
 // This is useful if the option is usually disabled.
@@ -755,7 +757,7 @@ def Wp_COMMA : CommaJoined<["-"], "Wp,">,
 def Wundef_prefix_EQ : CommaJoined<["-"], "Wundef-prefix=">, 
Group,
   Flags<[CC1Option, CoreOption, HelpHidden]>, MetaVarName<"">,
   HelpText<"Enable warnings for undefined macros with a prefix in the comma 
separated list ">,
-  MarshallingInfoStringVector<"DiagnosticOpts->UndefPrefixes">;
+  MarshallingInfoStringVector<"UndefPrefixes">, IsDiag;
 def Wwrite_strings : Flag<["-"], "Wwrite-strings">, Group, 
Flags<[CC1Option, HelpHidden]>;
 def Wno_write_strings : Flag<["-"], "Wno-write-strings">, Group, 
Flags<[CC1Option, HelpHidden]>;
 def W_Joined : Joined<["-"], "W">, Group, Flags<[CC1Option, 
CoreOption]>,
@@ -1188,7 +1190,9 @@ defm borland_extensions : 
BoolFOption<"borland-extensions",
 def fbuiltin : Flag<["-"], "fbuiltin">, Group, Flags<[CoreOption]>;
 def fbuiltin_module_map : Flag <["-"], "fbuiltin-module-map">, Group,
   Flags<[NoXarchOption]>, HelpText<"Load the clang builtins module map file.">;
-defm caret_diagnostics : OptOutFFlag<"caret-diagnostics", "", "">;
+defm caret_diagnostics : BoolFOption<"caret-diagnostics",
+  "ShowCarets", DefaultsToTrue,
+  ChangedBy, ResetBy>, IsDiag;
 def fclang_abi_compat_EQ : Joined<["-"], "fclang-abi-compat=">, 
Group,
   Flags<[CC1Option]>, MetaVarName<"">, 
Values<".,latest">,
   HelpText<"Attempt to match the ABI of Clang ">;
@@ -1200,7 +1204,7 @@ def fdiagnostics_color : Flag<["-"], 
"fdiagnostics-color">, Group,
 def fdiagnostics_color_EQ : Joined<["-"], "fdiagnostics-color=">, 
Group;
 def fansi_escape_codes : Flag<["-"], "fansi-escape-codes">, Group,
   Flags<[CoreOption, CC1Option]>, HelpText<"Use ANSI escape codes for 
diagnostics">,
-  MarshallingInfoFlag<"DiagnosticOpts->UseANSIEscapeCodes">;
+  MarshallingInfoFlag<"UseANSIEscapeCodes">, IsDiag;
 def fcomment_block_commands : CommaJoined<["-"], "fcomment-block-commands=">, 
Group, Flags<[CC1Option]>,
   HelpText<"Treat each comma separated argument in  as a documentation 
comment block command">,
   MetaVarName<"">, 
MarshallingInfoStringVector<"LangOpts->CommentOpts.BlockCommandNames">;
@@ -1253,11 +1257,16 @@ def fdebug_pass_structure : Flag<["-"], 
"fdebug-pass-structure">, Group
 def fdepfile_entry : Joined<["-"], "fd

[llvm-branch-commits] [llvm] 40abeb1 - [NFC][InstructionCost] Change LoopVectorizationCostModel::getInstructionCost to return InstructionCost

[David Sherwood via llvm-branch-commits]

Author: David Sherwood
Date: 2021-01-11T09:22:37Z
New Revision: 40abeb11f4584e8a07163d6c7e24011ac45f104c

URL: 
https://github.com/llvm/llvm-project/commit/40abeb11f4584e8a07163d6c7e24011ac45f104c
DIFF: 
https://github.com/llvm/llvm-project/commit/40abeb11f4584e8a07163d6c7e24011ac45f104c.diff

LOG: [NFC][InstructionCost] Change 
LoopVectorizationCostModel::getInstructionCost to return InstructionCost

This patch is part of a series of patches that migrate integer
instruction costs to use InstructionCost. In the function
selectVectorizationFactor I have simply asserted that the cost
is valid and extracted the value as is. In future we expect
to encounter invalid costs, but we should filter out those
vectorization factors that lead to such invalid costs.

See this patch for the introduction of the type: https://reviews.llvm.org/D91174
See this thread for context: 
http://lists.llvm.org/pipermail/llvm-dev/2020-November/146408.html

Differential Revision: https://reviews.llvm.org/D92178

Added: 


Modified: 
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp 
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 180cbb8ef847..e6cadf8f8796 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -130,6 +130,7 @@
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/InstructionCost.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
@@ -1635,7 +1636,7 @@ class LoopVectorizationCostModel {
   /// is
   /// false, then all operations will be scalarized (i.e. no vectorization has
   /// actually taken place).
-  using VectorizationCostTy = std::pair;
+  using VectorizationCostTy = std::pair;
 
   /// Returns the expected execution cost. The unit of the cost does
   /// not matter because we use the 'cost' units to compare 
diff erent
@@ -1649,7 +1650,8 @@ class LoopVectorizationCostModel {
 
   /// The cost-computation logic from getInstructionCost which provides
   /// the vector type as an output parameter.
-  unsigned getInstructionCost(Instruction *I, ElementCount VF, Type 
*&VectorTy);
+  InstructionCost getInstructionCost(Instruction *I, ElementCount VF,
+ Type *&VectorTy);
 
   /// Calculate vectorization cost of memory instruction \p I.
   unsigned getMemoryInstructionCost(Instruction *I, ElementCount VF);
@@ -1693,7 +1695,7 @@ class LoopVectorizationCostModel {
   /// A type representing the costs for instructions if they were to be
   /// scalarized rather than vectorized. The entries are Instruction-Cost
   /// pairs.
-  using ScalarCostsTy = DenseMap;
+  using ScalarCostsTy = DenseMap;
 
   /// A set containing all BasicBlocks that are known to present after
   /// vectorization as a predicated block.
@@ -5759,10 +5761,13 @@ 
LoopVectorizationCostModel::selectVectorizationFactor(ElementCount MaxVF) {
   // vectors when the loop has a hint to enable vectorization for a given VF.
   assert(!MaxVF.isScalable() && "scalable vectors not yet supported");
 
-  float Cost = expectedCost(ElementCount::getFixed(1)).first;
-  const float ScalarCost = Cost;
+  InstructionCost ExpectedCost = expectedCost(ElementCount::getFixed(1)).first;
+  LLVM_DEBUG(dbgs() << "LV: Scalar loop costs: " << ExpectedCost << ".\n");
+  assert(ExpectedCost.isValid() && "Unexpected invalid cost for scalar loop");
+
   unsigned Width = 1;
-  LLVM_DEBUG(dbgs() << "LV: Scalar loop costs: " << (int)ScalarCost << ".\n");
+  const float ScalarCost = *ExpectedCost.getValue();
+  float Cost = ScalarCost;
 
   bool ForceVectorization = Hints->getForce() == 
LoopVectorizeHints::FK_Enabled;
   if (ForceVectorization && MaxVF.isVector()) {
@@ -5777,7 +5782,8 @@ 
LoopVectorizationCostModel::selectVectorizationFactor(ElementCount MaxVF) {
 // we need to divide the cost of the vector loops by the width of
 // the vector elements.
 VectorizationCostTy C = expectedCost(ElementCount::getFixed(i));
-float VectorCost = C.first / (float)i;
+assert(C.first.isValid() && "Unexpected invalid cost for vector loop");
+float VectorCost = *C.first.getValue() / (float)i;
 LLVM_DEBUG(dbgs() << "LV: Vector loop of width " << i
   << " costs: " << (int)VectorCost << ".\n");
 if (!C.second && !ForceVectorization) {
@@ -6119,8 +6125,10 @@ unsigned 
LoopVectorizationCostModel::selectInterleaveCount(ElementCount VF,
 
   // If we did not calculate the cost for VF (because the user selected the VF)
   // then we calculate the cost of VF here.
-  if (LoopCost == 0)
-LoopCost = expectedCost(VF).first;
+  if (LoopCost == 0) {
+assert(expectedCost(VF).first.isValid() && "Expected a valid cost");
+L

[llvm-branch-commits] [llvm] 8165a03 - [ARM] Add debug messages for the load store optimizer. NFC

[David Green via llvm-branch-commits]

Author: David Green
Date: 2021-01-11T09:24:28Z
New Revision: 8165a0342033e58ce6090fbc425ebdc7c455469f

URL: 
https://github.com/llvm/llvm-project/commit/8165a0342033e58ce6090fbc425ebdc7c455469f
DIFF: 
https://github.com/llvm/llvm-project/commit/8165a0342033e58ce6090fbc425ebdc7c455469f.diff

LOG: [ARM] Add debug messages for the load store optimizer. NFC

Added: 


Modified: 
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Removed: 




diff  --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp 
b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index a5da50608087..5144cf953e99 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -1268,6 +1268,7 @@ findIncDecAfter(MachineBasicBlock::iterator MBBI, 
Register Reg,
 bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineInstr *MI) {
   // Thumb1 is already using updating loads/stores.
   if (isThumb1) return false;
+  LLVM_DEBUG(dbgs() << "Attempting to merge update of: " << *MI);
 
   const MachineOperand &BaseOP = MI->getOperand(0);
   Register Base = BaseOP.getReg();
@@ -1319,8 +1320,10 @@ bool 
ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineInstr *MI) {
 return false;
 }
   }
-  if (MergeInstr != MBB.end())
+  if (MergeInstr != MBB.end()) {
+LLVM_DEBUG(dbgs() << "  Erasing old increment: " << *MergeInstr);
 MBB.erase(MergeInstr);
+  }
 
   unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
@@ -1335,6 +1338,7 @@ bool 
ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineInstr *MI) {
   // Transfer memoperands.
   MIB.setMemRefs(MI->memoperands());
 
+  LLVM_DEBUG(dbgs() << "  Added new load/store: " << *MIB);
   MBB.erase(MBBI);
   return true;
 }
@@ -1445,6 +1449,7 @@ bool 
ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
   // Thumb1 doesn't have updating LDR/STR.
   // FIXME: Use LDM/STM with single register instead.
   if (isThumb1) return false;
+  LLVM_DEBUG(dbgs() << "Attempting to merge update of: " << *MI);
 
   Register Base = getLoadStoreBaseOp(*MI).getReg();
   bool BaseKill = getLoadStoreBaseOp(*MI).isKill();
@@ -1486,6 +1491,7 @@ bool 
ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
 } else
   return false;
   }
+  LLVM_DEBUG(dbgs() << "  Erasing old increment: " << *MergeInstr);
   MBB.erase(MergeInstr);
 
   ARM_AM::AddrOpc AddSub = Offset < 0 ? ARM_AM::sub : ARM_AM::add;
@@ -1497,39 +1503,50 @@ bool 
ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
 // updating load/store-multiple instructions can be used with only one
 // register.)
 MachineOperand &MO = MI->getOperand(0);
-BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
-  .addReg(Base, getDefRegState(true)) // WB base register
-  .addReg(Base, getKillRegState(isLd ? BaseKill : false))
-  .addImm(Pred).addReg(PredReg)
-  .addReg(MO.getReg(), (isLd ? getDefRegState(true) :
-getKillRegState(MO.isKill(
-  .cloneMemRefs(*MI);
+auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
+   .addReg(Base, getDefRegState(true)) // WB base register
+   .addReg(Base, getKillRegState(isLd ? BaseKill : false))
+   .addImm(Pred)
+   .addReg(PredReg)
+   .addReg(MO.getReg(), (isLd ? getDefRegState(true)
+  : getKillRegState(MO.isKill(
+   .cloneMemRefs(*MI);
+LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
   } else if (isLd) {
 if (isAM2) {
   // LDR_PRE, LDR_POST
   if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
-BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
-  .addReg(Base, RegState::Define)
-  .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg)
-  .cloneMemRefs(*MI);
+auto MIB =
+BuildMI(MBB, MBBI, DL, TII->get(NewOpc), 
MI->getOperand(0).getReg())
+.addReg(Base, RegState::Define)
+.addReg(Base)
+.addImm(Offset)
+.addImm(Pred)
+.addReg(PredReg)
+.cloneMemRefs(*MI);
+LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
   } else {
 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
-BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
-.addReg(Base, RegState::Define)
-.addReg(Base)
-.addReg(0)
-.addImm(Imm)
-.add(predOps(Pred, PredReg))
-.cloneMemRefs(*MI);
+auto MIB =
+BuildMI(MBB, MBBI, DL, TII->get(NewOpc), 
MI->getOperand(0).getReg())
+.addReg(Base, RegState::Define)
+.addReg(Base)
+.addRe

[llvm-branch-commits] [clang-tools-extra] 1677c86 - [clangd] Add metrics for go-to-implementation.

[Haojian Wu via llvm-branch-commits]

Author: Haojian Wu
Date: 2021-01-11T10:26:50+01:00
New Revision: 1677c86124e5b82a8dbf991f2d5fc450d06db4ad

URL: 
https://github.com/llvm/llvm-project/commit/1677c86124e5b82a8dbf991f2d5fc450d06db4ad
DIFF: 
https://github.com/llvm/llvm-project/commit/1677c86124e5b82a8dbf991f2d5fc450d06db4ad.diff

LOG: [clangd] Add metrics for go-to-implementation.

Differential Revision: https://reviews.llvm.org/D94393

Added: 


Modified: 
clang-tools-extra/clangd/XRefs.cpp

Removed: 




diff  --git a/clang-tools-extra/clangd/XRefs.cpp 
b/clang-tools-extra/clangd/XRefs.cpp
index 667a90aa2efb..8bb74ed7ae43 100644
--- a/clang-tools-extra/clangd/XRefs.cpp
+++ b/clang-tools-extra/clangd/XRefs.cpp
@@ -298,6 +298,17 @@ std::vector 
findImplementors(llvm::DenseSet IDs,
 llvm::StringRef MainFilePath) {
   if (IDs.empty())
 return {};
+  static constexpr trace::Metric FindImplementorsMetric(
+  "find_implementors", trace::Metric::Counter, "case");
+  switch (Predicate) {
+  case RelationKind::BaseOf:
+FindImplementorsMetric.record(1, "find-base");
+break;
+  case RelationKind::OverriddenBy:
+FindImplementorsMetric.record(1, "find-override");
+break;
+  }
+
   RelationsRequest Req;
   Req.Predicate = Predicate;
   Req.Subjects = std::move(IDs);



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[llvm-branch-commits] [llvm] c5be0e0 - [X86] Fix tile register spill issue.

[via llvm-branch-commits]

Author: Luo, Yuanke
Date: 2021-01-11T18:35:09+08:00
New Revision: c5be0e0cc0e2fca19a5d130b742ae16c66f99111

URL: 
https://github.com/llvm/llvm-project/commit/c5be0e0cc0e2fca19a5d130b742ae16c66f99111
DIFF: 
https://github.com/llvm/llvm-project/commit/c5be0e0cc0e2fca19a5d130b742ae16c66f99111.diff

LOG: [X86] Fix tile register spill issue.

The tile register spill need 2 instructions.
%46:gr64_nosp = MOV64ri 64
TILESTORED %stack.2, 1, killed %46:gr64_nosp, 0, $noreg, %43:tile
The first instruction load the stride to a GPR, and the second
instruction store tile register to stack slot. The optimization of merge
spill instruction is done after register allocation. And spill tile
register need create a new virtual register to for stride, so we can't
hoist tile spill instruction in postOptimization() of register
allocation. We can't hoist TILESTORED alone and we can't hoist the 2
instuctions together because MOV64ri will clobber some GPR. This patch
is to disble the spill merge for any spill which need 2 instructions.

Differential Revision: https://reviews.llvm.org/D93898

Added: 
llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll

Modified: 
llvm/lib/CodeGen/InlineSpiller.cpp

Removed: 




diff  --git a/llvm/lib/CodeGen/InlineSpiller.cpp 
b/llvm/lib/CodeGen/InlineSpiller.cpp
index 02f7721c219a..81ab9e5ab738 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -269,6 +269,14 @@ static Register isFullCopyOf(const MachineInstr &MI, 
Register Reg) {
   return Register();
 }
 
+static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) {
+  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
+const MachineOperand &MO = MI.getOperand(I);
+if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
+  LIS.getInterval(MO.getReg());
+  }
+}
+
 /// isSnippet - Identify if a live interval is a snippet that should be 
spilled.
 /// It is assumed that SnipLI is a virtual register with the same original as
 /// Edit->getReg().
@@ -410,14 +418,21 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval 
&SpillLI,
 MII = DefMI;
 ++MII;
   }
+  MachineInstrSpan MIS(MII, MBB);
   // Insert spill without kill flag immediately after def.
   TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
   MRI.getRegClass(SrcReg), &TRI);
+  LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII);
+  for (const MachineInstr &MI : make_range(MIS.begin(), MII))
+getVDefInterval(MI, LIS);
   --MII; // Point to store instruction.
-  LIS.InsertMachineInstrInMaps(*MII);
   LLVM_DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII);
 
-  HSpiller.addToMergeableSpills(*MII, StackSlot, Original);
+  // If there is only 1 store instruction is required for spill, add it
+  // to mergeable list. In X86 AMX, 2 intructions are required to store.
+  // We disable the merge for this case.
+  if (std::distance(MIS.begin(), MII) <= 1)
+HSpiller.addToMergeableSpills(*MII, StackSlot, Original);
   ++NumSpills;
   return true;
 }
@@ -918,7 +933,11 @@ foldMemoryOperand(ArrayRef> Ops,
 ++NumFolded;
   else if (Ops.front().second == 0) {
 ++NumSpills;
-HSpiller.addToMergeableSpills(*FoldMI, StackSlot, Original);
+// If there is only 1 store instruction is required for spill, add it
+// to mergeable list. In X86 AMX, 2 intructions are required to store.
+// We disable the merge for this case.
+if (std::distance(MIS.begin(), MIS.end()) <= 1)
+  HSpiller.addToMergeableSpills(*FoldMI, StackSlot, Original);
   } else
 ++NumReloads;
   return true;
@@ -965,6 +984,7 @@ void InlineSpiller::insertSpill(Register NewVReg, bool 
isKill,
   MachineInstrSpan MIS(MI, &MBB);
   MachineBasicBlock::iterator SpillBefore = std::next(MI);
   bool IsRealSpill = isRealSpill(*MI);
+
   if (IsRealSpill)
 TII.storeRegToStackSlot(MBB, SpillBefore, NewVReg, isKill, StackSlot,
 MRI.getRegClass(NewVReg), &TRI);
@@ -978,11 +998,16 @@ void InlineSpiller::insertSpill(Register NewVReg, bool 
isKill,
 
   MachineBasicBlock::iterator Spill = std::next(MI);
   LIS.InsertMachineInstrRangeInMaps(Spill, MIS.end());
+  for (const MachineInstr &MI : make_range(Spill, MIS.end()))
+getVDefInterval(MI, LIS);
 
   LLVM_DEBUG(
   dumpMachineInstrRangeWithSlotIndex(Spill, MIS.end(), LIS, "spill"));
   ++NumSpills;
-  if (IsRealSpill)
+  // If there is only 1 store instruction is required for spill, add it
+  // to mergeable list. In X86 AMX, 2 intructions are required to store.
+  // We disable the merge for this case.
+  if (IsRealSpill && std::distance(Spill, MIS.end()) <= 1)
 HSpiller.addToMergeableSpills(*Spill, StackSlot, Original);
 }
 
@@ -1529,9 +1554,12 @@ void HoistSpillHelper::hoistAllSpills() {
   MachineBasicBlock *BB = Insert.first;
   Register LiveReg = Insert.second;
   MachineBasicBlock

[llvm-branch-commits] [llvm] 675be65 - Require chained analyses in BasicAA and AAResults to be transitive

[Bjorn Pettersson via llvm-branch-commits]

Author: Bjorn Pettersson
Date: 2021-01-11T11:50:07+01:00
New Revision: 675be651062476cd0cd4b491b35c275bb03d7b2c

URL: 
https://github.com/llvm/llvm-project/commit/675be651062476cd0cd4b491b35c275bb03d7b2c
DIFF: 
https://github.com/llvm/llvm-project/commit/675be651062476cd0cd4b491b35c275bb03d7b2c.diff

LOG: Require chained analyses in BasicAA and AAResults to be transitive

This patch fixes a bug that could result in miscompiles (at least
in an OOT target). The problem could be seen by adding checks that
the DominatorTree used in BasicAliasAnalysis and ValueTracking was
valid (e.g. by adding DT->verify() call before every DT dereference
and then running all tests in test/CodeGen).

Problem was that the LegacyPassManager calculated "last user"
incorrectly for passes such as the DominatorTree when not telling
the pass manager that there was a transitive dependency between
the different analyses. And then it could happen that an incorrect
dominator tree was used when doing alias analysis (which was a pretty
serious bug as the alias analysis result could be invalid).

Fixes: https://bugs.llvm.org/show_bug.cgi?id=48709

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D94138

Added: 


Modified: 
llvm/lib/Analysis/AliasAnalysis.cpp
llvm/lib/Analysis/BasicAliasAnalysis.cpp
llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
llvm/lib/Transforms/Scalar/GVNHoist.cpp

Removed: 




diff  --git a/llvm/lib/Analysis/AliasAnalysis.cpp 
b/llvm/lib/Analysis/AliasAnalysis.cpp
index f5b62ef06a23..fae7a84332fd 100644
--- a/llvm/lib/Analysis/AliasAnalysis.cpp
+++ b/llvm/lib/Analysis/AliasAnalysis.cpp
@@ -883,8 +883,8 @@ bool AAResultsWrapperPass::runOnFunction(Function &F) {
 
 void AAResultsWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.setPreservesAll();
-  AU.addRequired();
-  AU.addRequired();
+  AU.addRequiredTransitive();
+  AU.addRequiredTransitive();
 
   // We also need to mark all the alias analysis passes we will potentially
   // probe in runOnFunction as used here to ensure the legacy pass manager

diff  --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp 
b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
index 1440906944eb..313a85ccc4de 100644
--- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp
+++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
@@ -1899,9 +1899,9 @@ bool BasicAAWrapperPass::runOnFunction(Function &F) {
 
 void BasicAAWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.setPreservesAll();
-  AU.addRequired();
-  AU.addRequired();
-  AU.addRequired();
+  AU.addRequiredTransitive();
+  AU.addRequiredTransitive();
+  AU.addRequiredTransitive();
   AU.addUsedIfAvailable();
 }
 

diff  --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp 
b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
index 68c79d2a113f..76cc8f402c5a 100644
--- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
@@ -165,7 +165,6 @@ class HexagonLoopIdiomRecognizeLegacyPass : public LoopPass 
{
 AU.addRequiredID(LoopSimplifyID);
 AU.addRequiredID(LCSSAID);
 AU.addRequired();
-AU.addPreserved();
 AU.addRequired();
 AU.addRequired();
 AU.addRequired();

diff  --git a/llvm/lib/Transforms/Scalar/GVNHoist.cpp 
b/llvm/lib/Transforms/Scalar/GVNHoist.cpp
index e2b40942f300..8d0bd5674964 100644
--- a/llvm/lib/Transforms/Scalar/GVNHoist.cpp
+++ b/llvm/lib/Transforms/Scalar/GVNHoist.cpp
@@ -547,7 +547,6 @@ class GVNHoistLegacyPass : public FunctionPass {
 AU.addPreserved();
 AU.addPreserved();
 AU.addPreserved();
-AU.addPreserved();
   }
 };
 



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[llvm-branch-commits] [llvm] c37f68a - [SVE][CodeGen] Fix legalisation of floating-point masked gathers

[Kerry McLaughlin via llvm-branch-commits]

Author: Kerry McLaughlin
Date: 2021-01-11T10:57:46Z
New Revision: c37f68a8885cf55e9a6603613a918c4e7474e9af

URL: 
https://github.com/llvm/llvm-project/commit/c37f68a8885cf55e9a6603613a918c4e7474e9af
DIFF: 
https://github.com/llvm/llvm-project/commit/c37f68a8885cf55e9a6603613a918c4e7474e9af.diff

LOG: [SVE][CodeGen] Fix legalisation of floating-point masked gathers

Changes in this patch:
- When lowering floating-point masked gathers, cast the result of the
  gather back to the original type with reinterpret_cast before returning.
- Added patterns for reinterpret_casts from integer to floating point, and
  concat_vector patterns for bfloat16.
- Tests for various legalisation scenarios with floating point types.

Reviewed By: sdesmalen, david-arm

Differential Revision: https://reviews.llvm.org/D94171

Added: 


Modified: 
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll

Removed: 




diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp 
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 1dff16234bbd..b4cb62cd5348 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1167,6 +1167,7 @@ AArch64TargetLowering::AArch64TargetLowering(const 
TargetMachine &TM,
 }
 
 for (auto VT : {MVT::nxv2bf16, MVT::nxv4bf16, MVT::nxv8bf16}) {
+  setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
   setOperationAction(ISD::MGATHER, VT, Custom);
   setOperationAction(ISD::MSCATTER, VT, Custom);
 }
@@ -3990,7 +3991,6 @@ SDValue AArch64TargetLowering::LowerMGATHER(SDValue Op,
 
   // Handle FP data
   if (VT.isFloatingPoint()) {
-VT = VT.changeVectorElementTypeToInteger();
 ElementCount EC = VT.getVectorElementCount();
 auto ScalarIntVT =
 MVT::getIntegerVT(AArch64::SVEBitsPerBlock / EC.getKnownMinValue());
@@ -4013,7 +4013,14 @@ SDValue AArch64TargetLowering::LowerMGATHER(SDValue Op,
 Opcode = getSignExtendedGatherOpcode(Opcode);
 
   SDValue Ops[] = {Chain, Mask, BasePtr, Index, InputVT, PassThru};
-  return DAG.getNode(Opcode, DL, VTs, Ops);
+  SDValue Gather = DAG.getNode(Opcode, DL, VTs, Ops);
+
+  if (VT.isFloatingPoint()) {
+SDValue Cast = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, VT, Gather);
+return DAG.getMergeValues({Cast, Gather}, DL);
+  }
+
+  return Gather;
 }
 
 SDValue AArch64TargetLowering::LowerMSCATTER(SDValue Op,

diff  --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td 
b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index f5ccbee0f232..50368199effb 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1183,6 +1183,10 @@ let Predicates = [HasSVE] in {
 (UZP1_ZZZ_H $v1, $v2)>;
   def : Pat<(nxv4f32 (concat_vectors nxv2f32:$v1, nxv2f32:$v2)),
 (UZP1_ZZZ_S $v1, $v2)>;
+  def : Pat<(nxv4bf16 (concat_vectors nxv2bf16:$v1, nxv2bf16:$v2)),
+(UZP1_ZZZ_S $v1, $v2)>;
+  def : Pat<(nxv8bf16 (concat_vectors nxv4bf16:$v1, nxv4bf16:$v2)),
+(UZP1_ZZZ_H $v1, $v2)>;
 
   defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs", SETUGE, SETULE>;
   defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi", SETUGT, SETULT>;
@@ -1736,6 +1740,16 @@ let Predicates = [HasSVE] in {
   def : Pat<(nxv2i64 (reinterpret_cast (nxv2bf16 ZPR:$src))), 
(COPY_TO_REGCLASS ZPR:$src, ZPR)>;
   def : Pat<(nxv4i32 (reinterpret_cast (nxv4bf16 ZPR:$src))), 
(COPY_TO_REGCLASS ZPR:$src, ZPR)>;
 
+  def : Pat<(nxv2f16 (reinterpret_cast (nxv2i64 ZPR:$src))), (COPY_TO_REGCLASS 
ZPR:$src, ZPR)>;
+  def : Pat<(nxv2f32 (reinterpret_cast (nxv2i64 ZPR:$src))), (COPY_TO_REGCLASS 
ZPR:$src, ZPR)>;
+  def : Pat<(nxv2f64 (reinterpret_cast (nxv2i64 ZPR:$src))), (COPY_TO_REGCLASS 
ZPR:$src, ZPR)>;
+  def : Pat<(nxv4f16 (reinterpret_cast (nxv4i32 ZPR:$src))), (COPY_TO_REGCLASS 
ZPR:$src, ZPR)>;
+  def : Pat<(nxv4f32 (reinterpret_cast (nxv4i32 ZPR:$src))), (COPY_TO_REGCLASS 
ZPR:$src, ZPR)>;
+  def : Pat<(nxv8f16 (reinterpret_cast (nxv8i16 ZPR:$src))), (COPY_TO_REGCLASS 
ZPR:$src, ZPR)>;
+  def : Pat<(nxv2bf16 (reinterpret_cast (nxv2i64 ZPR:$src))), 
(COPY_TO_REGCLASS ZPR:$src, ZPR)>;
+  def : Pat<(nxv4bf16 (reinterpret_cast (nxv4i32 ZPR:$src))), 
(COPY_TO_REGCLASS ZPR:$src, ZPR)>;
+  def : Pat<(nxv8bf16 (reinterpret_cast (nxv8i16 ZPR:$src))), 
(COPY_TO_REGCLASS ZPR:$src, ZPR)>;
+
   def : Pat<(nxv16i1 (and PPR:$Ps1, PPR:$Ps2)),
 (AND_PPzPP (PTRUE_B 31), PPR:$Ps1, PPR:$Ps2)>;
   def : Pat<(nxv8i1 (and PPR:$Ps1, PPR:$Ps2)),

diff  --git a/llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll 
b/llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
index 6b1dc031dbb2..e71ec8178034 100644
--- a/llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
+++ b/llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
@@ -71,6 +

[llvm-branch-commits] [llvm] 41bf338 - Revert rGd43a264a5dd3 "Revert "[X86][SSE] Fold unpack(hop(), hop()) -> permute(hop())""

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-11T11:29:04Z
New Revision: 41bf338dd1e7f07c1e89f171ff6d53578f5125be

URL: 
https://github.com/llvm/llvm-project/commit/41bf338dd1e7f07c1e89f171ff6d53578f5125be
DIFF: 
https://github.com/llvm/llvm-project/commit/41bf338dd1e7f07c1e89f171ff6d53578f5125be.diff

LOG: Revert rGd43a264a5dd3 "Revert "[X86][SSE] Fold unpack(hop(),hop()) -> 
permute(hop())""

This reapplies commit rG80dee7965dffdfb866afa9d74f3a4a97453708b2.

[X86][SSE] Fold unpack(hop(),hop()) -> permute(hop())

UNPCKL/UNPCKH only uses one op from each hop, so we can merge the hops and then 
permute the result.

REAPPLIED with a fix for unary unpacks of HOP.

Added: 


Modified: 
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/horizontal-shuffle-2.ll

Removed: 




diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp 
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 16f1023ed5f8..7895f883863f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -37513,10 +37513,12 @@ static SDValue combineShuffleOfConcatUndef(SDNode *N, 
SelectionDAG &DAG,
 
 /// Eliminate a redundant shuffle of a horizontal math op.
 static SDValue foldShuffleOfHorizOp(SDNode *N, SelectionDAG &DAG) {
+  // TODO: Can we use getTargetShuffleInputs instead?
   unsigned Opcode = N->getOpcode();
   if (Opcode != X86ISD::MOVDDUP && Opcode != X86ISD::VBROADCAST)
-if (Opcode != ISD::VECTOR_SHUFFLE || !N->getOperand(1).isUndef())
-  return SDValue();
+if (Opcode != X86ISD::UNPCKL && Opcode != X86ISD::UNPCKH)
+  if (Opcode != ISD::VECTOR_SHUFFLE || !N->getOperand(1).isUndef())
+return SDValue();
 
   // For a broadcast, peek through an extract element of index 0 to find the
   // horizontal op: broadcast (ext_vec_elt HOp, 0)
@@ -37535,6 +37537,28 @@ static SDValue foldShuffleOfHorizOp(SDNode *N, 
SelectionDAG &DAG) {
   HOp.getOpcode() != X86ISD::HSUB && HOp.getOpcode() != X86ISD::FHSUB)
 return SDValue();
 
+  // unpcklo(hop(x,y),hop(z,w)) -> permute(hop(x,z)).
+  // unpckhi(hop(x,y),hop(z,w)) -> permute(hop(y,w)).
+  // Don't fold if hop(x,y) == hop(z,w).
+  if (Opcode == X86ISD::UNPCKL || Opcode == X86ISD::UNPCKH) {
+SDValue HOp2 = N->getOperand(1);
+if (HOp.getOpcode() != HOp2.getOpcode() || VT.getScalarSizeInBits() != 32)
+  return SDValue();
+if (HOp == HOp2)
+  return SDValue();
+SDLoc DL(HOp);
+unsigned LoHi = Opcode == X86ISD::UNPCKL ? 0 : 1;
+SDValue Res = DAG.getNode(HOp.getOpcode(), DL, VT, HOp.getOperand(LoHi),
+  HOp2.getOperand(LoHi));
+// Use SHUFPS for the permute so this will work on SSE3 targets, shuffle
+// combining and domain handling will simplify this later on.
+EVT ShuffleVT = VT.changeVectorElementType(MVT::f32);
+Res = DAG.getBitcast(ShuffleVT, Res);
+Res = DAG.getNode(X86ISD::SHUFP, DL, ShuffleVT, Res, Res,
+  getV4X86ShuffleImm8ForMask({0, 2, 1, 3}, DL, DAG));
+return DAG.getBitcast(VT, Res);
+  }
+
   // 128-bit horizontal math instructions are defined to operate on adjacent
   // lanes of each operand as:
   // v4X32: A[0] + A[1] , A[2] + A[3] , B[0] + B[1] , B[2] + B[3]

diff  --git a/llvm/test/CodeGen/X86/horizontal-shuffle-2.ll 
b/llvm/test/CodeGen/X86/horizontal-shuffle-2.ll
index c012c88c6ed2..4f747db94341 100644
--- a/llvm/test/CodeGen/X86/horizontal-shuffle-2.ll
+++ b/llvm/test/CodeGen/X86/horizontal-shuffle-2.ll
@@ -9,9 +9,8 @@
 define <4 x float> @test_unpacklo_hadd_v4f32(<4 x float> %0, <4 x float> %1, 
<4 x float> %2, <4 x float> %3) {
 ; CHECK-LABEL: test_unpacklo_hadd_v4f32:
 ; CHECK:   ## %bb.0:
-; CHECK-NEXT:vhaddps %xmm0, %xmm0, %xmm0
-; CHECK-NEXT:vhaddps %xmm0, %xmm2, %xmm1
-; CHECK-NEXT:vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT:vhaddps %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]
 ; CHECK-NEXT:ret{{[l|q]}}
   %5 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %0, <4 x 
float> %1) #4
   %6 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %2, <4 x 
float> %3) #4
@@ -22,9 +21,8 @@ define <4 x float> @test_unpacklo_hadd_v4f32(<4 x float> %0, 
<4 x float> %1, <4
 define <4 x float> @test_unpackhi_hadd_v4f32(<4 x float> %0, <4 x float> %1, 
<4 x float> %2, <4 x float> %3) {
 ; CHECK-LABEL: test_unpackhi_hadd_v4f32:
 ; CHECK:   ## %bb.0:
-; CHECK-NEXT:vhaddps %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:vhaddps %xmm3, %xmm0, %xmm1
-; CHECK-NEXT:vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT:vhaddps %xmm3, %xmm1, %xmm0
+; CHECK-NEXT:vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]
 ; CHECK-NEXT:ret{{[l|q]}}
   %5 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %0, <4 x 
float> %1) #4
   %6 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %2, <4 x 
float> %3) #4
@@ -

[llvm-branch-commits] [llvm] 5963229 - [X86][SSE] Add missing SSE test coverage for permute(hop, hop) folds

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-11T11:29:04Z
New Revision: 5963229266303d83b2e9de09bce7e063276e41d0

URL: 
https://github.com/llvm/llvm-project/commit/5963229266303d83b2e9de09bce7e063276e41d0
DIFF: 
https://github.com/llvm/llvm-project/commit/5963229266303d83b2e9de09bce7e063276e41d0.diff

LOG: [X86][SSE] Add missing SSE test coverage for permute(hop,hop) folds

Should help avoid bugs like reported in rG80dee7965dff

Added: 
llvm/test/CodeGen/X86/horizontal-shuffle-3.ll

Modified: 
llvm/test/CodeGen/X86/horizontal-shuffle-2.ll

Removed: 




diff  --git a/llvm/test/CodeGen/X86/horizontal-shuffle-2.ll 
b/llvm/test/CodeGen/X86/horizontal-shuffle-2.ll
index 4f747db94341..78c30e431574 100644
--- a/llvm/test/CodeGen/X86/horizontal-shuffle-2.ll
+++ b/llvm/test/CodeGen/X86/horizontal-shuffle-2.ll
@@ -1,17 +1,21 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx2 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s
-
-;
-; 128-bit Vectors
-;
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse4.1 | FileCheck %s 
--check-prefix=SSE
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx2 | FileCheck %s 
--check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s 
--check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s 
--check-prefix=AVX
 
 define <4 x float> @test_unpacklo_hadd_v4f32(<4 x float> %0, <4 x float> %1, 
<4 x float> %2, <4 x float> %3) {
-; CHECK-LABEL: test_unpacklo_hadd_v4f32:
-; CHECK:   ## %bb.0:
-; CHECK-NEXT:vhaddps %xmm2, %xmm0, %xmm0
-; CHECK-NEXT:vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; CHECK-NEXT:ret{{[l|q]}}
+; SSE-LABEL: test_unpacklo_hadd_v4f32:
+; SSE:   ## %bb.0:
+; SSE-NEXT:haddps %xmm2, %xmm0
+; SSE-NEXT:shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSE-NEXT:ret{{[l|q]}}
+;
+; AVX-LABEL: test_unpacklo_hadd_v4f32:
+; AVX:   ## %bb.0:
+; AVX-NEXT:vhaddps %xmm2, %xmm0, %xmm0
+; AVX-NEXT:vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX-NEXT:ret{{[l|q]}}
   %5 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %0, <4 x 
float> %1) #4
   %6 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %2, <4 x 
float> %3) #4
   %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> 
@@ -19,11 +23,18 @@ define <4 x float> @test_unpacklo_hadd_v4f32(<4 x float> 
%0, <4 x float> %1, <4
 }
 
 define <4 x float> @test_unpackhi_hadd_v4f32(<4 x float> %0, <4 x float> %1, 
<4 x float> %2, <4 x float> %3) {
-; CHECK-LABEL: test_unpackhi_hadd_v4f32:
-; CHECK:   ## %bb.0:
-; CHECK-NEXT:vhaddps %xmm3, %xmm1, %xmm0
-; CHECK-NEXT:vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; CHECK-NEXT:ret{{[l|q]}}
+; SSE-LABEL: test_unpackhi_hadd_v4f32:
+; SSE:   ## %bb.0:
+; SSE-NEXT:movaps %xmm1, %xmm0
+; SSE-NEXT:haddps %xmm3, %xmm0
+; SSE-NEXT:shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSE-NEXT:ret{{[l|q]}}
+;
+; AVX-LABEL: test_unpackhi_hadd_v4f32:
+; AVX:   ## %bb.0:
+; AVX-NEXT:vhaddps %xmm3, %xmm1, %xmm0
+; AVX-NEXT:vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX-NEXT:ret{{[l|q]}}
   %5 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %0, <4 x 
float> %1) #4
   %6 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %2, <4 x 
float> %3) #4
   %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> 
@@ -31,11 +42,17 @@ define <4 x float> @test_unpackhi_hadd_v4f32(<4 x float> 
%0, <4 x float> %1, <4
 }
 
 define <4 x float> @test_unpacklo_hsub_v4f32(<4 x float> %0, <4 x float> %1, 
<4 x float> %2, <4 x float> %3) {
-; CHECK-LABEL: test_unpacklo_hsub_v4f32:
-; CHECK:   ## %bb.0:
-; CHECK-NEXT:vhsubps %xmm2, %xmm0, %xmm0
-; CHECK-NEXT:vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; CHECK-NEXT:ret{{[l|q]}}
+; SSE-LABEL: test_unpacklo_hsub_v4f32:
+; SSE:   ## %bb.0:
+; SSE-NEXT:hsubps %xmm2, %xmm0
+; SSE-NEXT:shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; SSE-NEXT:ret{{[l|q]}}
+;
+; AVX-LABEL: test_unpacklo_hsub_v4f32:
+; AVX:   ## %bb.0:
+; AVX-NEXT:vhsubps %xmm2, %xmm0, %xmm0
+; AVX-NEXT:vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]
+; AVX-NEXT:ret{{[l|q]}}
   %5 = tail call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %0, <4 x 
float> %1) #4
   %6 = tail call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %2, <4 x 
float> %3) #4
   %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> 
@@ -43,11 +60,18 @@ define <4 x float> @test_unpacklo_hsub_v4f32(<4 x float> 
%0, <4 x float> %1, <4
 }
 
 define <4 x float> @test_unpackhi_hsub_v4f32(<4 x float> %0, <4 x float> %1, 
<4 x float> %2, <4 x float> %3) {
-; CHECK-LABEL: test_unpackhi_hsub_v4f32:
-; CHECK:   ## %bb.0:
-; CHECK-NEXT:vhsubps %xmm3, %xmm1, %xmm0
-; CHECK-NEXT:vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]
-; C

[llvm-branch-commits] [llvm] b72ca79 - [VE] Support intrinsic to isnert/extract_subreg of v512i1

[Kazushi Marukawa via llvm-branch-commits]

Author: Kazushi (Jam) Marukawa
Date: 2021-01-11T20:40:10+09:00
New Revision: b72ca799823e97b94ac0144bb87c094fb2db7324

URL: 
https://github.com/llvm/llvm-project/commit/b72ca799823e97b94ac0144bb87c094fb2db7324
DIFF: 
https://github.com/llvm/llvm-project/commit/b72ca799823e97b94ac0144bb87c094fb2db7324.diff

LOG: [VE] Support intrinsic to isnert/extract_subreg of v512i1

Support insert/extract_subreg intrinsic instructions for v512i1
registers and add regression tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D94298

Added: 
llvm/test/CodeGen/VE/VELIntrinsics/extract.ll
llvm/test/CodeGen/VE/VELIntrinsics/insert.ll

Modified: 
llvm/include/llvm/IR/IntrinsicsVE.td
llvm/lib/Target/VE/VEInstrIntrinsicVL.td

Removed: 




diff  --git a/llvm/include/llvm/IR/IntrinsicsVE.td 
b/llvm/include/llvm/IR/IntrinsicsVE.td
index 4e682eee7cc2..be4bccef0cc1 100644
--- a/llvm/include/llvm/IR/IntrinsicsVE.td
+++ b/llvm/include/llvm/IR/IntrinsicsVE.td
@@ -11,6 +11,24 @@ let TargetPrefix = "ve" in {
   def int_ve_vl_pack_f32a : GCCBuiltin<"__builtin_ve_vl_pack_f32a">,
 Intrinsic<[llvm_i64_ty], [llvm_ptr_ty],
   [IntrReadMem]>;
+
+  def int_ve_vl_extract_vm512u :
+  GCCBuiltin<"__builtin_ve_vl_extract_vm512u">,
+  Intrinsic<[LLVMType], [LLVMType], [IntrNoMem]>;
+
+  def int_ve_vl_extract_vm512l :
+  GCCBuiltin<"__builtin_ve_vl_extract_vm512l">,
+  Intrinsic<[LLVMType], [LLVMType], [IntrNoMem]>;
+
+  def int_ve_vl_insert_vm512u :
+  GCCBuiltin<"__builtin_ve_vl_insert_vm512u">,
+  Intrinsic<[LLVMType], [LLVMType, LLVMType],
+[IntrNoMem]>;
+
+  def int_ve_vl_insert_vm512l :
+  GCCBuiltin<"__builtin_ve_vl_insert_vm512l">,
+  Intrinsic<[LLVMType], [LLVMType, LLVMType],
+[IntrNoMem]>;
 }
 
 // Define intrinsics automatically generated

diff  --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td 
b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
index 3525484af108..9ccfbe1ea42e 100644
--- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
+++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
@@ -17,6 +17,19 @@ def : Pat<(i64 (int_ve_vl_pack_f32a ADDRrii:$addr)),
  !add(32, 64)), 0,
   (HI32 (i64 0x00010001>;
 
+// The extract/insert patterns.
+def : Pat<(v256i1 (int_ve_vl_extract_vm512u v512i1:$vm)),
+  (EXTRACT_SUBREG v512i1:$vm, sub_vm_even)>;
+
+def : Pat<(v256i1 (int_ve_vl_extract_vm512l v512i1:$vm)),
+  (EXTRACT_SUBREG v512i1:$vm, sub_vm_odd)>;
+
+def : Pat<(v512i1 (int_ve_vl_insert_vm512u v512i1:$vmx, v256i1:$vmy)),
+  (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_even)>;
+
+def : Pat<(v512i1 (int_ve_vl_insert_vm512l v512i1:$vmx, v256i1:$vmy)),
+  (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_odd)>;
+
 // LSV patterns.
 def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
   (LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>;

diff  --git a/llvm/test/CodeGen/VE/VELIntrinsics/extract.ll 
b/llvm/test/CodeGen/VE/VELIntrinsics/extract.ll
new file mode 100644
index ..0e69448d7421
--- /dev/null
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/extract.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test extract intrinsic instructions
+;;;
+;;; Note:
+;;;   We test extract_vm512u and extract_vm512l pseudo instructions.
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @extract_vm512u(<512 x i1> %0) {
+; CHECK-LABEL: extract_vm512u:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:andm %vm1, %vm0, %vm2
+; CHECK-NEXT:b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.extract.vm512u(<512 x i1> %0)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.extract.vm512u(<512 x i1>)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x i1> @extract_vm512l(<512 x i1> %0) {
+; CHECK-LABEL: extract_vm512l:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:andm %vm0, %vm0, %vm2
+; CHECK-NEXT:andm %vm1, %vm0, %vm3
+; CHECK-NEXT:b.l.t (, %s10)
+  %2 = tail call <256 x i1> @llvm.ve.vl.extract.vm512l(<512 x i1> %0)
+  ret <256 x i1> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x i1> @llvm.ve.vl.extract.vm512l(<512 x i1>)

diff  --git a/llvm/test/CodeGen/VE/VELIntrinsics/insert.ll 
b/llvm/test/CodeGen/VE/VELIntrinsics/insert.ll
new file mode 100644
index ..faa17be94f6e
--- /dev/null
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/insert.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test insert intrinsic instructions
+;;;
+;;; Note:
+;;;   We test insert_vm512u and insert_vm512l pseudo instructions.
+
+; Function Attrs: nounwind readnone
+define fastcc <512 x i1> @insert_vm512u(<512 x i1> %0, <256 x i1> %1) {
+; CHECK-LABEL: insert_vm512u:
+; CHECK:   # %bb.0:
+;

[llvm-branch-commits] [llvm] d02de13 - [VE] Support additional VMRGW and VMV intrinsic instructions

[Kazushi Marukawa via llvm-branch-commits]

Author: Kazushi (Jam) Marukawa
Date: 2021-01-11T20:50:31+09:00
New Revision: d02de13932488841eb104ad2a5665fdf7db4026b

URL: 
https://github.com/llvm/llvm-project/commit/d02de13932488841eb104ad2a5665fdf7db4026b
DIFF: 
https://github.com/llvm/llvm-project/commit/d02de13932488841eb104ad2a5665fdf7db4026b.diff

LOG: [VE] Support additional VMRGW and VMV intrinsic instructions

Support missing VMRGW and VMV intrinsic instructions and add regression
tests.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D94300

Added: 


Modified: 
llvm/lib/Target/VE/VEInstrIntrinsicVL.td
llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll
llvm/test/CodeGen/VE/VELIntrinsics/vmv.ll

Removed: 




diff  --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td 
b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
index 9ccfbe1ea42e..69ea133ceed0 100644
--- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
+++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td
@@ -30,6 +30,24 @@ def : Pat<(v512i1 (int_ve_vl_insert_vm512u v512i1:$vmx, 
v256i1:$vmy)),
 def : Pat<(v512i1 (int_ve_vl_insert_vm512l v512i1:$vmx, v256i1:$vmy)),
   (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_odd)>;
 
+// VMRG patterns.
+def : Pat<(int_ve_vl_vmrgw_vsvMl i32:$sy, v256f64:$vz, v512i1:$vm, i32:$vl),
+  (VMRGWrvml (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_vmrgw_vsvMvl i32:$sy, v256f64:$vz, v512i1:$vm,
+  v256f64:$pt, i32:$vl),
+  (VMRGWrvml_v (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl,
+   v256f64:$pt)>;
+
+// VMV patterns.
+def : Pat<(int_ve_vl_vmv_vsvl i32:$sy, v256f64:$vz, i32:$vl),
+  (VMVrvl (i2l i32:$sy), v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_vmv_vsvvl i32:$sy, v256f64:$vz, v256f64:$pt, i32:$vl),
+  (VMVrvl_v (i2l i32:$sy), v256f64:$vz, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_vmv_vsvmvl i32:$sy, v256f64:$vz, v256i1:$vm, v256f64:$pt,
+i32:$vl),
+  (VMVrvml_v (i2l i32:$sy), v256f64:$vz, v256i1:$vm, i32:$vl,
+ v256f64:$pt)>;
+
 // LSV patterns.
 def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
   (LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>;

diff  --git a/llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll 
b/llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll
index 0c81db934607..23b320042c3a 100644
--- a/llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/vmrg.ll
@@ -131,3 +131,38 @@ define fastcc <256 x double> @vmrgw_vvvMvl(<256 x double> 
%0, <256 x double> %1,
 
 ; Function Attrs: nounwind readnone
 declare <256 x double> @llvm.ve.vl.vmrgw.vvvMvl(<256 x double>, <256 x 
double>, <512 x i1>, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @vmrgw_vsvMl(i32 signext %0, <256 x double> %1, 
<512 x i1> %2) {
+; CHECK-LABEL: vmrgw_vsvMl:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:and %s0, %s0, (32)0
+; CHECK-NEXT:lea %s1, 256
+; CHECK-NEXT:lvl %s1
+; CHECK-NEXT:vmrg.w %v0, %s0, %v0, %vm2
+; CHECK-NEXT:b.l.t (, %s10)
+  %4 = tail call fast <256 x double> @llvm.ve.vl.vmrgw.vsvMl(i32 %0, <256 x 
double> %1, <512 x i1> %2, i32 256)
+  ret <256 x double> %4
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.vmrgw.vsvMl(i32, <256 x double>, <512 x 
i1>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @vmrgw_vsvMvl(i32 signext %0, <256 x double> %1, 
<512 x i1> %2, <256 x double> %3) {
+; CHECK-LABEL: vmrgw_vsvMvl:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:and %s0, %s0, (32)0
+; CHECK-NEXT:lea %s1, 128
+; CHECK-NEXT:lvl %s1
+; CHECK-NEXT:vmrg.w %v1, %s0, %v0, %vm2
+; CHECK-NEXT:lea %s16, 256
+; CHECK-NEXT:lvl %s16
+; CHECK-NEXT:vor %v0, (0)1, %v1
+; CHECK-NEXT:b.l.t (, %s10)
+  %5 = tail call fast <256 x double> @llvm.ve.vl.vmrgw.vsvMvl(i32 %0, <256 x 
double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
+  ret <256 x double> %5
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.vmrgw.vsvMvl(i32, <256 x double>, <512 x 
i1>, <256 x double>, i32)

diff  --git a/llvm/test/CodeGen/VE/VELIntrinsics/vmv.ll 
b/llvm/test/CodeGen/VE/VELIntrinsics/vmv.ll
index 58dec2417690..c54d3dfe39d2 100644
--- a/llvm/test/CodeGen/VE/VELIntrinsics/vmv.ll
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/vmv.ll
@@ -6,18 +6,19 @@
 ;;;   We test VMVivl and VMVivl_v, and VMVivml_v instructions.
 
 ; Function Attrs: nounwind
-define void @vmv_vsvl(i8* %0, i64 %1, i32 signext %2) {
+define void @vmv_vsvl(i8* %0, i32 signext %1) {
 ; CHECK-LABEL: vmv_vsvl:
 ; CHECK:   # %bb.0:
-; CHECK-NEXT:lea %s1, 256
-; CHECK-NEXT:lvl %s1
+; CHECK-NEXT:lea %s2, 256
+; CHECK-NEXT:lvl %s2
 ; CHECK-NEXT:vld %v0, 8, %s0
-; CHECK-NEXT:vmv %v0, 31, %v0
+; CHECK-NEXT:and %s1, %s1, (32)0
+; CHECK-NEXT:vmv %v0,

[llvm-branch-commits] [llvm] c74751d - [obj2yaml] - Fix the crash in getUniquedSectionName().

[Georgii Rymar via llvm-branch-commits]

Author: Georgii Rymar
Date: 2021-01-11T15:04:00+03:00
New Revision: c74751d4b5bd8e6753ba8dbc5baa88d7c8929c5c

URL: 
https://github.com/llvm/llvm-project/commit/c74751d4b5bd8e6753ba8dbc5baa88d7c8929c5c
DIFF: 
https://github.com/llvm/llvm-project/commit/c74751d4b5bd8e6753ba8dbc5baa88d7c8929c5c.diff

LOG: [obj2yaml] - Fix the crash in getUniquedSectionName().

`getUniquedSectionName(const Elf_Shdr *Sec)` assumes that
`Sec` is not `nullptr`.

I've found one place in `getUniquedSymbolName` where it is
not true (because of that we crash when trying to dump
unnamed null section symbols).

Patch fixes the crash and changes the signature of the
`getUniquedSectionName` section to accept a reference.

Differential revision: https://reviews.llvm.org/D93754

Added: 


Modified: 
llvm/test/tools/obj2yaml/ELF/symbol.yaml
llvm/tools/obj2yaml/elf2yaml.cpp

Removed: 




diff  --git a/llvm/test/tools/obj2yaml/ELF/symbol.yaml 
b/llvm/test/tools/obj2yaml/ELF/symbol.yaml
index 3684d4f70c6c..3afe2d13d162 100644
--- a/llvm/test/tools/obj2yaml/ELF/symbol.yaml
+++ b/llvm/test/tools/obj2yaml/ELF/symbol.yaml
@@ -25,3 +25,44 @@ Symbols:
   - Name:  bar
 Size:  0x1
 Value: 0x1
+
+## Check how we dump unnamed section symbols.
+## Check we are able to handle the section symbol for the null section.
+## Document we name them with a section name they describe.
+
+# RUN: yaml2obj --docnum=2 %s -o %t2
+# RUN: obj2yaml %t2 | FileCheck %s --check-prefix=SECTION-SYM
+
+# SECTION-SYM:  --- !ELF
+# SECTION-SYM-NEXT: FileHeader:
+# SECTION-SYM-NEXT:   Class: ELFCLASS64
+# SECTION-SYM-NEXT:   Data:  ELFDATA2LSB
+# SECTION-SYM-NEXT:   Type:  ET_REL
+# SECTION-SYM-NEXT: Sections:
+# SECTION-SYM-NEXT:   - Name: .section
+# SECTION-SYM-NEXT: Type: SHT_PROGBITS
+# SECTION-SYM-NEXT: Symbols:
+# SECTION-SYM-NEXT:   - Type: STT_SECTION
+# SECTION-SYM-NEXT:   - Name:.section
+# SECTION-SYM-NEXT: Type:STT_SECTION
+# SECTION-SYM-NEXT: Section: .section
+# SECTION-SYM-NEXT:   - Name:.section
+# SECTION-SYM-NEXT: Type:STT_SECTION
+# SECTION-SYM-NEXT: Section: .section
+# SECTION-SYM-NEXT: ...
+
+--- !ELF
+FileHeader:
+  Class: ELFCLASS64
+  Data:  ELFDATA2LSB
+  Type:  ET_REL
+Sections:
+  - Name: .section
+Type: SHT_PROGBITS
+Symbols:
+  - Type:  STT_SECTION
+Index: 0
+  - Type:  STT_SECTION
+Index: 1
+  - Type:  STT_SECTION
+Index: 1

diff  --git a/llvm/tools/obj2yaml/elf2yaml.cpp 
b/llvm/tools/obj2yaml/elf2yaml.cpp
index da32eaba5a69..dacbaaf482c0 100644
--- a/llvm/tools/obj2yaml/elf2yaml.cpp
+++ b/llvm/tools/obj2yaml/elf2yaml.cpp
@@ -37,7 +37,7 @@ class ELFDumper {
 
   BumpPtrAllocator StringAllocator;
 
-  Expected getUniquedSectionName(const Elf_Shdr *Sec);
+  Expected getUniquedSectionName(const Elf_Shdr &Sec);
   Expected getUniquedSymbolName(const Elf_Sym *Sym,
StringRef StrTable,
const Elf_Shdr *SymTab);
@@ -115,13 +115,12 @@ ELFDumper::ELFDumper(const object::ELFFile &O,
 
 template 
 Expected
-ELFDumper::getUniquedSectionName(const Elf_Shdr *Sec) {
-  unsigned SecIndex = Sec - &Sections[0];
-  assert(&Sections[SecIndex] == Sec);
+ELFDumper::getUniquedSectionName(const Elf_Shdr &Sec) {
+  unsigned SecIndex = &Sec - &Sections[0];
   if (!SectionNames[SecIndex].empty())
 return SectionNames[SecIndex];
 
-  auto NameOrErr = Obj.getSectionName(*Sec);
+  auto NameOrErr = Obj.getSectionName(Sec);
   if (!NameOrErr)
 return NameOrErr;
   StringRef Name = *NameOrErr;
@@ -150,10 +149,12 @@ ELFDumper::getUniquedSymbolName(const Elf_Sym *Sym, 
StringRef StrTable,
 return SymbolNameOrErr;
   StringRef Name = *SymbolNameOrErr;
   if (Name.empty() && Sym->getType() == ELF::STT_SECTION) {
-auto ShdrOrErr = Obj.getSection(*Sym, SymTab, ShndxTables.lookup(SymTab));
+Expected ShdrOrErr =
+Obj.getSection(*Sym, SymTab, ShndxTables.lookup(SymTab));
 if (!ShdrOrErr)
   return ShdrOrErr.takeError();
-return getUniquedSectionName(*ShdrOrErr);
+// The null section has no name.
+return (*ShdrOrErr == nullptr) ? "" : getUniquedSectionName(**ShdrOrErr);
   }
 
   // Symbols in .symtab can have duplicate names. For example, it is a common
@@ -678,7 +679,7 @@ Error ELFDumper::dumpSymbol(const Elf_Sym *Sym, const 
Elf_Shdr *SymTab,
   if (!Shdr)
 return Error::success();
 
-  auto NameOrErr = getUniquedSectionName(Shdr);
+  auto NameOrErr = getUniquedSectionName(*Shdr);
   if (!NameOrErr)
 return NameOrErr.takeError();
   S.Section = NameOrErr.get();
@@ -755,7 +756,7 @@ Error ELFDumper::dumpCommonSection(const Elf_Shdr 
*Shdr,
 
   S.OriginalSecNdx = Shdr - &Sections[0];
 
-  auto NameOrErr = getUniquedSectionName(Shdr);
+  Expected NameOrErr = getUniquedSectionName(*Shdr);
   if (!NameOrErr)
 return NameOrErr.takeError();
   S.Name = NameOrErr.get();
@@ -764,14 +765,14 @@ Er

[llvm-branch-commits] [clang] 8ea72b3 - [clang][AArch64][SVE] Avoid going through memory for coerced VLST return values

[Joe Ellis via llvm-branch-commits]

Author: Joe Ellis
Date: 2021-01-11T12:10:59Z
New Revision: 8ea72b388734ce660f861e0dfbe53d203e94876a

URL: 
https://github.com/llvm/llvm-project/commit/8ea72b388734ce660f861e0dfbe53d203e94876a
DIFF: 
https://github.com/llvm/llvm-project/commit/8ea72b388734ce660f861e0dfbe53d203e94876a.diff

LOG: [clang][AArch64][SVE] Avoid going through memory for coerced VLST return 
values

VLST return values are coerced to VLATs in the function epilog for
consistency with the VLAT ABI. Previously, this coercion was done
through memory. It is preferable to use the
llvm.experimental.vector.insert intrinsic to avoid going through memory
here.

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D94290

Added: 


Modified: 
clang/lib/CodeGen/CGCall.cpp
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c

Removed: 




diff  --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index f1987408165b..2cc7203d1194 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -1265,6 +1265,21 @@ static llvm::Value *CreateCoercedLoad(Address Src, 
llvm::Type *Ty,
 return CGF.Builder.CreateLoad(Src);
   }
 
+  // If coercing a fixed vector to a scalable vector for ABI compatibility, and
+  // the types match, use the llvm.experimental.vector.insert intrinsic to
+  // perform the conversion.
+  if (auto *ScalableDst = dyn_cast(Ty)) {
+if (auto *FixedSrc = dyn_cast(SrcTy)) {
+  if (ScalableDst->getElementType() == FixedSrc->getElementType()) {
+auto *Load = CGF.Builder.CreateLoad(Src);
+auto *UndefVec = llvm::UndefValue::get(ScalableDst);
+auto *Zero = llvm::Constant::getNullValue(CGF.CGM.Int64Ty);
+return CGF.Builder.CreateInsertVector(ScalableDst, UndefVec, Load, 
Zero,
+  "castScalableSve");
+  }
+}
+  }
+
   // Otherwise do coercion through memory. This is stupid, but simple.
   Address Tmp =
   CreateTempAllocaForCoercion(CGF, Ty, Src.getAlignment(), Src.getName());

diff  --git 
a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp 
b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
index 6fafc2ca2db9..a808d50884ea 100644
--- a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
+++ b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
@@ -48,14 +48,11 @@ void test02() {
 // CHECK-SAME:[[#VBITS]]
 // CHECK-SAME:EES_( %x.coerce,  
%y.coerce)
 // CHECK-NEXT: entry:
-// CHECK-NEXT:   [[RETVAL_COERCE:%.*]] = alloca , align 16
 // CHECK-NEXT:   [[X:%.*]] = call <[[#div(VBITS, 32)]] x i32> 
@llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
 // CHECK-NEXT:   [[Y:%.*]] = call <[[#div(VBITS, 32)]] x i32> 
@llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32( [[X_COERCE1:%.*]], i64 0)
 // CHECK-NEXT:   [[ADD:%.*]] = add <[[#div(VBITS, 32)]] x i32> [[Y]], [[X]]
-// CHECK-NEXT:   [[RETVAL_0__SROA_CAST:%.*]] = bitcast * 
[[RETVAL_COERCE]] to <[[#div(VBITS, 32)]] x i32>*
-// CHECK-NEXT:   store <[[#div(VBITS, 32)]] x i32> [[ADD]], <[[#div(VBITS, 
32)]] x i32>* [[RETVAL_0__SROA_CAST]], align 16
-// CHECK-NEXT:   [[TMP0:%.*]] = load , * 
[[RETVAL_COERCE]], align 16
-// CHECK-NEXT:   ret  [[TMP0]]
+// CHECK-NEXT:   [[CASTSCALABLESVE:%.*]] = call  
@llvm.experimental.vector.insert.nxv4i32.v[[#div(VBITS, 32)]]i32( undef, <[[#div(VBITS, 32)]] x i32> [[ADD]], i64 0)
+// CHECK-NEXT:   ret  [[CASTSCALABLESVE]]
 typedef svint32_t vec __attribute__((arm_sve_vector_bits(N)));
 auto f(vec x, vec y) { return x + y; } // Returns a vec.
 #endif

diff  --git a/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c 
b/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
index f909b7164622..f988d54bacd4 100644
--- a/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
+++ b/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
@@ -24,14 +24,11 @@ svint32_t sizeless_callee(svint32_t x) {
 
 // CHECK-LABEL: @fixed_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
 // CHECK-NEXT:[[X:%.*]] = call <16 x i32> 
@llvm.experimental.vector.extract.v16i32.nxv4i32( 
[[X_COERCE:%.*]], i64 0)
 // CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  
@llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x 
i32> [[X]], i64 0)
 // CHECK-NEXT:[[CASTFIXEDSVE:%.*]] = call <16 x i32> 
@llvm.experimental.vector.extract.v16i32.nxv4i32( 
[[CASTSCALABLESVE]], i64 0)
-// CHECK-NEXT:[[RETVAL_0__SROA_CAST:%.*]] = bitcast * 
[[RETVAL_COERCE]] to <16 x i32>*
-// CHECK-NEXT:store <16 x i32> [[CASTFIXEDSVE]], <16 x i32>* 
[[RETVAL_0__SROA_CAST]], align 16
-// C

[llvm-branch-commits] [llvm] a6db7cf - [llvm-readelf/obj] - Index phdrs and relocations from 0 when reporting warnings.

[Georgii Rymar via llvm-branch-commits]

Author: Georgii Rymar
Date: 2021-01-11T15:13:54+03:00
New Revision: a6db7cf1ce7f3523adb132819c1697a572bdcfde

URL: 
https://github.com/llvm/llvm-project/commit/a6db7cf1ce7f3523adb132819c1697a572bdcfde
DIFF: 
https://github.com/llvm/llvm-project/commit/a6db7cf1ce7f3523adb132819c1697a572bdcfde.diff

LOG: [llvm-readelf/obj] - Index phdrs and relocations from 0 when reporting 
warnings.

As was mentioned in comments here:
https://reviews.llvm.org/D92636#inline-864967

we are not consistent and sometimes index things from 0, but sometimes
from 1 in warnings.

This patch fixes 2 places: messages reported for
program headers and messages reported for relocations.

Differential revision: https://reviews.llvm.org/D93805

Added: 


Modified: 
llvm/test/tools/llvm-readobj/ELF/gnu-notes.test
llvm/test/tools/llvm-readobj/ELF/note-core-ntfile-bad.test
llvm/test/tools/llvm-readobj/ELF/relocation-errors.test
llvm/test/tools/llvm-readobj/ELF/relocations.test
llvm/test/tools/llvm-readobj/ELF/stack-sizes.test
llvm/tools/llvm-readobj/ELFDumper.cpp

Removed: 




diff  --git a/llvm/test/tools/llvm-readobj/ELF/gnu-notes.test 
b/llvm/test/tools/llvm-readobj/ELF/gnu-notes.test
index 4a5cb1a38473..83b5be8ac57d 100644
--- a/llvm/test/tools/llvm-readobj/ELF/gnu-notes.test
+++ b/llvm/test/tools/llvm-readobj/ELF/gnu-notes.test
@@ -172,7 +172,7 @@ Sections:
 
 # ERR3-GNU:  Displaying notes found at file offset 0x with length 
0x:
 # ERR3-GNU-NEXT:   OwnerData sizeDescription
-# ERR3-GNU-NEXT: warning: '[[FILE]]': unable to read notes from the PT_NOTE 
segment with index 1: invalid offset (0x) or size (0x0)
+# ERR3-GNU-NEXT: warning: '[[FILE]]': unable to read notes from the PT_NOTE 
segment with index 0: invalid offset (0x) or size (0x0)
 # ERR3-GNU-NOT: {{.}}
 
 # ERR3-LLVM:  Notes [
@@ -180,7 +180,7 @@ Sections:
 # ERR3-LLVM-NEXT: Name: 
 # ERR3-LLVM-NEXT: Offset: 0x
 # ERR3-LLVM-NEXT: Size: 0x0
-# ERR3-LLVM-NEXT: warning: '[[FILE]]': unable to read notes from the PT_NOTE 
segment with index 1: invalid offset (0x) or size (0x0)
+# ERR3-LLVM-NEXT: warning: '[[FILE]]': unable to read notes from the PT_NOTE 
segment with index 0: invalid offset (0x) or size (0x0)
 # ERR3-LLVM-NEXT:   }
 # ERR3-LLVM-NEXT: ]
 
@@ -203,7 +203,7 @@ ProgramHeaders:
 
 # ERR4-GNU:  Displaying notes found at file offset 0x with length 
0x:
 # ERR4-GNU-NEXT:   OwnerData sizeDescription
-# ERR4-GNU-NEXT: warning: '[[FILE]]': unable to read notes from the PT_NOTE 
segment with index 1: invalid offset (0x0) or size (0x)
+# ERR4-GNU-NEXT: warning: '[[FILE]]': unable to read notes from the PT_NOTE 
segment with index 0: invalid offset (0x0) or size (0x)
 # ERR4-GNU-NOT: {{.}}
 
 # ERR4-LLVM:  Notes [
@@ -211,7 +211,7 @@ ProgramHeaders:
 # ERR4-LLVM-NEXT: Name: 
 # ERR4-LLVM-NEXT: Offset: 0x0
 # ERR4-LLVM-NEXT: Size: 0x
-# ERR4-LLVM-NEXT: warning: '[[FILE]]': unable to read notes from the PT_NOTE 
segment with index 1: invalid offset (0x0) or size (0x)
+# ERR4-LLVM-NEXT: warning: '[[FILE]]': unable to read notes from the PT_NOTE 
segment with index 0: invalid offset (0x0) or size (0x)
 # ERR4-LLVM-NEXT:   }
 # ERR4-LLVM-NEXT: ]
 

diff  --git a/llvm/test/tools/llvm-readobj/ELF/note-core-ntfile-bad.test 
b/llvm/test/tools/llvm-readobj/ELF/note-core-ntfile-bad.test
index 5a497c23a795..92553aa05596 100644
--- a/llvm/test/tools/llvm-readobj/ELF/note-core-ntfile-bad.test
+++ b/llvm/test/tools/llvm-readobj/ELF/note-core-ntfile-bad.test
@@ -11,7 +11,7 @@
 # RUN: llvm-readelf -n %t1.o 2>&1 | FileCheck -DFILE=%t1.o %s 
--check-prefix=ERR-HEADER-SHORT
 # RUN: llvm-readobj -n %t1.o 2>&1 | FileCheck -DFILE=%t1.o %s 
--check-prefix=ERR-HEADER-SHORT
 
-# ERR-HEADER-SHORT: warning: '[[FILE]]': unable to read note with index 0 from 
the PT_NOTE segment with index 1: the note of size 0x8 is too short, expected 
at least 0x10
+# ERR-HEADER-SHORT: warning: '[[FILE]]': unable to read note with index 0 from 
the PT_NOTE segment with index 0: the note of size 0x8 is too short, expected 
at least 0x10
 
 # .section ".note.foo", "a"
 #   .align 4
@@ -42,7 +42,7 @@ ProgramHeaders:
 # RUN: llvm-readelf -n %t2.o 2>&1 | FileCheck -DFILE=%t2.o %s 
--check-prefix=ERR-NULL-TERM
 # RUN: llvm-readobj -n %t2.o 2>&1 | FileCheck -DFILE=%t2.o %s 
--check-prefix=ERR-NULL-TERM
 
-# ERR-NULL-TERM: warning: '[[FILE]]': unable to read note with index 0 from 
the PT_NOTE segment with index 1: the note is not NUL terminated
+# ERR-NULL-TERM: warning: '[[FILE]]': unable to read note with index 0 from 
the PT_NOTE segment with index 0: the note is not NUL terminated
 
 # .section ".note.foo", "a"
 #   .align 4
@@ -78,7 +78,7 @@ ProgramHeaders:
 # RUN: llvm-readelf -n %t3.o 2>&1 | FileCheck -DFILE=

[llvm-branch-commits] [llvm] a94497a - [VPlan] Move initial quote emission from ::print to ::dumpBasicBlock.

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2021-01-11T12:22:15Z
New Revision: a94497a34290bea077398c83d3031179c08ec2e7

URL: 
https://github.com/llvm/llvm-project/commit/a94497a34290bea077398c83d3031179c08ec2e7
DIFF: 
https://github.com/llvm/llvm-project/commit/a94497a34290bea077398c83d3031179c08ec2e7.diff

LOG: [VPlan] Move initial quote emission from ::print to ::dumpBasicBlock.

This means there will be no stray " when printing individual recipes
using print()/dump() in a debugger, for example.

Added: 


Modified: 
llvm/lib/Transforms/Vectorize/VPlan.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp 
b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index bca6d73dc44b..039d7ac0f6cb 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -502,7 +502,7 @@ void VPInstruction::execute(VPTransformState &State) {
 
 void VPInstruction::print(raw_ostream &O, const Twine &Indent,
   VPSlotTracker &SlotTracker) const {
-  O << "\"EMIT ";
+  O << "EMIT ";
   print(O, SlotTracker);
 }
 
@@ -761,7 +761,7 @@ void VPlanPrinter::dumpBasicBlock(const VPBasicBlock 
*BasicBlock) {
   // Dump the block predicate.
   const VPValue *Pred = BasicBlock->getPredicate();
   if (Pred) {
-OS << " +\n" << Indent << " \"BlockPredicate: ";
+OS << " +\n" << Indent << " \"BlockPredicate: \"";
 if (const VPInstruction *PredI = dyn_cast(Pred)) {
   PredI->printAsOperand(OS, SlotTracker);
   OS << " (" << DOT::EscapeString(PredI->getParent()->getName())
@@ -771,7 +771,7 @@ void VPlanPrinter::dumpBasicBlock(const VPBasicBlock 
*BasicBlock) {
   }
 
   for (const VPRecipeBase &Recipe : *BasicBlock) {
-OS << " +\n" << Indent;
+OS << " +\n" << Indent << "\"";
 Recipe.print(OS, Indent, SlotTracker);
 OS << "\\l\"";
   }
@@ -833,7 +833,7 @@ void VPlanPrinter::printAsIngredient(raw_ostream &O, const 
Value *V) {
 
 void VPWidenCallRecipe::print(raw_ostream &O, const Twine &Indent,
   VPSlotTracker &SlotTracker) const {
-  O << "\"WIDEN-CALL ";
+  O << "WIDEN-CALL ";
 
   auto *CI = cast(getUnderlyingInstr());
   if (CI->getType()->isVoidTy())
@@ -850,7 +850,7 @@ void VPWidenCallRecipe::print(raw_ostream &O, const Twine 
&Indent,
 
 void VPWidenSelectRecipe::print(raw_ostream &O, const Twine &Indent,
 VPSlotTracker &SlotTracker) const {
-  O << "\"WIDEN-SELECT ";
+  O << "WIDEN-SELECT ";
   printAsOperand(O, SlotTracker);
   O << " = select ";
   getOperand(0)->printAsOperand(O, SlotTracker);
@@ -863,7 +863,7 @@ void VPWidenSelectRecipe::print(raw_ostream &O, const Twine 
&Indent,
 
 void VPWidenRecipe::print(raw_ostream &O, const Twine &Indent,
   VPSlotTracker &SlotTracker) const {
-  O << "\"WIDEN ";
+  O << "WIDEN ";
   printAsOperand(O, SlotTracker);
   O << " = " << getUnderlyingInstr()->getOpcodeName() << " ";
   printOperands(O, SlotTracker);
@@ -871,7 +871,7 @@ void VPWidenRecipe::print(raw_ostream &O, const Twine 
&Indent,
 
 void VPWidenIntOrFpInductionRecipe::print(raw_ostream &O, const Twine &Indent,
   VPSlotTracker &SlotTracker) const {
-  O << "\"WIDEN-INDUCTION";
+  O << "WIDEN-INDUCTION";
   if (Trunc) {
 O << "\\l\"";
 O << " +\n" << Indent << "\"  " << VPlanIngredient(IV) << "\\l\"";
@@ -882,7 +882,7 @@ void VPWidenIntOrFpInductionRecipe::print(raw_ostream &O, 
const Twine &Indent,
 
 void VPWidenGEPRecipe::print(raw_ostream &O, const Twine &Indent,
  VPSlotTracker &SlotTracker) const {
-  O << "\"WIDEN-GEP ";
+  O << "WIDEN-GEP ";
   O << (IsPtrLoopInvariant ? "Inv" : "Var");
   size_t IndicesNumber = IsIndexLoopInvariant.size();
   for (size_t I = 0; I < IndicesNumber; ++I)
@@ -896,12 +896,12 @@ void VPWidenGEPRecipe::print(raw_ostream &O, const Twine 
&Indent,
 
 void VPWidenPHIRecipe::print(raw_ostream &O, const Twine &Indent,
  VPSlotTracker &SlotTracker) const {
-  O << "\"WIDEN-PHI " << VPlanIngredient(Phi);
+  O << "WIDEN-PHI " << VPlanIngredient(Phi);
 }
 
 void VPBlendRecipe::print(raw_ostream &O, const Twine &Indent,
   VPSlotTracker &SlotTracker) const {
-  O << "\"BLEND ";
+  O << "BLEND ";
   Phi->printAsOperand(O, false);
   O << " =";
   if (getNumIncomingValues() == 1) {
@@ -921,7 +921,7 @@ void VPBlendRecipe::print(raw_ostream &O, const Twine 
&Indent,
 
 void VPReductionRecipe::print(raw_ostream &O, const Twine &Indent,
   VPSlotTracker &SlotTracker) const {
-  O << "\"REDUCE ";
+  O << "REDUCE ";
   printAsOperand(O, SlotTracker);
   O << " = ";
   getChainOp()->printAsOperand(O, SlotTracker);
@@ -937,7 +937,7 @@ void VPReductionRecipe::print(raw_ostream &O, const Twine 
&Indent,
 
 void VPReplicateRecipe::print(raw_ostream &O, const Twine &Indent,
   

[llvm-branch-commits] [llvm] a5b484c - [obj2yaml][test] - Improve and fix section-group.yaml test.

[Georgii Rymar via llvm-branch-commits]

Author: Georgii Rymar
Date: 2021-01-11T15:24:21+03:00
New Revision: a5b484c4d41a7452b590a2c1c98dc31f43d3dc1a

URL: 
https://github.com/llvm/llvm-project/commit/a5b484c4d41a7452b590a2c1c98dc31f43d3dc1a
DIFF: 
https://github.com/llvm/llvm-project/commit/a5b484c4d41a7452b590a2c1c98dc31f43d3dc1a.diff

LOG: [obj2yaml][test] - Improve and fix section-group.yaml test.

It has multiple issues fixed by this patch:
1) It shouldn't test how llvm-readelf/yaml2obj works.
2) It should use "-NEXT" prefix for check lines.
3) It can use YAML macros, that allows to use a single YAML.
4) It should probably test the case when a group member is a null section.

Differential revision: https://reviews.llvm.org/D93753

Added: 


Modified: 
llvm/test/tools/obj2yaml/ELF/section-group.yaml

Removed: 




diff  --git a/llvm/test/tools/obj2yaml/ELF/section-group.yaml 
b/llvm/test/tools/obj2yaml/ELF/section-group.yaml
index aba787ff59ac..33044ceeb36c 100644
--- a/llvm/test/tools/obj2yaml/ELF/section-group.yaml
+++ b/llvm/test/tools/obj2yaml/ELF/section-group.yaml
@@ -1,30 +1,17 @@
 ## Checks that the tool is able to read section groups from ELF.
 
-# RUN: yaml2obj --docnum=1 %s -o %t1.o
-# RUN: llvm-readobj --elf-section-groups %t1.o | FileCheck %s -check-prefix=OBJ
-# RUN: obj2yaml %t1.o | FileCheck %s --check-prefix YAML
-
-# OBJ:  Groups {
-# OBJ-NEXT:   Group {
-# OBJ-NEXT: Name: .group
-# OBJ-NEXT: Index: 1
-# OBJ-NEXT: Link: 3
-# OBJ-NEXT: Info: 1
-# OBJ-NEXT: Type: COMDAT (0x1)
-# OBJ-NEXT: Signature: signature
-# OBJ-NEXT: Section(s) in group [
-# OBJ-NEXT:   .rodata (2)
-# OBJ-NEXT: ]
-# OBJ-NEXT:   }
-# OBJ-NEXT: }
-
-# YAML: - Name: .group
-# YAML:   Type: SHT_GROUP
-# YAML:   Link: .symtab
-# YAML:   Info: signature
-# YAML:   Members:
-# YAML: - SectionOrType: GRP_COMDAT
-# YAML: - SectionOrType: .rodata
+# RUN: yaml2obj %s -o %t1.o
+# RUN: obj2yaml %t1.o | FileCheck %s -DSEC=.rodata
+
+# CHECK:  - Name:.group
+# CHECK-NEXT:   Type:SHT_GROUP
+# CHECK-NEXT:   Link:.symtab
+# CHECK-NEXT:   EntSize: 0x4
+# CHECK-NEXT:   Info:signature
+# CHECK-NEXT:   Members:
+# CHECK-NEXT: - SectionOrType: GRP_COMDAT
+# CHECK-NEXT: - SectionOrType: [[SEC]]
+# CHECK-NEXT: - Name:
 
 --- !ELF
 FileHeader:
@@ -35,10 +22,10 @@ Sections:
   - Name: .group
 Type: SHT_GROUP
 Link: .symtab
-Info: signature
+Info: [[INFO=signature]]
 Members:
   - SectionOrType: GRP_COMDAT
-  - SectionOrType: .rodata
+  - SectionOrType: [[SEC=.rodata]]
   - Name: .rodata
 Type: SHT_PROGBITS
 Symbols:
@@ -46,24 +33,16 @@ Symbols:
 Type:STT_OBJECT
 Section: .rodata
 
+## Check we are able to dump members of the SHT_GROUP section even when
+## one of them has section index 0.
+
+# RUN: yaml2obj -DSEC=0 %s -o %tnull.o
+# RUN: obj2yaml %tnull.o | FileCheck %s -DSEC="''"
+
 ## Check obj2yaml report an error when sh_info field of
 ## group section contains invalid (too large) signature symbol index.
 
-# RUN: yaml2obj --docnum=2 %s -o %t2.o
-# RUN: not obj2yaml %t2.o 2>&1 | FileCheck %s --check-prefix ERR
-
 !ELF
-FileHeader:
-  Class: ELFCLASS64
-  Data:  ELFDATA2LSB
-  Type:  ET_REL
-Sections:
-  - Name: .group
-Type: SHT_GROUP
-Link: .symtab
-Info: 0xFF
-Members:
-  - SectionOrType: GRP_COMDAT
-Symbols: []
+# RUN: yaml2obj -DINFO=0xFF %s -o %t2.o
+# RUN: not obj2yaml %t2.o 2>&1 | FileCheck %s -DFILE=%t2.o --check-prefix=ERR
 
-# ERR: Error reading file: {{.*}}2.o: unable to get symbol from section [index 
2]: invalid symbol index (255)
+# ERR: Error reading file: [[FILE]]: unable to get symbol from section [index 
3]: invalid symbol index (255)



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[llvm-branch-commits] [lldb] d36e879 - [lldb] Disable PipeTest.OpenAsReader on windows

[Pavel Labath via llvm-branch-commits]

Author: Pavel Labath
Date: 2021-01-11T13:37:49+01:00
New Revision: d36e879c21c9620c9b6a1a8f45afe46379142d2f

URL: 
https://github.com/llvm/llvm-project/commit/d36e879c21c9620c9b6a1a8f45afe46379142d2f
DIFF: 
https://github.com/llvm/llvm-project/commit/d36e879c21c9620c9b6a1a8f45afe46379142d2f.diff

LOG: [lldb] Disable PipeTest.OpenAsReader on windows

This test seems to be broken there (which is not totally surprising as
this functionality was never used on windows). Disable the test while I
investigate.

Added: 


Modified: 
lldb/unittests/Host/PipeTest.cpp

Removed: 




diff  --git a/lldb/unittests/Host/PipeTest.cpp 
b/lldb/unittests/Host/PipeTest.cpp
index e8d2c49c4490..35a44ccf0373 100644
--- a/lldb/unittests/Host/PipeTest.cpp
+++ b/lldb/unittests/Host/PipeTest.cpp
@@ -29,6 +29,8 @@ TEST_F(PipeTest, CreateWithUniqueName) {
 llvm::Succeeded());
 }
 
+// Test broken
+#ifndef _WIN32
 TEST_F(PipeTest, OpenAsReader) {
   Pipe pipe;
   llvm::SmallString<0> name;
@@ -46,3 +48,4 @@ TEST_F(PipeTest, OpenAsReader) {
   pipe.OpenAsReader(name_ref, /*child_process_inherit=*/false).ToError(),
   llvm::Succeeded());
 }
+#endif



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[llvm-branch-commits] [llvm] 8112a25 - [X86][SSE] Add 'vectorized sum' test patterns

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-11T12:51:18Z
New Revision: 8112a2598ce180ab4cd106f154a71e813fc28d91

URL: 
https://github.com/llvm/llvm-project/commit/8112a2598ce180ab4cd106f154a71e813fc28d91
DIFF: 
https://github.com/llvm/llvm-project/commit/8112a2598ce180ab4cd106f154a71e813fc28d91.diff

LOG: [X86][SSE] Add 'vectorized sum' test patterns

These are often generated when building a vector from the reduction sums of 
independent vectors.

I've implemented some typical patterns from various v4f32/v4i32 based off 
current codegen emitted from the vectorizers, although these tests are more 
about tweaking some hadd style backend folds to handle whatever the 
vectorizers/vectorcombine throws at us...

Added: 
llvm/test/CodeGen/X86/horizontal-sum.ll

Modified: 


Removed: 




diff  --git a/llvm/test/CodeGen/X86/horizontal-sum.ll 
b/llvm/test/CodeGen/X86/horizontal-sum.ll
new file mode 100644
index ..47d44171d99a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/horizontal-sum.ll
@@ -0,0 +1,1189 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3   | FileCheck %s 
--check-prefixes=SSSE3,SSSE3-SLOW
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s 
--check-prefixes=SSSE3,SSSE3-FAST
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s 
--check-prefixes=AVX,AVX-SLOW,AVX1-SLOW
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops   | FileCheck %s 
--check-prefixes=AVX,AVX-FAST,AVX1-FAST
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2| FileCheck %s 
--check-prefixes=AVX,AVX-SLOW,AVX2-SLOW
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2,fast-hops  | FileCheck %s 
--check-prefixes=AVX,AVX-FAST,AVX2-FAST
+
+; Vectorized Pairwise Sum Reductions
+; e.g.
+; inline STYPE sum(VTYPE x) {
+;   return (x[0] + x[1]) + (x[2] + x[3]);
+; }
+;
+; VTYPE sum4(VTYPE A0, VTYPE A1, VTYPE A2, VTYPE A3) {
+;   return (VTYPE) { sum( A0 ), sum( A1 ), sum( A2 ), sum( A3 ) };
+; }
+
+define <4 x float> @pair_sum_v4f32_v4f32(<4 x float> %0, <4 x float> %1, <4 x 
float> %2, <4 x float> %3) {
+; SSSE3-SLOW-LABEL: pair_sum_v4f32_v4f32:
+; SSSE3-SLOW:   # %bb.0:
+; SSSE3-SLOW-NEXT:haddps %xmm0, %xmm0
+; SSSE3-SLOW-NEXT:movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; SSSE3-SLOW-NEXT:addps %xmm4, %xmm0
+; SSSE3-SLOW-NEXT:haddps %xmm1, %xmm1
+; SSSE3-SLOW-NEXT:movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3]
+; SSSE3-SLOW-NEXT:addps %xmm1, %xmm4
+; SSSE3-SLOW-NEXT:unpcklps {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
+; SSSE3-SLOW-NEXT:haddps %xmm2, %xmm2
+; SSSE3-SLOW-NEXT:movshdup {{.*#+}} xmm1 = xmm2[1,1,3,3]
+; SSSE3-SLOW-NEXT:addps %xmm2, %xmm1
+; SSSE3-SLOW-NEXT:haddps %xmm3, %xmm3
+; SSSE3-SLOW-NEXT:movshdup {{.*#+}} xmm2 = xmm3[1,1,3,3]
+; SSSE3-SLOW-NEXT:addps %xmm3, %xmm2
+; SSSE3-SLOW-NEXT:movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSSE3-SLOW-NEXT:shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
+; SSSE3-SLOW-NEXT:retq
+;
+; SSSE3-FAST-LABEL: pair_sum_v4f32_v4f32:
+; SSSE3-FAST:   # %bb.0:
+; SSSE3-FAST-NEXT:haddps %xmm0, %xmm0
+; SSSE3-FAST-NEXT:haddps %xmm1, %xmm1
+; SSSE3-FAST-NEXT:haddps %xmm1, %xmm0
+; SSSE3-FAST-NEXT:haddps %xmm2, %xmm2
+; SSSE3-FAST-NEXT:haddps %xmm3, %xmm3
+; SSSE3-FAST-NEXT:haddps %xmm2, %xmm3
+; SSSE3-FAST-NEXT:shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[2,0]
+; SSSE3-FAST-NEXT:retq
+;
+; AVX1-SLOW-LABEL: pair_sum_v4f32_v4f32:
+; AVX1-SLOW:   # %bb.0:
+; AVX1-SLOW-NEXT:vhaddps %xmm0, %xmm0, %xmm0
+; AVX1-SLOW-NEXT:vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
+; AVX1-SLOW-NEXT:vaddps %xmm4, %xmm0, %xmm0
+; AVX1-SLOW-NEXT:vhaddps %xmm1, %xmm1, %xmm1
+; AVX1-SLOW-NEXT:vmovshdup {{.*#+}} xmm4 = xmm1[1,1,3,3]
+; AVX1-SLOW-NEXT:vaddps %xmm4, %xmm1, %xmm1
+; AVX1-SLOW-NEXT:vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; AVX1-SLOW-NEXT:vhaddps %xmm2, %xmm2, %xmm1
+; AVX1-SLOW-NEXT:vmovshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
+; AVX1-SLOW-NEXT:vaddps %xmm2, %xmm1, %xmm1
+; AVX1-SLOW-NEXT:vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX1-SLOW-NEXT:vhaddps %xmm3, %xmm3, %xmm1
+; AVX1-SLOW-NEXT:vmovshdup {{.*#+}} xmm2 = xmm1[1,1,3,3]
+; AVX1-SLOW-NEXT:vaddps %xmm2, %xmm1, %xmm1
+; AVX1-SLOW-NEXT:vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; AVX1-SLOW-NEXT:retq
+;
+; AVX1-FAST-LABEL: pair_sum_v4f32_v4f32:
+; AVX1-FAST:   # %bb.0:
+; AVX1-FAST-NEXT:vhaddps %xmm0, %xmm0, %xmm0
+; AVX1-FAST-NEXT:vhaddps %xmm1, %xmm1, %xmm1
+; AVX1-FAST-NEXT:vhaddps %xmm1, %xmm0, %xmm0
+; AVX1-FAST-NEXT:vhaddps %xmm2, %xmm2, %xmm1
+; AVX1-FAST-NEXT:vhaddps %xmm1, %xmm1, %xmm1
+; AVX1-FAST-NEXT:vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,1]
+; AVX1-FAST-NEXT:vhaddps %xmm3, %xmm3, %xmm1
+; AVX

[llvm-branch-commits] [llvm] 2e17d9c - [ARM] Add uses for locals introduced for debug messages. NFC.

[Stephan Herhut via llvm-branch-commits]

Author: Stephan Herhut
Date: 2021-01-11T14:27:28+01:00
New Revision: 2e17d9c0ee7a0ba2aff7dd449005e4d0fd10fe57

URL: 
https://github.com/llvm/llvm-project/commit/2e17d9c0ee7a0ba2aff7dd449005e4d0fd10fe57
DIFF: 
https://github.com/llvm/llvm-project/commit/2e17d9c0ee7a0ba2aff7dd449005e4d0fd10fe57.diff

LOG: [ARM] Add uses for locals introduced for debug messages. NFC.

This adds uses for locals introduced for new debug messages for the load store 
optimizer. Those locals are only used on debug statements and otherwise create 
unused variable warnings.

Differential Revision: https://reviews.llvm.org/D94398

Added: 


Modified: 
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Removed: 




diff  --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp 
b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 5144cf953e99..aa1fe4e4ffda 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -1511,6 +1511,7 @@ bool 
ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
.addReg(MO.getReg(), (isLd ? getDefRegState(true)
   : getKillRegState(MO.isKill(
.cloneMemRefs(*MI);
+(void)MIB;
 LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
   } else if (isLd) {
 if (isAM2) {
@@ -1524,6 +1525,7 @@ bool 
ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
 .addImm(Pred)
 .addReg(PredReg)
 .cloneMemRefs(*MI);
+(void)MIB;
 LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
   } else {
 int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
@@ -1535,6 +1537,7 @@ bool 
ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
 .addImm(Imm)
 .add(predOps(Pred, PredReg))
 .cloneMemRefs(*MI);
+(void)MIB;
 LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
   }
 } else {
@@ -1546,6 +1549,7 @@ bool 
ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
   .addImm(Offset)
   .add(predOps(Pred, PredReg))
   .cloneMemRefs(*MI);
+  (void)MIB;
   LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
 }
   } else {
@@ -1563,6 +1567,7 @@ bool 
ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
  .addImm(Imm)
  .add(predOps(Pred, PredReg))
  .cloneMemRefs(*MI);
+  (void)MIB;
   LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
 } else {
   // t2STR_PRE, t2STR_POST
@@ -1572,6 +1577,7 @@ bool 
ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
  .addImm(Offset)
  .add(predOps(Pred, PredReg))
  .cloneMemRefs(*MI);
+  (void)MIB;
   LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
 }
   }



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[llvm-branch-commits] [llvm] 6dcf920 - [AMDGPU] Fix a urem combine test to test what it was supposed to

[Jay Foad via llvm-branch-commits]

Author: Jay Foad
Date: 2021-01-11T13:32:34Z
New Revision: 6dcf9207df11f5cdb0126e5c5632e93532642ed9

URL: 
https://github.com/llvm/llvm-project/commit/6dcf9207df11f5cdb0126e5c5632e93532642ed9
DIFF: 
https://github.com/llvm/llvm-project/commit/6dcf9207df11f5cdb0126e5c5632e93532642ed9.diff

LOG: [AMDGPU] Fix a urem combine test to test what it was supposed to

Added: 


Modified: 
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir

Removed: 




diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir 
b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir
index f92e32dab08f..da6c8480b25e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir
@@ -48,12 +48,14 @@ body: |
 
 ; GCN-LABEL: name: urem_s32_var_const2
 ; GCN: liveins: $vgpr0
-; GCN: %const:_(s32) = G_CONSTANT i32 1
+; GCN: %var:_(s32) = COPY $vgpr0
+; GCN: %const:_(s32) = G_CONSTANT i32 2
 ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
 ; GCN: [[ADD:%[0-9]+]]:_(s32) = G_ADD %const, [[C]]
-; GCN: $vgpr0 = COPY [[ADD]](s32)
+; GCN: %rem:_(s32) = G_AND %var, [[ADD]]
+; GCN: $vgpr0 = COPY %rem(s32)
 %var:_(s32) = COPY $vgpr0
-%const:_(s32) = G_CONSTANT i32 1
+%const:_(s32) = G_CONSTANT i32 2
 %rem:_(s32) = G_UREM %var, %const
 $vgpr0 = COPY %rem
 ...



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[llvm-branch-commits] [mlir] 4fe7b16 - [mlir] Remove unnecessary llvm.mlir.cast in AsyncToLLVM lowering.

[Christian Sigg via llvm-branch-commits]

Author: Christian Sigg
Date: 2021-01-11T14:41:07+01:00
New Revision: 4fe7b16ae3f48a36967e58ab753381cb34295962

URL: 
https://github.com/llvm/llvm-project/commit/4fe7b16ae3f48a36967e58ab753381cb34295962
DIFF: 
https://github.com/llvm/llvm-project/commit/4fe7b16ae3f48a36967e58ab753381cb34295962.diff

LOG: [mlir] Remove unnecessary llvm.mlir.cast in AsyncToLLVM lowering.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D94400

Added: 


Modified: 
mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp

Removed: 




diff  --git a/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp 
b/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
index 92b01cea6fca..488432722959 100644
--- a/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
+++ b/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
@@ -945,13 +945,7 @@ class AwaitValueOpLowering : public 
AwaitOpLoweringBase {
 loc, LLVM::LLVMPointerType::get(llvmValueType), storage.getResult(0));
 
 // Load from the async value storage.
-auto loaded = rewriter.create(loc, 
castedStorage.getResult());
-
-// Cast from LLVM type to the expected value type if necessary. This cast
-// will become no-op after lowering to LLVM.
-if (valueType == loaded.getType())
-  return loaded;
-return rewriter.create(loc, valueType, loaded);
+return rewriter.create(loc, castedStorage.getResult());
   }
 };
 



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[llvm-branch-commits] [mlir] 4c372a3 - [mlir] Make GpuAsyncRegion pass depend on async dialect.

[Christian Sigg via llvm-branch-commits]

Author: Christian Sigg
Date: 2021-01-11T14:43:07+01:00
New Revision: 4c372a35cd892c0847da45540057447633a31d99

URL: 
https://github.com/llvm/llvm-project/commit/4c372a35cd892c0847da45540057447633a31d99
DIFF: 
https://github.com/llvm/llvm-project/commit/4c372a35cd892c0847da45540057447633a31d99.diff

LOG: [mlir] Make GpuAsyncRegion pass depend on async dialect.

Do not cache gpu.async.token type so that the pass can be created before the 
GPU dialect is registered.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D94397

Added: 


Modified: 
mlir/include/mlir/Dialect/GPU/Passes.td
mlir/lib/Dialect/GPU/Transforms/AsyncRegionRewriter.cpp
mlir/lib/Dialect/GPU/Transforms/PassDetail.h

Removed: 




diff  --git a/mlir/include/mlir/Dialect/GPU/Passes.td 
b/mlir/include/mlir/Dialect/GPU/Passes.td
index b9a83f7ef534..da1899c325fc 100644
--- a/mlir/include/mlir/Dialect/GPU/Passes.td
+++ b/mlir/include/mlir/Dialect/GPU/Passes.td
@@ -19,6 +19,7 @@ def GpuKernelOutlining : Pass<"gpu-kernel-outlining", 
"ModuleOp"> {
 def GpuAsyncRegionPass : FunctionPass<"gpu-async-region"> {
   let summary = "Make GPU ops async";
   let constructor = "mlir::createGpuAsyncRegionPass()";
+  let dependentDialects = ["async::AsyncDialect"];
 }
 
 #endif // MLIR_DIALECT_GPU_PASSES

diff  --git a/mlir/lib/Dialect/GPU/Transforms/AsyncRegionRewriter.cpp 
b/mlir/lib/Dialect/GPU/Transforms/AsyncRegionRewriter.cpp
index 4f0eefb05931..37e0b9373d42 100644
--- a/mlir/lib/Dialect/GPU/Transforms/AsyncRegionRewriter.cpp
+++ b/mlir/lib/Dialect/GPU/Transforms/AsyncRegionRewriter.cpp
@@ -78,6 +78,8 @@ struct GpuAsyncRegionPass::ThreadTokenCallback {
 if (op->getNumRegions() > 0)
   return op->emitOpError("regions are not supported");
 
+auto tokenType = builder.getType();
+
 // If there is no current token, insert a `gpu.wait async` without
 // dependencies to create one.
 if (!currentToken)
@@ -108,7 +110,7 @@ struct GpuAsyncRegionPass::ThreadTokenCallback {
   }
 
   OpBuilder builder;
-  const Type tokenType = builder.getType();
+
   // The token that represents the current asynchronous dependency. It's valid
   // range starts with a `gpu.wait async` op, and ends with a `gpu.wait` op.
   // In between, each gpu::AsyncOpInterface depends on the current token and

diff  --git a/mlir/lib/Dialect/GPU/Transforms/PassDetail.h 
b/mlir/lib/Dialect/GPU/Transforms/PassDetail.h
index 2e6fb9217189..c83ac3035a40 100644
--- a/mlir/lib/Dialect/GPU/Transforms/PassDetail.h
+++ b/mlir/lib/Dialect/GPU/Transforms/PassDetail.h
@@ -9,6 +9,7 @@
 #ifndef DIALECT_GPU_TRANSFORMS_PASSDETAIL_H_
 #define DIALECT_GPU_TRANSFORMS_PASSDETAIL_H_
 
+#include "mlir/Dialect/Async/IR/Async.h"
 #include "mlir/Pass/Pass.h"
 
 namespace mlir {



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[llvm-branch-commits] [flang] 8298ec2 - [flang][driver] Copy input files into a temp dir when testing

[Andrzej Warzynski via llvm-branch-commits]

Author: Andrzej Warzynski
Date: 2021-01-11T13:54:19Z
New Revision: 8298ec2d6299a95d2920cb8ee993ac6c5e604097

URL: 
https://github.com/llvm/llvm-project/commit/8298ec2d6299a95d2920cb8ee993ac6c5e604097
DIFF: 
https://github.com/llvm/llvm-project/commit/8298ec2d6299a95d2920cb8ee993ac6c5e604097.diff

LOG: [flang][driver] Copy input files into a temp dir when testing

The following frontend driver invocation will generate 2 output files
in the same directory as the input files:
```
flang-new -fc1 input-1.f input-2.f
```
This is the desired behaviour. However, when testing we need to make
sure that we don't pollute the source directory. To this end, copy test
input files into a temporary directory.

Differential Revision: https://reviews.llvm.org/D94243

Added: 


Modified: 
flang/test/Frontend/multiple-input-files.f90

Removed: 




diff  --git a/flang/test/Frontend/multiple-input-files.f90 
b/flang/test/Frontend/multiple-input-files.f90
index 04fe25fdf6f3..f1fb7d1caae3 100644
--- a/flang/test/Frontend/multiple-input-files.f90
+++ b/flang/test/Frontend/multiple-input-files.f90
@@ -16,9 +16,13 @@
 ! FLANG FRONTEND DRIVER (flang-new -fc1)
 !
 ! TEST 3: Both input files are processed
-! RUN: %flang-new -fc1 -test-io  %S/Inputs/hello-world.f90 %s 2>&1 \
-! RUN:  && FileCheck %s --input-file=%S/multiple-input-files.txt 
--match-full-lines -check-prefix=FC1-OUTPUT1 \
-! RUN:  && FileCheck %s --input-file=%S/Inputs/hello-world.txt 
--match-full-lines -check-prefix=FC1-OUTPUT2
+! This particular test case generates output files in the same directory as 
the input files. We need to copy the input files into a
+! temporary directory to avoid polluting the source directory.
+! RUN: rm -rf %t-dir && mkdir -p %t-dir && cd %t-dir
+! RUN: cp %s . && cp %S/Inputs/hello-world.f90 .
+! RUN: %flang-new -fc1 -test-io  hello-world.f90 multiple-input-files.f90 2>&1 
\
+! RUN:  && FileCheck %s --input-file=multiple-input-files.txt 
--match-full-lines -check-prefix=FC1-OUTPUT1 \
+! RUN:  && FileCheck %s --input-file=hello-world.txt --match-full-lines 
-check-prefix=FC1-OUTPUT2
 
 ! TEST 4: Only the last input file is processed
 ! RUN: %flang-new -fc1 -test-io %s %S/Inputs/hello-world.f90 -o %t 2>&1 \



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[llvm-branch-commits] [mlir] df86f15 - [mlir][linalg] Support parsing attributes in named op spec

[Lei Zhang via llvm-branch-commits]

Author: Lei Zhang
Date: 2021-01-11T09:05:20-05:00
New Revision: df86f15f0c53c395dac5a14aba08745bc12b9b9b

URL: 
https://github.com/llvm/llvm-project/commit/df86f15f0c53c395dac5a14aba08745bc12b9b9b
DIFF: 
https://github.com/llvm/llvm-project/commit/df86f15f0c53c395dac5a14aba08745bc12b9b9b.diff

LOG: [mlir][linalg] Support parsing attributes in named op spec

With this, now we can specify a list of attributes on named ops
generated from the spec. The format is defined as

```
attr-id ::= bare-id (`?`)?
attr-typedef ::= type (`[` `]`)?
attr-def ::= attr-id `:` attr-typedef

tc-attr-def ::= `attr` `(` attr-def-list `)`
tc-def ::= `def` bare-id
  `(`tensor-def-list`)` `->` `(` tensor-def-list`)`
  (tc-attr-def)?
```

For example,

```
ods_def
def some_op(...) -> (...)
attr(
  f32_attr: f32,
  i32_attr: i32,
  array_attr : f32[],
  optional_attr? : f32
)
```

where `?` means optional attribute and `[]` means array type.

Reviewed By: hanchung, nicolasvasilache

Differential Revision: https://reviews.llvm.org/D94240

Added: 


Modified: 
mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp

Removed: 




diff  --git a/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc 
b/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
index f81380f02bb3..1ef128760637 100644
--- a/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
+++ b/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
@@ -72,3 +72,25 @@ ods_def :
 def test3(A: f32(Batch, M, K), B: f32(K, N)) -> (C: f32(Batch, M, N)) {
   C(b, m, n) = std_addf(std_mulf(A(b, m, k), B(k, n)));
 }
+
+// Test attribute definitions
+// ODS-LABEL: def Test4Op
+// ODS: F32ArrayAttr:$array_attr,
+// ODS: F32:$f32_attr,
+// ODS: RankedF32ElementsAttr<[4]>:$fvec_attr,
+// ODS: I32:$i32_attr,
+// ODS: RankedI32ElementsAttr<[5, 6]>:$ivec_attr,
+// ODS: OptionalAttr:$optional_attr
+//
+ods_def :
+def test4(A: f32(Batch, M, K), B: f32(K, N)) -> (C: f32(Batch, M, N))
+attr(
+  f32_attr: f32,
+  i32_attr: i32,
+  fvec_attr: 4xf32,
+  ivec_attr: 5x6xi32,
+  array_attr : f32[],
+  optional_attr? : f32
+) {
+  C(b, m, n) = std_addf(std_mulf(A(b, m, k), B(k, n)));
+}

diff  --git a/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp 
b/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
index 592e6cb774fb..e7ab5edc1118 100644
--- a/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
+++ b/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
@@ -20,11 +20,17 @@
 #include "mlir/Support/LLVM.h"
 #include "mlir/Support/LogicalResult.h"
 #include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Twine.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormatVariadic.h"
 #include "llvm/Support/ToolOutputFile.h"
 
+#include 
+
 #define DEBUG_TYPE "linalg-ods-gen"
 
 static llvm::cl::OptionCategory ODSGenCat("Linalg ODS Gen");
@@ -79,11 +85,14 @@ class Token {
 gt,
 l_brace,
 l_paren,
+l_square,
 lt,
 minus,
 plus,
+question,
 r_brace,
 r_paren,
+r_square,
 semicolon,
 star,
 
@@ -91,6 +100,7 @@ class Token {
 kw_def,
 FIRST_KEYWORD = kw_def,
 kw_ods_def,
+kw_attr_def,
 kw_floordiv,
 kw_ceildiv,
 kw_mod,
@@ -151,6 +161,10 @@ class Lexer {
   Token emitError(llvm::SMLoc loc, const Twine &msg);
   Token emitError(const char *loc, const Twine &msg);
 
+  /// Change the position of the lexer cursor. The next token we lex will start
+  /// at the designated point in the input.
+  void resetPointer(const char *newPtr) { curPtr = newPtr; }
+
 private:
   Token formToken(Token::Kind kind, const char *tokStart) {
 return Token(kind, StringRef(tokStart, curPtr - tokStart));
@@ -247,10 +261,14 @@ Token Lexer::lexToken() {
   return formToken(Token::Kind::l_brace, tokStart);
 case '(':
   return formToken(Token::Kind::l_paren, tokStart);
+case '[':
+  return formToken(Token::Kind::l_square, tokStart);
 case '}':
   return formToken(Token::Kind::r_brace, tokStart);
 case ')':
   return formToken(Token::Kind::r_paren, tokStart);
+case ']':
+  return formToken(Token::Kind::r_square, tokStart);
 case '<':
   return formToken(Token::Kind::lt, tokStart);
 case '>':
@@ -263,6 +281,8 @@ Token Lexer::lexToken() {
   return formToken(Token::Kind::semicolon, tokStart);
 case '*':
   return formToken(Token::Kind::star, tokStart);
+case '?':
+  return formToken(Token::Kind::question, tokStart);
 case '/':
   if (*curPtr == '/') {
 skipComment();
@@ -289,6 +309,7 @@ Token Lexer::lexIdentifier(const char *tokStart) {
   // Check to see if this identifier is a keyword.
   StringRef str(tokStart, curPtr - tokStart);
   Token::Kind kind = StringSwit

[llvm-branch-commits] [mlir] 5522547 - [mlir][linalg] Support permutation when lowering to loop nests

[Lei Zhang via llvm-branch-commits]

Author: Lei Zhang
Date: 2021-01-11T09:13:06-05:00
New Revision: 55225471d9838e452cfb31e0edae6162b7226221

URL: 
https://github.com/llvm/llvm-project/commit/55225471d9838e452cfb31e0edae6162b7226221
DIFF: 
https://github.com/llvm/llvm-project/commit/55225471d9838e452cfb31e0edae6162b7226221.diff

LOG: [mlir][linalg] Support permutation when lowering to loop nests

Linalg ops are perfect loop nests. When materializing the concrete
loop nest, the default order specified by the Linalg op's iterators
may not be the best for further CodeGen: targets frequently need
to plan the loop order in order to gain better data access. And
different targets can have different preferences. So there should
exist a way to control the order.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D91795

Added: 
mlir/test/Dialect/Linalg/loop-order.mlir

Modified: 
mlir/include/mlir/Dialect/Linalg/Passes.td
mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
mlir/lib/Dialect/Linalg/Transforms/Loops.cpp

Removed: 




diff  --git a/mlir/include/mlir/Dialect/Linalg/Passes.td 
b/mlir/include/mlir/Dialect/Linalg/Passes.td
index 14f845589a6f..a20289af3054 100644
--- a/mlir/include/mlir/Dialect/Linalg/Passes.td
+++ b/mlir/include/mlir/Dialect/Linalg/Passes.td
@@ -28,8 +28,8 @@ def LinalgFoldUnitExtentDims : 
FunctionPass<"linalg-fold-unit-extent-dims"> {
   let options = [
 Option<"foldOneTripLoopsOnly", "fold-one-trip-loops-only", "bool",
 /*default=*/"false",
-   "Only folds the one-trip loops from Linalg ops on tensors "
-   "(for testing purposes only)">
+   "Only folds the one-trip loops from Linalg ops on tensors "
+   "(for testing purposes only)">
   ];
   let dependentDialects = ["linalg::LinalgDialect"];
 }
@@ -52,12 +52,24 @@ def LinalgLowerToAffineLoops : 
FunctionPass<"convert-linalg-to-affine-loops"> {
   let summary = "Lower the operations from the linalg dialect into affine "
 "loops";
   let constructor = "mlir::createConvertLinalgToAffineLoopsPass()";
+  let options = [
+ListOption<"interchangeVector", "interchange-vector", "unsigned",
+   "Permute the loops in the nest following the given "
+   "interchange vector",
+   "llvm::cl::ZeroOrMore, llvm::cl::MiscFlags::CommaSeparated">
+  ];
   let dependentDialects = ["linalg::LinalgDialect", "AffineDialect"];
 }
 
 def LinalgLowerToLoops : FunctionPass<"convert-linalg-to-loops"> {
   let summary = "Lower the operations from the linalg dialect into loops";
   let constructor = "mlir::createConvertLinalgToLoopsPass()";
+  let options = [
+ListOption<"interchangeVector", "interchange-vector", "unsigned",
+   "Permute the loops in the nest following the given "
+   "interchange vector",
+   "llvm::cl::ZeroOrMore, llvm::cl::MiscFlags::CommaSeparated">
+  ];
   let dependentDialects = ["linalg::LinalgDialect", "scf::SCFDialect", 
"AffineDialect"];
 }
 
@@ -72,6 +84,12 @@ def LinalgLowerToParallelLoops
   let summary = "Lower the operations from the linalg dialect into parallel "
 "loops";
   let constructor = "mlir::createConvertLinalgToParallelLoopsPass()";
+  let options = [
+ListOption<"interchangeVector", "interchange-vector", "unsigned",
+   "Permute the loops in the nest following the given "
+   "interchange vector",
+   "llvm::cl::ZeroOrMore, llvm::cl::MiscFlags::CommaSeparated">
+  ];
   let dependentDialects = ["AffineDialect", "linalg::LinalgDialect", 
"scf::SCFDialect"];
 }
 

diff  --git a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h 
b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
index dc82569aac38..d816414ef8b4 100644
--- a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
+++ b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
@@ -267,16 +267,28 @@ void vectorizeLinalgOp(OpBuilder &builder, Operation *op);
 
 /// Emits a loop nest of `LoopTy` with the proper body for `op`.
 template 
-Optional linalgLowerOpToLoops(OpBuilder &builder, Operation *op);
-
-/// Emits a loop nest of `scf.for` with the proper body for `op`.
-LogicalResult linalgOpToLoops(OpBuilder &builder, Operation *op);
-
-/// Emits a loop nest of `scf.parallel` with the proper body for `op`.
-LogicalResult linalgOpToParallelLoops(OpBuilder &builder, Operation *op);
+Optional
+linalgLowerOpToLoops(OpBuilder &builder, Operation *op,
+ ArrayRef interchangeVector = {});
+
+/// Emits a loop nest of `scf.for` with the proper body for `op`. The generated
+/// loop nest will follow the `interchangeVector`-permutated iterator order. If
+/// `interchangeVector` is empty, then no permutation happens.
+LogicalResult linalgOpToLoops(OpBuilder &builder, Operation *op,
+  ArrayRef interchangeVector = {});

[llvm-branch-commits] [llvm] 0073582 - [DAGCombiner] Use getVectorElementCount inside visitINSERT_SUBVECTOR

[Joe Ellis via llvm-branch-commits]

Author: Joe Ellis
Date: 2021-01-11T14:15:11Z
New Revision: 007358239decd45819a6fa44eb2a2e07fd85e796

URL: 
https://github.com/llvm/llvm-project/commit/007358239decd45819a6fa44eb2a2e07fd85e796
DIFF: 
https://github.com/llvm/llvm-project/commit/007358239decd45819a6fa44eb2a2e07fd85e796.diff

LOG: [DAGCombiner] Use getVectorElementCount inside visitINSERT_SUBVECTOR

This avoids TypeSize-/ElementCount-related warnings.

Differential Revision: https://reviews.llvm.org/D92747

Added: 
llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll

Modified: 
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 




diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index be57d9250db7..75dbc2227f6a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -21008,8 +21008,8 @@ SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
   if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST &&
   N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR &&
   N1.getOperand(0).getOperand(1) == N2 &&
-  N1.getOperand(0).getOperand(0).getValueType().getVectorNumElements() ==
-  VT.getVectorNumElements() &&
+  N1.getOperand(0).getOperand(0).getValueType().getVectorElementCount() ==
+  VT.getVectorElementCount() &&
   N1.getOperand(0).getOperand(0).getValueType().getSizeInBits() ==
   VT.getSizeInBits()) {
 return DAG.getBitcast(VT, N1.getOperand(0).getOperand(0));
@@ -21026,7 +21026,7 @@ SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
 EVT CN1VT = CN1.getValueType();
 if (CN0VT.isVector() && CN1VT.isVector() &&
 CN0VT.getVectorElementType() == CN1VT.getVectorElementType() &&
-CN0VT.getVectorNumElements() == VT.getVectorNumElements()) {
+CN0VT.getVectorElementCount() == VT.getVectorElementCount()) {
   SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N),
   CN0.getValueType(), CN0, CN1, N2);
   return DAG.getBitcast(VT, NewINSERT);
@@ -21107,8 +21107,10 @@ SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
   // If the input vector is a concatenation, and the insert replaces
   // one of the pieces, we can optimize into a single concat_vectors.
   if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() &&
-  N0.getOperand(0).getValueType() == N1.getValueType()) {
-unsigned Factor = N1.getValueType().getVectorNumElements();
+  N0.getOperand(0).getValueType() == N1.getValueType() &&
+  N0.getOperand(0).getValueType().isScalableVector() ==
+  N1.getValueType().isScalableVector()) {
+unsigned Factor = N1.getValueType().getVectorMinNumElements();
 SmallVector Ops(N0->op_begin(), N0->op_end());
 Ops[InsIdx / Factor] = N1;
 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);

diff  --git a/llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll 
b/llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll
new file mode 100644
index ..a89e3a09c1f1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -o /dev/null 2>&1 | FileCheck --allow-empty %s
+
+; This regression test is defending against a ElementCount warning 'Possible 
incorrect use of
+; EVT::getVectorNumElements() for scalable vector'. This warning appeared in
+; DAGCombiner::visitINSERT_SUBVECTOR because of the use of 
getVectorNumElements() on scalable
+; types.
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions 
on how to resolve it.
+; CHECK-NOT: warning:
+
+target triple = "aarch64-unknown-linux-gnu"
+attributes #0 = {"target-features"="+sve"}
+
+declare <16 x float> @llvm.experimental.vector.extract.v16f32.nxv4f32(, i64)
+declare  
@llvm.experimental.vector.insert.nxv2f64.v8f64(, <8 x 
double>, i64)
+
+define  @reproducer_one( %vec_a) #0 {
+  %a = call <16 x float> 
@llvm.experimental.vector.extract.v16f32.nxv4f32( %vec_a, 
i64 0)
+  %b = bitcast <16 x float> %a to <8 x double>
+  %retval = call  
@llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 
x double> %b, i64 0)
+  ret  %retval
+}
+
+define  @reproducer_two(<4 x double> %a, <4 x double> %b) 
#0 {
+  %concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> 
+  %retval = call  
@llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 
x double> %concat, i64 0)
+  ret  %retval
+}



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[llvm-branch-commits] [clang] c163aae - [attributes] Add a facility for enforcing a Trusted Computing Base.

[Artem Dergachev via llvm-branch-commits]

Author: Artem Dergachev
Date: 2021-01-11T06:39:42-08:00
New Revision: c163aae45ef6b7f3bd99601195d3ce4aad5850c6

URL: 
https://github.com/llvm/llvm-project/commit/c163aae45ef6b7f3bd99601195d3ce4aad5850c6
DIFF: 
https://github.com/llvm/llvm-project/commit/c163aae45ef6b7f3bd99601195d3ce4aad5850c6.diff

LOG: [attributes]  Add a facility for enforcing a Trusted Computing Base.

Introduce a function attribute 'enforce_tcb' that prevents the function
from calling other functions without the same attribute. This allows
isolating code that's considered to be somehow privileged so that it could not
use its privileges to exhibit arbitrary behavior.

Introduce an on-by-default warning '-Wtcb-enforcement' that warns
about violations of the above rule.

Introduce a function attribute 'enforce_tcb_leaf' that suppresses
the new warning within the function it is attached to. Such leaf functions
may implement common functionality between the trusted and the untrusted code
but they require extra careful audit with respect to their capabilities.

Differential Revision: https://reviews.llvm.org/D91898

Added: 
clang/test/Sema/attr-enforce-tcb-errors.cpp
clang/test/Sema/attr-enforce-tcb.c
clang/test/Sema/attr-enforce-tcb.cpp

Modified: 
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaChecking.cpp
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaDeclAttr.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/Attr.td 
b/clang/include/clang/Basic/Attr.td
index 248409946123..c51e95fa6fa8 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -3653,3 +3653,19 @@ def Builtin : InheritableAttr {
   let SemaHandler = 0;
   let Documentation = [Undocumented];
 }
+
+def EnforceTCB : InheritableAttr {
+  let Spellings = [Clang<"enforce_tcb">];
+  let Subjects = SubjectList<[Function]>;
+  let Args = [StringArgument<"TCBName">];
+  let Documentation = [EnforceTCBDocs];
+  bit InheritEvenIfAlreadyPresent = 1;
+}
+
+def EnforceTCBLeaf : InheritableAttr {
+  let Spellings = [Clang<"enforce_tcb_leaf">];
+  let Subjects = SubjectList<[Function]>;
+  let Args = [StringArgument<"TCBName">];
+  let Documentation = [EnforceTCBLeafDocs];
+  bit InheritEvenIfAlreadyPresent = 1;
+}

diff  --git a/clang/include/clang/Basic/AttrDocs.td 
b/clang/include/clang/Basic/AttrDocs.td
index 9cf0c59e07bb..fffede41db1e 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5725,3 +5725,28 @@ Attribute docs`_, and `the GCC Inline docs`_.
 }];
   let Heading = "always_inline, __force_inline";
 }
+
+def EnforceTCBDocs : Documentation {
+  let Category = DocCatFunction;
+  let Content = [{
+  The ``enforce_tcb`` attribute can be placed on functions to enforce that a
+  trusted compute base (TCB) does not call out of the TCB. This generates a
+  warning every time a function not marked with an ``enforce_tcb`` attribute is
+  called from a function with the ``enforce_tcb`` attribute. A function may be 
a
+  part of multiple TCBs. Invocations through function pointers are currently
+  not checked. Builtins are considered to a part of every TCB.
+
+  - ``enforce_tcb(Name)`` indicates that this function is a part of the TCB 
named ``Name``
+  }];
+}
+
+def EnforceTCBLeafDocs : Documentation {
+  let Category = DocCatFunction;
+  let Content = [{
+  The ``enforce_tcb_leaf`` attribute satisfies the requirement enforced by
+  ``enforce_tcb`` for the marked function to be in the named TCB but does not
+  continue to check the functions called from within the leaf function.
+
+  - ``enforce_tcb_leaf(Name)`` indicates that this function is a part of the 
TCB named ``Name``
+  }];
+}

diff  --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td 
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 0405195912b2..c048fc89813f 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -6,4 +6,11 @@ def err_probability_not_constant_float : Error<
 def err_probability_out_of_range : Error<
"probability argument to __builtin_expect_with_probability is outside the "
"range [0.0, 1.0]">;
+
+// TCB warnings
+def err_tcb_conflicting_attributes : Error<
+  "attributes '%0(\"%2\")' and '%1(\"%2\")' are mutually exclusive">;
+def warn_tcb_enforcement_violation : Warning<
+  "calling %0 is a violation of trusted computing base '%1'">,
+  InGroup>;
 } // end of sema component.

diff  --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 1d79e5716ef7..4de3b962c660 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -3210,6 +3210,9 @@ class Sema final {
   Decl *D, const WebAssemblyImportNameAttr &AL);
   WebAssemblyImportModule

[llvm-branch-commits] [llvm] eb0371e - [VPlan] Unify value/recipe printing after VPDef transition.

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2021-01-11T14:42:46Z
New Revision: eb0371e403a67fdb580e24b9911107bfc9a828b3

URL: 
https://github.com/llvm/llvm-project/commit/eb0371e403a67fdb580e24b9911107bfc9a828b3
DIFF: 
https://github.com/llvm/llvm-project/commit/eb0371e403a67fdb580e24b9911107bfc9a828b3.diff

LOG: [VPlan] Unify value/recipe printing after VPDef transition.

This patch unifies the way recipes and VPValues are printed after the
transition to VPDef.

VPSlotTracker has been updated to iterate over all recipes and all
their defined values to number those. There is no need to number
values in Value2VPValue.

It also updates a few places that only used slot numbers for
VPInstruction. All recipes now can produce numbered VPValues.

Added: 


Modified: 
llvm/lib/Transforms/Vectorize/VPlan.cpp
llvm/lib/Transforms/Vectorize/VPlan.h
llvm/lib/Transforms/Vectorize/VPlanSLP.cpp
llvm/lib/Transforms/Vectorize/VPlanValue.h
llvm/test/Transforms/LoopVectorize/vplan-printing.ll
llvm/unittests/Transforms/Vectorize/VPlanTest.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp 
b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index 039d7ac0f6cb..3c941fe8eda5 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -71,22 +71,24 @@ VPValue::~VPValue() {
 }
 
 void VPValue::print(raw_ostream &OS, VPSlotTracker &SlotTracker) const {
-  if (const VPInstruction *Instr = dyn_cast(this))
-Instr->print(OS, SlotTracker);
+  if (const VPRecipeBase *R = dyn_cast_or_null(Def))
+R->print(OS, "", SlotTracker);
   else
 printAsOperand(OS, SlotTracker);
 }
 
 void VPValue::dump() const {
-  const VPInstruction *Instr = dyn_cast(this);
+  const VPRecipeBase *Instr = dyn_cast_or_null(this->Def);
   VPSlotTracker SlotTracker(
   (Instr && Instr->getParent()) ? Instr->getParent()->getPlan() : nullptr);
   print(dbgs(), SlotTracker);
   dbgs() << "\n";
 }
 
-void VPRecipeBase::dump() const {
-  VPSlotTracker SlotTracker(nullptr);
+void VPDef::dump() const {
+  const VPRecipeBase *Instr = dyn_cast_or_null(this);
+  VPSlotTracker SlotTracker(
+  (Instr && Instr->getParent()) ? Instr->getParent()->getPlan() : nullptr);
   print(dbgs(), "", SlotTracker);
   dbgs() << "\n";
 }
@@ -500,18 +502,15 @@ void VPInstruction::execute(VPTransformState &State) {
 generateInstruction(State, Part);
 }
 
+void VPInstruction::dump() const {
+  VPSlotTracker SlotTracker(getParent()->getPlan());
+  print(dbgs(), "", SlotTracker);
+}
+
 void VPInstruction::print(raw_ostream &O, const Twine &Indent,
   VPSlotTracker &SlotTracker) const {
   O << "EMIT ";
-  print(O, SlotTracker);
-}
 
-void VPInstruction::print(raw_ostream &O) const {
-  VPSlotTracker SlotTracker(getParent()->getPlan());
-  print(O, SlotTracker);
-}
-
-void VPInstruction::print(raw_ostream &O, VPSlotTracker &SlotTracker) const {
   if (hasResult()) {
 printAsOperand(O, SlotTracker);
 O << " = ";
@@ -1087,13 +1086,6 @@ VPInterleavedAccessInfo::VPInterleavedAccessInfo(VPlan 
&Plan,
 
 void VPSlotTracker::assignSlot(const VPValue *V) {
   assert(Slots.find(V) == Slots.end() && "VPValue already has a slot!");
-  const Value *UV = V->getUnderlyingValue();
-  if (UV)
-return;
-  const auto *VPI = dyn_cast(V);
-  if (VPI && !VPI->hasResult())
-return;
-
   Slots[V] = NextSlot++;
 }
 
@@ -1112,10 +1104,8 @@ void VPSlotTracker::assignSlots(const VPRegionBlock 
*Region) {
 
 void VPSlotTracker::assignSlots(const VPBasicBlock *VPBB) {
   for (const VPRecipeBase &Recipe : *VPBB) {
-if (const auto *VPI = dyn_cast(&Recipe))
-  assignSlot(VPI);
-else if (const auto *VPIV = dyn_cast(&Recipe))
-  assignSlot(VPIV->getVPValue());
+for (VPValue *Def : Recipe.definedValues())
+  assignSlot(Def);
   }
 }
 
@@ -1124,10 +1114,6 @@ void VPSlotTracker::assignSlots(const VPlan &Plan) {
   for (const VPValue *V : Plan.VPExternalDefs)
 assignSlot(V);
 
-  for (auto &E : Plan.Value2VPValue)
-if (!isa(E.second))
-  assignSlot(E.second);
-
   for (const VPValue *V : Plan.VPCBVs)
 assignSlot(V);
 

diff  --git a/llvm/lib/Transforms/Vectorize/VPlan.h 
b/llvm/lib/Transforms/Vectorize/VPlan.h
index 332bd9b79ab4..4500e761a6e1 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -645,13 +645,6 @@ class VPRecipeBase : public 
ilist_node_with_parent,
   /// this VPRecipe, thereby "executing" the VPlan.
   virtual void execute(struct VPTransformState &State) = 0;
 
-  /// Each recipe prints itself.
-  virtual void print(raw_ostream &O, const Twine &Indent,
- VPSlotTracker &SlotTracker) const = 0;
-
-  /// Dump the recipe to stderr (for debugging).
-  void dump() const;
-
   /// Insert an unlinked recipe into a basic block immediately before
   /// the specified recipe.
   void insertBefore(VPRecipeBase *InsertPos

[llvm-branch-commits] [clang] 419ef38 - Revert "[attributes] Add a facility for enforcing a Trusted Computing Base."

[Nico Weber via llvm-branch-commits]

Author: Nico Weber
Date: 2021-01-11T09:51:06-05:00
New Revision: 419ef38a50293c58078f830517f5e305068dbee6

URL: 
https://github.com/llvm/llvm-project/commit/419ef38a50293c58078f830517f5e305068dbee6
DIFF: 
https://github.com/llvm/llvm-project/commit/419ef38a50293c58078f830517f5e305068dbee6.diff

LOG: Revert "[attributes]  Add a facility for enforcing a Trusted Computing 
Base."

This reverts commit c163aae45ef6b7f3bd99601195d3ce4aad5850c6.
Doesn't compile on some bots
(http://lab.llvm.org:8011/#/builders/98/builds/3387/steps/9/logs/stdio),
breaks tests on bots where it does compile
(http://45.33.8.238/linux/36843/step_7.txt).

Added: 


Modified: 
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaChecking.cpp
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaDeclAttr.cpp

Removed: 
clang/test/Sema/attr-enforce-tcb-errors.cpp
clang/test/Sema/attr-enforce-tcb.c
clang/test/Sema/attr-enforce-tcb.cpp



diff  --git a/clang/include/clang/Basic/Attr.td 
b/clang/include/clang/Basic/Attr.td
index c51e95fa6fa8..248409946123 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -3653,19 +3653,3 @@ def Builtin : InheritableAttr {
   let SemaHandler = 0;
   let Documentation = [Undocumented];
 }
-
-def EnforceTCB : InheritableAttr {
-  let Spellings = [Clang<"enforce_tcb">];
-  let Subjects = SubjectList<[Function]>;
-  let Args = [StringArgument<"TCBName">];
-  let Documentation = [EnforceTCBDocs];
-  bit InheritEvenIfAlreadyPresent = 1;
-}
-
-def EnforceTCBLeaf : InheritableAttr {
-  let Spellings = [Clang<"enforce_tcb_leaf">];
-  let Subjects = SubjectList<[Function]>;
-  let Args = [StringArgument<"TCBName">];
-  let Documentation = [EnforceTCBLeafDocs];
-  bit InheritEvenIfAlreadyPresent = 1;
-}

diff  --git a/clang/include/clang/Basic/AttrDocs.td 
b/clang/include/clang/Basic/AttrDocs.td
index fffede41db1e..9cf0c59e07bb 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5725,28 +5725,3 @@ Attribute docs`_, and `the GCC Inline docs`_.
 }];
   let Heading = "always_inline, __force_inline";
 }
-
-def EnforceTCBDocs : Documentation {
-  let Category = DocCatFunction;
-  let Content = [{
-  The ``enforce_tcb`` attribute can be placed on functions to enforce that a
-  trusted compute base (TCB) does not call out of the TCB. This generates a
-  warning every time a function not marked with an ``enforce_tcb`` attribute is
-  called from a function with the ``enforce_tcb`` attribute. A function may be 
a
-  part of multiple TCBs. Invocations through function pointers are currently
-  not checked. Builtins are considered to a part of every TCB.
-
-  - ``enforce_tcb(Name)`` indicates that this function is a part of the TCB 
named ``Name``
-  }];
-}
-
-def EnforceTCBLeafDocs : Documentation {
-  let Category = DocCatFunction;
-  let Content = [{
-  The ``enforce_tcb_leaf`` attribute satisfies the requirement enforced by
-  ``enforce_tcb`` for the marked function to be in the named TCB but does not
-  continue to check the functions called from within the leaf function.
-
-  - ``enforce_tcb_leaf(Name)`` indicates that this function is a part of the 
TCB named ``Name``
-  }];
-}

diff  --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td 
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index c048fc89813f..0405195912b2 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -6,11 +6,4 @@ def err_probability_not_constant_float : Error<
 def err_probability_out_of_range : Error<
"probability argument to __builtin_expect_with_probability is outside the "
"range [0.0, 1.0]">;
-
-// TCB warnings
-def err_tcb_conflicting_attributes : Error<
-  "attributes '%0(\"%2\")' and '%1(\"%2\")' are mutually exclusive">;
-def warn_tcb_enforcement_violation : Warning<
-  "calling %0 is a violation of trusted computing base '%1'">,
-  InGroup>;
 } // end of sema component.

diff  --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 4de3b962c660..1d79e5716ef7 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -3210,9 +3210,6 @@ class Sema final {
   Decl *D, const WebAssemblyImportNameAttr &AL);
   WebAssemblyImportModuleAttr *mergeImportModuleAttr(
   Decl *D, const WebAssemblyImportModuleAttr &AL);
-  EnforceTCBAttr *mergeEnforceTCBAttr(Decl *D, const EnforceTCBAttr &AL);
-  EnforceTCBLeafAttr *mergeEnforceTCBLeafAttr(Decl *D,
-  const EnforceTCBLeafAttr &AL);
 
   void mergeDeclAttributes(NamedDecl *New, Decl *Old,
AvailabilityMergeKind AMK = AMK_Redeclaration);
@@ -12430,8 +12427,6 @@ class Sema fin

[llvm-branch-commits] [mlir] d59ddba - [mlir] Fix gpu-to-llvm lowering for gpu.alloc with dynamic sizes.

[Christian Sigg via llvm-branch-commits]

Author: Christian Sigg
Date: 2021-01-11T15:55:48+01:00
New Revision: d59ddba777251c59a667d03021900c72f9882a4b

URL: 
https://github.com/llvm/llvm-project/commit/d59ddba777251c59a667d03021900c72f9882a4b
DIFF: 
https://github.com/llvm/llvm-project/commit/d59ddba777251c59a667d03021900c72f9882a4b.diff

LOG: [mlir] Fix gpu-to-llvm lowering for gpu.alloc with dynamic sizes.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D94402

Added: 


Modified: 
mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h
mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
mlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
mlir/test/Conversion/GPUCommon/lower-alloc-to-gpu-runtime-calls.mlir

Removed: 




diff  --git 
a/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h 
b/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h
index 82cf7e772afe..357bd2f021b1 100644
--- a/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h
+++ b/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h
@@ -533,7 +533,7 @@ class ConvertToLLVMPattern : public ConversionPattern {
   ///  : (!llvm.ptr, i64) -> !llvm.ptr
   /// `sizeBytes`  = llvm.ptrtoint %gep : !llvm.ptr to i64
   void getMemRefDescriptorSizes(Location loc, MemRefType memRefType,
-ArrayRef dynamicSizes,
+ValueRange dynamicSizes,
 ConversionPatternRewriter &rewriter,
 SmallVectorImpl &sizes,
 SmallVectorImpl &strides,

diff  --git a/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp 
b/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
index 8c89b6d20099..cee1d7ba20e3 100644
--- a/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
+++ b/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
@@ -373,19 +373,19 @@ LogicalResult 
ConvertAllocOpToGpuRuntimeCallPattern::matchAndRewrite(
 return failure();
 
   auto loc = allocOp.getLoc();
+  auto adaptor = gpu::AllocOpAdaptor(operands, allocOp->getAttrDictionary());
 
   // Get shape of the memref as values: static sizes are constant
   // values and dynamic sizes are passed to 'alloc' as operands.
   SmallVector shape;
   SmallVector strides;
   Value sizeBytes;
-  getMemRefDescriptorSizes(loc, memRefType, operands, rewriter, shape, strides,
-   sizeBytes);
+  getMemRefDescriptorSizes(loc, memRefType, adaptor.dynamicSizes(), rewriter,
+   shape, strides, sizeBytes);
 
   // Allocate the underlying buffer and store a pointer to it in the MemRef
   // descriptor.
   Type elementPtrType = this->getElementPtrType(memRefType);
-  auto adaptor = gpu::AllocOpAdaptor(operands, allocOp->getAttrDictionary());
   auto stream = adaptor.asyncDependencies().front();
   Value allocatedPtr =
   allocCallBuilder.create(loc, rewriter, {sizeBytes, stream}).getResult(0);

diff  --git a/mlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp 
b/mlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
index 0978e8cf756a..604b4576fc1b 100644
--- a/mlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
+++ b/mlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
@@ -212,8 +212,8 @@ class GPULaunchLowering : public 
ConvertOpToLLVMPattern {
   SmallVector sizes;
   SmallVector strides;
   Value sizeBytes;
-  getMemRefDescriptorSizes(loc, memRefType, operand.value(), rewriter,
-   sizes, strides, sizeBytes);
+  getMemRefDescriptorSizes(loc, memRefType, {}, rewriter, sizes, strides,
+   sizeBytes);
   MemRefDescriptor descriptor(operand.value());
   Value src = descriptor.allocatedPtr(rewriter, loc);
 

diff  --git a/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp 
b/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
index 53ebd6721863..512273347e4b 100644
--- a/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
+++ b/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
@@ -1083,11 +1083,14 @@ Type ConvertToLLVMPattern::getElementPtrType(MemRefType 
type) const {
 }
 
 void ConvertToLLVMPattern::getMemRefDescriptorSizes(
-Location loc, MemRefType memRefType, ArrayRef dynamicSizes,
+Location loc, MemRefType memRefType, ValueRange dynamicSizes,
 ConversionPatternRewriter &rewriter, SmallVectorImpl &sizes,
 SmallVectorImpl &strides, Value &sizeBytes) const {
   assert(isConvertibleAndHasIdentityMaps(memRefType) &&
  "layout maps must have been normalized away");
+  assert(count(memRefType.getShape(), ShapedType::kDynamicSize) ==
+ static_cast

[llvm-branch-commits] [llvm] a46982a - [X86] Add nounwind to lzcnt-cmp tests

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-11T15:06:38Z
New Revision: a46982a25511bd0da82f3f2637912dfd86042929

URL: 
https://github.com/llvm/llvm-project/commit/a46982a25511bd0da82f3f2637912dfd86042929
DIFF: 
https://github.com/llvm/llvm-project/commit/a46982a25511bd0da82f3f2637912dfd86042929.diff

LOG: [X86] Add nounwind to lzcnt-cmp tests

Remove unnecessary cfi markup

Added: 


Modified: 
llvm/test/CodeGen/X86/lzcnt-cmp.ll

Removed: 




diff  --git a/llvm/test/CodeGen/X86/lzcnt-cmp.ll 
b/llvm/test/CodeGen/X86/lzcnt-cmp.ll
index 3823524f552a..5bf0dbec7510 100644
--- a/llvm/test/CodeGen/X86/lzcnt-cmp.ll
+++ b/llvm/test/CodeGen/X86/lzcnt-cmp.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -mtriple=i686-- -mattr=+lzcnt | FileCheck %s 
--check-prefixes=X86
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+lzcnt | FileCheck %s 
--check-prefix=X64
 
-define i1 @lshr_ctlz_cmpeq_one_i64(i64 %in) {
+define i1 @lshr_ctlz_cmpeq_one_i64(i64 %in) nounwind {
 ; X86-LABEL: lshr_ctlz_cmpeq_one_i64:
 ; X86:   # %bb.0:
 ; X86-NEXT:movl {{[0-9]+}}(%esp), %eax
@@ -21,7 +21,7 @@ define i1 @lshr_ctlz_cmpeq_one_i64(i64 %in) {
   ret i1 %icmp
 }
 
-define i1 @lshr_ctlz_undef_cmpeq_one_i64(i64 %in) {
+define i1 @lshr_ctlz_undef_cmpeq_one_i64(i64 %in) nounwind {
 ; X86-LABEL: lshr_ctlz_undef_cmpeq_one_i64:
 ; X86:   # %bb.0:
 ; X86-NEXT:xorl %eax, %eax
@@ -48,7 +48,7 @@ define i1 @lshr_ctlz_undef_cmpeq_one_i64(i64 %in) {
   ret i1 %icmp
 }
 
-define i1 @lshr_ctlz_cmpne_zero_i64(i64 %in) {
+define i1 @lshr_ctlz_cmpne_zero_i64(i64 %in) nounwind {
 ; X86-LABEL: lshr_ctlz_cmpne_zero_i64:
 ; X86:   # %bb.0:
 ; X86-NEXT:movl {{[0-9]+}}(%esp), %eax
@@ -67,7 +67,7 @@ define i1 @lshr_ctlz_cmpne_zero_i64(i64 %in) {
   ret i1 %icmp
 }
 
-define i1 @lshr_ctlz_undef_cmpne_zero_i64(i64 %in) {
+define i1 @lshr_ctlz_undef_cmpne_zero_i64(i64 %in) nounwind {
 ; X86-LABEL: lshr_ctlz_undef_cmpne_zero_i64:
 ; X86:   # %bb.0:
 ; X86-NEXT:xorl %eax, %eax
@@ -93,12 +93,10 @@ define i1 @lshr_ctlz_undef_cmpne_zero_i64(i64 %in) {
   ret i1 %icmp
 }
 
-define <2 x i64> @lshr_ctlz_cmpeq_zero_v2i64(<2 x i64> %in) {
+define <2 x i64> @lshr_ctlz_cmpeq_zero_v2i64(<2 x i64> %in) nounwind {
 ; X86-LABEL: lshr_ctlz_cmpeq_zero_v2i64:
 ; X86:   # %bb.0:
 ; X86-NEXT:pushl %esi
-; X86-NEXT:.cfi_def_cfa_offset 8
-; X86-NEXT:.cfi_offset %esi, -8
 ; X86-NEXT:movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:movl {{[0-9]+}}(%esp), %esi
 ; X86-NEXT:movl {{[0-9]+}}(%esp), %edx
@@ -115,7 +113,6 @@ define <2 x i64> @lshr_ctlz_cmpeq_zero_v2i64(<2 x i64> %in) 
{
 ; X86-NEXT:movl %ecx, 4(%eax)
 ; X86-NEXT:movl %ecx, (%eax)
 ; X86-NEXT:popl %esi
-; X86-NEXT:.cfi_def_cfa_offset 4
 ; X86-NEXT:retl $4
 ;
 ; X64-LABEL: lshr_ctlz_cmpeq_zero_v2i64:
@@ -134,12 +131,10 @@ define <2 x i64> @lshr_ctlz_cmpeq_zero_v2i64(<2 x i64> 
%in) {
   ret <2 x i64> %sext
 }
 
-define <2 x i64> @lshr_ctlz_cmpne_zero_v2i64(<2 x i64> %in) {
+define <2 x i64> @lshr_ctlz_cmpne_zero_v2i64(<2 x i64> %in) nounwind {
 ; X86-LABEL: lshr_ctlz_cmpne_zero_v2i64:
 ; X86:   # %bb.0:
 ; X86-NEXT:pushl %esi
-; X86-NEXT:.cfi_def_cfa_offset 8
-; X86-NEXT:.cfi_offset %esi, -8
 ; X86-NEXT:movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:movl {{[0-9]+}}(%esp), %esi
 ; X86-NEXT:movl {{[0-9]+}}(%esp), %edx
@@ -156,7 +151,6 @@ define <2 x i64> @lshr_ctlz_cmpne_zero_v2i64(<2 x i64> %in) 
{
 ; X86-NEXT:movl %ecx, 4(%eax)
 ; X86-NEXT:movl %ecx, (%eax)
 ; X86-NEXT:popl %esi
-; X86-NEXT:.cfi_def_cfa_offset 4
 ; X86-NEXT:retl $4
 ;
 ; X64-LABEL: lshr_ctlz_cmpne_zero_v2i64:



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[llvm-branch-commits] [llvm] a0f8274 - [X86] Extend lzcnt-cmp tests to test on non-lzcnt targets

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-11T15:27:08Z
New Revision: a0f82749f4f3373ba85de40c69b866081f77abce

URL: 
https://github.com/llvm/llvm-project/commit/a0f82749f4f3373ba85de40c69b866081f77abce
DIFF: 
https://github.com/llvm/llvm-project/commit/a0f82749f4f3373ba85de40c69b866081f77abce.diff

LOG: [X86] Extend lzcnt-cmp tests to test on non-lzcnt targets

Added: 


Modified: 
llvm/test/CodeGen/X86/lzcnt-cmp.ll

Removed: 




diff  --git a/llvm/test/CodeGen/X86/lzcnt-cmp.ll 
b/llvm/test/CodeGen/X86/lzcnt-cmp.ll
index 5bf0dbec7510..c094920d59eb 100644
--- a/llvm/test/CodeGen/X86/lzcnt-cmp.ll
+++ b/llvm/test/CodeGen/X86/lzcnt-cmp.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-- -mattr=+lzcnt | FileCheck %s 
--check-prefixes=X86
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+lzcnt | FileCheck %s 
--check-prefix=X64
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=X86,X86-BSR
+; RUN: llc < %s -mtriple=i686-- -mattr=+lzcnt | FileCheck %s 
--check-prefixes=X86,X86-LZCNT
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefixes=X64,X64-BSR
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+lzcnt | FileCheck %s 
--check-prefixes=X64,X64-LZCNT
 
 define i1 @lshr_ctlz_cmpeq_one_i64(i64 %in) nounwind {
 ; X86-LABEL: lshr_ctlz_cmpeq_one_i64:
@@ -10,11 +12,27 @@ define i1 @lshr_ctlz_cmpeq_one_i64(i64 %in) nounwind {
 ; X86-NEXT:sete %al
 ; X86-NEXT:retl
 ;
-; X64-LABEL: lshr_ctlz_cmpeq_one_i64:
-; X64:   # %bb.0:
-; X64-NEXT:testq %rdi, %rdi
-; X64-NEXT:sete %al
-; X64-NEXT:retq
+; X64-BSR-LABEL: lshr_ctlz_cmpeq_one_i64:
+; X64-BSR:   # %bb.0:
+; X64-BSR-NEXT:testq %rdi, %rdi
+; X64-BSR-NEXT:je .LBB0_1
+; X64-BSR-NEXT:  # %bb.2: # %cond.false
+; X64-BSR-NEXT:bsrq %rdi, %rax
+; X64-BSR-NEXT:xorq $63, %rax
+; X64-BSR-NEXT:jmp .LBB0_3
+; X64-BSR-NEXT:  .LBB0_1:
+; X64-BSR-NEXT:movl $64, %eax
+; X64-BSR-NEXT:  .LBB0_3: # %cond.end
+; X64-BSR-NEXT:shrq $6, %rax
+; X64-BSR-NEXT:cmpq $1, %rax
+; X64-BSR-NEXT:sete %al
+; X64-BSR-NEXT:retq
+;
+; X64-LZCNT-LABEL: lshr_ctlz_cmpeq_one_i64:
+; X64-LZCNT:   # %bb.0:
+; X64-LZCNT-NEXT:testq %rdi, %rdi
+; X64-LZCNT-NEXT:sete %al
+; X64-LZCNT-NEXT:retq
   %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 0)
   %lshr = lshr i64 %ctlz, 6
   %icmp = icmp eq i64 %lshr, 1
@@ -22,26 +40,48 @@ define i1 @lshr_ctlz_cmpeq_one_i64(i64 %in) nounwind {
 }
 
 define i1 @lshr_ctlz_undef_cmpeq_one_i64(i64 %in) nounwind {
-; X86-LABEL: lshr_ctlz_undef_cmpeq_one_i64:
-; X86:   # %bb.0:
-; X86-NEXT:xorl %eax, %eax
-; X86-NEXT:cmpl $0, {{[0-9]+}}(%esp)
-; X86-NEXT:jne .LBB1_2
-; X86-NEXT:  # %bb.1:
-; X86-NEXT:lzcntl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:addl $32, %eax
-; X86-NEXT:  .LBB1_2:
-; X86-NEXT:testb $64, %al
-; X86-NEXT:setne %al
-; X86-NEXT:retl
+; X86-BSR-LABEL: lshr_ctlz_undef_cmpeq_one_i64:
+; X86-BSR:   # %bb.0:
+; X86-BSR-NEXT:xorl %eax, %eax
+; X86-BSR-NEXT:cmpl $0, {{[0-9]+}}(%esp)
+; X86-BSR-NEXT:jne .LBB1_2
+; X86-BSR-NEXT:  # %bb.1:
+; X86-BSR-NEXT:bsrl {{[0-9]+}}(%esp), %eax
+; X86-BSR-NEXT:xorl $31, %eax
+; X86-BSR-NEXT:addl $32, %eax
+; X86-BSR-NEXT:  .LBB1_2:
+; X86-BSR-NEXT:testl $-64, %eax
+; X86-BSR-NEXT:setne %al
+; X86-BSR-NEXT:retl
 ;
-; X64-LABEL: lshr_ctlz_undef_cmpeq_one_i64:
-; X64:   # %bb.0:
-; X64-NEXT:lzcntq %rdi, %rax
-; X64-NEXT:shrq $6, %rax
-; X64-NEXT:cmpl $1, %eax
-; X64-NEXT:sete %al
-; X64-NEXT:retq
+; X86-LZCNT-LABEL: lshr_ctlz_undef_cmpeq_one_i64:
+; X86-LZCNT:   # %bb.0:
+; X86-LZCNT-NEXT:xorl %eax, %eax
+; X86-LZCNT-NEXT:cmpl $0, {{[0-9]+}}(%esp)
+; X86-LZCNT-NEXT:jne .LBB1_2
+; X86-LZCNT-NEXT:  # %bb.1:
+; X86-LZCNT-NEXT:lzcntl {{[0-9]+}}(%esp), %eax
+; X86-LZCNT-NEXT:addl $32, %eax
+; X86-LZCNT-NEXT:  .LBB1_2:
+; X86-LZCNT-NEXT:testb $64, %al
+; X86-LZCNT-NEXT:setne %al
+; X86-LZCNT-NEXT:retl
+;
+; X64-BSR-LABEL: lshr_ctlz_undef_cmpeq_one_i64:
+; X64-BSR:   # %bb.0:
+; X64-BSR-NEXT:bsrq %rdi, %rax
+; X64-BSR-NEXT:shrq $6, %rax
+; X64-BSR-NEXT:cmpl $1, %eax
+; X64-BSR-NEXT:sete %al
+; X64-BSR-NEXT:retq
+;
+; X64-LZCNT-LABEL: lshr_ctlz_undef_cmpeq_one_i64:
+; X64-LZCNT:   # %bb.0:
+; X64-LZCNT-NEXT:lzcntq %rdi, %rax
+; X64-LZCNT-NEXT:shrq $6, %rax
+; X64-LZCNT-NEXT:cmpl $1, %eax
+; X64-LZCNT-NEXT:sete %al
+; X64-LZCNT-NEXT:retq
   %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 -1)
   %lshr = lshr i64 %ctlz, 6
   %icmp = icmp eq i64 %lshr, 1
@@ -56,11 +96,26 @@ define i1 @lshr_ctlz_cmpne_zero_i64(i64 %in) nounwind {
 ; X86-NEXT:sete %al
 ; X86-NEXT:retl
 ;
-; X64-LABEL: lshr_ctlz_cmpne_zero_i64:
-; X64:   # %bb.0:
-; X64-NEXT:testq %rdi, %rdi
-; X64-NEXT:sete %al
-; X64-NEXT:retq
+; X64-BSR-LABEL:

[llvm-branch-commits] [llvm] dbd5fa1 - [ARM] Update existing test case with +pauth targets

[Ranjeet Singh via llvm-branch-commits]

Author: Ranjeet Singh
Date: 2021-01-11T15:39:13Z
New Revision: dbd5fa1e75d812ab31b1d71b23f506c2cbc7a93d

URL: 
https://github.com/llvm/llvm-project/commit/dbd5fa1e75d812ab31b1d71b23f506c2cbc7a93d
DIFF: 
https://github.com/llvm/llvm-project/commit/dbd5fa1e75d812ab31b1d71b23f506c2cbc7a93d.diff

LOG: [ARM] Update existing test case with +pauth targets

Differential Revision: https://reviews.llvm.org/D94414

Added: 


Modified: 
llvm/test/MC/Disassembler/AArch64/armv8.3a-signed-pointer.txt

Removed: 




diff  --git a/llvm/test/MC/Disassembler/AArch64/armv8.3a-signed-pointer.txt 
b/llvm/test/MC/Disassembler/AArch64/armv8.3a-signed-pointer.txt
index 110c6681cd7f..33297da59159 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.3a-signed-pointer.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.3a-signed-pointer.txt
@@ -1,4 +1,6 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s 
2>&1 | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s 
2>&1 | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+pauth --disassemble < %s 
2>&1 | FileCheck %s
 
 # CHECK: warning: potentially undefined instruction encoding
 # CHECK-NEXT: [0x00,0x0c,0x20,0xf8]



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[llvm-branch-commits] [clang-tools-extra] a2dbf34 - [clangd] Fix -check mode doesn't respect any tidy configs.

[Haojian Wu via llvm-branch-commits]

Author: Haojian Wu
Date: 2021-01-11T16:43:33+01:00
New Revision: a2dbf3443af79426c80e8a808821236c5a2b305e

URL: 
https://github.com/llvm/llvm-project/commit/a2dbf3443af79426c80e8a808821236c5a2b305e
DIFF: 
https://github.com/llvm/llvm-project/commit/a2dbf3443af79426c80e8a808821236c5a2b305e.diff

LOG: [clangd] Fix -check mode doesn't respect any tidy configs.

Differential Revision: https://reviews.llvm.org/D94411

Added: 


Modified: 
clang-tools-extra/clangd/tool/Check.cpp

Removed: 




diff  --git a/clang-tools-extra/clangd/tool/Check.cpp 
b/clang-tools-extra/clangd/tool/Check.cpp
index 18d2837b89c2..e42596bb4bf4 100644
--- a/clang-tools-extra/clangd/tool/Check.cpp
+++ b/clang-tools-extra/clangd/tool/Check.cpp
@@ -123,6 +123,7 @@ class Checker {
 std::vector CC1Args;
 Inputs.CompileCommand = Cmd;
 Inputs.TFS = &TFS;
+Inputs.ClangTidyProvider = Opts.ClangTidyProvider;
 if (Contents.hasValue()) {
   Inputs.Contents = *Contents;
   log("Imaginary source file contents:\n{0}", Inputs.Contents);



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[llvm-branch-commits] [clang-tools-extra] 31732e6 - [clangd] Remove ScratchFS from tests

[Nathan James via llvm-branch-commits]

Author: Nathan James
Date: 2021-01-11T16:14:26Z
New Revision: 31732e6f52c8e5e722d3e4cca053db793dae3b8c

URL: 
https://github.com/llvm/llvm-project/commit/31732e6f52c8e5e722d3e4cca053db793dae3b8c
DIFF: 
https://github.com/llvm/llvm-project/commit/31732e6f52c8e5e722d3e4cca053db793dae3b8c.diff

LOG: [clangd] Remove ScratchFS from tests

This can lead to issues if files in the tmp directory we don't care about / 
control are found.
This was partially addressed in D94321, but this is a more permanent fix.
Fixes https://github.com/clangd/clangd/issues/354

Reviewed By: adamcz, sammccall

Differential Revision: https://reviews.llvm.org/D94359

Added: 


Modified: 
clang-tools-extra/clangd/unittests/GlobalCompilationDatabaseTests.cpp

Removed: 




diff  --git 
a/clang-tools-extra/clangd/unittests/GlobalCompilationDatabaseTests.cpp 
b/clang-tools-extra/clangd/unittests/GlobalCompilationDatabaseTests.cpp
index 12c986572d8b..63b1b731656a 100644
--- a/clang-tools-extra/clangd/unittests/GlobalCompilationDatabaseTests.cpp
+++ b/clang-tools-extra/clangd/unittests/GlobalCompilationDatabaseTests.cpp
@@ -169,48 +169,6 @@ TEST_F(OverlayCDBTest, Adjustments) {
"-DFallback", "-DAdjust_baz.cc"));
 }
 
-// Allows placement of files for tests and cleans them up after.
-// FIXME: GlobalCompilationDatabase is mostly VFS-clean now, switch to MockFS?
-class ScratchFS {
-  llvm::SmallString<128> Root;
-
-public:
-  ScratchFS() {
-EXPECT_FALSE(llvm::sys::fs::createUniqueDirectory("clangd-cdb-test", Root))
-<< "Failed to create unique directory";
-  }
-
-  ~ScratchFS() {
-EXPECT_FALSE(llvm::sys::fs::remove_directories(Root))
-<< "Failed to cleanup " << Root;
-  }
-
-  llvm::StringRef root() const { return Root; }
-
-  void write(PathRef RelativePath, llvm::StringRef Contents) {
-std::string AbsPath = path(RelativePath);
-EXPECT_FALSE(llvm::sys::fs::create_directories(
-llvm::sys::path::parent_path(AbsPath)))
-<< "Failed to create directories for: " << AbsPath;
-
-std::error_code EC;
-llvm::raw_fd_ostream OS(AbsPath, EC);
-EXPECT_FALSE(EC) << "Failed to open " << AbsPath << " for writing";
-OS << llvm::formatv(Contents.data(),
-llvm::sys::path::convert_to_slash(Root));
-OS.close();
-
-EXPECT_FALSE(OS.has_error());
-  }
-
-  std::string path(PathRef RelativePath) const {
-llvm::SmallString<128> AbsPath(Root);
-llvm::sys::path::append(AbsPath, RelativePath);
-llvm::sys::path::native(AbsPath);
-return AbsPath.str().str();
-  }
-};
-
 TEST(GlobalCompilationDatabaseTest, DiscoveryWithNestedCDBs) {
   const char *const CDBOuter =
   R"cdb(
@@ -242,34 +200,35 @@ TEST(GlobalCompilationDatabaseTest, 
DiscoveryWithNestedCDBs) {
 }
   ]
   )cdb";
-  ScratchFS FS;
-  RealThreadsafeFS TFS;
-  FS.write("compile_commands.json", CDBOuter);
-  FS.write("build/compile_commands.json", CDBInner);
+  MockFS FS;
+  FS.Files[testPath("compile_commands.json")] =
+  llvm::formatv(CDBOuter, llvm::sys::path::convert_to_slash(testRoot()));
+  FS.Files[testPath("build/compile_commands.json")] =
+  llvm::formatv(CDBInner, llvm::sys::path::convert_to_slash(testRoot()));
 
   // Note that gen2.cc goes missing with our following model, not sure this
   // happens in practice though.
   {
-DirectoryBasedGlobalCompilationDatabase DB(TFS);
+DirectoryBasedGlobalCompilationDatabase DB(FS);
 std::vector DiscoveredFiles;
 auto Sub =
 DB.watch([&DiscoveredFiles](const std::vector Changes) {
   DiscoveredFiles = Changes;
 });
 
-DB.getCompileCommand(FS.path("build/../a.cc"));
+DB.getCompileCommand(testPath("build/../a.cc"));
 EXPECT_THAT(DiscoveredFiles, UnorderedElementsAre(AllOf(
  EndsWith("a.cc"), Not(HasSubstr("..");
 DiscoveredFiles.clear();
 
-DB.getCompileCommand(FS.path("build/gen.cc"));
+DB.getCompileCommand(testPath("build/gen.cc"));
 EXPECT_THAT(DiscoveredFiles, UnorderedElementsAre(EndsWith("gen.cc")));
   }
 
   // With a custom compile commands dir.
   {
-DirectoryBasedGlobalCompilationDatabase::Options Opts(TFS);
-Opts.CompileCommandsDir = FS.root().str();
+DirectoryBasedGlobalCompilationDatabase::Options Opts(FS);
+Opts.CompileCommandsDir = testRoot();
 DirectoryBasedGlobalCompilationDatabase DB(Opts);
 std::vector DiscoveredFiles;
 auto Sub =
@@ -277,24 +236,23 @@ TEST(GlobalCompilationDatabaseTest, 
DiscoveryWithNestedCDBs) {
   DiscoveredFiles = Changes;
 });
 
-DB.getCompileCommand(FS.path("a.cc"));
+DB.getCompileCommand(testPath("a.cc"));
 EXPECT_THAT(DiscoveredFiles,
 UnorderedElementsAre(EndsWith("a.cc"), EndsWith("gen.cc"),
  EndsWith("gen2.cc")));
 DiscoveredFiles.

[llvm-branch-commits] [llvm] e5eb5c8 - NFC: Use -LABEL more

[Paul Robinson via llvm-branch-commits]

Author: Paul Robinson
Date: 2021-01-11T08:14:58-08:00
New Revision: e5eb5c8a7f30ddb01b7e00a010714ac9711f29de

URL: 
https://github.com/llvm/llvm-project/commit/e5eb5c8a7f30ddb01b7e00a010714ac9711f29de
DIFF: 
https://github.com/llvm/llvm-project/commit/e5eb5c8a7f30ddb01b7e00a010714ac9711f29de.diff

LOG: NFC: Use -LABEL more

There were a number of tests needing updates for D91734, and I added a
bunch of LABEL directives to help track down where those had to go.
These directives are an improvement independent of the functional
patch, so I'm committing them as their own separate patch.

Added: 


Modified: 
llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
llvm/test/CodeGen/AArch64/arm64-fast-isel.ll
llvm/test/CodeGen/AArch64/elf-globals-static.ll
llvm/test/CodeGen/ARM/fast-isel-call.ll
llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
llvm/test/CodeGen/ARM/fast-isel-select.ll
llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll

Removed: 




diff  --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll 
b/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
index 586b7d116f5c..00016a6a7fff 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
@@ -78,7 +78,7 @@ declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 
zeroext, i8 zeroext, i8
 ; Test materialization of integers.  Target-independent selector handles this.
 define i32 @t2() {
 entry:
-; CHECK-LABEL: t2
+; CHECK-LABEL: t2:
 ; CHECK:   mov x0, xzr
 ; CHECK:   mov w1, #-8
 ; CHECK:   mov [[REG2:w[0-9]+]], #1023
@@ -99,6 +99,7 @@ declare i32 @func2(i64 zeroext, i32 signext, i16 zeroext, i8 
signext, i1 zeroext
 declare void @callee_b0f(i8 %bp10, i8 %bp11, i8 %bp12, i8 %bp13, i8 %bp14, i8 
%bp15, i8 %bp17, i8 %bp18, i8 %bp19)
 define void @caller_b1f() {
 entry:
+; CHECK-LABEL: caller_b1f
 ; CHECK-BE-LABEL: caller_b1f
 ; CHECK-BE:   strb w{{.*}}, [sp, #7]
   call void @callee_b0f(i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 42)

diff  --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll 
b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll
index 7dc849b7d2c4..6d402c95ee3f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll
@@ -2,7 +2,7 @@
 
 define void @t0(i32 %a) nounwind {
 entry:
-; CHECK: t0
+; CHECK-LABEL: t0:
 ; CHECK: str {{w[0-9]+}}, [sp, #12]
 ; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]
 ; CHECK-NEXT: str [[REGISTER]], [sp, #12]
@@ -15,7 +15,7 @@ entry:
 }
 
 define void @t1(i64 %a) nounwind {
-; CHECK: t1
+; CHECK-LABEL: t1:
 ; CHECK: str {{x[0-9]+}}, [sp, #8]
 ; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8]
 ; CHECK-NEXT: str [[REGISTER]], [sp, #8]
@@ -29,7 +29,7 @@ define void @t1(i64 %a) nounwind {
 
 define zeroext i1 @i1(i1 %a) nounwind {
 entry:
-; CHECK: @i1
+; CHECK-LABEL: i1:
 ; CHECK: and [[REG:w[0-9]+]], w0, #0x1
 ; CHECK: strb [[REG]], [sp, #15]
 ; CHECK: ldrb [[REG1:w[0-9]+]], [sp, #15]
@@ -84,7 +84,7 @@ entry:
 }
 
 define void @t6() nounwind {
-; CHECK: t6
+; CHECK-LABEL: t6:
 ; CHECK: brk #0x1
   tail call void @llvm.trap()
   ret void

diff  --git a/llvm/test/CodeGen/AArch64/elf-globals-static.ll 
b/llvm/test/CodeGen/AArch64/elf-globals-static.ll
index 928ec70af0b1..393f42049011 100644
--- a/llvm/test/CodeGen/AArch64/elf-globals-static.ll
+++ b/llvm/test/CodeGen/AArch64/elf-globals-static.ll
@@ -15,6 +15,7 @@ define i8 @test_i8(i8 %new) {
 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
 
+; CHECK-FAST-LABEL: test_i8:
 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8
 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
 }
@@ -28,6 +29,7 @@ define i16 @test_i16(i16 %new) {
 ; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
 ; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
 
+; CHECK-FAST-LABEL: test_i16:
 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var16
 ; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
 }
@@ -41,6 +43,7 @@ define i32 @test_i32(i32 %new) {
 ; CHECK: ldr {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
 ; CHECK: str {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
 
+; CHECK-FAST-LABEL: test_i32:
 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var32
 ; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var32
 }
@@ -54,6 +57,7 @@ define i64 @test_i64(i64 %new) {
 ; CHECK: ldr {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
 ; CHECK: str {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
 
+; CHECK-FAST-LABEL: test_i64:
 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var64
 ; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var64
 }
@@ -64,6 +68,7 @@ define i64* @test_addr() {
 ; CHECK: adrp [[HIREG:x[0-9]+]], var64
 ; CHECK: add x0, [[HIREG]], :lo12:var64
 
+; CHECK-FAST-LABEL: test_addr:
 ; CHECK-FAST: adrp [[HIREG:x[0-9]+]], var64
 ; CHECK-FAST: add x0, [[HIREG]], :lo12:var64
 }

diff  --git a/llvm/test/CodeGen/ARM/fast-isel-call.ll 
b/llvm/test/CodeGen/

[llvm-branch-commits] [lld] c161775 - [FastISel] Flush local value map on every instruction

[Paul Robinson via llvm-branch-commits]

Author: Paul Robinson
Date: 2021-01-11T08:32:36-08:00
New Revision: c161775decddcc86fbbfefd7485a5d0ef5842aec

URL: 
https://github.com/llvm/llvm-project/commit/c161775decddcc86fbbfefd7485a5d0ef5842aec
DIFF: 
https://github.com/llvm/llvm-project/commit/c161775decddcc86fbbfefd7485a5d0ef5842aec.diff

LOG: [FastISel] Flush local value map on every instruction

Local values are constants or addresses that can't be folded into
the instruction that uses them. FastISel materializes these in a
"local value" area that always dominates the current insertion
point, to try to avoid materializing these values more than once
(per block).

https://reviews.llvm.org/D43093 added code to sink these local
value instructions to their first use, which has two beneficial
effects. One, it is likely to avoid some unnecessary spills and
reloads; two, it allows us to attach the debug location of the
user to the local value instruction. The latter effect can
improve the debugging experience for debuggers with a "set next
statement" feature, such as the Visual Studio debugger and PS4
debugger, because instructions to set up constants for a given
statement will be associated with the appropriate source line.

There are also some constants (primarily addresses) that could be
produced by no-op casts or GEP instructions; the main difference
from "local value" instructions is that these are values from
separate IR instructions, and therefore could have multiple users
across multiple basic blocks. D43093 avoided sinking these, even
though they were emitted to the same "local value" area as the
other instructions. The patch comment for D43093 states:

  Local values may also be used by no-op casts, which adds the
  register to the RegFixups table. Without reversing the RegFixups
  map direction, we don't have enough information to sink these
  instructions.

This patch undoes most of D43093, and instead flushes the local
value map after(*) every IR instruction, using that instruction's
debug location. This avoids sometimes incorrect locations used
previously, and emits instructions in a more natural order.

In addition, constants materialized due to PHI instructions are
not assigned a debug location immediately; instead, when the
local value map is flushed, if the first local value instruction
has no debug location, it is given the same location as the
first non-local-value-map instruction.  This prevents PHIs
from introducing unattributed instructions, which would either
be implicitly attributed to the location for the preceding IR
instruction, or given line 0 if they are at the beginning of
a machine basic block.  Neither of those consequences is good
for debugging.

This does mean materialized values are not re-used across IR
instruction boundaries; however, only about 5% of those values
were reused in an experimental self-build of clang.

(*) Actually, just prior to the next instruction. It seems like
it would be cleaner the other way, but I was having trouble
getting that to work.

This reapplies commits cf1c774d and dc35368c, and adds the
modification to PHI handling, which should avoid problems
with debugging under gdb.

Differential Revision: https://reviews.llvm.org/D91734

Added: 
llvm/test/CodeGen/X86/fast-isel-prolog-dbgloc.ll

Modified: 
lld/test/wasm/debug-removed-fn.ll
lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp
lldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp
llvm/include/llvm/CodeGen/FastISel.h
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/test/CodeGen/AArch64/arm64-abi_align.ll
llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll
llvm/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll
llvm/test/CodeGen/AArch64/arm64-fast-isel.ll
llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
llvm/test/CodeGen/AArch64/cfguard-checks.ll
llvm/test/CodeGen/AArch64/elf-globals-static.ll
llvm/test/CodeGen/AArch64/large-stack.ll
llvm/test/CodeGen/ARM/fast-isel-call.ll
llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
llvm/test/CodeGen/ARM/fast-isel-select.ll
llvm/test/CodeGen/ARM/fast-isel.ll
llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll
llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll
llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll
llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
llvm/test/CodeGen/PowerPC/elf-common.ll
llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll
llvm/test/CodeGen/PowerPC/mcm-1.ll
llvm/test/CodeGen/PowerPC/mcm-13.ll
llvm/test/CodeGen/PowerPC/mcm-2.ll
   

[llvm-branch-commits] [llvm] 4214ca9 - [X86][AVX] Attempt to fold vpermf128(op(x, i), op(y, i)) -> op(vpermf128(x, y), i)

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2021-01-11T16:59:25Z
New Revision: 4214ca96145c9487407925b121b85fafb1179209

URL: 
https://github.com/llvm/llvm-project/commit/4214ca96145c9487407925b121b85fafb1179209
DIFF: 
https://github.com/llvm/llvm-project/commit/4214ca96145c9487407925b121b85fafb1179209.diff

LOG: [X86][AVX] Attempt to fold vpermf128(op(x,i),op(y,i)) -> 
op(vpermf128(x,y),i)

If vpermf128/vpermi128 is acting on 2 similar 'inlane' ops, then try to perform 
the vpermf128 first which will allow us to merge the ops.

This will help us fix one of the regressions in D56387

Added: 


Modified: 
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/vector-trunc.ll

Removed: 




diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp 
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7895f883863f..2f9de876a87f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36665,6 +36665,43 @@ static SDValue combineCommutableSHUFP(SDValue N, MVT 
VT, const SDLoc &DL,
   return SDValue();
 }
 
+/// Attempt to fold vpermf128(op(),op()) -> op(vpermf128(),vpermf128()).
+static SDValue canonicalizeLaneShuffleWithRepeatedOps(SDValue V,
+  SelectionDAG &DAG,
+  const SDLoc &DL) {
+  assert(V.getOpcode() == X86ISD::VPERM2X128 && "Unknown lane shuffle");
+
+  MVT VT = V.getSimpleValueType();
+  SDValue Src0 = peekThroughBitcasts(V.getOperand(0));
+  SDValue Src1 = peekThroughBitcasts(V.getOperand(1));
+  unsigned SrcOpc0 = Src0.getOpcode();
+  unsigned SrcOpc1 = Src1.getOpcode();
+  EVT SrcVT0 = Src0.getValueType();
+  EVT SrcVT1 = Src1.getValueType();
+
+  // TODO: Under what circumstances should we push perm2f128 up when we have 
one
+  // active src?
+  if (SrcOpc0 != SrcOpc1 || SrcVT0 != SrcVT1)
+return SDValue();
+
+  switch (SrcOpc0) {
+  case X86ISD::VSHLI:
+  case X86ISD::VSRLI:
+  case X86ISD::VSRAI:
+if (Src0.getOperand(1) == Src1.getOperand(1)) {
+  SDValue Res = DAG.getNode(
+  X86ISD::VPERM2X128, DL, VT, DAG.getBitcast(VT, Src0.getOperand(0)),
+  DAG.getBitcast(VT, Src1.getOperand(0)), V.getOperand(2));
+  Res = DAG.getNode(SrcOpc0, DL, SrcVT0, DAG.getBitcast(SrcVT0, Res),
+Src0.getOperand(1));
+  return DAG.getBitcast(VT, Res);
+}
+break;
+  }
+
+  return SDValue();
+}
+
 /// Try to combine x86 target specific shuffles.
 static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
 TargetLowering::DAGCombinerInfo &DCI,
@@ -37045,6 +37082,9 @@ static SDValue combineTargetShuffle(SDValue N, 
SelectionDAG &DAG,
 return SDValue();
   }
   case X86ISD::VPERM2X128: {
+if (SDValue Res = canonicalizeLaneShuffleWithRepeatedOps(N, DAG, DL))
+return Res;
+
 // If both 128-bit values were inserted into high halves of 256-bit values,
 // the shuffle can be reduced to a concatenation of subvectors:
 // vperm2x128 (ins ?, X, C1), (ins ?, Y, C2), 0x31 --> concat X, Y
@@ -37053,6 +37093,7 @@ static SDValue combineTargetShuffle(SDValue N, 
SelectionDAG &DAG,
 SDValue Ins0 = peekThroughBitcasts(N.getOperand(0));
 SDValue Ins1 = peekThroughBitcasts(N.getOperand(1));
 unsigned Imm = N.getConstantOperandVal(2);
+
 if (!(Imm == 0x31 &&
   Ins0.getOpcode() == ISD::INSERT_SUBVECTOR &&
   Ins1.getOpcode() == ISD::INSERT_SUBVECTOR &&

diff  --git a/llvm/test/CodeGen/X86/vector-trunc.ll 
b/llvm/test/CodeGen/X86/vector-trunc.ll
index bd8b7dd355cc..f35e315bbb0b 100644
--- a/llvm/test/CodeGen/X86/vector-trunc.ll
+++ b/llvm/test/CodeGen/X86/vector-trunc.ll
@@ -107,11 +107,9 @@ define <8 x i32> @trunc8i64_8i32_lshr(<8 x i64> %a) {
 ;
 ; AVX2-SLOW-LABEL: trunc8i64_8i32_lshr:
 ; AVX2-SLOW:   # %bb.0: # %entry
-; AVX2-SLOW-NEXT:vpsrlq $32, %ymm1, %ymm1
-; AVX2-SLOW-NEXT:vpsrlq $32, %ymm0, %ymm0
-; AVX2-SLOW-NEXT:vperm2i128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]
-; AVX2-SLOW-NEXT:vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX2-SLOW-NEXT:vshufps {{.*#+}} ymm0 = 
ymm0[0,2],ymm2[0,2],ymm0[4,6],ymm2[4,6]
+; AVX2-SLOW-NEXT:vperm2f128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]
+; AVX2-SLOW-NEXT:vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX2-SLOW-NEXT:vshufps {{.*#+}} ymm0 = 
ymm0[1,3],ymm2[1,3],ymm0[5,7],ymm2[5,7]
 ; AVX2-SLOW-NEXT:retq
 ;
 ; AVX2-FAST-LABEL: trunc8i64_8i32_lshr:



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[llvm-branch-commits] [mlir] 9c0dc0b - [mlir][Linalg] Fold init_tensor -> linalg.tensor_reshape.

[via llvm-branch-commits]

Author: MaheshRavishankar
Date: 2021-01-11T09:22:35-08:00
New Revision: 9c0dc0b2c1cc973056237bdd80dbba749941ea63

URL: 
https://github.com/llvm/llvm-project/commit/9c0dc0b2c1cc973056237bdd80dbba749941ea63
DIFF: 
https://github.com/llvm/llvm-project/commit/9c0dc0b2c1cc973056237bdd80dbba749941ea63.diff

LOG: [mlir][Linalg] Fold init_tensor -> linalg.tensor_reshape.

Reshaping an init_tensor can be folded to a init_tensor op of the
final type.

Differential Revision: https://reviews.llvm.org/D93773

Added: 


Modified: 
mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
mlir/test/Dialect/Linalg/canonicalize.mlir

Removed: 




diff  --git a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp 
b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
index 8a97753e1a5c..8732065bb042 100644
--- a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+++ b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
@@ -718,9 +718,123 @@ struct ReplaceDimOfInitTensorOp : public 
OpRewritePattern {
 };
 } // namespace
 
+static Value getCollapsedInitTensor(OpBuilder &builder,
+TensorReshapeOp reshapeOp) {
+  Location loc = reshapeOp.getLoc();
+  SmallVector dynamicShapes;
+  SmallVector staticShapes;
+  auto reassociation = reshapeOp.getReassociationMaps();
+  Value src = reshapeOp.src();
+  RankedTensorType srcType = reshapeOp.getSrcType();
+  ArrayRef srcShape = srcType.getShape();
+  for (auto map : reassociation) {
+Value linearizedDynamicDim = nullptr;
+int64_t linearizedStaticDim = 1;
+for (unsigned i : llvm::map_range(map.getResults(), [](AffineExpr e) {
+   return e.cast().getPosition();
+ })) {
+  if (ShapedType::isDynamic(srcShape[i])) {
+Value shapeVal = builder.create(loc, src, i);
+if (linearizedDynamicDim) {
+  linearizedDynamicDim =
+  builder.create(loc, linearizedDynamicDim, shapeVal);
+} else {
+  linearizedDynamicDim = shapeVal;
+}
+  } else {
+linearizedStaticDim *= srcShape[i];
+  }
+}
+if (linearizedDynamicDim) {
+  if (linearizedStaticDim != 1) {
+linearizedDynamicDim = builder.create(
+loc, linearizedDynamicDim,
+builder.create(loc, linearizedStaticDim));
+  }
+  dynamicShapes.push_back(linearizedDynamicDim);
+  staticShapes.push_back(ShapedType::kDynamicSize);
+} else {
+  staticShapes.push_back(linearizedStaticDim);
+}
+  }
+  return builder.create(loc, dynamicShapes, staticShapes,
+  srcType.getElementType());
+}
+
+static Value getExpandedInitTensor(OpBuilder &builder,
+   TensorReshapeOp reshapeOp) {
+  SmallVector dynamicShapes;
+  SmallVector staticShapes;
+  auto reassociation = reshapeOp.getReassociationMaps();
+  Value src = reshapeOp.src();
+  RankedTensorType srcType = reshapeOp.getSrcType();
+  ArrayRef srcShape = srcType.getShape();
+  ArrayRef dstShape = reshapeOp.getResultType().getShape();
+  Location loc = reshapeOp.getLoc();
+  for (auto map : enumerate(reassociation)) {
+int64_t linearizedStaticDim = 1;
+bool hasDynamic = false;
+for (unsigned i :
+ llvm::map_range(map.value().getResults(), [](AffineExpr e) {
+   return e.cast().getPosition();
+ })) {
+  if (ShapedType::isDynamic(dstShape[i])) {
+// Only one of the dimensions of the expanded shape should be dynamic.
+if (hasDynamic)
+  return nullptr;
+hasDynamic = true;
+staticShapes.push_back(ShapedType::kDynamicSize);
+continue;
+  }
+  staticShapes.push_back(dstShape[i]);
+  linearizedStaticDim *= dstShape[i];
+}
+if (hasDynamic) {
+  // If the expanded dimensions has a dynamic shape, the src shape must be
+  // dynamic as well.
+  if (!ShapedType::isDynamic(srcShape[map.index()]))
+return nullptr;
+  Value dynamicDim = builder.create(loc, src, map.index());
+  if (linearizedStaticDim != 1) {
+dynamicDim = builder.create(
+loc, dynamicDim,
+builder.create(loc, linearizedStaticDim));
+  }
+  dynamicShapes.push_back(dynamicDim);
+}
+  }
+  return builder.create(loc, dynamicShapes, staticShapes,
+  srcType.getElementType());
+}
+
+namespace {
+struct FoldWithTensorReshapeOp : public OpRewritePattern {
+  using OpRewritePattern::OpRewritePattern;
+
+  LogicalResult matchAndRewrite(TensorReshapeOp reshapeOp,
+PatternRewriter &rewriter) const override {
+if (!reshapeOp.src().getDefiningOp())
+  return failure();
+RankedTensorType collapsedType = reshapeOp.getSrcType();
+RankedTensorType expandedType = reshapeOp.getResultType();
+bool isCollapsed = expandedType.getRank() < collapsedType.getRank();
+if (isCollapsed)
+  std::swap(collapsedType, expande

[llvm-branch-commits] [clang] c15b0e2 - [Clang][Docs] Fix ambiguity in clang-offload-bundler docs

[Scott Linder via llvm-branch-commits]

Author: Scott Linder
Date: 2021-01-11T17:23:24Z
New Revision: c15b0e2229ea04d1c36fafaa1f717f433a995e9a

URL: 
https://github.com/llvm/llvm-project/commit/c15b0e2229ea04d1c36fafaa1f717f433a995e9a
DIFF: 
https://github.com/llvm/llvm-project/commit/c15b0e2229ea04d1c36fafaa1f717f433a995e9a.diff

LOG: [Clang][Docs] Fix ambiguity in clang-offload-bundler docs

Differential Revision: https://reviews.llvm.org/D94338

Added: 


Modified: 
clang/docs/ClangOffloadBundler.rst

Removed: 




diff  --git a/clang/docs/ClangOffloadBundler.rst 
b/clang/docs/ClangOffloadBundler.rst
index 050925be993b..68c5116b235f 100644
--- a/clang/docs/ClangOffloadBundler.rst
+++ b/clang/docs/ClangOffloadBundler.rst
@@ -44,7 +44,7 @@ The layout of a bundled code object is defined by the 
following table:
 Field   TypeSize in BytesDescription
 === ===  
===
 Magic Stringstring  24   
``__CLANG_OFFLOAD_BUNDLE__``
-Number Of Code Objects  integer 8Number od 
bundled code objects.
+Number Of Bundle Entriesinteger 8Number of 
bundle entries.
 1st Bundle Entry Code Object Offset integer 8Byte offset 
from beginning of
  bundled code 
object to 1st code
  object.
@@ -208,4 +208,4 @@ Target specific information is available for the following:
   features `_
   supported.
 
-Most other targets do not support target IDs.
\ No newline at end of file
+Most other targets do not support target IDs.



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[llvm-branch-commits] [llvm] 7200d2c - [NFC] Disallow unused prefixes in CodeGen/PowerPC tests.

[Mircea Trofin via llvm-branch-commits]

Author: Mircea Trofin
Date: 2021-01-11T09:24:52-08:00
New Revision: 7200d2cf0891ef56607fd0336029b33bd4097eed

URL: 
https://github.com/llvm/llvm-project/commit/7200d2cf0891ef56607fd0336029b33bd4097eed
DIFF: 
https://github.com/llvm/llvm-project/commit/7200d2cf0891ef56607fd0336029b33bd4097eed.diff

LOG: [NFC] Disallow unused prefixes in CodeGen/PowerPC tests.

Also removed where applicable.

Differential Revision: https://reviews.llvm.org/D94385

Added: 


Modified: 
llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
llvm/test/CodeGen/PowerPC/lit.local.cfg
llvm/test/CodeGen/PowerPC/lower-massv.ll
llvm/test/CodeGen/PowerPC/popcnt-zext.ll
llvm/test/CodeGen/PowerPC/ppc32-pic.ll
llvm/test/CodeGen/PowerPC/srem-lkk.ll
llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
llvm/test/CodeGen/PowerPC/testComparesigeui.ll
llvm/test/CodeGen/PowerPC/testComparesigeull.ll
llvm/test/CodeGen/PowerPC/testComparesigeus.ll
llvm/test/CodeGen/PowerPC/testComparesileuc.ll
llvm/test/CodeGen/PowerPC/testComparesileui.ll
llvm/test/CodeGen/PowerPC/testComparesileull.ll
llvm/test/CodeGen/PowerPC/testComparesileus.ll
llvm/test/CodeGen/PowerPC/testComparesiltsc.ll
llvm/test/CodeGen/PowerPC/testComparesiltsi.ll
llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
llvm/test/CodeGen/PowerPC/testComparesiltss.ll
llvm/test/CodeGen/PowerPC/testComparesiltuc.ll
llvm/test/CodeGen/PowerPC/testComparesiltui.ll
llvm/test/CodeGen/PowerPC/testComparesiltus.ll
llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
llvm/test/CodeGen/PowerPC/testComparesllgeull.ll
llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
llvm/test/CodeGen/PowerPC/testComparesllleui.ll
llvm/test/CodeGen/PowerPC/testComparesllleull.ll
llvm/test/CodeGen/PowerPC/testComparesllleus.ll
llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
llvm/test/CodeGen/PowerPC/testComparesllltuc.ll
llvm/test/CodeGen/PowerPC/testComparesllltus.ll
llvm/test/CodeGen/PowerPC/urem-lkk.ll
llvm/test/CodeGen/PowerPC/vec_splat.ll
llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
llvm/test/CodeGen/PowerPC/vmladduhm.ll

Removed: 




diff  --git a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll 
b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
index ec3d9c3c03f1..4201b7450a6a 100644
--- a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
@@ -27,10 +27,10 @@
 ; RUN: --check-prefixes=64LARGE-ASM,LARGE-ASM %s
 
 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -function-sections < %s | FileCheck \
-; RUN: --check-prefixes=FUNC-ASM,CHECK %s
+; RUN: --check-prefix=FUNC-ASM %s
 
 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -function-sections < %s | 
FileCheck \
-; RUN: --check-prefixes=FUNC-ASM,CHECK %s
+; RUN: --check-prefix=FUNC-ASM %s
 
   define i32 @jump_table(i32 %a) {
   entry:

diff  --git a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll 
b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
index cb1544ef9756..e8821cb91577 100644
--- a/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
+++ b/llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -O2 -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp 
-verify-machineinstrs < %s | \
-; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
+; RUN: FileCheck --check-prefix=32BIT %s
 
 ; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
 ; RUN:  -mtriple powerpc-ibm-aix-xcoff < %s | \
-; RUN: FileCheck --check-prefixes=CHECKASM,ASM32 %s
+; RUN: FileCheck --check-prefix=ASM32 %s
 
   define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr  {
   entry:

diff  --git a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll 
b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
index 7ee8dd0a3712..4c2daf3b4ecf 100644
--- a/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -O2 -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp 
-verify-machineinstrs < %s | \
-; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
+; RUN: FileCheck --check-prefix=64BIT %s
 
 ; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
 ; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \
-; RUN: FileCheck --check-prefixes=CHECKASM,ASM64 %s
+; RUN: FileCheck --check-prefix=ASM64 %s
 
   define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr  {
   entry:

diff  --git a/llvm/test/CodeGen/PowerPC/lit.local.cfg 
b/llvm/test/CodeGen/PowerPC/lit.local.cfg
index 1dbbf92fcf5e..19bfd981b645 100644
--- a/llvm/test/CodeGen/PowerPC/lit.local.cfg
+++ b/llvm/test/CodeGen/PowerPC/lit.local.cfg
@@ -1,4

[llvm-branch-commits] [mlir] 3d693bd - [mlir][vector] Add memory effects to transfer_read transfer_write ops

[Thomas Raoux via llvm-branch-commits]

Author: Thomas Raoux
Date: 2021-01-11T09:25:37-08:00
New Revision: 3d693bd0bd77fe6f0dd922be374b7ba74739871a

URL: 
https://github.com/llvm/llvm-project/commit/3d693bd0bd77fe6f0dd922be374b7ba74739871a
DIFF: 
https://github.com/llvm/llvm-project/commit/3d693bd0bd77fe6f0dd922be374b7ba74739871a.diff

LOG: [mlir][vector] Add memory effects to transfer_read transfer_write ops

This allow more accurate modeling of the side effects and allow dead code
elimination to remove dead transfer ops.

Differential Revision: https://reviews.llvm.org/D94318

Added: 


Modified: 
mlir/include/mlir/Dialect/Vector/VectorOps.td
mlir/lib/Dialect/Vector/VectorOps.cpp
mlir/test/Conversion/VectorToSCF/vector-to-loops.mlir
mlir/test/Dialect/Vector/canonicalize.mlir

Removed: 




diff  --git a/mlir/include/mlir/Dialect/Vector/VectorOps.td 
b/mlir/include/mlir/Dialect/Vector/VectorOps.td
index 7f57dcd77def..6bfa89939b04 100644
--- a/mlir/include/mlir/Dialect/Vector/VectorOps.td
+++ b/mlir/include/mlir/Dialect/Vector/VectorOps.td
@@ -1055,7 +1055,8 @@ def Vector_ExtractStridedSliceOp :
 def Vector_TransferReadOp :
   Vector_Op<"transfer_read", [
   DeclareOpInterfaceMethods,
-  DeclareOpInterfaceMethods
+  DeclareOpInterfaceMethods,
+  DeclareOpInterfaceMethods
 ]>,
 Arguments<(ins AnyShaped:$source, Variadic:$indices,
AffineMapAttr:$permutation_map, AnyType:$padding,
@@ -1224,7 +1225,8 @@ def Vector_TransferReadOp :
 def Vector_TransferWriteOp :
   Vector_Op<"transfer_write", [
   DeclareOpInterfaceMethods,
-  DeclareOpInterfaceMethods
+  DeclareOpInterfaceMethods,
+  DeclareOpInterfaceMethods
   ]>,
 Arguments<(ins AnyVector:$vector, AnyShaped:$source,
Variadic:$indices,

diff  --git a/mlir/lib/Dialect/Vector/VectorOps.cpp 
b/mlir/lib/Dialect/Vector/VectorOps.cpp
index 91eab5027962..731ddae85ead 100644
--- a/mlir/lib/Dialect/Vector/VectorOps.cpp
+++ b/mlir/lib/Dialect/Vector/VectorOps.cpp
@@ -2227,6 +2227,14 @@ Optional> 
TransferReadOp::getShapeForUnroll() {
   return SmallVector{s.begin(), s.end()};
 }
 
+void TransferReadOp::getEffects(
+SmallVectorImpl>
+&effects) {
+  if (getShapedType().isa())
+effects.emplace_back(MemoryEffects::Read::get(), source(),
+ SideEffects::DefaultResource::get());
+}
+
 
//===--===//
 // TransferWriteOp
 
//===--===//
@@ -2341,6 +2349,14 @@ Optional> 
TransferWriteOp::getShapeForUnroll() {
   return llvm::to_vector<4>(getVectorType().getShape());
 }
 
+void TransferWriteOp::getEffects(
+SmallVectorImpl>
+&effects) {
+  if (getShapedType().isa())
+effects.emplace_back(MemoryEffects::Write::get(), source(),
+ SideEffects::DefaultResource::get());
+}
+
 
//===--===//
 // MaskedLoadOp
 
//===--===//

diff  --git a/mlir/test/Conversion/VectorToSCF/vector-to-loops.mlir 
b/mlir/test/Conversion/VectorToSCF/vector-to-loops.mlir
index 76e71b1c0bfd..e5bb65aa4208 100644
--- a/mlir/test/Conversion/VectorToSCF/vector-to-loops.mlir
+++ b/mlir/test/Conversion/VectorToSCF/vector-to-loops.mlir
@@ -1,5 +1,5 @@
-// RUN: mlir-opt %s -convert-vector-to-scf -split-input-file | FileCheck %s
-// RUN: mlir-opt %s -convert-vector-to-scf=full-unroll=true -split-input-file 
| FileCheck %s --check-prefix=FULL-UNROLL
+// RUN: mlir-opt %s -convert-vector-to-scf -split-input-file 
-allow-unregistered-dialect | FileCheck %s
+// RUN: mlir-opt %s -convert-vector-to-scf=full-unroll=true -split-input-file 
-allow-unregistered-dialect | FileCheck %s --check-prefix=FULL-UNROLL
 
 // CHECK-LABEL: func @materialize_read_1d() {
 func @materialize_read_1d() {
@@ -22,6 +22,9 @@ func @materialize_read_1d() {
   // CHECK-NEXT: else
   // CHECK-NEXT: vector.insertelement
   // CHECK-NEXT: store
+  // Add a dummy use to prevent dead code elimination from removing 
transfer
+  // read ops.
+  "dummy_use"(%f1, %f2, %f3, %f4) : (vector<4xf32>, vector<4xf32>, 
vector<4xf32>, vector<4xf32>) -> ()
 }
   }
   return
@@ -41,6 +44,9 @@ func @materialize_read_1d_partially_specialized(%dyn1 : 
index, %dyn2 : index, %d
 %f1 = vector.transfer_read %A[%i0, %i1, %i2, %i3, %i4], %f0 
{permutation_map = affine_map<(d0, d1, d2, d3, d4) -> (d3)>} : 
memref<7x?x?x42x?xf32>, vector<4xf32>
 %i3p1 = affine.apply affine_map<(d0) -> (d0 + 1)> (%i3)
 %f2 = vector.transfer_read %A[%i0, %i1, %i2, %i3p1, %i4], %f0 
{permutation_map = affine_map<(d0, d1, d2, d3, d4) -> (d3)>} : 
memref<7x?x?x42x?xf32>, vector<4xf32>
+// Add a dummy use to prevent dead code elimination from removin

[llvm-branch-commits] [mlir] c4486cf - [mlir][Linalg] Fix reshape fusion to reshape the outs instead of creating new tensors.

[via llvm-branch-commits]

Author: MaheshRavishankar
Date: 2021-01-11T09:26:22-08:00
New Revision: c4486cfd556869a837911c7719fb6c36018bbd1f

URL: 
https://github.com/llvm/llvm-project/commit/c4486cfd556869a837911c7719fb6c36018bbd1f
DIFF: 
https://github.com/llvm/llvm-project/commit/c4486cfd556869a837911c7719fb6c36018bbd1f.diff

LOG: [mlir][Linalg] Fix reshape fusion to reshape the outs instead of creating 
new tensors.

When fusing tensor_reshape ops with generic/indexed_Generic op, new
linalg.init_tensor operations were created for the `outs` of the fused
op. While correct (technically) it is better to just reshape the
original `outs` operands and rely on canonicalization of init_tensor
-> tensor_reshape to achieve the same effect.

Differential Revision: https://reviews.llvm.org/D93774

Added: 


Modified: 
mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
mlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
mlir/test/Dialect/Linalg/reshape_fusion.mlir
mlir/test/Dialect/Linalg/reshape_linearization_fusion.mlir

Removed: 




diff  --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td 
b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
index a2e7d436eeb8..0ce86e403681 100644
--- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
+++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
@@ -183,6 +183,14 @@ class Linalg_ReshapeLikeOp 
traits = []> :
   return llvm::to_vector<4>(llvm::map_range(reassociation(), [
   ](Attribute a) { return a.cast().getValue(); }));
 }
+SmallVector getReassociationExprs() {
+  return
+llvm::to_vector<4>(llvm::map_range(reassociation(),
+ [](Attribute a) {
+   return llvm::to_vector<2>(
+ a.cast().getValue().getResults());
+ }));
+}
   }];
   let assemblyFormat = [{
 $src $reassociation attr-dict `:` type($src) `into` type(results)

diff  --git a/mlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp 
b/mlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
index 37062ac33e2b..833662d282b6 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
@@ -566,45 +566,6 @@ static RankedTensorType getExpandedType(RankedTensorType 
originalType,
   return RankedTensorType::get(expandedShape, originalType.getElementType());
 }
 
-/// Get the value to use for the output in the expanded operation given the
-/// `indexingMap` for the output in the original op. Creates an
-/// `linalg.init_tensor` operation to materialize the tensor that carries the
-/// shape information. This is only used when the tensor_reshape is expanding
-/// and is a consumer. In such cases, the tensor_reshape op semantics 
gaurantees
-/// that the shape of the output is computable from the shape of the input 
since
-/// at most one of the expanded dims can be dynamic.
-static Value getOutputValueForExpandedOp(OpBuilder &builder, Location loc,
- AffineMap indexingMap, Value result,
- const ExpansionInfo &expansionInfo) {
-  SmallVector dynamicDims;
-  SmallVector staticDims;
-  ShapedType resultType = result.getType().cast();
-  ArrayRef origShape = resultType.getShape();
-  for (AffineExpr expr : indexingMap.getResults()) {
-unsigned origDimPos = expr.cast().getPosition();
-bool foundDynamic = false;
-int64_t linearizedShape = 1;
-for (int64_t extent : expansionInfo.getExpandedShapeOfDim(origDimPos)) {
-  if (ShapedType::isDynamic(extent)) {
-assert(!foundDynamic &&
-   "Expanded dimensions of reshape can have only one dynamic dim");
-staticDims.push_back(ShapedType::kDynamicSize);
-foundDynamic = true;
-continue;
-  }
-  staticDims.push_back(extent);
-  linearizedShape *= extent;
-}
-if (ShapedType::isDynamic(origShape[origDimPos])) {
-  Value origDim = builder.create(loc, result, origDimPos);
-  dynamicDims.push_back(builder.create(
-  loc, origDim, builder.create(loc, 
linearizedShape)));
-}
-  }
-  return builder.create(loc, dynamicDims, staticDims,
-  resultType.getElementType());
-}
-
 /// Returns the reassociation maps to use in the `linalg.tensor_reshape`
 /// operation to convert the operands of the origial operation to operands of
 /// the expanded operation. The same method is used to compute the
@@ -734,8 +695,16 @@ fuseWithReshapeByExpansion(LinalgOp linalgOp, 
TensorReshapeOp reshapeOp,
   SmallVector outputs;
   for (auto result : llvm::enumerate(linalgOp.getOutputs())) {
 AffineMap indexingMap = linalgOp.getOutputIndexingMap(result.index());
-outputs.push_back(getOutputValueForExpandedOp(
-rewriter, loc, indexingMap, result.value(), expansionInfo));
+RankedTensorType expandedOutputType =
+getExpandedType(result.value().getType().

[llvm-branch-commits] [llvm] be179b9 - [FastISel] NFC: Remove obsolete -fast-isel-sink-local-values option

[Paul Robinson via llvm-branch-commits]

Author: Paul Robinson
Date: 2021-01-11T09:32:49-08:00
New Revision: be179b9946f6dfd6e3d957d9f7a6ee992d1f69d2

URL: 
https://github.com/llvm/llvm-project/commit/be179b9946f6dfd6e3d957d9f7a6ee992d1f69d2
DIFF: 
https://github.com/llvm/llvm-project/commit/be179b9946f6dfd6e3d957d9f7a6ee992d1f69d2.diff

LOG: [FastISel] NFC: Remove obsolete -fast-isel-sink-local-values option

This option is not used for anything after #c161665 (D91737).
This commit reapplies #a474657.

Added: 


Modified: 
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/test/CodeGen/AArch64/arm64-abi_align.ll
llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll
llvm/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll
llvm/test/CodeGen/AArch64/arm64-fast-isel.ll
llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll
llvm/test/CodeGen/AArch64/swifterror.ll
llvm/test/CodeGen/ARM/fast-isel-call.ll
llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
llvm/test/CodeGen/ARM/fast-isel-select.ll
llvm/test/CodeGen/ARM/fast-isel-vararg.ll
llvm/test/CodeGen/ARM/swifterror.ll
llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll
llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
llvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll
llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
llvm/test/CodeGen/X86/fast-isel-call-cleanup.ll
llvm/test/CodeGen/X86/inreg.ll
llvm/test/CodeGen/X86/pr32241.ll
llvm/test/CodeGen/X86/pr32284.ll
llvm/test/CodeGen/X86/pr32340.ll
llvm/test/CodeGen/X86/pr32345.ll
llvm/test/CodeGen/X86/pr32484.ll
llvm/test/CodeGen/X86/sink-local-value.ll
llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
llvm/test/DebugInfo/Mips/delay-slot.ll
llvm/test/DebugInfo/X86/prologue-stack.ll

Removed: 




diff  --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp 
b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 27e359a5c696..e9b116798ad3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -113,11 +113,6 @@ using namespace PatternMatch;
 
 #define DEBUG_TYPE "isel"
 
-// FIXME: Remove this after the feature has proven reliable.
-static cl::opt SinkLocalValues("fast-isel-sink-local-values",
- cl::init(true), cl::Hidden,
- cl::desc("Sink local values in 
FastISel"));
-
 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
  "target-independent selector");
 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "

diff  --git a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll 
b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
index fe0b31fb2db9..5224eca76619 100644
--- a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
@@ -1,5 +1,5 @@
-; RUN: llc -fast-isel-sink-local-values -aarch64-load-store-renaming=true < %s 
-mtriple=arm64-apple-darwin -mcpu=cyclone -enable-misched=false 
-frame-pointer=all | FileCheck %s
-; RUN: llc -fast-isel-sink-local-values -aarch64-load-store-renaming=true  < 
%s -mtriple=arm64-apple-darwin -O0 -frame-pointer=all -fast-isel | FileCheck 
-check-prefix=FAST %s
+; RUN: llc -aarch64-load-store-renaming=true < %s -mtriple=arm64-apple-darwin 
-mcpu=cyclone -enable-misched=false -frame-pointer=all | FileCheck %s
+; RUN: llc -aarch64-load-store-renaming=true  < %s -mtriple=arm64-apple-darwin 
-O0 -frame-pointer=all -fast-isel | FileCheck -check-prefix=FAST %s
 
 ; rdar://12648441
 ; Generated from arm64-arguments.c with -O2.

diff  --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll 
b/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
index a677d4a14353..9b9eb8d29bed 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
@@ -1,6 +1,6 @@
-; RUN: llc -fast-isel-sink-local-values -O0 -fast-isel -fast-isel-abort=2 
-code-model=small -verify-machineinstrs -frame-pointer=all 
-mtriple=arm64-apple-darwin   < %s | FileCheck %s
-; RUN: llc -fast-isel-sink-local-values -O0 -fast-isel -fast-isel-abort=2 
-code-model=large -verify-machineinstrs -frame-pointer=all 
-mtriple=arm64-apple-darwin   < %s | FileCheck %s --check-prefix=LARGE
-; RUN: llc -fast-isel-sink-local-values -O0 -fast-isel -fast-isel-abort=2 
-code-model=small -verify-machineinstrs -frame-pointer=all 
-mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -O0 -fast-isel -fast-isel-abort=2 -code-model=small 
-verify-machineinstrs -frame-pointer=all -mtriple=arm64-apple-darwin   < %s | 
FileCheck %s
+; RUN: llc -O0 -fast-isel -fast-isel-abort=2 -code-model=large 
-verify-machineinstrs -frame-pointer=all -mtriple=arm64-apple-darwin   < %s | 
FileCheck %s --check-prefix=LARGE
+; RUN: llc -O0

[llvm-branch-commits] [lld] ac2224c - [ELF] --exclude-libs: localize defined libcall symbols referenced by lto.tmp

[Fangrui Song via llvm-branch-commits]

Author: Fangrui Song
Date: 2021-01-11T09:33:22-08:00
New Revision: ac2224c02282039f41294842396cbbe47ea29a23

URL: 
https://github.com/llvm/llvm-project/commit/ac2224c02282039f41294842396cbbe47ea29a23
DIFF: 
https://github.com/llvm/llvm-project/commit/ac2224c02282039f41294842396cbbe47ea29a23.diff

LOG: [ELF] --exclude-libs: localize defined libcall symbols referenced by 
lto.tmp

Fixes PR48681: after LTO, lto.tmp may reference a libcall symbol not in an IR
symbol table of any bitcode file. If such a symbol is defined in an archive
matched by a --exclude-libs, we don't correctly localize the symbol.

Add another `excludeLibs` after `compileBitcodeFiles` to localize such libcall
symbols. Unfortunately we have keep the existing one for D43126.

Using VER_NDX_LOCAL is an implementation detail of `--exclude-libs`, it does not
necessarily tie to the "localize" behavior.  `local:` patterns in a version
script can be omitted.
The `symbol ... has undefined version ...` error should not be exempted.
Ideally we should error as GNU ld does. 
https://issuetracker.google.com/issues/73020933

Reviewed By: psmith

Differential Revision: https://reviews.llvm.org/D94280

Added: 
lld/test/ELF/lto/exclude-libs-libcall.ll

Modified: 
lld/ELF/Driver.cpp

Removed: 




diff  --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp
index 5cc32f81c2ec..e1395a568ea2 100644
--- a/lld/ELF/Driver.cpp
+++ b/lld/ELF/Driver.cpp
@@ -2146,7 +2146,11 @@ template  void 
LinkerDriver::link(opt::InputArgList &args) {
   // They also might be exported if referenced by DSOs.
   script->declareSymbols();
 
-  // Handle the -exclude-libs option.
+  // Handle --exclude-libs. This is before scanVersionScript() due to a
+  // workaround for Android ndk: for a defined versioned symbol in an archive
+  // without a version node in the version script, Android does not expect a
+  // 'has undefined version' error in -shared --exclude-libs=ALL mode 
(PR36295).
+  // GNU ld errors in this case.
   if (args.hasArg(OPT_exclude_libs))
 excludeLibs(args);
 
@@ -2179,6 +2183,11 @@ template  void 
LinkerDriver::link(opt::InputArgList &args) {
   // except a few linker-synthesized ones will be added to the symbol table.
   compileBitcodeFiles();
 
+  // Handle --exclude-libs again because lto.tmp may reference additional
+  // libcalls symbols defined in an excluded archive.
+  if (args.hasArg(OPT_exclude_libs))
+excludeLibs(args);
+
   // Symbol resolution finished. Report backward reference problems.
   reportBackrefs();
   if (errorCount())

diff  --git a/lld/test/ELF/lto/exclude-libs-libcall.ll 
b/lld/test/ELF/lto/exclude-libs-libcall.ll
new file mode 100644
index ..ece587f1c4da
--- /dev/null
+++ b/lld/test/ELF/lto/exclude-libs-libcall.ll
@@ -0,0 +1,28 @@
+; REQUIRES: x86
+; RUN: rm -rf %t && split-file %s %t
+; RUN: llvm-as %t/a.ll -o %t/a.bc
+; RUN: llvm-mc -filetype=obj -triple=x86_64 %t/b.s -o %t/b.o
+; RUN: llvm-ar rc %t/b.a %t/b.o
+; RUN: ld.lld -shared --exclude-libs=b.a %t/a.bc %t/b.a -o %t.so -y __divti3 
2>&1 | FileCheck %s --check-prefix=TRACE
+; RUN: llvm-readelf --dyn-syms %t.so | FileCheck %s
+
+; TRACE:  {{.*}}/b.a: lazy definition of __divti3
+; TRACE-NEXT: lto.tmp: reference to __divti3
+; TRACE-NEXT: {{.*}}/b.a(b.o): definition of __divti3
+
+; CHECK: Symbol table '.dynsym' contains 2 entries:
+; CHECK-NOT: __divti3
+
+;--- a.ll
+target triple = "x86_64-unknown-linux"
+target datalayout = 
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+
+define i128 @foo(i128 %x, i128 %y) {
+entry:
+  %div = sdiv i128 %x, %y
+  ret i128 %div
+}
+
+;--- b.s
+.globl __divti3
+__divti3:



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[llvm-branch-commits] [llvm] 171771e - [SystemZ] Minor NFC fix in SchedModels.

[Jonas Paulsson via llvm-branch-commits]

Author: Jonas Paulsson
Date: 2021-01-11T11:38:23-06:00
New Revision: 171771e0780fd5d028a24f8650a11299478df266

URL: 
https://github.com/llvm/llvm-project/commit/171771e0780fd5d028a24f8650a11299478df266
DIFF: 
https://github.com/llvm/llvm-project/commit/171771e0780fd5d028a24f8650a11299478df266.diff

LOG: [SystemZ]  Minor NFC fix in SchedModels.

The unused LRMux opcode was removed by 8f8c381, but a regexp still matched
for it in the scheduler files which is now removed.

Review: Ulrich Weigand

Added: 


Modified: 
llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td

Removed: 




diff  --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td 
b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
index b3266051da4e1..de49106a5a601 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -204,7 +204,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex 
"LLIL(F|H|L)$")>;
 
 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>;
 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR$")>;
 
 // Load and zero rightmost byte
 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>;

diff  --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td 
b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
index df7282a2961b8..5ea269cb891d6 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -205,7 +205,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex 
"LLIL(F|H|L)$")>;
 
 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>;
 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR$")>;
 
 // Load and zero rightmost byte
 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>;

diff  --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td 
b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index 56ceb88f35d4f..6a28aec6f846e 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -206,7 +206,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex 
"LLIL(F|H|L)$")>;
 
 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>;
 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR$")>;
 
 // Load and zero rightmost byte
 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>;

diff  --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td 
b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
index ca714ef1a702b..9a306591a34f7 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -182,7 +182,7 @@ def : InstRW<[WLat1, FXU, NormalGr], (instregex 
"LLIL(F|H|L)$")>;
 
 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(F|H)I$")>;
 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>;
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR(Mux)?$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR$")>;
 
 // Load and test
 def : InstRW<[WLat1LSU, WLat1LSU, LSU, FXU, NormalGr], (instregex "LT(G)?$")>;

diff  --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td 
b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
index fb226be678dad..f3ff1dfaba75c 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -187,7 +187,7 @@ def : InstRW<[WLat1, FXU, NormalGr], (instregex 
"LLIL(F|H|L)$")>;
 
 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(F|H)I$")>;
 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>;
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR(Mux)?$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR$")>;
 
 // Load and trap
 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "L(FH|G)?AT$")>;



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[llvm-branch-commits] [llvm] 1f9c292 - [FastISel] NFC: Clean up unnecessary bookkeeping

[Paul Robinson via llvm-branch-commits]

Author: Paul Robinson
Date: 2021-01-11T09:40:39-08:00
New Revision: 1f9c29228cecfde9e993cd2818d9cd3119189163

URL: 
https://github.com/llvm/llvm-project/commit/1f9c29228cecfde9e993cd2818d9cd3119189163
DIFF: 
https://github.com/llvm/llvm-project/commit/1f9c29228cecfde9e993cd2818d9cd3119189163.diff

LOG: [FastISel] NFC: Clean up unnecessary bookkeeping

Now that we flush the local value map for every instruction, we don't
need any extra flushes for specific cases.  Also, LastFlushPoint is
not used for anything.  Follow-ups to #c161665 (D91734).

This reapplies #3fd39d3.

Differential Revision: https://reviews.llvm.org/D92338

Added: 


Modified: 
llvm/include/llvm/CodeGen/FastISel.h
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

Removed: 




diff  --git a/llvm/include/llvm/CodeGen/FastISel.h 
b/llvm/include/llvm/CodeGen/FastISel.h
index d20f443e3013..81c1d6aad49a 100644
--- a/llvm/include/llvm/CodeGen/FastISel.h
+++ b/llvm/include/llvm/CodeGen/FastISel.h
@@ -224,10 +224,6 @@ class FastISel {
   /// makes sense (for example, on function calls)
   MachineInstr *EmitStartPt;
 
-  /// Last local value flush point. On a subsequent flush, no local value will
-  /// sink past this point.
-  MachineBasicBlock::iterator LastFlushPoint;
-
 public:
   virtual ~FastISel();
 

diff  --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp 
b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index e9b116798ad3..c018f1647169 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -236,7 +236,6 @@ void FastISel::flushLocalValueMap() {
   LastLocalValue = EmitStartPt;
   recomputeInsertPt();
   SavedInsertPt = FuncInfo.InsertPt;
-  LastFlushPoint = FuncInfo.InsertPt;
 }
 
 bool FastISel::hasTrivialKill(const Value *V) {
@@ -458,8 +457,6 @@ void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
   assert(I.isValid() && E.isValid() && std::distance(I, E) > 0 &&
  "Invalid iterator!");
   while (I != E) {
-if (LastFlushPoint == I)
-  LastFlushPoint = E;
 if (SavedInsertPt == I)
   SavedInsertPt = E;
 if (EmitStartPt == I)
@@ -1210,11 +1207,6 @@ bool FastISel::selectCall(const User *I) {
 
   // Handle simple inline asms.
   if (const InlineAsm *IA = dyn_cast(Call->getCalledOperand())) {
-// If the inline asm has side effects, then make sure that no local value
-// lives across by flushing the local value map.
-if (IA->hasSideEffects())
-  flushLocalValueMap();
-
 // Don't attempt to handle constraints.
 if (!IA->getConstraintString().empty())
   return false;
@@ -1244,15 +1236,6 @@ bool FastISel::selectCall(const User *I) {
   if (const auto *II = dyn_cast(Call))
 return selectIntrinsicCall(II);
 
-  // Usually, it does not make sense to initialize a value,
-  // make an unrelated function call and use the value, because
-  // it tends to be spilled on the stack. So, we move the pointer
-  // to the last local value to the beginning of the block, so that
-  // all the values which have already been materialized,
-  // appear after the call. It also makes sense to skip intrinsics
-  // since they tend to be inlined.
-  flushLocalValueMap();
-
   return lowerCall(Call);
 }
 
@@ -1409,20 +1392,6 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst 
*II) {
 return selectXRayCustomEvent(II);
   case Intrinsic::xray_typedevent:
 return selectXRayTypedEvent(II);
-
-  case Intrinsic::memcpy:
-  case Intrinsic::memcpy_element_unordered_atomic:
-  case Intrinsic::memcpy_inline:
-  case Intrinsic::memmove:
-  case Intrinsic::memmove_element_unordered_atomic:
-  case Intrinsic::memset:
-  case Intrinsic::memset_element_unordered_atomic:
-// Flush the local value map just like we do for regular calls,
-// to avoid excessive spills and reloads.
-// These intrinsics mostly turn into library calls at O0; and
-// even memcpy_inline should be treated like one for this purpose.
-flushLocalValueMap();
-break;
   }
 
   return fastLowerIntrinsicCall(II);



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[llvm-branch-commits] [clang] 35c9baa - [attributes] Add a facility for enforcing a Trusted Computing Base.

[Artem Dergachev via llvm-branch-commits]

Author: Sean Dooher
Date: 2021-01-11T10:20:51-08:00
New Revision: 35c9baa11e4be6ae570674eec2de8bd928639b18

URL: 
https://github.com/llvm/llvm-project/commit/35c9baa11e4be6ae570674eec2de8bd928639b18
DIFF: 
https://github.com/llvm/llvm-project/commit/35c9baa11e4be6ae570674eec2de8bd928639b18.diff

LOG: [attributes]  Add a facility for enforcing a Trusted Computing Base.

Introduce a function attribute 'enforce_tcb' that prevents the function
from calling other functions without the same attribute. This allows
isolating code that's considered to be somehow privileged so that it could not
use its privileges to exhibit arbitrary behavior.

Introduce an on-by-default warning '-Wtcb-enforcement' that warns
about violations of the above rule.

Introduce a function attribute 'enforce_tcb_leaf' that suppresses
the new warning within the function it is attached to. Such leaf functions
may implement common functionality between the trusted and the untrusted code
but they require extra careful audit with respect to their capabilities.

Fixes after a revert in 419ef38a50293c58078f830517f5e305068dbee6:
Fix a test.
Add workaround for GCC bug (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67274).
Attribute the patch appropriately!

Differential Revision: https://reviews.llvm.org/D91898

Added: 
clang/test/Sema/attr-enforce-tcb-errors.cpp
clang/test/Sema/attr-enforce-tcb.c
clang/test/Sema/attr-enforce-tcb.cpp

Modified: 
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaChecking.cpp
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaDeclAttr.cpp
clang/test/Misc/pragma-attribute-supported-attributes-list.test

Removed: 




diff  --git a/clang/include/clang/Basic/Attr.td 
b/clang/include/clang/Basic/Attr.td
index 248409946123e..c51e95fa6fa87 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -3653,3 +3653,19 @@ def Builtin : InheritableAttr {
   let SemaHandler = 0;
   let Documentation = [Undocumented];
 }
+
+def EnforceTCB : InheritableAttr {
+  let Spellings = [Clang<"enforce_tcb">];
+  let Subjects = SubjectList<[Function]>;
+  let Args = [StringArgument<"TCBName">];
+  let Documentation = [EnforceTCBDocs];
+  bit InheritEvenIfAlreadyPresent = 1;
+}
+
+def EnforceTCBLeaf : InheritableAttr {
+  let Spellings = [Clang<"enforce_tcb_leaf">];
+  let Subjects = SubjectList<[Function]>;
+  let Args = [StringArgument<"TCBName">];
+  let Documentation = [EnforceTCBLeafDocs];
+  bit InheritEvenIfAlreadyPresent = 1;
+}

diff  --git a/clang/include/clang/Basic/AttrDocs.td 
b/clang/include/clang/Basic/AttrDocs.td
index 9cf0c59e07bba..fffede41db1e8 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5725,3 +5725,28 @@ Attribute docs`_, and `the GCC Inline docs`_.
 }];
   let Heading = "always_inline, __force_inline";
 }
+
+def EnforceTCBDocs : Documentation {
+  let Category = DocCatFunction;
+  let Content = [{
+  The ``enforce_tcb`` attribute can be placed on functions to enforce that a
+  trusted compute base (TCB) does not call out of the TCB. This generates a
+  warning every time a function not marked with an ``enforce_tcb`` attribute is
+  called from a function with the ``enforce_tcb`` attribute. A function may be 
a
+  part of multiple TCBs. Invocations through function pointers are currently
+  not checked. Builtins are considered to a part of every TCB.
+
+  - ``enforce_tcb(Name)`` indicates that this function is a part of the TCB 
named ``Name``
+  }];
+}
+
+def EnforceTCBLeafDocs : Documentation {
+  let Category = DocCatFunction;
+  let Content = [{
+  The ``enforce_tcb_leaf`` attribute satisfies the requirement enforced by
+  ``enforce_tcb`` for the marked function to be in the named TCB but does not
+  continue to check the functions called from within the leaf function.
+
+  - ``enforce_tcb_leaf(Name)`` indicates that this function is a part of the 
TCB named ``Name``
+  }];
+}

diff  --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td 
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 0405195912b23..c048fc89813f8 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -6,4 +6,11 @@ def err_probability_not_constant_float : Error<
 def err_probability_out_of_range : Error<
"probability argument to __builtin_expect_with_probability is outside the "
"range [0.0, 1.0]">;
+
+// TCB warnings
+def err_tcb_conflicting_attributes : Error<
+  "attributes '%0(\"%2\")' and '%1(\"%2\")' are mutually exclusive">;
+def warn_tcb_enforcement_violation : Warning<
+  "calling %0 is a violation of trusted computing base '%1'">,
+  InGroup>;
 } // end of sema component.

diff  --git a/clang/include/clang/Sema/Sema.h b/clan

[llvm-branch-commits] [llvm] a902147 - [Hexagon] Custom-widen SETCC's operands

[Krzysztof Parzyszek via llvm-branch-commits]

Author: Krzysztof Parzyszek
Date: 2021-01-11T12:21:49-06:00
New Revision: a90214760d0414912953e77b5b314be2b8e7df77

URL: 
https://github.com/llvm/llvm-project/commit/a90214760d0414912953e77b5b314be2b8e7df77
DIFF: 
https://github.com/llvm/llvm-project/commit/a90214760d0414912953e77b5b314be2b8e7df77.diff

LOG: [Hexagon] Custom-widen SETCC's operands

The result cannot be widened, unfortunately, because widening vNi1
would depend on the context in which it appears (i.e. the type alone
is not sufficient to tell if it needs to be widened).

Added: 
llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll

Modified: 
llvm/lib/Target/Hexagon/HexagonISelLowering.h
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

Removed: 




diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h 
b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index e174e5279ac1..cfccb14a09c9 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -486,6 +486,7 @@ class HexagonTargetLowering : public TargetLowering {
   SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;
   SDValue WidenHvxLoad(SDValue Op, SelectionDAG &DAG) const;
   SDValue WidenHvxStore(SDValue Op, SelectionDAG &DAG) const;
+  SDValue WidenHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
   SDValue WidenHvxExtend(SDValue Op, SelectionDAG &DAG) const;
   SDValue WidenHvxTruncate(SDValue Op, SelectionDAG &DAG) const;
 

diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 
b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index f228e0a23794..161035b93e8b 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -51,6 +51,13 @@ HexagonTargetLowering::initializeHVXLowering() {
 addRegisterClass(MVT::v256i8,  &Hexagon::HvxWRRegClass);
 addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass);
 addRegisterClass(MVT::v64i32,  &Hexagon::HvxWRRegClass);
+// Treat v16i1 as a legal type, since there is no way to widen vNi1:
+// the validity of vNi1 may depend on how the result was obtained.
+// For example v32i1 is ok when it's a result of comparing v32i32,
+// but would need to be widened if it came from comparing v32i16.
+// This precludes using getTypeToTransformTo, since it doesn't have
+// the necessary context to decide what to do.
+addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass);
 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass);
 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass);
 addRegisterClass(MVT::v128i1, &Hexagon::HvxQRRegClass);
@@ -241,7 +248,6 @@ HexagonTargetLowering::initializeHVXLowering() {
   }
 
   // Handle store widening for short vectors.
-  std::vector ShortTys;
   unsigned HwLen = Subtarget.getVectorLength();
   for (MVT ElemTy : Subtarget.getHVXElementTypes()) {
 if (ElemTy == MVT::i1)
@@ -254,6 +260,7 @@ HexagonTargetLowering::initializeHVXLowering() {
   if (Action == TargetLoweringBase::TypeWidenVector) {
 setOperationAction(ISD::LOAD, VecTy, Custom);
 setOperationAction(ISD::STORE,VecTy, Custom);
+setOperationAction(ISD::SETCC,VecTy, Custom);
 setOperationAction(ISD::TRUNCATE, VecTy, Custom);
 setOperationAction(ISD::ANY_EXTEND,   VecTy, Custom);
 setOperationAction(ISD::SIGN_EXTEND,  VecTy, Custom);
@@ -1932,6 +1939,27 @@ HexagonTargetLowering::WidenHvxStore(SDValue Op, 
SelectionDAG &DAG) const {
 MemOp, ISD::UNINDEXED, false, false);
 }
 
+SDValue
+HexagonTargetLowering::WidenHvxSetCC(SDValue Op, SelectionDAG &DAG) const {
+  const SDLoc &dl(Op);
+  SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
+  MVT ElemTy = ty(Op0).getVectorElementType();
+  unsigned HwLen = Subtarget.getVectorLength();
+
+  unsigned WideOpLen = (8 * HwLen) / ElemTy.getSizeInBits();
+  assert(WideOpLen * ElemTy.getSizeInBits() == 8 * HwLen);
+  MVT WideOpTy = MVT::getVectorVT(ElemTy, WideOpLen);
+
+  SDValue WideOp0 = appendUndef(Op0, WideOpTy, DAG);
+  SDValue WideOp1 = appendUndef(Op1, WideOpTy, DAG);
+  EVT ResTy =
+  getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), WideOpTy);
+  SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy,
+  {WideOp0, WideOp1, Op.getOperand(2)});
+  return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ty(Op),
+ {SetCC, getZero(dl, MVT::i32, DAG)});
+}
+
 SDValue
 HexagonTargetLowering::WidenHvxExtend(SDValue Op, SelectionDAG &DAG) const {
   const SDLoc &dl(Op);
@@ -2102,20 +2130,28 @@ HexagonTargetLowering::LowerHvxOperationWrapper(SDNode 
*N,
 case ISD::ANY_EXTEND:
 case ISD::SIGN_EXTEND:
 case ISD::ZERO_EXTEND:
-  assert(shouldWidenToHvx(ty(Op.getOperand(0)), DAG) && "Not widening?");
-  if (SDValue T = WidenHvxExtend(Op, DAG))
-Results.push_back(T

[llvm-branch-commits] [llvm] bcec0f2 - [AMDGPU] Deduplicate VOP tablegen asm & ins

[Joe Nash via llvm-branch-commits]

Author: Joe Nash
Date: 2021-01-11T13:49:26-05:00
New Revision: bcec0f27a2c37b64d5e8b84bbbfa563edae6affe

URL: 
https://github.com/llvm/llvm-project/commit/bcec0f27a2c37b64d5e8b84bbbfa563edae6affe
DIFF: 
https://github.com/llvm/llvm-project/commit/bcec0f27a2c37b64d5e8b84bbbfa563edae6affe.diff

LOG: [AMDGPU] Deduplicate VOP tablegen asm & ins

VOP3 and VOP DPP subroutines to generate input
operands and asm strings were essentially copy
pasted several times. They are deduplicated to
reduce the maintenance burden and allow faster
development.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D94102

Change-Id: I76225eed3c33239d9573351e0c8a0abfad0146ea

Added: 


Modified: 
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/VOP3Instructions.td

Removed: 




diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td 
b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index e48138e56d71..78600bebdad2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1587,7 +1587,7 @@ class getIns32  {
 // Returns the input arguments for VOP3 instructions for the given SrcVT.
 class getIns64  {
 
   dag ret =
@@ -1602,7 +1602,7 @@ class getIns64  {
+  // getInst64 handles clamp and omod. implicit mutex between vop3p and omod
+  dag base = getIns64 .ret;
+  dag opsel = (ins op_sel0:$op_sel);
+  dag vop3pFields = (ins op_sel_hi0:$op_sel_hi, neg_lo0:$neg_lo, 
neg_hi0:$neg_hi);
+  dag ret = !con(base,
+ !if(HasOpSel, opsel,(ins)),
+ !if(IsVOP3P, vop3pFields,(ins)));
+}
 
-// The modifiers (except clamp) are dummy operands for the benefit of
-// printing and parsing. They defer their values to looking at the
-// srcN_modifiers for what to print.
 class getInsVOP3P  {
-  dag ret = !if (!eq(NumSrcArgs, 2),
-!if (HasClamp,
-  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
-   Src1Mod:$src1_modifiers, Src1RC:$src1,
-   clampmod0:$clamp,
-   op_sel0:$op_sel, op_sel_hi0:$op_sel_hi,
-   neg_lo0:$neg_lo, neg_hi0:$neg_hi),
-  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
-   Src1Mod:$src1_modifiers, Src1RC:$src1,
-   op_sel0:$op_sel, op_sel_hi0:$op_sel_hi,
-   neg_lo0:$neg_lo, neg_hi0:$neg_hi)),
-// else NumSrcArgs == 3
-!if (HasClamp,
-  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
-   Src1Mod:$src1_modifiers, Src1RC:$src1,
-   Src2Mod:$src2_modifiers, Src2RC:$src2,
-   clampmod0:$clamp,
-   op_sel0:$op_sel, op_sel_hi0:$op_sel_hi,
-   neg_lo0:$neg_lo, neg_hi0:$neg_hi),
-  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
-   Src1Mod:$src1_modifiers, Src1RC:$src1,
-   Src2Mod:$src2_modifiers, Src2RC:$src2,
-   op_sel0:$op_sel, op_sel_hi0:$op_sel_hi,
-   neg_lo0:$neg_lo, neg_hi0:$neg_hi))
-  );
+  dag ret = getInsVOP3Base.ret;
 }
 
-class getInsVOP3OpSel  {
-  dag ret = !if (!eq(NumSrcArgs, 2),
-!if (HasClamp,
-  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
-   Src1Mod:$src1_modifiers, Src1RC:$src1,
-   clampmod0:$clamp,
-   op_sel0:$op_sel),
-  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
-   Src1Mod:$src1_modifiers, Src1RC:$src1,
-   op_sel0:$op_sel)),
-// else NumSrcArgs == 3
-!if (HasClamp,
-  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
-   Src1Mod:$src1_modifiers, Src1RC:$src1,
-   Src2Mod:$src2_modifiers, Src2RC:$src2,
-   clampmod0:$clamp,
-   op_sel0:$op_sel),
-  (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
-   Src1Mod:$src1_modifiers, Src1RC:$src1,
-   Src2Mod:$src2_modifiers, Src2RC:$src2,
-   op_sel0:$op_sel))
-  );
+class getInsVOP3OpSel  {
+  dag ret = getInsVOP3Base.ret;
 }
 
-class getInsDPP  {
 
   dag ret = !if (!eq(NumSrcArgs, 0),
 // VOP1 without input operands (V_NOP)
-(ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl),
+(ins ),
 !if (!eq(NumSrcArgs, 1),
   !if (HasModifiers,
 // VOP1_DPP with modifiers
 (ins DstRC:$old, Src0Mod:$src0_modifiers,
- Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
+ Src0RC:$src0)
   /* else */,
 // VOP1_DPP without modifiers
-(ins DstRC:$old, Src0RC:$src0,
- dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
- bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
-  /* endif */)
-  /* NumSrcArgs == 2 */,
+(ins DstRC:$old, Src0RC:$src0)
+  /* endif */),
   !if (HasModifiers,
 // VOP2_DPP with modifiers
 (ins DstRC:$old,

[llvm-branch-commits] [mlir] 74628c4 - [mlir] Add Python bindings for AffineExpr

[Alex Zinenko via llvm-branch-commits]

Author: Alex Zinenko
Date: 2021-01-11T19:57:13+01:00
New Revision: 74628c43053b482f35f0f1e6b4eac743fbe425e5

URL: 
https://github.com/llvm/llvm-project/commit/74628c43053b482f35f0f1e6b4eac743fbe425e5
DIFF: 
https://github.com/llvm/llvm-project/commit/74628c43053b482f35f0f1e6b4eac743fbe425e5.diff

LOG: [mlir] Add Python bindings for AffineExpr

This adds the Python bindings for AffineExpr and a couple of utility functions
to the C API. AffineExpr is a top-level context-owned object and is modeled
similarly to attributes and types. It is required, e.g., to build layout maps
of the built-in memref type.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94225

Added: 
mlir/test/Bindings/Python/ir_affine_expr.py

Modified: 
mlir/include/mlir-c/AffineExpr.h
mlir/include/mlir-c/Bindings/Python/Interop.h
mlir/lib/Bindings/Python/IRModules.cpp
mlir/lib/Bindings/Python/IRModules.h
mlir/lib/CAPI/IR/AffineExpr.cpp
mlir/test/CAPI/ir.c

Removed: 




diff  --git a/mlir/include/mlir-c/AffineExpr.h 
b/mlir/include/mlir-c/AffineExpr.h
index 93b8e832b44f..2eb8ae03e03d 100644
--- a/mlir/include/mlir-c/AffineExpr.h
+++ b/mlir/include/mlir-c/AffineExpr.h
@@ -45,6 +45,16 @@ DEFINE_C_API_STRUCT(MlirAffineExpr, const void);
 MLIR_CAPI_EXPORTED MlirContext
 mlirAffineExprGetContext(MlirAffineExpr affineExpr);
 
+/// Returns `true` if the two affine expressions are equal.
+MLIR_CAPI_EXPORTED bool mlirAffineExprEqual(MlirAffineExpr lhs,
+MlirAffineExpr rhs);
+
+/// Returns `true` if the given affine expression is a null expression. Note
+/// constant zero is not a null expression.
+inline bool mlirAffineExprIsNull(MlirAffineExpr affineExpr) {
+  return affineExpr.ptr == NULL;
+}
+
 /** Prints an affine expression by sending chunks of the string representation
  * and forwarding `userData to `callback`. Note that the callback may be called
  * several times with consecutive chunks of the string. */
@@ -82,6 +92,9 @@ MLIR_CAPI_EXPORTED bool 
mlirAffineExprIsFunctionOfDim(MlirAffineExpr affineExpr,
 // Affine Dimension Expression.
 
//===--===//
 
+/// Checks whether the given affine expression is a dimension expression.
+MLIR_CAPI_EXPORTED bool mlirAffineExprIsADim(MlirAffineExpr affineExpr);
+
 /// Creates an affine dimension expression with 'position' in the context.
 MLIR_CAPI_EXPORTED MlirAffineExpr mlirAffineDimExprGet(MlirContext ctx,
intptr_t position);
@@ -94,6 +107,9 @@ mlirAffineDimExprGetPosition(MlirAffineExpr affineExpr);
 // Affine Symbol Expression.
 
//===--===//
 
+/// Checks whether the given affine expression is a symbol expression.
+MLIR_CAPI_EXPORTED bool mlirAffineExprIsASymbol(MlirAffineExpr affineExpr);
+
 /// Creates an affine symbol expression with 'position' in the context.
 MLIR_CAPI_EXPORTED MlirAffineExpr mlirAffineSymbolExprGet(MlirContext ctx,
   intptr_t position);
@@ -106,6 +122,9 @@ mlirAffineSymbolExprGetPosition(MlirAffineExpr affineExpr);
 // Affine Constant Expression.
 
//===--===//
 
+/// Checks whether the given affine expression is a constant expression.
+MLIR_CAPI_EXPORTED bool mlirAffineExprIsAConstant(MlirAffineExpr affineExpr);
+
 /// Creates an affine constant expression with 'constant' in the context.
 MLIR_CAPI_EXPORTED MlirAffineExpr mlirAffineConstantExprGet(MlirContext ctx,
 int64_t constant);
@@ -173,6 +192,9 @@ MLIR_CAPI_EXPORTED MlirAffineExpr 
mlirAffineCeilDivExprGet(MlirAffineExpr lhs,
 // Affine Binary Operation Expression.
 
//===--===//
 
+/// Checks whether the given affine expression is binary.
+MLIR_CAPI_EXPORTED bool mlirAffineExprIsABinary(MlirAffineExpr affineExpr);
+
 /** Returns the left hand side affine expression of the given affine binary
  * operation expression. */
 MLIR_CAPI_EXPORTED MlirAffineExpr

diff  --git a/mlir/include/mlir-c/Bindings/Python/Interop.h 
b/mlir/include/mlir-c/Bindings/Python/Interop.h
index ae9d3a84a0a3..d1eda4202345 100644
--- a/mlir/include/mlir-c/Bindings/Python/Interop.h
+++ b/mlir/include/mlir-c/Bindings/Python/Interop.h
@@ -23,10 +23,12 @@
 
 #include 
 
+#include "mlir-c/AffineExpr.h"
 #include "mlir-c/AffineMap.h"
 #include "mlir-c/IR.h"
 #include "mlir-c/Pass.h"
 
+#define MLIR_PYTHON_CAPSULE_AFFINE_EXPR "mlir.ir.AffineExpr._CAPIPtr"
 #define MLIR_PYTHON_CAPSULE_AFFINE_MAP "mlir.ir.AffineMap._CAPIPtr"
 #define MLIR_PYTHON_CAPSULE_ATTRIBUTE "mlir.ir.Attribute._CAPIPtr"
 #define MLIR_PYTHON_CAPSULE_CONTEXT "mlir.ir.C

[llvm-branch-commits] [mlir] e79bd0b - [mlir] More Python bindings for AffineMap

[Alex Zinenko via llvm-branch-commits]

Author: Alex Zinenko
Date: 2021-01-11T19:57:15+01:00
New Revision: e79bd0b4f25e68130a2ac273d6508ea322028b61

URL: 
https://github.com/llvm/llvm-project/commit/e79bd0b4f25e68130a2ac273d6508ea322028b61
DIFF: 
https://github.com/llvm/llvm-project/commit/e79bd0b4f25e68130a2ac273d6508ea322028b61.diff

LOG: [mlir] More Python bindings for AffineMap

Now that the bindings for AffineExpr have been added, add more bindings for
constructing and inspecting AffineMap that consists of AffineExprs.

Depends On D94225

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94297

Added: 


Modified: 
mlir/include/mlir-c/AffineExpr.h
mlir/include/mlir-c/AffineMap.h
mlir/lib/Bindings/Python/IRModules.cpp
mlir/lib/CAPI/IR/AffineMap.cpp
mlir/test/Bindings/Python/ir_affine_map.py
mlir/test/CAPI/ir.c

Removed: 




diff  --git a/mlir/include/mlir-c/AffineExpr.h 
b/mlir/include/mlir-c/AffineExpr.h
index 2eb8ae03e03d..ec445682c011 100644
--- a/mlir/include/mlir-c/AffineExpr.h
+++ b/mlir/include/mlir-c/AffineExpr.h
@@ -10,7 +10,6 @@
 #ifndef MLIR_C_AFFINEEXPR_H
 #define MLIR_C_AFFINEEXPR_H
 
-#include "mlir-c/AffineMap.h"
 #include "mlir-c/IR.h"
 
 #ifdef __cplusplus

diff  --git a/mlir/include/mlir-c/AffineMap.h b/mlir/include/mlir-c/AffineMap.h
index c52fe6826251..bf0c7c7b5381 100644
--- a/mlir/include/mlir-c/AffineMap.h
+++ b/mlir/include/mlir-c/AffineMap.h
@@ -10,6 +10,7 @@
 #ifndef MLIR_C_AFFINEMAP_H
 #define MLIR_C_AFFINEMAP_H
 
+#include "mlir-c/AffineExpr.h"
 #include "mlir-c/IR.h"
 
 #ifdef __cplusplus
@@ -67,9 +68,18 @@ MLIR_CAPI_EXPORTED MlirAffineMap 
mlirAffineMapEmptyGet(MlirContext ctx);
 
 /** Creates a zero result affine map of the given dimensions and symbols in the
  * context. The affine map is owned by the context. */
+MLIR_CAPI_EXPORTED MlirAffineMap mlirAffineMapZeroResultGet(
+MlirContext ctx, intptr_t dimCount, intptr_t symbolCount);
+
+/** Creates an affine map with results defined by the given list of affine
+ * expressions. The map resulting map also has the requested number of input
+ * dimensions and symbols, regardless of them being used in the results.
+ */
 MLIR_CAPI_EXPORTED MlirAffineMap mlirAffineMapGet(MlirContext ctx,
   intptr_t dimCount,
-  intptr_t symbolCount);
+  intptr_t symbolCount,
+  intptr_t nAffineExprs,
+  MlirAffineExpr *affineExprs);
 
 /** Creates a single constant result affine map in the context. The affine map
  * is owned by the context. */
@@ -124,6 +134,10 @@ MLIR_CAPI_EXPORTED intptr_t 
mlirAffineMapGetNumSymbols(MlirAffineMap affineMap);
 /// Returns the number of results of the given affine map.
 MLIR_CAPI_EXPORTED intptr_t mlirAffineMapGetNumResults(MlirAffineMap 
affineMap);
 
+/// Returns the result at the given position.
+MLIR_CAPI_EXPORTED MlirAffineExpr
+mlirAffineMapGetResult(MlirAffineMap affineMap, intptr_t pos);
+
 /** Returns the number of inputs (dimensions + symbols) of the given affine
  * map. */
 MLIR_CAPI_EXPORTED intptr_t mlirAffineMapGetNumInputs(MlirAffineMap affineMap);

diff  --git a/mlir/lib/Bindings/Python/IRModules.cpp 
b/mlir/lib/Bindings/Python/IRModules.cpp
index 2d18a7a488e7..81f84b8152f4 100644
--- a/mlir/lib/Bindings/Python/IRModules.cpp
+++ b/mlir/lib/Bindings/Python/IRModules.cpp
@@ -11,6 +11,7 @@
 #include "Globals.h"
 #include "PybindUtils.h"
 
+#include "mlir-c/AffineMap.h"
 #include "mlir-c/Bindings/Python/Interop.h"
 #include "mlir-c/BuiltinAttributes.h"
 #include "mlir-c/BuiltinTypes.h"
@@ -2943,9 +2944,43 @@ PyAffineExpr PyAffineExpr::createFromCapsule(py::object 
capsule) {
 }
 
 
//--
-// PyAffineMap.
+// PyAffineMap and utilities.
 
//--
 
+namespace {
+/// A list of expressions contained in an affine map. Internally these are
+/// stored as a consecutive array leading to inexpensive random access. Both
+/// the map and the expression are owned by the context so we need not bother
+/// with lifetime extension.
+class PyAffineMapExprList
+: public Sliceable {
+public:
+  static constexpr const char *pyClassName = "AffineExprList";
+
+  PyAffineMapExprList(PyAffineMap map, intptr_t startIndex = 0,
+  intptr_t length = -1, intptr_t step = 1)
+  : Sliceable(startIndex,
+  length == -1 ? mlirAffineMapGetNumResults(map) : length,
+  step),
+affineMap(map) {}
+
+  intptr_t getNumElements() { return mlirAffineMapGetNumResults(affineMap); }
+
+  PyAffineExpr getElement(intptr_t pos) {
+return PyAffineExpr(affineMap.getContext(),
+

[llvm-branch-commits] [mlir] 547e3ee - [mlir] Expose MemRef layout in Python bindings

[Alex Zinenko via llvm-branch-commits]

Author: Alex Zinenko
Date: 2021-01-11T19:57:16+01:00
New Revision: 547e3eef14a8e75a867dfcc6b45cd1f0547d4e07

URL: 
https://github.com/llvm/llvm-project/commit/547e3eef14a8e75a867dfcc6b45cd1f0547d4e07
DIFF: 
https://github.com/llvm/llvm-project/commit/547e3eef14a8e75a867dfcc6b45cd1f0547d4e07.diff

LOG: [mlir] Expose MemRef layout in Python bindings

This wasn't possible before because there was no support for affine expressions
as maps. Now that this support is available, provide the mechanism for
constructing maps with a layout and inspecting it.

Rework the `get` method on MemRefType in Python to avoid needing an explicit
memory space or layout map. Remove the `get_num_maps`, it is too low-level,
using the length of the now-avaiable pseudo-list of layout maps is more
pythonic.

Depends On D94297

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94302

Added: 


Modified: 
mlir/include/mlir-c/BuiltinTypes.h
mlir/lib/Bindings/Python/IRModules.cpp
mlir/lib/CAPI/IR/BuiltinTypes.cpp
mlir/test/Bindings/Python/ir_types.py

Removed: 




diff  --git a/mlir/include/mlir-c/BuiltinTypes.h 
b/mlir/include/mlir-c/BuiltinTypes.h
index 77898be41565..9712d58ad87a 100644
--- a/mlir/include/mlir-c/BuiltinTypes.h
+++ b/mlir/include/mlir-c/BuiltinTypes.h
@@ -225,7 +225,13 @@ MLIR_CAPI_EXPORTED bool mlirTypeIsAUnrankedMemRef(MlirType 
type);
  * same context as element type. The type is owned by the context. */
 MLIR_CAPI_EXPORTED MlirType mlirMemRefTypeGet(
 MlirType elementType, intptr_t rank, const int64_t *shape, intptr_t 
numMaps,
-MlirAttribute const *affineMaps, unsigned memorySpace);
+MlirAffineMap const *affineMaps, unsigned memorySpace);
+
+/** Same as "mlirMemRefTypeGet" but returns a nullptr-wrapping MlirType o
+ * illegal arguments, emitting appropriate diagnostics. */
+MLIR_CAPI_EXPORTED MlirType mlirMemRefTypeGetChecked(
+MlirType elementType, intptr_t rank, const int64_t *shape, intptr_t 
numMaps,
+MlirAffineMap const *affineMaps, unsigned memorySpace, MlirLocation loc);
 
 /** Creates a MemRef type with the given rank, shape, memory space and element
  * type in the same context as the element type. The type has no affine maps,

diff  --git a/mlir/lib/Bindings/Python/IRModules.cpp 
b/mlir/lib/Bindings/Python/IRModules.cpp
index 81f84b8152f4..218099bedc6f 100644
--- a/mlir/lib/Bindings/Python/IRModules.cpp
+++ b/mlir/lib/Bindings/Python/IRModules.cpp
@@ -2535,6 +2535,8 @@ class PyUnrankedTensorType
   }
 };
 
+class PyMemRefLayoutMapList;
+
 /// Ranked MemRef Type subclass - MemRefType.
 class PyMemRefType : public PyConcreteType {
 public:
@@ -2542,16 +2544,22 @@ class PyMemRefType : public 
PyConcreteType {
   static constexpr const char *pyClassName = "MemRefType";
   using PyConcreteType::PyConcreteType;
 
+  PyMemRefLayoutMapList getLayout();
+
   static void bindDerived(ClassTy &c) {
-// TODO: Add mlirMemRefTypeGet and mlirMemRefTypeGetAffineMap binding
-// once the affine map binding is completed.
 c.def_static(
- "get_contiguous_memref",
- // TODO: Make the location optional and create a default location.
+ "get",
  [](PyType &elementType, std::vector shape,
-unsigned memorySpace, DefaultingPyLocation loc) {
-   MlirType t = mlirMemRefTypeContiguousGetChecked(
-   elementType, shape.size(), shape.data(), memorySpace, loc);
+std::vector layout, unsigned memorySpace,
+DefaultingPyLocation loc) {
+   SmallVector maps;
+   maps.reserve(layout.size());
+   for (PyAffineMap &map : layout)
+ maps.push_back(map);
+
+   MlirType t = mlirMemRefTypeGetChecked(elementType, shape.size(),
+ shape.data(), maps.size(),
+ maps.data(), memorySpace, 
loc);
// TODO: Rework error reporting once diagnostic engine is exposed
// in C API.
if (mlirTypeIsNull(t)) {
@@ -2565,15 +2573,11 @@ class PyMemRefType : public 
PyConcreteType {
}
return PyMemRefType(elementType.getContext(), t);
  },
- py::arg("element_type"), py::arg("shape"), py::arg("memory_space"),
+ py::arg("element_type"), py::arg("shape"),
+ py::arg("layout") = py::list(), py::arg("memory_space") = 0,
  py::arg("loc") = py::none(), "Create a memref type")
-.def_property_readonly(
-"num_affine_maps",
-[](PyMemRefType &self) -> intptr_t {
-  return mlirMemRefTypeGetNumAffineMaps(self);
-},
-"Returns the number of affine layout maps in the given MemRef "
-"type.")
+.def_property_readonly("layout", &PyMemRefType::getLayout,
+   "The list of layout maps of the MemRef type.")

[llvm-branch-commits] [flang] 47567ca - [flang][openxx][NFC] Remove duplicated function to check required clauses

[via llvm-branch-commits]

Author: Valentin Clement
Date: 2021-01-11T14:08:51-05:00
New Revision: 47567ca5faca147bcc28bcbbaa6bf448354bb5d4

URL: 
https://github.com/llvm/llvm-project/commit/47567ca5faca147bcc28bcbbaa6bf448354bb5d4
DIFF: 
https://github.com/llvm/llvm-project/commit/47567ca5faca147bcc28bcbbaa6bf448354bb5d4.diff

LOG: [flang][openxx][NFC] Remove duplicated function to check required clauses

Remove duplicated function to check for required clauses on a directive. This 
was
still there from the merging of OpenACC and OpenMP common semantic checks and 
it can now be
removed so we use only one function.

Reviewed By: sameeranjoshi

Differential Revision: https://reviews.llvm.org/D93575

Added: 


Modified: 
flang/lib/Semantics/check-directive-structure.h
flang/lib/Semantics/check-omp-structure.cpp
flang/test/Semantics/omp-device-constructs.f90

Removed: 




diff  --git a/flang/lib/Semantics/check-directive-structure.h 
b/flang/lib/Semantics/check-directive-structure.h
index 822cdca9b66a..062f85b63b85 100644
--- a/flang/lib/Semantics/check-directive-structure.h
+++ b/flang/lib/Semantics/check-directive-structure.h
@@ -232,8 +232,6 @@ class DirectiveStructureChecker : public virtual 
BaseChecker {
   // Check that only clauses in set are after the specific clauses.
   void CheckOnlyAllowedAfter(C clause, common::EnumSet set);
 
-  void CheckRequired(C clause);
-
   void CheckRequireAtLeastOneOf();
 
   void CheckAllowed(C clause);
@@ -326,6 +324,8 @@ DirectiveStructureChecker::ClauseSetToString(
 template 
 void DirectiveStructureChecker::CheckRequireAtLeastOneOf() {
+  if (GetContext().requiredClauses.empty())
+return;
   for (auto cl : GetContext().actualClauses) {
 if (GetContext().requiredClauses.test(cl))
   return;
@@ -447,17 +447,6 @@ void DirectiveStructureChecker::SayNotMatching(
   .Attach(beginSource, "Does not match directive"_en_US);
 }
 
-// Check that at least one of the required clauses is present on the directive.
-template 
-void DirectiveStructureChecker::CheckRequired(C c) {
-  if (!FindClause(c)) {
-context_.Say(GetContext().directiveSource,
-"At least one %s clause must appear on the %s directive"_err_en_US,
-parser::ToUpperCaseLetters(getClauseName(c).str()),
-ContextDirectiveAsFortran());
-  }
-}
-
 // Check the value of the clause is a positive parameter.
 template 
 void DirectiveStructureCheckerhttps://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] d8c6d24 - -funique-internal-linkage-names appends a hex md5hash suffix to the symbol name which is not demangler friendly, convert it to decimal.

[Sriraman Tallam via llvm-branch-commits]

Author: Sriraman Tallam
Date: 2021-01-11T11:10:29-08:00
New Revision: d8c6d24359f17c55a8966231ef74e8f4b03ad282

URL: 
https://github.com/llvm/llvm-project/commit/d8c6d24359f17c55a8966231ef74e8f4b03ad282
DIFF: 
https://github.com/llvm/llvm-project/commit/d8c6d24359f17c55a8966231ef74e8f4b03ad282.diff

LOG: -funique-internal-linkage-names appends a hex md5hash suffix to the symbol 
name which is not demangler friendly, convert it to decimal.

Please see D93747 for more context which tries to make linkage names of internal
linkage functions to be the uniqueified names. This causes a problem with gdb
because breaking using the demangled function name will not work if the new
uniqueified name cannot be demangled. The problem is the generated suffix which
is a mix of integers and letters which do not demangle. The demangler accepts
either all numbers or all letters. This patch simply converts the hash to 
decimal.

There is no loss of uniqueness by doing this as the precision is maintained.
The symbol names get longer by a few characters though.

Differential Revision: https://reviews.llvm.org/D94154

Added: 


Modified: 
clang/test/CodeGen/unique-internal-linkage-names.cpp
llvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp
llvm/test/Transforms/UniqueInternalLinkageNames/unique_symbol_names.ll

Removed: 




diff  --git a/clang/test/CodeGen/unique-internal-linkage-names.cpp 
b/clang/test/CodeGen/unique-internal-linkage-names.cpp
index 3ad3bdc9f1bb..b731ed07f4a7 100644
--- a/clang/test/CodeGen/unique-internal-linkage-names.cpp
+++ b/clang/test/CodeGen/unique-internal-linkage-names.cpp
@@ -53,15 +53,15 @@ int mver_call() {
 // PLAIN: define weak_odr i32 ()* @_ZL4mverv.resolver()
 // PLAIN: define internal i32 @_ZL4mverv()
 // PLAIN: define internal i32 @_ZL4mverv.sse4.2()
-// UNIQUE: @_ZL4glob.__uniq.{{[0-9a-f]+}} = internal global
-// UNIQUE: @_ZZ8retAnonMvE5fGlob.__uniq.{{[0-9a-f]+}} = internal global
-// UNIQUE: @_ZN12_GLOBAL__N_16anon_mE.__uniq.{{[0-9a-f]+}} = internal global
-// UNIQUE: define internal i32 @_ZL3foov.__uniq.{{[0-9a-f]+}}()
-// UNIQUE: define internal i32 @_ZN12_GLOBAL__N_14getMEv.__uniq.{{[0-9a-f]+}}
+// UNIQUE: @_ZL4glob.__uniq.{{[0-9]+}} = internal global
+// UNIQUE: @_ZZ8retAnonMvE5fGlob.__uniq.{{[0-9]+}} = internal global
+// UNIQUE: @_ZN12_GLOBAL__N_16anon_mE.__uniq.{{[0-9]+}} = internal global
+// UNIQUE: define internal i32 @_ZL3foov.__uniq.{{[0-9]+}}()
+// UNIQUE: define internal i32 @_ZN12_GLOBAL__N_14getMEv.__uniq.{{[0-9]+}}
 // UNIQUE: define weak_odr i32 ()* @_ZL4mverv.resolver()
-// UNIQUE: define internal i32 @_ZL4mverv.__uniq.{{[0-9a-f]+}}()
-// UNIQUE: define internal i32 @_ZL4mverv.sse4.2.__uniq.{{[0-9a-f]+}}
-// UNIQUEO1: define internal i32 @_ZL3foov.__uniq.{{[0-9a-f]+}}()
+// UNIQUE: define internal i32 @_ZL4mverv.__uniq.{{[0-9]+}}()
+// UNIQUE: define internal i32 @_ZL4mverv.sse4.2.__uniq.{{[0-9]+}}
+// UNIQUEO1: define internal i32 @_ZL3foov.__uniq.{{[0-9]+}}()
 // UNIQUEO1: define weak_odr i32 ()* @_ZL4mverv.resolver()
-// UNIQUEO1: define internal i32 @_ZL4mverv.__uniq.{{[0-9a-f]+}}()
-// UNIQUEO1: define internal i32 @_ZL4mverv.sse4.2.__uniq.{{[0-9a-f]+}}
+// UNIQUEO1: define internal i32 @_ZL4mverv.__uniq.{{[0-9]+}}()
+// UNIQUEO1: define internal i32 @_ZL4mverv.sse4.2.__uniq.{{[0-9]+}}

diff  --git a/llvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp 
b/llvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp
index 385bf8bb429a..29ad0b6fcae5 100644
--- a/llvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp
+++ b/llvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp
@@ -27,9 +27,12 @@ static bool uniqueifyInternalLinkageNames(Module &M) {
   Md5.final(R);
   SmallString<32> Str;
   llvm::MD5::stringifyResult(R, Str);
+  // Convert MD5hash to Decimal. Demangler suffixes can either contain numbers
+  // or characters but not both.
+  APInt IntHash = APInt(128, Str.str(), 16);
   // Prepend "__uniq" before the hash for tools like profilers to understand 
that
   // this symbol is of internal linkage type.
-  std::string ModuleNameHash = (Twine(".__uniq.") + Twine(Str)).str();
+  std::string ModuleNameHash = (Twine(".__uniq.") + Twine(IntHash.toString(10, 
false))).str();
   bool Changed = false;
 
   // Append the module hash to all internal linkage functions.

diff  --git 
a/llvm/test/Transforms/UniqueInternalLinkageNames/unique_symbol_names.ll 
b/llvm/test/Transforms/UniqueInternalLinkageNames/unique_symbol_names.ll
index bf15daebda38..492c716a0bb1 100644
--- a/llvm/test/Transforms/UniqueInternalLinkageNames/unique_symbol_names.ll
+++ b/llvm/test/Transforms/UniqueInternalLinkageNames/unique_symbol_names.ll
@@ -10,5 +10,5 @@ entry:
   ret i32 0
 }
 
-; CHECK: @glob.__uniq.6ae72bb15a7d1834b42ae042a58f7a4d = internal global
-; CHECK: define internal i32 @foo.__uniq.6ae72bb15a7d1834b42ae042a58f7a4d()
+; CHECK: @glob.__uniq.14209847432252523067699167782

[llvm-branch-commits] [llvm] 43a830e - Introduce new quiet mode and new option handling for -print-changed.

[Jamie Schmeiser via llvm-branch-commits]

Author: Jamie Schmeiser
Date: 2021-01-11T14:15:18-05:00
New Revision: 43a830ed94180f72533263bb1c40af29510c017a

URL: 
https://github.com/llvm/llvm-project/commit/43a830ed94180f72533263bb1c40af29510c017a
DIFF: 
https://github.com/llvm/llvm-project/commit/43a830ed94180f72533263bb1c40af29510c017a.diff

LOG: Introduce new quiet mode and new option handling for -print-changed.
Summary:
Introduce a new mode of operation for -print-changed that only reports
after a pass changes the IR with all of the other messages suppressed (ie,
no initial IR and no messages about ignored, filtered or non-modifying
passes).

The option processing for -print-changed is changed to take an optional
string indicating options for print-changed. Initially, the only option
supported is quiet (as described above). This new quiet mode is specified
with -print-changed=quiet while -print-changed will continue to function
in the same way. It is intended that there will be more options in the
future.

Author: Jamie Schmeiser 
Reviewed By: aeubanks (Arthur Eubanks)
Differential Revision: https://reviews.llvm.org/D92589

Added: 


Modified: 
llvm/include/llvm/Passes/StandardInstrumentations.h
llvm/lib/Passes/StandardInstrumentations.cpp
llvm/test/Other/change-printer.ll

Removed: 




diff  --git a/llvm/include/llvm/Passes/StandardInstrumentations.h 
b/llvm/include/llvm/Passes/StandardInstrumentations.h
index 42751beb0685..795a980878e2 100644
--- a/llvm/include/llvm/Passes/StandardInstrumentations.h
+++ b/llvm/include/llvm/Passes/StandardInstrumentations.h
@@ -152,7 +152,7 @@ class PreservedCFGCheckerInstrumentation {
 // 8.  To compare two IR representations (of type \p T).
 template  class ChangeReporter {
 protected:
-  ChangeReporter() {}
+  ChangeReporter(bool RunInVerboseMode) : VerboseMode(RunInVerboseMode) {}
 
 public:
   virtual ~ChangeReporter();
@@ -204,6 +204,9 @@ template  class ChangeReporter {
   std::vector BeforeStack;
   // Is this the first IR seen?
   bool InitialIR = true;
+
+  // Run in verbose mode, printing everything?
+  const bool VerboseMode;
 };
 
 // An abstract template base class that handles printing banners and
@@ -211,7 +214,7 @@ template  class ChangeReporter {
 template 
 class TextChangeReporter : public ChangeReporter {
 protected:
-  TextChangeReporter();
+  TextChangeReporter(bool Verbose);
 
   // Print a module dump of the first IR that is changed.
   void handleInitialIR(Any IR) override;
@@ -235,7 +238,8 @@ class TextChangeReporter : public ChangeReporter {
 // included in this representation but it is massaged before reporting.
 class IRChangedPrinter : public TextChangeReporter {
 public:
-  IRChangedPrinter() {}
+  IRChangedPrinter(bool VerboseMode)
+  : TextChangeReporter(VerboseMode) {}
   ~IRChangedPrinter() override;
   void registerCallbacks(PassInstrumentationCallbacks &PIC);
 
@@ -274,9 +278,7 @@ class StandardInstrumentations {
   bool VerifyEach;
 
 public:
-  StandardInstrumentations(bool DebugLogging, bool VerifyEach = false)
-  : PrintPass(DebugLogging), OptNone(DebugLogging), Verify(DebugLogging),
-VerifyEach(VerifyEach) {}
+  StandardInstrumentations(bool DebugLogging, bool VerifyEach = false);
 
   void registerCallbacks(PassInstrumentationCallbacks &PIC);
 

diff  --git a/llvm/lib/Passes/StandardInstrumentations.cpp 
b/llvm/lib/Passes/StandardInstrumentations.cpp
index d6351a01ef27..04ff0af2f804 100644
--- a/llvm/lib/Passes/StandardInstrumentations.cpp
+++ b/llvm/lib/Passes/StandardInstrumentations.cpp
@@ -64,10 +64,17 @@ static cl::opt
 // can be combined, allowing only changed IRs for certain passes on certain
 // functions to be reported in 
diff erent formats, with the rest being
 // reported as filtered out.  The -print-before-changed option will print
-// the IR as it was before each pass that changed it.
-static cl::opt PrintChanged("print-changed",
-  cl::desc("Print changed IRs"),
-  cl::init(false), cl::Hidden);
+// the IR as it was before each pass that changed it.  The optional
+// value of quiet will only report when the IR changes, suppressing
+// all other messages, including the initial IR.
+enum ChangePrinter { NoChangePrinter, PrintChangedVerbose, PrintChangedQuiet };
+static cl::opt PrintChanged(
+"print-changed", cl::desc("Print changed IRs"), cl::Hidden,
+cl::ValueOptional, cl::init(NoChangePrinter),
+cl::values(clEnumValN(PrintChangedQuiet, "quiet", "Run in quiet mode"),
+   // Sentinel value for unspecified option.
+   clEnumValN(PrintChangedVerbose, "", "")));
+
 // An option that supports the -print-changed option.  See
 // the description for -print-changed for an explanation of the use
 // of this option.  Note that this option has no effect without -print-changed.
@@ -287,7 +294,8 @@ void ChangeReporter::saveIRBeforePass(Any IR, 
StringRef

[llvm-branch-commits] [llvm] 5464baa - Fix minor build issue (NFC)

[Reid Kleckner via llvm-branch-commits]

Author: David Stuttard
Date: 2021-01-11T11:24:09-08:00
New Revision: 5464baaae8c19997c5b0b76930d2b5ee13f68dfa

URL: 
https://github.com/llvm/llvm-project/commit/5464baaae8c19997c5b0b76930d2b5ee13f68dfa
DIFF: 
https://github.com/llvm/llvm-project/commit/5464baaae8c19997c5b0b76930d2b5ee13f68dfa.diff

LOG: Fix minor build issue (NFC)

Change [x86] Fix tile register spill issue was causing problems for our build
using gcc-5.4.1

The problem was caused by this line:

for (const MachineInstr &MI : make_range(MIS.begin(), MI))

where MI was previously defined as a MachineBasicBlock iterator.

Differential Revision: https://reviews.llvm.org/D94415

Added: 


Modified: 
llvm/lib/CodeGen/InlineSpiller.cpp

Removed: 




diff  --git a/llvm/lib/CodeGen/InlineSpiller.cpp 
b/llvm/lib/CodeGen/InlineSpiller.cpp
index 81ab9e5ab738..236a70904690 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -1553,12 +1553,12 @@ void HoistSpillHelper::hoistAllSpills() {
 for (auto const &Insert : SpillsToIns) {
   MachineBasicBlock *BB = Insert.first;
   Register LiveReg = Insert.second;
-  MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, *BB);
-  MachineInstrSpan MIS(MI, BB);
-  TII.storeRegToStackSlot(*BB, MI, LiveReg, false, Slot,
+  MachineBasicBlock::iterator MII = IPA.getLastInsertPointIter(OrigLI, 
*BB);
+  MachineInstrSpan MIS(MII, BB);
+  TII.storeRegToStackSlot(*BB, MII, LiveReg, false, Slot,
   MRI.getRegClass(LiveReg), &TRI);
-  LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
-  for (const MachineInstr &MI : make_range(MIS.begin(), MI))
+  LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII);
+  for (const MachineInstr &MI : make_range(MIS.begin(), MII))
 getVDefInterval(MI, LIS);
   ++NumSpills;
 }



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[llvm-branch-commits] [llvm] 1027a22 - [SystemZ][z/OS] Fix Permission denied pattern matching

[Abhina Sreeskantharajan via llvm-branch-commits]

Author: Abhina Sreeskantharajan
Date: 2021-01-11T14:31:27-05:00
New Revision: 1027a22ccd72bb127253cf7d27f528712fa21fa0

URL: 
https://github.com/llvm/llvm-project/commit/1027a22ccd72bb127253cf7d27f528712fa21fa0
DIFF: 
https://github.com/llvm/llvm-project/commit/1027a22ccd72bb127253cf7d27f528712fa21fa0.diff

LOG: [SystemZ][z/OS] Fix Permission denied pattern matching

On z/OS, the error message "EDC5111I Permission denied." is not matched 
correctly in lit tests. This patch updates the check expression to match 
successfully.

Reviewed By: fanbo-meng

Differential Revision: https://reviews.llvm.org/D94432

Added: 


Modified: 
llvm/test/tools/llvm-elfabi/fail-file-write.test

Removed: 




diff  --git a/llvm/test/tools/llvm-elfabi/fail-file-write.test 
b/llvm/test/tools/llvm-elfabi/fail-file-write.test
index 3590409234fb..c3c479e73887 100644
--- a/llvm/test/tools/llvm-elfabi/fail-file-write.test
+++ b/llvm/test/tools/llvm-elfabi/fail-file-write.test
@@ -15,4 +15,4 @@ Arch: AArch64
 Symbols: {}
 ...
 
-# ERR: Permission denied when trying to open `{{.*}}.TestDir/Output.TestFile` 
for writing
+# ERR: {{.*}}Permission denied{{.*}} when trying to open 
`{{.*}}.TestDir/Output.TestFile` for writing



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[llvm-branch-commits] [mlir] 195728c - [mlir] Add structural conversion to async dialect lowering.

[Christian Sigg via llvm-branch-commits]

Author: Christian Sigg
Date: 2021-01-11T20:36:49+01:00
New Revision: 195728c75aa41d80254175c5d7ac2f881333b139

URL: 
https://github.com/llvm/llvm-project/commit/195728c75aa41d80254175c5d7ac2f881333b139
DIFF: 
https://github.com/llvm/llvm-project/commit/195728c75aa41d80254175c5d7ac2f881333b139.diff

LOG: [mlir] Add structural conversion to async dialect lowering.

Lowering of async dialect uses a fixed type converter and therefore does not 
support lowering non-standard types.

This revision adds a structural conversion so that non-standard types in 
`!async.value`s can be lowered to LLVM before lowering the async dialect itself.

Reviewed By: ezhulenev

Differential Revision: https://reviews.llvm.org/D94404

Added: 


Modified: 
mlir/include/mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h
mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp

Removed: 




diff  --git a/mlir/include/mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h 
b/mlir/include/mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h
index abb5d216028f..938c5cbbebce 100644
--- a/mlir/include/mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h
+++ b/mlir/include/mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h
@@ -13,13 +13,29 @@
 
 namespace mlir {
 
+class ConversionTarget;
 class ModuleOp;
 template 
 class OperationPass;
+class MLIRContext;
+class OwningRewritePatternList;
+class TypeConverter;
 
 /// Create a pass to convert Async operations to the LLVM dialect.
 std::unique_ptr> createConvertAsyncToLLVMPass();
 
+/// Populates patterns for async structural type conversions.
+///
+/// A "structural" type conversion is one where the underlying ops are
+/// completely agnostic to the actual types involved and simply need to update
+/// their types. An example of this is async.execute -- the async.execute op 
and
+/// the corresponding async.yield ops need to update their types accordingly to
+/// the TypeConverter, but otherwise don't care what type conversions are
+/// happening.
+void populateAsyncStructuralTypeConversionsAndLegality(
+MLIRContext *context, TypeConverter &typeConverter,
+OwningRewritePatternList &patterns, ConversionTarget &target);
+
 } // namespace mlir
 
 #endif // MLIR_CONVERSION_ASYNCTOLLVM_ASYNCTOLLVM_H

diff  --git a/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp 
b/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
index 488432722959..587f49754446 100644
--- a/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
+++ b/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
@@ -1132,6 +1132,71 @@ void ConvertAsyncToLLVMPass::runOnOperation() {
 }
 } // namespace
 
+namespace {
+class ConvertExecuteOpTypes : public OpConversionPattern {
+public:
+  using OpConversionPattern::OpConversionPattern;
+  LogicalResult
+  matchAndRewrite(ExecuteOp op, ArrayRef operands,
+  ConversionPatternRewriter &rewriter) const override {
+ExecuteOp newOp =
+cast(rewriter.cloneWithoutRegions(*op.getOperation()));
+rewriter.inlineRegionBefore(op.getRegion(), newOp.getRegion(),
+newOp.getRegion().end());
+
+// Set operands and update block argument and result types.
+newOp->setOperands(operands);
+if (failed(rewriter.convertRegionTypes(&newOp.getRegion(), 
*typeConverter)))
+  return failure();
+for (auto result : newOp.getResults())
+  result.setType(typeConverter->convertType(result.getType()));
+
+rewriter.replaceOp(op, newOp.getResults());
+return success();
+  }
+};
+
+// Dummy pattern to trigger the appropriate type conversion / materialization.
+class ConvertAwaitOpTypes : public OpConversionPattern {
+public:
+  using OpConversionPattern::OpConversionPattern;
+  LogicalResult
+  matchAndRewrite(AwaitOp op, ArrayRef operands,
+  ConversionPatternRewriter &rewriter) const override {
+rewriter.replaceOpWithNewOp(op, operands.front());
+return success();
+  }
+};
+
+// Dummy pattern to trigger the appropriate type conversion / materialization.
+class ConvertYieldOpTypes : public OpConversionPattern {
+public:
+  using OpConversionPattern::OpConversionPattern;
+  LogicalResult
+  matchAndRewrite(async::YieldOp op, ArrayRef operands,
+  ConversionPatternRewriter &rewriter) const override {
+rewriter.replaceOpWithNewOp(op, operands);
+return success();
+  }
+};
+} // namespace
+
 std::unique_ptr> mlir::createConvertAsyncToLLVMPass() {
   return std::make_unique();
 }
+
+void mlir::populateAsyncStructuralTypeConversionsAndLegality(
+MLIRContext *context, TypeConverter &typeConverter,
+OwningRewritePatternList &patterns, ConversionTarget &target) {
+  typeConverter.addConversion([&](TokenType type) { return type; });
+  typeConverter.addConversion([&](ValueType type) {
+return ValueType::get(typeConverter.convertType(type.getValueType()));
+  });
+
+  patterns
+  .insert(
+  typeConverter, context);
+
+  target.addDynamicallyLegal

[llvm-branch-commits] [libcxx] 30a7d43 - [libc++] Turn off auto-formatting of generated files. NFC.

[Marek Kurdej via llvm-branch-commits]

Author: Marek Kurdej
Date: 2021-01-11T20:49:26+01:00
New Revision: 30a7d430e869bb0d8c61efa04f56e4dd2377

URL: 
https://github.com/llvm/llvm-project/commit/30a7d430e869bb0d8c61efa04f56e4dd2377
DIFF: 
https://github.com/llvm/llvm-project/commit/30a7d430e869bb0d8c61efa04f56e4dd2377.diff

LOG: [libc++] Turn off auto-formatting of generated files. NFC.

This adds `// clang-format off` in the auto-generated file to avoid lint 
warnings.

Reviewed By: ldionne, #libc

Differential Revision: https://reviews.llvm.org/D94410

Added: 


Modified: 

libcxx/test/std/language.support/support.limits/support.limits.general/algorithm.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/any.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/array.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/atomic.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/barrier.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/bit.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/chrono.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/cmath.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/compare.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/complex.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/concepts.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/cstddef.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/deque.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/exception.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/execution.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/filesystem.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/forward_list.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/iomanip.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/istream.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/iterator.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/latch.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/limits.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/list.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/locale.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/map.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/memory.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/mutex.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/new.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/numbers.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/numeric.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/optional.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/ostream.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/regex.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/scoped_allocator.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/semaphore.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/set.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/shared_mutex.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/span.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/string.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/string_view.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/thread.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/tuple.version.pass.cpp

libcxx/test/std/language.support/support.limits/support.limits.general/type_traits.version.pass.cpp

[llvm-branch-commits] [llvm] 72f1f08 - [NFC][AMDGPU] Clarify memory model support for volatile

[Tony Tye via llvm-branch-commits]

Author: Tony Tye
Date: 2021-01-11T19:59:55Z
New Revision: 72f1f084670ed66362ecb7c4079ee372665ce842

URL: 
https://github.com/llvm/llvm-project/commit/72f1f084670ed66362ecb7c4079ee372665ce842
DIFF: 
https://github.com/llvm/llvm-project/commit/72f1f084670ed66362ecb7c4079ee372665ce842.diff

LOG: [NFC][AMDGPU] Clarify memory model support for volatile

Reorder the AMDGPUUage description of the memory model code sequences
for volatile so clear that it applies independent of the nontemporal
setting.

Differential Revision: https://reviews.llvm.org/D94358

Added: 


Modified: 
llvm/docs/AMDGPUUsage.rst

Removed: 




diff  --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 81734dd30cd2..f661684d9b74 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -4732,7 +4732,12 @@ in table 
:ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table`.
   - generic
   - private1. 
buffer/global/flat_load
   - constant
- - volatile & 
!nontemporal
+ - !volatile & 
nontemporal
+
+   1. 
buffer/global/flat_load
+  glc=1 slc=1
+
+ - volatile
 
1. 
buffer/global/flat_load
   glc=1
@@ -4750,17 +4755,17 @@ in table 
:ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table`.
   be reordered by
   hardware.
 
- - !volatile & 
nontemporal
-
-   1. 
buffer/global/flat_load
-  glc=1 slc=1
-
  load *none*   *none* - local1. ds_load
  store*none*   *none* - global   - !volatile & 
!nontemporal
   - generic
   - private1. 
buffer/global/flat_store
   - constant
- - volatile & 
!nontemporal
+ - !volatile & 
nontemporal
+
+   1. 
buffer/global/flat_store
+  glc=1 slc=1
+
+ - volatile
 
1. 
buffer/global/flat_store
2. s_waitcnt 
vmcnt(0)
@@ -4777,11 +4782,6 @@ in table 
:ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table`.
   be reordered by
   hardware.
 
- - !volatile & 
nontemporal
-
-   1. 
buffer/global/flat_store
-  glc=1 slc=1
-
  store*none*   *none* - local1. ds_store
  **Unordered Atomic**
  

@@ -6034,7 +6034,12 @@ table 
:ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx10-table`.
   - generic
   - private1. 
buffer/global/flat_load
   - constant
- - volatile & 
!nontemporal
+ - !volatile & 
nontemporal
+
+   1. 
buffer/global/flat_load
+  slc=1
+
+ - volatile
 
1. 
buffer/global/flat_load
   glc=1 dlc=1
@@ -6052,17 +6057,17 @@ table 
:ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx10-table`.
   be reordered by
   hardware.
 
-

[llvm-branch-commits] [mlir] 2074177 - [mlir][ODS] Add a C++ abstraction for OpBuilders

[River Riddle via llvm-branch-commits]

Author: River Riddle
Date: 2021-01-11T12:06:22-08:00
New Revision: 207417730134931c7d5bf82e0b16c7757ad05e05

URL: 
https://github.com/llvm/llvm-project/commit/207417730134931c7d5bf82e0b16c7757ad05e05
DIFF: 
https://github.com/llvm/llvm-project/commit/207417730134931c7d5bf82e0b16c7757ad05e05.diff

LOG: [mlir][ODS] Add a C++ abstraction for OpBuilders

This removes the need for OpDefinitionsGen to use raw tablegen API, and will 
also
simplify adding builders to TypeDefs as well.

Differential Revision: https://reviews.llvm.org/D94273

Added: 
mlir/include/mlir/TableGen/Builder.h
mlir/lib/TableGen/Builder.cpp

Modified: 
mlir/include/mlir/TableGen/Operator.h
mlir/lib/TableGen/CMakeLists.txt
mlir/lib/TableGen/Operator.cpp
mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp

Removed: 




diff  --git a/mlir/include/mlir/TableGen/Builder.h 
b/mlir/include/mlir/TableGen/Builder.h
new file mode 100644
index ..b901c8414e81
--- /dev/null
+++ b/mlir/include/mlir/TableGen/Builder.h
@@ -0,0 +1,85 @@
+//===- Builder.h - Builder classes --*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Builder wrapper to simplify using TableGen Record for building
+// operations/types/etc.
+//
+//===--===//
+
+#ifndef MLIR_TABLEGEN_BUILDER_H_
+#define MLIR_TABLEGEN_BUILDER_H_
+
+#include "mlir/Support/LLVM.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+
+namespace llvm {
+class Init;
+class Record;
+class SMLoc;
+} // end namespace llvm
+
+namespace mlir {
+namespace tblgen {
+
+/// Wrapper class with helper methods for accessing Builders defined in
+/// TableGen.
+class Builder {
+public:
+  /// This class represents a single parameter to a builder method.
+  class Parameter {
+  public:
+/// Return a string containing the C++ type of this parameter.
+StringRef getCppType() const;
+
+/// Return an optional string containing the name of this parameter. If
+/// None, no name was specified for this parameter by the user.
+Optional getName() const { return name; }
+
+/// Return an optional string containing the default value to use for this
+/// parameter.
+Optional getDefaultValue() const;
+
+  private:
+Parameter(Optional name, const llvm::Init *def)
+: name(name), def(def) {}
+
+/// The optional name of the parameter.
+Optional name;
+
+/// The tablegen definition of the parameter. This is either a StringInit,
+/// or a CArg DefInit.
+const llvm::Init *def;
+
+// Allow access to the constructor.
+friend Builder;
+  };
+
+  /// Construct a builder from the given Record instance.
+  Builder(const llvm::Record *record, ArrayRef loc);
+
+  /// Return a list of parameters used in this build method.
+  ArrayRef getParameters() const { return parameters; }
+
+  /// Return an optional string containing the body of the builder.
+  Optional getBody() const;
+
+protected:
+  /// The TableGen definition of this builder.
+  const llvm::Record *def;
+
+private:
+  /// A collection of parameters to the builder.
+  SmallVector parameters;
+};
+
+} // end namespace tblgen
+} // end namespace mlir
+
+#endif // MLIR_TABLEGEN_BUILDER_H_

diff  --git a/mlir/include/mlir/TableGen/Operator.h 
b/mlir/include/mlir/TableGen/Operator.h
index 16d154b3beb0..d21b4b213ee4 100644
--- a/mlir/include/mlir/TableGen/Operator.h
+++ b/mlir/include/mlir/TableGen/Operator.h
@@ -16,6 +16,7 @@
 #include "mlir/Support/LLVM.h"
 #include "mlir/TableGen/Argument.h"
 #include "mlir/TableGen/Attribute.h"
+#include "mlir/TableGen/Builder.h"
 #include "mlir/TableGen/Dialect.h"
 #include "mlir/TableGen/OpTrait.h"
 #include "mlir/TableGen/Region.h"
@@ -287,6 +288,9 @@ class Operator {
   // Returns the OperandOrAttribute corresponding to the index.
   OperandOrAttribute getArgToOperandOrAttribute(int index) const;
 
+  // Returns the builders of this operation.
+  ArrayRef getBuilders() const { return builders; }
+
 private:
   // Populates the vectors containing operands, attributes, results and traits.
   void populateOpStructure();
@@ -332,6 +336,9 @@ class Operator {
   // Map from argument to attribute or operand number.
   SmallVector attrOrOperandMapping;
 
+  // The builders of this operator.
+  SmallVector builders;
+
   // The number of native attributes stored in the leading positions of
   // `attributes`.
   int numNativeAttributes;

diff  --git a/mlir/lib/TableGen/Builder.cpp b/mlir/lib/TableGen/Builder.cpp
new file mode 100644
index ..8210e8fe1a12
--- /dev/null
++

[llvm-branch-commits] [mlir] 948be58 - [mlir][TypeDefGen] Add support for adding builders when generating a TypeDef

[River Riddle via llvm-branch-commits]

Author: River Riddle
Date: 2021-01-11T12:06:22-08:00
New Revision: 948be58258dd81d56b1057657193f7dcf6dfa9bd

URL: 
https://github.com/llvm/llvm-project/commit/948be58258dd81d56b1057657193f7dcf6dfa9bd
DIFF: 
https://github.com/llvm/llvm-project/commit/948be58258dd81d56b1057657193f7dcf6dfa9bd.diff

LOG: [mlir][TypeDefGen] Add support for adding builders when generating a 
TypeDef

This allows for specifying additional get/getChecked methods that should be 
generated on the type, and acts similarly to how OpBuilders work. TypeBuilders 
have two additional components though:
* InferredContextParam
  - Bit indicating that the context parameter of a get method is inferred from 
one of the builder parameters
* checkedBody
  - A code block representing the body of the equivalent getChecked method.

Differential Revision: https://reviews.llvm.org/D94274

Added: 


Modified: 
mlir/docs/OpDefinitions.md
mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td
mlir/include/mlir/IR/OpBase.td
mlir/include/mlir/TableGen/TypeDef.h
mlir/lib/TableGen/TypeDef.cpp
mlir/test/lib/Dialect/Test/TestTypeDefs.td
mlir/test/lib/Dialect/Test/TestTypes.cpp
mlir/test/mlir-tblgen/typedefs.td
mlir/tools/mlir-tblgen/TypeDefGen.cpp

Removed: 




diff  --git a/mlir/docs/OpDefinitions.md b/mlir/docs/OpDefinitions.md
index bfd3d43c60b9..dd522904dd73 100644
--- a/mlir/docs/OpDefinitions.md
+++ b/mlir/docs/OpDefinitions.md
@@ -1536,6 +1536,171 @@ responsible for parsing/printing the types in 
`Dialect::printType` and
 -   The `extraClassDeclaration` field is used to include extra code in the 
class
 declaration.
 
+### Type builder methods
+
+For each type, there are a few builders(`get`/`getChecked`) automatically
+generated based on the parameters of the type. For example, given the following
+type definition:
+
+```tablegen
+def MyType : ... {
+  let parameters = (ins "int":$intParam);
+}
+```
+
+The following builders are generated:
+
+```c++
+// Type builders are named `get`, and return a new instance of a type for a
+// given set of parameters.
+static MyType get(MLIRContext *context, int intParam);
+
+// If `genVerifyInvariantsDecl` is set to 1, the following method is also
+// generated.
+static MyType getChecked(Location loc, int intParam);
+```
+
+If these autogenerated methods are not desired, such as when they conflict with
+a custom builder method, a type can set `skipDefaultBuilders` to 1 to signal
+that they should not be generated.
+
+ Custom type builder methods
+
+The default build methods may cover a majority of the simple cases related to
+type construction, but when they cannot satisfy a type's needs, you can define
+additional convenience get methods in the `builders` field as follows:
+
+```tablegen
+def MyType : ... {
+  let parameters = (ins "int":$intParam);
+
+  let builders = [
+TypeBuilder<(ins "int":$intParam)>,
+TypeBuilder<(ins CArg<"int", "0">:$intParam)>,
+TypeBuilder<(ins CArg<"int", "0">:$intParam), [{
+  // Write the body of the `get` builder inline here.
+  return Base::get($_ctxt, intParam);
+}]>,
+TypeBuilderWithInferredContext<(ins "Type":$typeParam), [{
+  // This builder states that it can infer an MLIRContext instance from
+  // its arguments.
+  return Base::get(typeParam.getContext(), ...);
+}]>,
+  ];
+}
+```
+
+The `builders` field is a list of custom builders that are added to the type
+class. In this example, we provide a several 
diff erent convenience builders that
+are useful in 
diff erent scenarios. The `ins` prefix is common to many function
+declarations in ODS, which use a TableGen [`dag`](#tablegen-syntax). What
+follows is a comma-separated list of types (quoted string or CArg) and names
+prefixed with the `$` sign. The use of `CArg` allows for providing a default
+value to that argument. Let's take a look at each of these builders 
individually
+
+The first builder will generate the declaration of a builder method that looks
+like:
+
+```tablegen
+  let builders = [
+TypeBuilder<(ins "int":$intParam)>,
+  ];
+```
+
+```c++
+class MyType : /*...*/ {
+  /*...*/
+  static MyType get(::mlir::MLIRContext *context, int intParam);
+};
+```
+
+This builder is identical to the one that will be automatically generated for
+`MyType`. The `context` parameter is implicitly added by the generator, and is
+used when building the file Type instance (with `Base::get`). The distinction
+here is that we can provide the implementation of this `get` method. With this
+style of builder definition only the declaration is generated, the implementor
+of MyType will need to provide a definition of `MyType::get`.
+
+The second builder will generate the declaration of a builder method that looks
+like:
+
+```tablegen
+  let builders = [
+TypeBuilder<(ins CArg<"int", "0">:$intParam)>,
+  ];
+```
+
+```c++
+class MyType : /*...*/ {
+  /*...*/
+  

[llvm-branch-commits] [mlir] d79642b - [mlir][IR][NFC] Move the definitions of Complex/Function/Integer/Opaque/TupleType to ODS

[River Riddle via llvm-branch-commits]

Author: River Riddle
Date: 2021-01-11T12:06:22-08:00
New Revision: d79642b3db1d74524f41d37f78385950158787a4

URL: 
https://github.com/llvm/llvm-project/commit/d79642b3db1d74524f41d37f78385950158787a4
DIFF: 
https://github.com/llvm/llvm-project/commit/d79642b3db1d74524f41d37f78385950158787a4.diff

LOG: [mlir][IR][NFC] Move the definitions of 
Complex/Function/Integer/Opaque/TupleType to ODS

The type tablegen backend now has enough support to represent these types well 
enough, so we can now move them to be declaratively defined.

Differential Revision: https://reviews.llvm.org/D94275

Added: 


Modified: 
mlir/include/mlir/IR/BuiltinTypes.h
mlir/include/mlir/IR/BuiltinTypes.td
mlir/lib/IR/BuiltinTypes.cpp
mlir/lib/IR/MLIRContext.cpp
mlir/lib/IR/TypeDetail.h

Removed: 




diff  --git a/mlir/include/mlir/IR/BuiltinTypes.h 
b/mlir/include/mlir/IR/BuiltinTypes.h
index d9d1a6e4e68c..835f46dc2295 100644
--- a/mlir/include/mlir/IR/BuiltinTypes.h
+++ b/mlir/include/mlir/IR/BuiltinTypes.h
@@ -29,119 +29,15 @@ class TypeRange;
 namespace detail {
 
 struct BaseMemRefTypeStorage;
-struct ComplexTypeStorage;
-struct FunctionTypeStorage;
-struct IntegerTypeStorage;
 struct MemRefTypeStorage;
-struct OpaqueTypeStorage;
 struct RankedTensorTypeStorage;
 struct ShapedTypeStorage;
-struct TupleTypeStorage;
 struct UnrankedMemRefTypeStorage;
 struct UnrankedTensorTypeStorage;
 struct VectorTypeStorage;
 
 } // namespace detail
 
-//===--===//
-// ComplexType
-//===--===//
-
-/// The 'complex' type represents a complex number with a parameterized element
-/// type, which is composed of a real and imaginary value of that element type.
-///
-/// The element must be a floating point or integer scalar type.
-///
-class ComplexType
-: public Type::TypeBase {
-public:
-  using Base::Base;
-
-  /// Get or create a ComplexType with the provided element type.
-  static ComplexType get(Type elementType);
-
-  /// Get or create a ComplexType with the provided element type.  This emits
-  /// and error at the specified location and returns null if the element type
-  /// isn't supported.
-  static ComplexType getChecked(Location location, Type elementType);
-
-  /// Verify the construction of an integer type.
-  static LogicalResult verifyConstructionInvariants(Location loc,
-Type elementType);
-
-  Type getElementType();
-};
-
-//===--===//
-// IntegerType
-//===--===//
-
-/// Integer types can have arbitrary bitwidth up to a large fixed limit.
-class IntegerType
-: public Type::TypeBase {
-public:
-  using Base::Base;
-
-  /// Signedness semantics.
-  enum SignednessSemantics : uint32_t {
-Signless, /// No signedness semantics
-Signed,   /// Signed integer
-Unsigned, /// Unsigned integer
-  };
-
-  /// Get or create a new IntegerType of the given width within the context.
-  /// The created IntegerType is signless (i.e., no signedness semantics).
-  /// Assume the width is within the allowed range and assert on failures. Use
-  /// getChecked to handle failures gracefully.
-  static IntegerType get(MLIRContext *context, unsigned width);
-
-  /// Get or create a new IntegerType of the given width within the context.
-  /// The created IntegerType has signedness semantics as indicated via
-  /// `signedness`. Assume the width is within the allowed range and assert on
-  /// failures. Use getChecked to handle failures gracefully.
-  static IntegerType get(MLIRContext *context, unsigned width,
- SignednessSemantics signedness);
-
-  /// Get or create a new IntegerType of the given width within the context,
-  /// defined at the given, potentially unknown, location.  The created
-  /// IntegerType is signless (i.e., no signedness semantics). If the width is
-  /// outside the allowed range, emit errors and return a null type.
-  static IntegerType getChecked(Location location, unsigned width);
-
-  /// Get or create a new IntegerType of the given width within the context,
-  /// defined at the given, potentially unknown, location. The created
-  /// IntegerType has signedness semantics as indicated via `signedness`. If 
the
-  /// width is outside the allowed range, emit errors and return a null type.
-  static IntegerType getChecked(Location location, unsigned width,
-SignednessSemantics signedness);
-
-  /// Verify the construction of an integer type.
-  static LogicalResult
-  verifyConstructionInvariants(Location loc, unsigned width,
-   SignednessSemantics signedness);
-
-  /// Return the bitwidth of this i

[llvm-branch-commits] [llvm] d3ff24c - [ADT] Add makeIntrusiveRefCnt helper function

[Nathan James via llvm-branch-commits]

Author: Nathan James
Date: 2021-01-11T20:12:53Z
New Revision: d3ff24cbf87224b23a0c99c74ed50744711909b2

URL: 
https://github.com/llvm/llvm-project/commit/d3ff24cbf87224b23a0c99c74ed50744711909b2
DIFF: 
https://github.com/llvm/llvm-project/commit/d3ff24cbf87224b23a0c99c74ed50744711909b2.diff

LOG: [ADT] Add makeIntrusiveRefCnt helper function

Works like std::make_unique but for IntrusiveRefCntPtr objects.
See https://lists.llvm.org/pipermail/llvm-dev/2021-January/147729.html

Reviewed By: dblaikie, MaskRay

Differential Revision: https://reviews.llvm.org/D94440

Added: 


Modified: 
llvm/include/llvm/ADT/IntrusiveRefCntPtr.h
llvm/unittests/ADT/IntrusiveRefCntPtrTest.cpp

Removed: 




diff  --git a/llvm/include/llvm/ADT/IntrusiveRefCntPtr.h 
b/llvm/include/llvm/ADT/IntrusiveRefCntPtr.h
index dcd35253c5f2..ca4c40db48b9 100644
--- a/llvm/include/llvm/ADT/IntrusiveRefCntPtr.h
+++ b/llvm/include/llvm/ADT/IntrusiveRefCntPtr.h
@@ -297,6 +297,12 @@ template  struct simplify_type> {
   }
 };
 
+/// Factory function for creating intrusive ref counted pointers.
+template 
+IntrusiveRefCntPtr makeIntrusiveRefCnt(Args &&...A) {
+  return IntrusiveRefCntPtr(new T(std::forward(A)...));
+}
+
 } // end namespace llvm
 
 #endif // LLVM_ADT_INTRUSIVEREFCNTPTR_H

diff  --git a/llvm/unittests/ADT/IntrusiveRefCntPtrTest.cpp 
b/llvm/unittests/ADT/IntrusiveRefCntPtrTest.cpp
index f69239162e3a..5dbc1b53d3fe 100644
--- a/llvm/unittests/ADT/IntrusiveRefCntPtrTest.cpp
+++ b/llvm/unittests/ADT/IntrusiveRefCntPtrTest.cpp
@@ -53,6 +53,22 @@ TYPED_TEST(IntrusiveRefCntPtrTest, InteropsWithUniquePtr) {
   EXPECT_EQ(0, NumInstances);
 }
 
+TYPED_TEST(IntrusiveRefCntPtrTest, MakeIntrusiveRefCnt) {
+  EXPECT_EQ(0, NumInstances);
+  {
+auto S1 = makeIntrusiveRefCnt();
+auto S2 = makeIntrusiveRefCnt();
+EXPECT_EQ(2, NumInstances);
+static_assert(
+std::is_same>::value,
+"Non-const type mismatch");
+static_assert(
+std::is_same>::value,
+"Const type mismatch");
+  }
+  EXPECT_EQ(0, NumInstances);
+}
+
 struct InterceptRefCounted : public RefCountedBase {
   InterceptRefCounted(bool *Released, bool *Retained)
 : Released(Released), Retained(Retained) {}



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[llvm-branch-commits] [llvm] 8ad998a - [tools] Mark output of tools as text if it is really text

[Abhina Sreeskantharajan via llvm-branch-commits]

Author: Abhina Sreeskantharajan
Date: 2021-01-11T15:14:03-05:00
New Revision: 8ad998a6115a8cd59a18ebdd5ec65329e42050e7

URL: 
https://github.com/llvm/llvm-project/commit/8ad998a6115a8cd59a18ebdd5ec65329e42050e7
DIFF: 
https://github.com/llvm/llvm-project/commit/8ad998a6115a8cd59a18ebdd5ec65329e42050e7.diff

LOG: [tools] Mark output of tools as text if it is really text

This is a continuation of https://reviews.llvm.org/D67696. The following tools 
also need to set the OF_Text flag correctly.

  -   llvm-profdata
  -   llvm-link

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D94313

Added: 


Modified: 
llvm/test/tools/llvm-profdata/csprof-dump.test
llvm/test/tools/llvm-profdata/instr-remap.test
llvm/tools/llvm-link/llvm-link.cpp
llvm/tools/llvm-profdata/llvm-profdata.cpp

Removed: 




diff  --git a/llvm/test/tools/llvm-profdata/csprof-dump.test 
b/llvm/test/tools/llvm-profdata/csprof-dump.test
index 39643dc38f20..a03b9d8a003e 100644
--- a/llvm/test/tools/llvm-profdata/csprof-dump.test
+++ b/llvm/test/tools/llvm-profdata/csprof-dump.test
@@ -27,5 +27,5 @@ Roundtrip test:
 
 RUN: llvm-profdata merge -o %t.0.profdata %S/Inputs/CSIR_profile.proftext
 RUN: llvm-profdata merge -text -o %t.0.proftext %t.0.profdata
-RUN: 
diff  %t.0.proftext %S/Inputs/CSIR_profile.proftext
+RUN: 
diff  -b %t.0.proftext %S/Inputs/CSIR_profile.proftext
 

diff  --git a/llvm/test/tools/llvm-profdata/instr-remap.test 
b/llvm/test/tools/llvm-profdata/instr-remap.test
index 159b7374ac35..27fddf609581 100644
--- a/llvm/test/tools/llvm-profdata/instr-remap.test
+++ b/llvm/test/tools/llvm-profdata/instr-remap.test
@@ -1,2 +1,2 @@
 ; RUN: llvm-profdata merge -text %S/Inputs/instr-remap.proftext -r 
%S/Inputs/instr-remap.remap -o %t.output
-; RUN: 
diff  %S/Inputs/instr-remap.expected %t.output
+; RUN: 
diff  -b %S/Inputs/instr-remap.expected %t.output

diff  --git a/llvm/tools/llvm-link/llvm-link.cpp 
b/llvm/tools/llvm-link/llvm-link.cpp
index 61d0c1561054..158b168107f1 100644
--- a/llvm/tools/llvm-link/llvm-link.cpp
+++ b/llvm/tools/llvm-link/llvm-link.cpp
@@ -456,7 +456,8 @@ int main(int argc, char **argv) {
 errs() << "Here's the assembly:\n" << *Composite;
 
   std::error_code EC;
-  ToolOutputFile Out(OutputFilename, EC, sys::fs::OF_None);
+  ToolOutputFile Out(OutputFilename, EC,
+ OutputAssembly ? sys::fs::OF_Text : sys::fs::OF_None);
   if (EC) {
 WithColor::error() << EC.message() << '\n';
 return 1;

diff  --git a/llvm/tools/llvm-profdata/llvm-profdata.cpp 
b/llvm/tools/llvm-profdata/llvm-profdata.cpp
index 122ffe73bf0f..ad188b6a5e92 100644
--- a/llvm/tools/llvm-profdata/llvm-profdata.cpp
+++ b/llvm/tools/llvm-profdata/llvm-profdata.cpp
@@ -296,7 +296,9 @@ static void writeInstrProfile(StringRef OutputFilename,
   ProfileFormat OutputFormat,
   InstrProfWriter &Writer) {
   std::error_code EC;
-  raw_fd_ostream Output(OutputFilename.data(), EC, sys::fs::OF_None);
+  raw_fd_ostream Output(OutputFilename.data(), EC,
+OutputFormat == PF_Text ? sys::fs::OF_Text
+: sys::fs::OF_None);
   if (EC)
 exitWithErrorCode(EC, OutputFilename);
 



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[llvm-branch-commits] [llvm] 05e90ce - [NFC] Disallow unused prefixes under llvm/test/CodeGen

[Mircea Trofin via llvm-branch-commits]

Author: Mircea Trofin
Date: 2021-01-11T12:32:18-08:00
New Revision: 05e90cefeb4bc5613b2cadedc2b8e2ecb2ed20ed

URL: 
https://github.com/llvm/llvm-project/commit/05e90cefeb4bc5613b2cadedc2b8e2ecb2ed20ed
DIFF: 
https://github.com/llvm/llvm-project/commit/05e90cefeb4bc5613b2cadedc2b8e2ecb2ed20ed.diff

LOG: [NFC] Disallow unused prefixes under llvm/test/CodeGen

This patch finishes addressing unused prefixes under CodeGen: 2
remaining tests fixed, and then undo-ing the lit.local.cfg changes under
various subdirs and moving the policy under CodeGen.

Differential Revision: https://reviews.llvm.org/D94430

Added: 
llvm/test/CodeGen/lit.local.cfg

Modified: 
llvm/test/CodeGen/AMDGPU/lit.local.cfg
llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
llvm/test/CodeGen/NVPTX/f16-instructions.ll
llvm/test/CodeGen/PowerPC/lit.local.cfg
llvm/test/CodeGen/X86/lit.local.cfg

Removed: 




diff  --git a/llvm/test/CodeGen/AMDGPU/lit.local.cfg 
b/llvm/test/CodeGen/AMDGPU/lit.local.cfg
index 42f23b00ea9b..2a665f06be72 100644
--- a/llvm/test/CodeGen/AMDGPU/lit.local.cfg
+++ b/llvm/test/CodeGen/AMDGPU/lit.local.cfg
@@ -1,12 +1,2 @@
-from lit.llvm.subst import ToolSubst
-
 if not 'AMDGPU' in config.root.targets:
 config.unsupported = True
-
-fc = ToolSubst('FileCheck', unresolved='fatal')
-# Insert this first. Then, we'll first update the blank FileCheck command; 
then,
-# the default substitution of FileCheck will replace it to its full path.
-config.substitutions.insert(0, (fc.regex,
-'FileCheck --allow-unused-prefixes=false'))
-
-

diff  --git a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll 
b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
index e62012faed88..7fe5a9ba2eb0 100644
--- a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
+++ b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
@@ -1,9 +1,9 @@
-; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs 
-mtriple=armv8-linux-gnueabi < %s | FileCheck %s 
--check-prefixes=CHECK,ARM,HARDEN,ISBDSB,ISBDSBDAGISEL -dump-input-context=100
-; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs 
-mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s 
--check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,ISBDSB,ISBDSBDAGISEL 
-dump-input-context=100
-; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb 
-verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s 
--check-prefixes=CHECK,ARM,HARDEN,SB,SBDAGISEL -dump-input-context=100
-; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb 
-verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s 
--check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,SB,SBDAGISEL 
-dump-input-context=100
-; RUN: llc -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck 
%s --check-prefixes=CHECK,ARM,NOHARDEN,NOHARDENARM -dump-input-context=100
-; RUN: llc -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | 
FileCheck %s --check-prefixes=CHECK,THUMB,NOHARDEN,NOHARDENTHUMB
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs 
-mtriple=armv8-linux-gnueabi < %s | FileCheck %s 
--check-prefixes=CHECK,ARM,HARDEN,ISBDSB -dump-input-context=100
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs 
-mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s 
--check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,ISBDSB -dump-input-context=100
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb 
-verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s 
--check-prefixes=CHECK,ARM,HARDEN,SB -dump-input-context=100
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb 
-verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s 
--check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,SB -dump-input-context=100
+; RUN: llc -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck 
%s --check-prefixes=CHECK,ARM,NOHARDENARM -dump-input-context=100
+; RUN: llc -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | 
FileCheck %s --check-prefixes=CHECK,THUMB,NOHARDENTHUMB
 ; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr 
-mattr=harden-sls-blr -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | 
FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,ISBDSB
 ; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr 
-mattr=harden-sls-blr -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s 
| FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,ISBDSB
 ; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr 
-mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs 
-mtriple=armv8-linux-gnueabi < %s | FileCheck %s 
--check-prefixes=CHECK,ARM,HARDEN,SB

diff  --git a/llvm/test/CodeGen/NVPTX/f16-instructions.ll 
b/llvm/test/CodeGen/NVPTX/f16-instructions.ll
index 3856cb63350d..b06316b48

[llvm-branch-commits] [mlir] c1ae378 - [mlir][vector] Add side-effect information to different load/store ops

[Thomas Raoux via llvm-branch-commits]

Author: Thomas Raoux
Date: 2021-01-11T12:34:14-08:00
New Revision: c1ae378205db72cd80a52b85b8474077d1aa5b15

URL: 
https://github.com/llvm/llvm-project/commit/c1ae378205db72cd80a52b85b8474077d1aa5b15
DIFF: 
https://github.com/llvm/llvm-project/commit/c1ae378205db72cd80a52b85b8474077d1aa5b15.diff

LOG: [mlir][vector] Add side-effect information to different load/store ops

Differential Revision: https://reviews.llvm.org/D94434

Added: 


Modified: 
mlir/include/mlir/Dialect/Vector/VectorOps.td
mlir/test/Dialect/Vector/canonicalize.mlir

Removed: 




diff  --git a/mlir/include/mlir/Dialect/Vector/VectorOps.td 
b/mlir/include/mlir/Dialect/Vector/VectorOps.td
index 6bfa89939b04..8bc21b179037 100644
--- a/mlir/include/mlir/Dialect/Vector/VectorOps.td
+++ b/mlir/include/mlir/Dialect/Vector/VectorOps.td
@@ -1318,7 +1318,7 @@ def Vector_TransferWriteOp :
 
 def Vector_MaskedLoadOp :
   Vector_Op<"maskedload">,
-Arguments<(ins AnyMemRef:$base,
+Arguments<(ins Arg:$base,
Variadic:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$pass_thru)>,
@@ -1370,7 +1370,7 @@ def Vector_MaskedLoadOp :
 
 def Vector_MaskedStoreOp :
   Vector_Op<"maskedstore">,
-Arguments<(ins AnyMemRef:$base,
+Arguments<(ins Arg:$base,
Variadic:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$value)> {
@@ -1418,7 +1418,7 @@ def Vector_MaskedStoreOp :
 
 def Vector_GatherOp :
   Vector_Op<"gather">,
-Arguments<(ins AnyMemRef:$base,
+Arguments<(ins Arg:$base,
VectorOfRankAndType<[1], [AnyInteger]>:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$pass_thru)>,
@@ -1475,7 +1475,7 @@ def Vector_GatherOp :
 
 def Vector_ScatterOp :
   Vector_Op<"scatter">,
-Arguments<(ins AnyMemRef:$base,
+Arguments<(ins Arg:$base,
VectorOfRankAndType<[1], [AnyInteger]>:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$value)> {
@@ -1531,7 +1531,7 @@ def Vector_ScatterOp :
 
 def Vector_ExpandLoadOp :
   Vector_Op<"expandload">,
-Arguments<(ins AnyMemRef:$base,
+Arguments<(ins Arg:$base,
Variadic:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$pass_thru)>,
@@ -1586,7 +1586,7 @@ def Vector_ExpandLoadOp :
 
 def Vector_CompressStoreOp :
   Vector_Op<"compressstore">,
-Arguments<(ins AnyMemRef:$base,
+Arguments<(ins Arg:$base,
Variadic:$indices,
VectorOfRankAndType<[1], [I1]>:$mask,
VectorOfRank<[1]>:$value)> {

diff  --git a/mlir/test/Dialect/Vector/canonicalize.mlir 
b/mlir/test/Dialect/Vector/canonicalize.mlir
index cf4473f15f49..0ff85da85bcb 100644
--- a/mlir/test/Dialect/Vector/canonicalize.mlir
+++ b/mlir/test/Dialect/Vector/canonicalize.mlir
@@ -677,3 +677,22 @@ func @dead_transfer_op(%arg0 : tensor<4x4xf32>, %arg1 : 
memref<4x4xf32>,
 vector<1x4xf32>, tensor<4x4xf32>
   return
 }
+
+// -
+
+// CHECK-LABEL: func @dead_load
+//   CHECK-NOT:   vector.maskedload
+//   CHECK-NOT:   vector.gather
+//   CHECK-NOT:   vector.expandload
+//   CHECK:   return
+func @dead_load(%base: memref, %indices: vector<16xi32>,
+  %mask: vector<16xi1>, %passthru: vector<16xf32>) {
+  %c0 = constant 0 : index
+  %0 = vector.maskedload %base[%c0], %mask, %passthru :
+memref, vector<16xi1>, vector<16xf32> into vector<16xf32>
+  %1 = vector.gather %base[%indices], %mask, %passthru :
+memref, vector<16xi32>, vector<16xi1>, vector<16xf32> into 
vector<16xf32>
+  %2 = vector.expandload %base[%c0], %mask, %passthru :
+memref, vector<16xi1>, vector<16xf32> into vector<16xf32>
+  return
+}



___
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[llvm-branch-commits] [mlir] 53c866c - Enable python bindings for tensor, shape and linalg dialects.

[Stella Laurenzo via llvm-branch-commits]

Author: Stella Laurenzo
Date: 2021-01-11T12:35:49-08:00
New Revision: 53c866c286a7ca52bd09c7661d4c532ce5c0def8

URL: 
https://github.com/llvm/llvm-project/commit/53c866c286a7ca52bd09c7661d4c532ce5c0def8
DIFF: 
https://github.com/llvm/llvm-project/commit/53c866c286a7ca52bd09c7661d4c532ce5c0def8.diff

LOG: Enable python bindings for tensor, shape and linalg dialects.

* We've got significant missing features in order to use most of these 
effectively (i.e. custom builders, region-based builders).
* We presently also lack a mechanism for actually registering these dialects 
but they can be use with contexts that allow unregistered dialects for further 
prototyping.

Differential Revision: https://reviews.llvm.org/D94368

Added: 
mlir/lib/Bindings/Python/LinalgOps.td
mlir/lib/Bindings/Python/ShapeOps.td
mlir/lib/Bindings/Python/TensorOps.td

Modified: 
mlir/cmake/modules/AddMLIRPythonExtension.cmake
mlir/lib/Bindings/Python/CMakeLists.txt
mlir/test/Bindings/Python/CMakeLists.txt

Removed: 




diff  --git a/mlir/cmake/modules/AddMLIRPythonExtension.cmake 
b/mlir/cmake/modules/AddMLIRPythonExtension.cmake
index 290b4a23aa315..dbbe71e22b132 100644
--- a/mlir/cmake/modules/AddMLIRPythonExtension.cmake
+++ b/mlir/cmake/modules/AddMLIRPythonExtension.cmake
@@ -136,17 +136,27 @@ function(add_mlir_python_extension libname extname)
 
 endfunction()
 
-function(add_mlir_dialect_python_bindings tblgen_target filename dialectname)
-  set(LLVM_TARGET_DEFINITIONS ${filename})
-  mlir_tablegen("${dialectname}.py" -gen-python-op-bindings
--bind-dialect=${dialectname})
-  add_public_tablegen_target(${tblgen_target})
+function(add_mlir_dialect_python_bindings tblgen_target)
+  cmake_parse_arguments(ARG
+""
+"TD_FILE;DIALECT_NAME"
+"DEPENDS"
+${ARGN})
+
+  set(LLVM_TARGET_DEFINITIONS ${ARG_TD_FILE})
+  mlir_tablegen("${ARG_DIALECT_NAME}.py" -gen-python-op-bindings
+-bind-dialect=${ARG_DIALECT_NAME})
+  add_public_tablegen_target(
+${tblgen_target})
+  if(ARG_DEPENDS)
+add_dependencies(${tblgen_target} ${ARG_DEPENDS})
+  endif()
 
   add_custom_command(
 TARGET ${tblgen_target} POST_BUILD
-COMMENT "Copying generated python source \"dialects/${dialectname}.py\""
+COMMENT "Copying generated python source 
\"dialects/${ARG_DIALECT_NAME}.py\""
 COMMAND "${CMAKE_COMMAND}" -E copy_if_
diff erent
-  "${CMAKE_CURRENT_BINARY_DIR}/${dialectname}.py"
-  "${PROJECT_BINARY_DIR}/python/mlir/dialects/${dialectname}.py")
+  "${CMAKE_CURRENT_BINARY_DIR}/${ARG_DIALECT_NAME}.py"
+  "${PROJECT_BINARY_DIR}/python/mlir/dialects/${ARG_DIALECT_NAME}.py")
 endfunction()
 

diff  --git a/mlir/lib/Bindings/Python/CMakeLists.txt 
b/mlir/lib/Bindings/Python/CMakeLists.txt
index 0c34f5b55415c..8273489137448 100644
--- a/mlir/lib/Bindings/Python/CMakeLists.txt
+++ b/mlir/lib/Bindings/Python/CMakeLists.txt
@@ -35,11 +35,27 @@ endforeach()
 # Generate dialect-specific bindings.
 

 
+add_mlir_dialect_python_bindings(MLIRBindingsPythonLinalgOps
+  TD_FILE LinalgOps.td
+  DIALECT_NAME linalg
+  DEPENDS LinalgOdsGen)
+add_dependencies(MLIRBindingsPythonSources MLIRBindingsPythonLinalgOps)
+
+add_mlir_dialect_python_bindings(MLIRBindingsPythonShapeOps
+  TD_FILE ShapeOps.td
+  DIALECT_NAME shape)
+add_dependencies(MLIRBindingsPythonSources MLIRBindingsPythonShapeOps)
+
 add_mlir_dialect_python_bindings(MLIRBindingsPythonStandardOps
-  StandardOps.td
-  std)
+  TD_FILE StandardOps.td
+  DIALECT_NAME std)
 add_dependencies(MLIRBindingsPythonSources MLIRBindingsPythonStandardOps)
 
+add_mlir_dialect_python_bindings(MLIRBindingsPythonTensorOps
+  TD_FILE TensorOps.td
+  DIALECT_NAME tensor)
+add_dependencies(MLIRBindingsPythonSources MLIRBindingsPythonTensorOps)
+
 

 # Build core python extension
 


diff  --git a/mlir/lib/Bindings/Python/LinalgOps.td 
b/mlir/lib/Bindings/Python/LinalgOps.td
new file mode 100644
index 0..7650e954d59ee
--- /dev/null
+++ b/mlir/lib/Bindings/Python/LinalgOps.td
@@ -0,0 +1,16 @@
+//===-- LinalgOps.td - Entry point for linalg bind -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef PYTHON_BINDINGS_LINALG_OPS
+#define PYTHON_BINDINGS_LINALG_OPS
+
+include "mlir/Bindings/Python/Attributes.td"
+include "mlir/Dialect/Linalg/IR/LinalgOps.td"
+include "mlir/Dialect/Linalg/IR/LinalgStructuredOps.td"
+
+#endif

diff  --git a/ml

[llvm-branch-commits] [mlir] cceb1bf - [mlir][CAPI] Introduce standard source layout for mlir-c dialect registration.

[Stella Laurenzo via llvm-branch-commits]

Author: Stella Laurenzo
Date: 2021-01-11T12:35:49-08:00
New Revision: cceb1bfcbbc4ee2e9cc56b76a4acc4cd52968791

URL: 
https://github.com/llvm/llvm-project/commit/cceb1bfcbbc4ee2e9cc56b76a4acc4cd52968791
DIFF: 
https://github.com/llvm/llvm-project/commit/cceb1bfcbbc4ee2e9cc56b76a4acc4cd52968791.diff

LOG: [mlir][CAPI] Introduce standard source layout for mlir-c dialect 
registration.

* Registers a small set of sample dialects.
* NFC with respect to existing C-API symbols but some headers have been moved 
down a level to the Dialect/ sub-directory.
* Adds an additional entry point per dialect that is needed for dynamic 
discovery/loading.
* See discussion: https://llvm.discourse.group/t/dialects-and-the-c-api/2306/16

Differential Revision: https://reviews.llvm.org/D94370

Added: 
mlir/include/mlir-c/Dialect/Linalg.h
mlir/include/mlir-c/Dialect/SCF.h
mlir/include/mlir-c/Dialect/Shape.h
mlir/include/mlir-c/Dialect/Standard.h
mlir/include/mlir-c/Dialect/Tensor.h
mlir/include/mlir/CAPI/Registration.h
mlir/lib/CAPI/Dialect/CMakeLists.txt
mlir/lib/CAPI/Dialect/Linalg.cpp
mlir/lib/CAPI/Dialect/SCF.cpp
mlir/lib/CAPI/Dialect/Shape.cpp
mlir/lib/CAPI/Dialect/Standard.cpp
mlir/lib/CAPI/Dialect/Tensor.cpp

Modified: 
mlir/include/mlir-c/Registration.h
mlir/lib/CAPI/CMakeLists.txt
mlir/test/CAPI/ir.c

Removed: 
mlir/include/mlir-c/StandardDialect.h
mlir/lib/CAPI/Standard/CMakeLists.txt
mlir/lib/CAPI/Standard/StandardDialect.cpp



diff  --git a/mlir/include/mlir-c/Dialect/Linalg.h 
b/mlir/include/mlir-c/Dialect/Linalg.h
new file mode 100644
index 0..56258ac19af45
--- /dev/null
+++ b/mlir/include/mlir-c/Dialect/Linalg.h
@@ -0,0 +1,25 @@
+//===-- mlir-c/Dialect/Linalg.h - C API for Linalg dialect *- C 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
+// Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef MLIR_C_DIALECT_LINALG_H
+#define MLIR_C_DIALECT_LINALG_H
+
+#include "mlir-c/Registration.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MLIR_DECLARE_CAPI_DIALECT_REGISTRATION(Linalg, linalg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MLIR_C_DIALECT_LINALG_H

diff  --git a/mlir/include/mlir-c/Dialect/SCF.h 
b/mlir/include/mlir-c/Dialect/SCF.h
new file mode 100644
index 0..c1b25677969bf
--- /dev/null
+++ b/mlir/include/mlir-c/Dialect/SCF.h
@@ -0,0 +1,25 @@
+//===-- mlir-c/Dialect/SCF.h - C API for SCF dialect --*- C 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
+// Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef MLIR_C_DIALECT_SCF_H
+#define MLIR_C_DIALECT_SCF_H
+
+#include "mlir-c/Registration.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MLIR_DECLARE_CAPI_DIALECT_REGISTRATION(SCF, scf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MLIR_C_DIALECT_SCF_H

diff  --git a/mlir/include/mlir-c/Dialect/Shape.h 
b/mlir/include/mlir-c/Dialect/Shape.h
new file mode 100644
index 0..f64da801610b2
--- /dev/null
+++ b/mlir/include/mlir-c/Dialect/Shape.h
@@ -0,0 +1,25 @@
+//===-- mlir-c/Dialect/Shape.h - C API for Shape dialect --*- C 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
+// Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef MLIR_C_DIALECT_SHAPE_H
+#define MLIR_C_DIALECT_SHAPE_H
+
+#include "mlir-c/Registration.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MLIR_DECLARE_CAPI_DIALECT_REGISTRATION(Shape, shape);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MLIR_C_DIALECT_SHAPE_H

diff  --git a/mlir/include/mlir-c/StandardDialect.h 
b/mlir/include/mlir-c/Dialect/Standard.h
similarity index 52%
rename from mlir/include/mlir-c/StandardDialect.h
rename to mlir/include/mlir-c/Dialect/Standard.h
index 191872103104e..200962177cb95 100644
--- a/mlir/include/mlir-c/StandardDialect.h
+++ b/mlir/include/mlir-c/Dialect/Standard.h
@@ -1,4 +1,4 @@
-//===-- mlir-c/StandardDialect.h - C API for Standard dialect -*- C 
-*-===//
+//===-- mlir-c/Dialect/Standard.h - C API for Standard dialect *- C 
-*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM
 // Exceptions.
@@ -15,29 +15,19 @@
 //
 
//===--===//
 
-#ifndef MLIR_C_STANDARDDIALECT_H
-#define MLIR_C_STANDARDDIALECT_H
+#i

[llvm-branch-commits] [mlir] 1107758 - Revert "[mlir][linalg] Support parsing attributes in named op spec"

[Mehdi Amini via llvm-branch-commits]

Author: Mehdi Amini
Date: 2021-01-11T20:43:42Z
New Revision: 110775809ad114e190132290657a86b2c292a878

URL: 
https://github.com/llvm/llvm-project/commit/110775809ad114e190132290657a86b2c292a878
DIFF: 
https://github.com/llvm/llvm-project/commit/110775809ad114e190132290657a86b2c292a878.diff

LOG: Revert "[mlir][linalg] Support parsing attributes in named op spec"

This reverts commit df86f15f0c53c395dac5a14aba08745bc12b9b9b.

The gcc-5 build was broken by this change:

  mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp:1275:77:   required 
from here
  /usr/include/c++/5/ext/new_allocator.h:120:4: error: no matching function for 
call to 'std::pair, 
{anonymous}::TCParser::RegisteredAttr>::pair(llvm::StringRef&, 
{anonymous}::TCParser::RegisteredAttr'

Added: 


Modified: 
mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp

Removed: 




diff  --git a/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc 
b/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
index 1ef128760637..f81380f02bb3 100644
--- a/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
+++ b/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
@@ -72,25 +72,3 @@ ods_def :
 def test3(A: f32(Batch, M, K), B: f32(K, N)) -> (C: f32(Batch, M, N)) {
   C(b, m, n) = std_addf(std_mulf(A(b, m, k), B(k, n)));
 }
-
-// Test attribute definitions
-// ODS-LABEL: def Test4Op
-// ODS: F32ArrayAttr:$array_attr,
-// ODS: F32:$f32_attr,
-// ODS: RankedF32ElementsAttr<[4]>:$fvec_attr,
-// ODS: I32:$i32_attr,
-// ODS: RankedI32ElementsAttr<[5, 6]>:$ivec_attr,
-// ODS: OptionalAttr:$optional_attr
-//
-ods_def :
-def test4(A: f32(Batch, M, K), B: f32(K, N)) -> (C: f32(Batch, M, N))
-attr(
-  f32_attr: f32,
-  i32_attr: i32,
-  fvec_attr: 4xf32,
-  ivec_attr: 5x6xi32,
-  array_attr : f32[],
-  optional_attr? : f32
-) {
-  C(b, m, n) = std_addf(std_mulf(A(b, m, k), B(k, n)));
-}

diff  --git a/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp 
b/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
index e7ab5edc1118..592e6cb774fb 100644
--- a/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
+++ b/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
@@ -20,17 +20,11 @@
 #include "mlir/Support/LLVM.h"
 #include "mlir/Support/LogicalResult.h"
 #include "llvm/ADT/SetVector.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/StringSwitch.h"
-#include "llvm/ADT/Twine.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormatVariadic.h"
 #include "llvm/Support/ToolOutputFile.h"
 
-#include 
-
 #define DEBUG_TYPE "linalg-ods-gen"
 
 static llvm::cl::OptionCategory ODSGenCat("Linalg ODS Gen");
@@ -85,14 +79,11 @@ class Token {
 gt,
 l_brace,
 l_paren,
-l_square,
 lt,
 minus,
 plus,
-question,
 r_brace,
 r_paren,
-r_square,
 semicolon,
 star,
 
@@ -100,7 +91,6 @@ class Token {
 kw_def,
 FIRST_KEYWORD = kw_def,
 kw_ods_def,
-kw_attr_def,
 kw_floordiv,
 kw_ceildiv,
 kw_mod,
@@ -161,10 +151,6 @@ class Lexer {
   Token emitError(llvm::SMLoc loc, const Twine &msg);
   Token emitError(const char *loc, const Twine &msg);
 
-  /// Change the position of the lexer cursor. The next token we lex will start
-  /// at the designated point in the input.
-  void resetPointer(const char *newPtr) { curPtr = newPtr; }
-
 private:
   Token formToken(Token::Kind kind, const char *tokStart) {
 return Token(kind, StringRef(tokStart, curPtr - tokStart));
@@ -261,14 +247,10 @@ Token Lexer::lexToken() {
   return formToken(Token::Kind::l_brace, tokStart);
 case '(':
   return formToken(Token::Kind::l_paren, tokStart);
-case '[':
-  return formToken(Token::Kind::l_square, tokStart);
 case '}':
   return formToken(Token::Kind::r_brace, tokStart);
 case ')':
   return formToken(Token::Kind::r_paren, tokStart);
-case ']':
-  return formToken(Token::Kind::r_square, tokStart);
 case '<':
   return formToken(Token::Kind::lt, tokStart);
 case '>':
@@ -281,8 +263,6 @@ Token Lexer::lexToken() {
   return formToken(Token::Kind::semicolon, tokStart);
 case '*':
   return formToken(Token::Kind::star, tokStart);
-case '?':
-  return formToken(Token::Kind::question, tokStart);
 case '/':
   if (*curPtr == '/') {
 skipComment();
@@ -309,7 +289,6 @@ Token Lexer::lexIdentifier(const char *tokStart) {
   // Check to see if this identifier is a keyword.
   StringRef str(tokStart, curPtr - tokStart);
   Token::Kind kind = StringSwitch(str)
- .Case("attr", Token::Kind::kw_attr_def)
  .Case("def", Token::Kind::kw_def)
  .Case("ods_def", Token::Kind::kw_ods_def)
  .Case("floordiv", Token::Kind::

[llvm-branch-commits] [llvm] 288f3fc - [InstCombine] reduce icmp(ashr X, C1), C2 to sign-bit test

[Sanjay Patel via llvm-branch-commits]

Author: Sanjay Patel
Date: 2021-01-11T15:53:39-05:00
New Revision: 288f3fc5dfee0c51fc00fe10a985f93c505073eb

URL: 
https://github.com/llvm/llvm-project/commit/288f3fc5dfee0c51fc00fe10a985f93c505073eb
DIFF: 
https://github.com/llvm/llvm-project/commit/288f3fc5dfee0c51fc00fe10a985f93c505073eb.diff

LOG: [InstCombine] reduce icmp(ashr X, C1), C2 to sign-bit test

This is a more basic pattern that we should handle before trying to solve:
https://llvm.org/PR48640

There might be a better way to think about this because the pre-condition
that I came up with (number of sign bits in the compare constant) misses a
potential transform for each of ugt and ult as commented on in the test file.

Tried to model this is in Alive:
https://rise4fun.com/Alive/juX1
...but I couldn't get the ComputeNumSignBits() pre-condition to work as
expected, so replaced with leading 0/1 preconditions instead.

  Name: ugt
  Pre: countLeadingZeros(C2) <= C1 && countLeadingOnes(C2) <= C1
  %a = ashr %x, C1
  %r = icmp ugt i8 %a, C2
=>
  %r = icmp slt i8 %x, 0

  Name: ult
  Pre: countLeadingZeros(C2) <= C1 && countLeadingOnes(C2) <= C1
  %a = ashr %x, C1
  %r = icmp ult i4 %a, C2
=>
  %r = icmp sgt i4 %x, -1

Also approximated in Alive2:
https://alive2.llvm.org/ce/z/u5hCcz
https://alive2.llvm.org/ce/z/__szVL

Differential Revision: https://reviews.llvm.org/D94014

Added: 


Modified: 
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/test/Transforms/InstCombine/icmp-shr.ll

Removed: 




diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp 
b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 852def699716..9b3cfb3bd754 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -2210,6 +2210,21 @@ Instruction 
*InstCombinerImpl::foldICmpShrConstant(ICmpInst &Cmp,
   (ShiftedC + 1).ashr(ShAmtVal) == (C + 1))
 return new ICmpInst(Pred, X, ConstantInt::get(ShrTy, ShiftedC));
 }
+
+// If the compare constant has significant bits above the lowest sign-bit,
+// then convert an unsigned cmp to a test of the sign-bit:
+// (ashr X, ShiftC) u> C --> X s< 0
+// (ashr X, ShiftC) u< C --> X s> -1
+if (C.getBitWidth() > 2 && C.getNumSignBits() <= ShAmtVal) {
+  if (Pred == CmpInst::ICMP_UGT) {
+return new ICmpInst(CmpInst::ICMP_SLT, X,
+ConstantInt::getNullValue(ShrTy));
+  }
+  if (Pred == CmpInst::ICMP_ULT) {
+return new ICmpInst(CmpInst::ICMP_SGT, X,
+ConstantInt::getAllOnesValue(ShrTy));
+  }
+}
   } else {
 if (Pred == CmpInst::ICMP_ULT || (Pred == CmpInst::ICMP_UGT && IsExact)) {
   // icmp ult (lshr X, ShAmtC), C --> icmp ult X, (C << ShAmtC)

diff  --git a/llvm/test/Transforms/InstCombine/icmp-shr.ll 
b/llvm/test/Transforms/InstCombine/icmp-shr.ll
index 22f61d2d5e6a..ad3eb713aa19 100644
--- a/llvm/test/Transforms/InstCombine/icmp-shr.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-shr.ll
@@ -507,6 +507,10 @@ define <2 x i1> @exact_eq0_multiuse(<2 x i32> %x, <2 x 
i32> %y) {
   ret <2 x i1> %cmp
 }
 
+; Verify conversions of ashr+icmp to a sign-bit test.
+
+; negative test, but 
diff erent transform possible
+
 define i1 @ashr_ugt_0(i4 %x) {
 ; CHECK-LABEL: @ashr_ugt_0(
 ; CHECK-NEXT:[[R:%.*]] = icmp ugt i4 [[X:%.*]], 1
@@ -517,6 +521,8 @@ define i1 @ashr_ugt_0(i4 %x) {
   ret i1 %r
 }
 
+; negative test
+
 define i1 @ashr_ugt_1(i4 %x) {
 ; CHECK-LABEL: @ashr_ugt_1(
 ; CHECK-NEXT:[[S:%.*]] = ashr i4 [[X:%.*]], 1
@@ -528,6 +534,8 @@ define i1 @ashr_ugt_1(i4 %x) {
   ret i1 %r
 }
 
+; negative test
+
 define i1 @ashr_ugt_2(i4 %x) {
 ; CHECK-LABEL: @ashr_ugt_2(
 ; CHECK-NEXT:[[S:%.*]] = ashr i4 [[X:%.*]], 1
@@ -539,6 +547,9 @@ define i1 @ashr_ugt_2(i4 %x) {
   ret i1 %r
 }
 
+; negative test
+; TODO: This is a sign-bit test, but we don't recognize the pattern.
+
 define i1 @ashr_ugt_3(i4 %x) {
 ; CHECK-LABEL: @ashr_ugt_3(
 ; CHECK-NEXT:[[S:%.*]] = ashr i4 [[X:%.*]], 1
@@ -552,8 +563,7 @@ define i1 @ashr_ugt_3(i4 %x) {
 
 define i1 @ashr_ugt_4(i4 %x) {
 ; CHECK-LABEL: @ashr_ugt_4(
-; CHECK-NEXT:[[S:%.*]] = ashr i4 [[X:%.*]], 1
-; CHECK-NEXT:[[R:%.*]] = icmp ugt i4 [[S]], 4
+; CHECK-NEXT:[[R:%.*]] = icmp slt i4 [[X:%.*]], 0
 ; CHECK-NEXT:ret i1 [[R]]
 ;
   %s = ashr i4 %x, 1
@@ -563,8 +573,7 @@ define i1 @ashr_ugt_4(i4 %x) {
 
 define i1 @ashr_ugt_5(i4 %x) {
 ; CHECK-LABEL: @ashr_ugt_5(
-; CHECK-NEXT:[[S:%.*]] = ashr i4 [[X:%.*]], 1
-; CHECK-NEXT:[[R:%.*]] = icmp ugt i4 [[S]], 5
+; CHECK-NEXT:[[R:%.*]] = icmp slt i4 [[X:%.*]], 0
 ; CHECK-NEXT:ret i1 [[R]]
 ;
   %s = ashr i4 %x, 1
@@ -574,8 +583,7 @@ define i1 @ashr_ugt_5(i4 %x) {
 
 define i1 @ashr_ugt_6(i4 %x) {
 ; CHECK-LABEL: @ashr_ugt_6(
-; CHECK-NEXT:[[S:%.*]] = ashr i4 [[X:%.*]], 1
-; CHECK-NEX

[llvm-branch-commits] [llvm] 32c073a - [GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT

[Bjorn Pettersson via llvm-branch-commits]

Author: Bjorn Pettersson
Date: 2021-01-11T21:53:56+01:00
New Revision: 32c073acb320db3b22ca76b1e21dd688a70b50e8

URL: 
https://github.com/llvm/llvm-project/commit/32c073acb320db3b22ca76b1e21dd688a70b50e8
DIFF: 
https://github.com/llvm/llvm-project/commit/32c073acb320db3b22ca76b1e21dd688a70b50e8.diff

LOG: [GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT

Before this patch there was generic mapping from vector_extract
to G_EXTRACT_VECTOR_ELT added in SelectionDAGCompat.td. That
mapping is now replaced by a mapping from extractelt instead.

The reasoning is that vector_extract is marked as deprecated,
so it is assumed that a majority of targets will use extractelt
and not vector_extract (and that the long term solution for all
targets would be to use extractelt).

Targets like AArch64 that still use vector_extract can add an
additional mapping from the deprecated vector_extract as target
specific tablegen definitions. Such a mapping is added for AArch64
in this patch to avoid breaking tests.

When adding the extractelt => G_EXTRACT_VECTOR_ELT mapping we
triggered some new code paths in GlobalISelEmitter, ending up in
an assert when trying to import a pattern containing EXTRACT_SUBREG
for ARM. Therefore this patch also adds a "failedImport" warning
for that situation (instead of hitting the assert).

Differential Revision: https://reviews.llvm.org/D93416

Added: 


Modified: 
llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
llvm/lib/Target/AArch64/AArch64InstrGISel.td
llvm/utils/TableGen/GlobalISelEmitter.cpp

Removed: 




diff  --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td 
b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index ff4cf3a5d98d..6fb8a6b15dd7 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -116,7 +116,7 @@ def : GINodeEquiv;
 def : GINodeEquiv;
 def : GINodeEquiv;
 def : GINodeEquiv;
-def : GINodeEquiv;
+def : GINodeEquiv;
 def : GINodeEquiv;
 def : GINodeEquiv;
 def : GINodeEquiv;

diff  --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td 
b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index 430155c52302..eadb6847ceb6 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -164,6 +164,8 @@ def : GINodeEquiv;
 def : GINodeEquiv;
 def : GINodeEquiv;
 
+def : GINodeEquiv;
+
 // These are patterns that we only use for GlobalISel via the importer.
 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
  (vector_extract (v2f32 FPR64:$Rn), (i64 1,

diff  --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp 
b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 28c7d8b9634a..c10f85abccc4 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -4690,6 +4690,8 @@ Expected 
GlobalISelEmitter::importExplicitUseRenderers(
 
   // EXTRACT_SUBREG needs to use a subregister COPY.
   if (Name == "EXTRACT_SUBREG") {
+if (!Dst->getChild(1)->isLeaf())
+  return failedImport("EXTRACT_SUBREG child #1 is not a leaf");
 DefInit *SubRegInit = dyn_cast(Dst->getChild(1)->getLeafValue());
 if (!SubRegInit)
   return failedImport("EXTRACT_SUBREG child #1 is not a subreg index");



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[llvm-branch-commits] [libc] aefeb5f - [libc][NFC] Make __support/common.h an in tree header.

[Siva Chandra Reddy via llvm-branch-commits]

Author: Siva Chandra Reddy
Date: 2021-01-11T13:10:56-08:00
New Revision: aefeb5f136e7b72b251ce2881cb39a1fe8f0d76a

URL: 
https://github.com/llvm/llvm-project/commit/aefeb5f136e7b72b251ce2881cb39a1fe8f0d76a
DIFF: 
https://github.com/llvm/llvm-project/commit/aefeb5f136e7b72b251ce2881cb39a1fe8f0d76a.diff

LOG: [libc][NFC] Make __support/common.h an in tree header.

It was previously a generated header. It can easily converted to a
generated header if required in future.

Reviewed By: michaelrj

Differential Revision: https://reviews.llvm.org/D94445

Added: 
libc/src/__support/common.h

Modified: 
libc/src/__support/CMakeLists.txt

Removed: 
libc/src/__support/common.h.def



diff  --git a/libc/src/__support/CMakeLists.txt 
b/libc/src/__support/CMakeLists.txt
index e9f9579b6d0f..980b510e374c 100644
--- a/libc/src/__support/CMakeLists.txt
+++ b/libc/src/__support/CMakeLists.txt
@@ -1,9 +1,5 @@
-add_gen_header(
+add_header_library(
   common
-  DEF_FILE common.h.def
-  PARAMS
-platform_defs=../../config/${LIBC_TARGET_OS}/platform_defs.h.inc
-  GEN_HDR common.h
-  DATA_FILES
-../../config/${LIBC_TARGET_OS}/platform_defs.h.inc
+  HDRS
+common.h
 )

diff  --git a/libc/src/__support/common.h.def b/libc/src/__support/common.h
similarity index 54%
rename from libc/src/__support/common.h.def
rename to libc/src/__support/common.h
index d2d18c696dff..208c8bdfea41 100644
--- a/libc/src/__support/common.h.def
+++ b/libc/src/__support/common.h
@@ -11,22 +11,22 @@
 
 #define LIBC_INLINE_ASM __asm__ __volatile__
 
-#define likely(x) __builtin_expect (!!(x), 1)
-#define unlikely(x) __builtin_expect (x, 0)
+#define likely(x) __builtin_expect(!!(x), 1)
+#define unlikely(x) __builtin_expect(x, 0)
 #define UNUSED __attribute__((unused))
 
 #ifndef LLVM_LIBC_FUNCTION_ATTR
-  #define LLVM_LIBC_FUNCTION_ATTR
+#define LLVM_LIBC_FUNCTION_ATTR
 #endif
 
 #ifdef LLVM_LIBC_PUBLIC_PACKAGING
-#define LLVM_LIBC_FUNCTION(type, name, arglist) \
-  LLVM_LIBC_FUNCTION_ATTR decltype(__llvm_libc::name) __##name##_impl__ 
__asm__(#name); \
-  decltype(__llvm_libc::name) name [[gnu::alias(#name)]]; \
-  type __##name##_impl__ arglist
+#define LLVM_LIBC_FUNCTION(type, name, arglist)
\
+  LLVM_LIBC_FUNCTION_ATTR decltype(__llvm_libc::name)  
\
+  __##name##_impl__ __asm__(#name);
\
+  decltype(__llvm_libc::name) name [[gnu::alias(#name)]];  
\
+  type __##name##_impl__ arglist
 #else
-#define LLVM_LIBC_FUNCTION(type, name, arglist)\
-  type name arglist
+#define LLVM_LIBC_FUNCTION(type, name, arglist) type name arglist
 #endif
 
 #endif // LLVM_LIBC_SUPPORT_COMMON_H



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[llvm-branch-commits] [clang] 9b222b1 - [c++20] Don't consider string literal operator templates for numeric

[Richard Smith via llvm-branch-commits]

Author: Richard Smith
Date: 2021-01-11T13:19:00-08:00
New Revision: 9b222b108a2e37eb45d3156ec8554d148d658a8a

URL: 
https://github.com/llvm/llvm-project/commit/9b222b108a2e37eb45d3156ec8554d148d658a8a
DIFF: 
https://github.com/llvm/llvm-project/commit/9b222b108a2e37eb45d3156ec8554d148d658a8a.diff

LOG: [c++20] Don't consider string literal operator templates for numeric
literals.

A literal interpretation of the standard wording allows this, but it was
never intended that string literal operator templates would be used for
anything other than user-defined string literals.

Added: 


Modified: 
clang/lib/Sema/SemaLookup.cpp
clang/test/SemaCXX/cxx2a-user-defined-literals.cpp

Removed: 




diff  --git a/clang/lib/Sema/SemaLookup.cpp b/clang/lib/Sema/SemaLookup.cpp
index 16dd8f5105961..29038ab9fe1ca 100644
--- a/clang/lib/Sema/SemaLookup.cpp
+++ b/clang/lib/Sema/SemaLookup.cpp
@@ -3384,6 +3384,13 @@ Sema::LookupLiteralOperator(Scope *S, LookupResult &R,
   TemplateParameterList *Params = FD->getTemplateParameters();
   if (Params->size() == 1) {
 IsTemplate = true;
+if (!Params->getParam(0)->isTemplateParameterPack() && !StringLit) {
+  // Implied but not stated: user-defined integer and floating literals
+  // only ever use numeric literal operator templates, not templates
+  // taking a parameter of class type.
+  F.erase();
+  continue;
+}
 
 // A string literal template is only considered if the string literal
 // is a well-formed template argument for the template parameter.

diff  --git a/clang/test/SemaCXX/cxx2a-user-defined-literals.cpp 
b/clang/test/SemaCXX/cxx2a-user-defined-literals.cpp
index d730eba741a88..12f672ff640a9 100644
--- a/clang/test/SemaCXX/cxx2a-user-defined-literals.cpp
+++ b/clang/test/SemaCXX/cxx2a-user-defined-literals.cpp
@@ -24,4 +24,33 @@ chrono::day bin_d = 0b011d;
 // expected-note@9{{candidate constructor (the implicit move constructor)}}
 chrono::day hex_d = 0x44d;
 chrono::year y  = 10y;
+
+namespace ignore_class_udl_for_numeric_literals {
+  struct A { constexpr A(const char*) {} };
+  struct B { constexpr B(char); };
+  struct C { constexpr C(int); };
+  template void operator""_a();
+  template void operator""_b();
+  template void operator""_c();
+  void test_class_udl_1() {
+1_a; // expected-error {{no matching}}
+1_b; // expected-error {{no matching}}
+1_c; // expected-error {{no matching}}
+"1"_a;
+"1"_b; // expected-error {{no matching}}
+"1"_c; // expected-error {{no matching}}
+  }
+  template void operator""_a();
+  template void operator""_b();
+  template void operator""_c();
+  void test_class_udl_2() {
+1_a;
+// FIXME: The standard appears to say these two are ambiguous!
+1_b;
+1_c;
+"1"_a;
+"1"_b; // expected-error {{no matching}}
+"1"_c; // expected-error {{no matching}}
+  }
+}
 #endif



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[llvm-branch-commits] [clang] f4cec70 - Add an assert to CGDebugInfo::getTypeOrNull

[Fangrui Song via llvm-branch-commits]

Author: Fangrui Song
Date: 2021-01-11T13:25:20-08:00
New Revision: f4cec703ec8452f9d8b04fae171ba459adf38123

URL: 
https://github.com/llvm/llvm-project/commit/f4cec703ec8452f9d8b04fae171ba459adf38123
DIFF: 
https://github.com/llvm/llvm-project/commit/f4cec703ec8452f9d8b04fae171ba459adf38123.diff

LOG: Add an assert to CGDebugInfo::getTypeOrNull

Added: 


Modified: 
clang/lib/CodeGen/CGDebugInfo.cpp

Removed: 




diff  --git a/clang/lib/CodeGen/CGDebugInfo.cpp 
b/clang/lib/CodeGen/CGDebugInfo.cpp
index 7dc6457d08d0..2beb80b2ab6c 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -3132,6 +3132,7 @@ static QualType UnwrapTypeForDebugInfo(QualType T, const 
ASTContext &C) {
 }
 
 llvm::DIType *CGDebugInfo::getTypeOrNull(QualType Ty) {
+  assert(Ty == UnwrapTypeForDebugInfo(Ty, CGM.getContext()));
   auto It = TypeCache.find(Ty.getAsOpaquePtr());
   if (It != TypeCache.end()) {
 // Verify that the debug info still exists.



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[llvm-branch-commits] [mlir] 046612d - [mlir][vector] verify memref of vector memory ops

[Aart Bik via llvm-branch-commits]

Author: Aart Bik
Date: 2021-01-11T13:32:39-08:00
New Revision: 046612d29d7894783e8fcecbc62ebd6b4a78499f

URL: 
https://github.com/llvm/llvm-project/commit/046612d29d7894783e8fcecbc62ebd6b4a78499f
DIFF: 
https://github.com/llvm/llvm-project/commit/046612d29d7894783e8fcecbc62ebd6b4a78499f.diff

LOG: [mlir][vector] verify memref of vector memory ops

This ensures the memref base + indices expression is well-formed

Reviewed By: ThomasRaoux, ftynse

Differential Revision: https://reviews.llvm.org/D94441

Added: 


Modified: 
mlir/lib/Dialect/Vector/VectorOps.cpp
mlir/test/Dialect/Vector/invalid.mlir

Removed: 




diff  --git a/mlir/lib/Dialect/Vector/VectorOps.cpp 
b/mlir/lib/Dialect/Vector/VectorOps.cpp
index 731ddae85ead..54e5e008e56f 100644
--- a/mlir/lib/Dialect/Vector/VectorOps.cpp
+++ b/mlir/lib/Dialect/Vector/VectorOps.cpp
@@ -2365,10 +2365,12 @@ static LogicalResult verify(MaskedLoadOp op) {
   VectorType maskVType = op.getMaskVectorType();
   VectorType passVType = op.getPassThruVectorType();
   VectorType resVType = op.getResultVectorType();
+  MemRefType memType = op.getMemRefType();
 
-  if (resVType.getElementType() != op.getMemRefType().getElementType())
+  if (resVType.getElementType() != memType.getElementType())
 return op.emitOpError("base and result element type should match");
-
+  if (llvm::size(op.indices()) != memType.getRank())
+return op.emitOpError("requires ") << memType.getRank() << " indices";
   if (resVType.getDimSize(0) != maskVType.getDimSize(0))
 return op.emitOpError("expected result dim to match mask dim");
   if (resVType != passVType)
@@ -2410,10 +2412,12 @@ void MaskedLoadOp::getCanonicalizationPatterns(
 static LogicalResult verify(MaskedStoreOp op) {
   VectorType maskVType = op.getMaskVectorType();
   VectorType valueVType = op.getValueVectorType();
+  MemRefType memType = op.getMemRefType();
 
-  if (valueVType.getElementType() != op.getMemRefType().getElementType())
+  if (valueVType.getElementType() != memType.getElementType())
 return op.emitOpError("base and value element type should match");
-
+  if (llvm::size(op.indices()) != memType.getRank())
+return op.emitOpError("requires ") << memType.getRank() << " indices";
   if (valueVType.getDimSize(0) != maskVType.getDimSize(0))
 return op.emitOpError("expected value dim to match mask dim");
   return success();
@@ -2454,10 +2458,10 @@ static LogicalResult verify(GatherOp op) {
   VectorType indicesVType = op.getIndicesVectorType();
   VectorType maskVType = op.getMaskVectorType();
   VectorType resVType = op.getResultVectorType();
+  MemRefType memType = op.getMemRefType();
 
-  if (resVType.getElementType() != op.getMemRefType().getElementType())
+  if (resVType.getElementType() != memType.getElementType())
 return op.emitOpError("base and result element type should match");
-
   if (resVType.getDimSize(0) != indicesVType.getDimSize(0))
 return op.emitOpError("expected result dim to match indices dim");
   if (resVType.getDimSize(0) != maskVType.getDimSize(0))
@@ -2500,10 +2504,10 @@ static LogicalResult verify(ScatterOp op) {
   VectorType indicesVType = op.getIndicesVectorType();
   VectorType maskVType = op.getMaskVectorType();
   VectorType valueVType = op.getValueVectorType();
+  MemRefType memType = op.getMemRefType();
 
-  if (valueVType.getElementType() != op.getMemRefType().getElementType())
+  if (valueVType.getElementType() != memType.getElementType())
 return op.emitOpError("base and value element type should match");
-
   if (valueVType.getDimSize(0) != indicesVType.getDimSize(0))
 return op.emitOpError("expected value dim to match indices dim");
   if (valueVType.getDimSize(0) != maskVType.getDimSize(0))
@@ -2544,10 +2548,12 @@ static LogicalResult verify(ExpandLoadOp op) {
   VectorType maskVType = op.getMaskVectorType();
   VectorType passVType = op.getPassThruVectorType();
   VectorType resVType = op.getResultVectorType();
+  MemRefType memType = op.getMemRefType();
 
-  if (resVType.getElementType() != op.getMemRefType().getElementType())
+  if (resVType.getElementType() != memType.getElementType())
 return op.emitOpError("base and result element type should match");
-
+  if (llvm::size(op.indices()) != memType.getRank())
+return op.emitOpError("requires ") << memType.getRank() << " indices";
   if (resVType.getDimSize(0) != maskVType.getDimSize(0))
 return op.emitOpError("expected result dim to match mask dim");
   if (resVType != passVType)
@@ -2589,10 +2595,12 @@ void ExpandLoadOp::getCanonicalizationPatterns(
 static LogicalResult verify(CompressStoreOp op) {
   VectorType maskVType = op.getMaskVectorType();
   VectorType valueVType = op.getValueVectorType();
+  MemRefType memType = op.getMemRefType();
 
-  if (valueVType.getElementType() != op.getMemRefType().getElementType())
+  if (valueVType.getElementType() != memType.getElementType())

[llvm-branch-commits] [llvm] a808d89 - [PredicateInfo] Add test for one unknown condition in and/or (NFC)

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-11T22:33:34+01:00
New Revision: a808d89d355c98d7475795e13271beb90e9436cb

URL: 
https://github.com/llvm/llvm-project/commit/a808d89d355c98d7475795e13271beb90e9436cb
DIFF: 
https://github.com/llvm/llvm-project/commit/a808d89d355c98d7475795e13271beb90e9436cb.diff

LOG: [PredicateInfo] Add test for one unknown condition in and/or (NFC)

Test the case where one part of and/or is an icmp, while the other
one is an arbitrary value.

Added: 


Modified: 
llvm/test/Transforms/Util/PredicateInfo/testandor.ll

Removed: 




diff  --git a/llvm/test/Transforms/Util/PredicateInfo/testandor.ll 
b/llvm/test/Transforms/Util/PredicateInfo/testandor.ll
index cd1491e31a8d..4697c9d3e059 100644
--- a/llvm/test/Transforms/Util/PredicateInfo/testandor.ll
+++ b/llvm/test/Transforms/Util/PredicateInfo/testandor.ll
@@ -209,3 +209,77 @@ nope:
   call void @foo(i1 %z)
   ret void
 }
+
+define void @test_and_one_unknown_cond(i32 %x, i1 %c1) {
+; CHECK-LABEL: @test_and_one_unknown_cond(
+; CHECK-NEXT:[[C2:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT:[[A:%.*]] = and i1 [[C1:%.*]], [[C2]]
+; CHECK-NEXT:br i1 [[A]], label [[BOTH:%.*]], label [[NOPE:%.*]]
+; CHECK:   both:
+; CHECK-NEXT:call void @bar(i32 [[X]])
+; CHECK-NEXT:call void @foo(i1 [[C1]])
+; CHECK-NEXT:call void @foo(i1 [[C2]])
+; CHECK-NEXT:call void @foo(i1 [[A]])
+; CHECK-NEXT:ret void
+; CHECK:   nope:
+; CHECK-NEXT:call void @bar(i32 [[X]])
+; CHECK-NEXT:call void @foo(i1 [[C1]])
+; CHECK-NEXT:call void @foo(i1 [[C2]])
+; CHECK-NEXT:call void @foo(i1 [[A]])
+; CHECK-NEXT:ret void
+;
+  %c2 = icmp eq i32 %x, 0
+  %a = and i1 %c1, %c2
+  br i1 %a, label %both, label %nope
+
+both:
+  call void @bar(i32 %x)
+  call void @foo(i1 %c1)
+  call void @foo(i1 %c2)
+  call void @foo(i1 %a)
+  ret void
+
+nope:
+  call void @bar(i32 %x)
+  call void @foo(i1 %c1)
+  call void @foo(i1 %c2)
+  call void @foo(i1 %a)
+  ret void
+}
+
+define void @test_or_one_unknown_cond(i32 %x, i1 %c1) {
+; CHECK-LABEL: @test_or_one_unknown_cond(
+; CHECK-NEXT:[[C2:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT:[[A:%.*]] = or i1 [[C1:%.*]], [[C2]]
+; CHECK-NEXT:br i1 [[A]], label [[NOPE:%.*]], label [[BOTH_INVERTED:%.*]]
+; CHECK:   both_inverted:
+; CHECK-NEXT:call void @bar(i32 [[X]])
+; CHECK-NEXT:call void @foo(i1 [[C1]])
+; CHECK-NEXT:call void @foo(i1 [[C2]])
+; CHECK-NEXT:call void @foo(i1 [[A]])
+; CHECK-NEXT:ret void
+; CHECK:   nope:
+; CHECK-NEXT:call void @bar(i32 [[X]])
+; CHECK-NEXT:call void @foo(i1 [[C1]])
+; CHECK-NEXT:call void @foo(i1 [[C2]])
+; CHECK-NEXT:call void @foo(i1 [[A]])
+; CHECK-NEXT:ret void
+;
+  %c2 = icmp eq i32 %x, 0
+  %a = or i1 %c1, %c2
+  br i1 %a, label %nope, label %both_inverted
+
+both_inverted:
+  call void @bar(i32 %x)
+  call void @foo(i1 %c1)
+  call void @foo(i1 %c2)
+  call void @foo(i1 %a)
+  ret void
+
+nope:
+  call void @bar(i32 %x)
+  call void @foo(i1 %c1)
+  call void @foo(i1 %c2)
+  call void @foo(i1 %a)
+  ret void
+}



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[llvm-branch-commits] [llvm] 00f773c - [SCCP] Fix misclassified conditions in test (NFC)

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2021-01-11T22:33:34+01:00
New Revision: 00f773cf424699d8eb31591fdc95e0ca18b2682c

URL: 
https://github.com/llvm/llvm-project/commit/00f773cf424699d8eb31591fdc95e0ca18b2682c
DIFF: 
https://github.com/llvm/llvm-project/commit/00f773cf424699d8eb31591fdc95e0ca18b2682c.diff

LOG: [SCCP] Fix misclassified conditions in test (NFC)

Added: 


Modified: 
llvm/test/Transforms/SCCP/conditions-ranges.ll

Removed: 




diff  --git a/llvm/test/Transforms/SCCP/conditions-ranges.ll 
b/llvm/test/Transforms/SCCP/conditions-ranges.ll
index dada59099d81..65c3440a207c 100644
--- a/llvm/test/Transforms/SCCP/conditions-ranges.ll
+++ b/llvm/test/Transforms/SCCP/conditions-ranges.ll
@@ -984,12 +984,8 @@ define void @f18_conditions_chained_and(i32 %a, i32 %b) {
 ; CHECK-NEXT:call void @use(i1 [[F_2]])
 ; CHECK-NEXT:[[F_3:%.*]] = icmp ugt i32 [[A]], 100
 ; CHECK-NEXT:call void @use(i1 [[F_3]])
-; CHECK-NEXT:[[F_4:%.*]] = icmp eq i32 [[B]], 0
-; CHECK-NEXT:call void @use(i1 [[F_3]])
-; CHECK-NEXT:[[F_5:%.*]] = icmp eq i32 [[B]], 20
-; CHECK-NEXT:call void @use(i1 [[F_5]])
-; CHECK-NEXT:[[F_6:%.*]] = icmp ugt i32 [[B]], 100
-; CHECK-NEXT:call void @use(i1 [[F_6]])
+; CHECK-NEXT:[[F_4:%.*]] = icmp ugt i32 [[B]], 100
+; CHECK-NEXT:call void @use(i1 [[F_4]])
 ; CHECK-NEXT:[[T_1:%.*]] = icmp ult i32 [[A]], 100
 ; CHECK-NEXT:call void @use(i1 [[T_1]])
 ; CHECK-NEXT:[[T_2:%.*]] = icmp ne i32 [[A]], 20
@@ -1000,16 +996,20 @@ define void @f18_conditions_chained_and(i32 %a, i32 %b) {
 ; CHECK-NEXT:call void @use(i1 [[C_2]])
 ; CHECK-NEXT:[[C_3:%.*]] = icmp ugt i32 [[A]], 50
 ; CHECK-NEXT:call void @use(i1 [[C_3]])
+; CHECK-NEXT:[[C_4:%.*]] = icmp eq i32 [[B]], 0
+; CHECK-NEXT:call void @use(i1 [[C_4]])
+; CHECK-NEXT:[[C_5:%.*]] = icmp eq i32 [[B]], 20
+; CHECK-NEXT:call void @use(i1 [[C_5]])
 ; CHECK-NEXT:ret void
 ; CHECK:   false:
-; CHECK-NEXT:[[F_7:%.*]] = icmp eq i32 [[A]], 50
-; CHECK-NEXT:call void @use(i1 [[F_7]])
+; CHECK-NEXT:[[F_5:%.*]] = icmp eq i32 [[A]], 50
+; CHECK-NEXT:call void @use(i1 [[F_5]])
 ; CHECK-NEXT:[[T_3:%.*]] = icmp ne i32 [[A]], 50
 ; CHECK-NEXT:call void @use(i1 [[T_3]])
-; CHECK-NEXT:[[C_4:%.*]] = icmp eq i32 [[A]], 10
-; CHECK-NEXT:call void @use(i1 [[C_4]])
-; CHECK-NEXT:[[C_5:%.*]] = icmp eq i32 [[B]], 100
-; CHECK-NEXT:call void @use(i1 [[C_5]])
+; CHECK-NEXT:[[C_6:%.*]] = icmp eq i32 [[A]], 10
+; CHECK-NEXT:call void @use(i1 [[C_6]])
+; CHECK-NEXT:[[C_7:%.*]] = icmp eq i32 [[B]], 100
+; CHECK-NEXT:call void @use(i1 [[C_7]])
 ; CHECK-NEXT:ret void
 ;
 entry:
@@ -1028,12 +1028,8 @@ true: ; %a in [21, 100)
   call void @use(i1 %f.2)
   %f.3 = icmp ugt i32 %a, 100
   call void @use(i1 %f.3)
-  %f.4 = icmp eq i32 %b, 0
-  call void @use(i1 %f.3)
-  %f.5 = icmp eq i32 %b, 20
-  call void @use(i1 %f.5)
-  %f.6 = icmp ugt i32 %b, 100
-  call void @use(i1 %f.6)
+  %f.4 = icmp ugt i32 %b, 100
+  call void @use(i1 %f.4)
 
 
   ; Conditions below are true.
@@ -1049,22 +1045,26 @@ true: ; %a in [21, 100)
   call void @use(i1 %c.2)
   %c.3 = icmp ugt i32 %a, 50
   call void @use(i1 %c.3)
+  %c.4 = icmp eq i32 %b, 0
+  call void @use(i1 %c.4)
+  %c.5 = icmp eq i32 %b, 20
+  call void @use(i1 %c.5)
   ret void
 
 false:
   ; Conditions below are false;
-  %f.7 = icmp eq i32 %a, 50
-  call void @use(i1 %f.7)
+  %f.5 = icmp eq i32 %a, 50
+  call void @use(i1 %f.5)
 
   ; Conditions below are true;
   %t.3 = icmp ne i32 %a, 50
   call void @use(i1 %t.3)
 
   ; Conditions below cannot be simplified.
-  %c.4 = icmp eq i32 %a, 10
-  call void @use(i1 %c.4)
-  %c.5 = icmp eq i32 %b, 100
-  call void @use(i1 %c.5)
+  %c.6 = icmp eq i32 %a, 10
+  call void @use(i1 %c.6)
+  %c.7 = icmp eq i32 %b, 100
+  call void @use(i1 %c.7)
   ret void
 }
 



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[llvm-branch-commits] [clang] b88c8f1 - CGDebugInfo: Delete unused parameters

[Fangrui Song via llvm-branch-commits]

Author: Fangrui Song
Date: 2021-01-11T13:39:03-08:00
New Revision: b88c8f1aab527f1aebe612ab6c50a418bff88584

URL: 
https://github.com/llvm/llvm-project/commit/b88c8f1aab527f1aebe612ab6c50a418bff88584
DIFF: 
https://github.com/llvm/llvm-project/commit/b88c8f1aab527f1aebe612ab6c50a418bff88584.diff

LOG: CGDebugInfo: Delete unused parameters

Added: 


Modified: 
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/CodeGen/CGDebugInfo.h
clang/lib/CodeGen/CodeGenFunction.cpp

Removed: 




diff  --git a/clang/lib/CodeGen/CGDebugInfo.cpp 
b/clang/lib/CodeGen/CGDebugInfo.cpp
index 2beb80b2ab6c..881ee24546c2 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -2109,8 +2109,7 @@ StringRef CGDebugInfo::getDynamicInitializerName(const 
VarDecl *VD,
 }
 
 void CGDebugInfo::CollectVTableInfo(const CXXRecordDecl *RD, llvm::DIFile 
*Unit,
-SmallVectorImpl &EltTys,
-llvm::DICompositeType *RecordTy) {
+SmallVectorImpl &EltTys) 
{
   // If this class is not dynamic then there is not any vtable info to collect.
   if (!RD->isDynamicClass())
 return;
@@ -2428,7 +2427,7 @@ llvm::DIType *CGDebugInfo::CreateTypeDefinition(const 
RecordType *Ty) {
   const auto *CXXDecl = dyn_cast(RD);
   if (CXXDecl) {
 CollectCXXBases(CXXDecl, DefUnit, EltTys, FwdDecl);
-CollectVTableInfo(CXXDecl, DefUnit, EltTys, FwdDecl);
+CollectVTableInfo(CXXDecl, DefUnit, EltTys);
   }
 
   // Collect data fields (including static variables and any initializers).
@@ -3794,11 +3793,9 @@ llvm::DISubroutineType 
*CGDebugInfo::getOrCreateFunctionType(const Decl *D,
   return cast(getOrCreateType(FnType, F));
 }
 
-void CGDebugInfo::EmitFunctionStart(GlobalDecl GD, SourceLocation Loc,
+void CGDebugInfo::emitFunctionStart(GlobalDecl GD, SourceLocation Loc,
 SourceLocation ScopeLoc, QualType FnType,
-llvm::Function *Fn, bool CurFuncIsThunk,
-CGBuilderTy &Builder) {
-
+llvm::Function *Fn, bool CurFuncIsThunk) {
   StringRef Name;
   StringRef LinkageName;
 

diff  --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 31fdd6b8ed18..afd5b50c182a 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -324,8 +324,7 @@ class CGDebugInfo {
   /// If the C++ class has vtable info then insert appropriate debug
   /// info entry in EltTys vector.
   void CollectVTableInfo(const CXXRecordDecl *Decl, llvm::DIFile *F,
- SmallVectorImpl &EltTys,
- llvm::DICompositeType *RecordTy);
+ SmallVectorImpl &EltTys);
   /// @}
 
   /// Create a new lexical block node and push it on the stack.
@@ -413,10 +412,9 @@ class CGDebugInfo {
   /// start of a new function.
   /// \param Loc   The location of the function header.
   /// \param ScopeLoc  The location of the function body.
-  void EmitFunctionStart(GlobalDecl GD, SourceLocation Loc,
+  void emitFunctionStart(GlobalDecl GD, SourceLocation Loc,
  SourceLocation ScopeLoc, QualType FnType,
- llvm::Function *Fn, bool CurFnIsThunk,
- CGBuilderTy &Builder);
+ llvm::Function *Fn, bool CurFnIsThunk);
 
   /// Start a new scope for an inlined function.
   void EmitInlineFunctionStart(CGBuilderTy &Builder, GlobalDecl GD);

diff  --git a/clang/lib/CodeGen/CodeGenFunction.cpp 
b/clang/lib/CodeGen/CodeGenFunction.cpp
index 49f13323297c..2c302ae48d61 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -977,8 +977,7 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType 
RetTy,
   ArgTypes.push_back(VD->getType());
 QualType FnType = getContext().getFunctionType(
 RetTy, ArgTypes, FunctionProtoType::ExtProtoInfo(CC));
-DI->EmitFunctionStart(GD, Loc, StartLoc, FnType, CurFn, CurFuncIsThunk,
-  Builder);
+DI->emitFunctionStart(GD, Loc, StartLoc, FnType, CurFn, CurFuncIsThunk);
   }
 
   if (ShouldInstrumentFunction()) {



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[llvm-branch-commits] [llvm] 32bcfcd - Rename debug linkage name with -funique-internal-linkage-names

[Hongtao Yu via llvm-branch-commits]

Author: Hongtao Yu
Date: 2021-01-11T13:56:07-08:00
New Revision: 32bcfcda4e28375e5a85268d2acfabcfcc011abf

URL: 
https://github.com/llvm/llvm-project/commit/32bcfcda4e28375e5a85268d2acfabcfcc011abf
DIFF: 
https://github.com/llvm/llvm-project/commit/32bcfcda4e28375e5a85268d2acfabcfcc011abf.diff

LOG: Rename debug linkage name with -funique-internal-linkage-names

Functions that are renamed under -funique-internal-linkage-names have their 
debug linkage name updated as well.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D93747

Added: 

llvm/test/Transforms/UniqueInternalLinkageNames/unique-internal-linkage-names.ll

Modified: 
llvm/include/llvm/IR/DebugInfoMetadata.h
llvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp

Removed: 
llvm/test/Transforms/UniqueLinkageNames/unique-internal-linkage-names.ll



diff  --git a/llvm/include/llvm/IR/DebugInfoMetadata.h 
b/llvm/include/llvm/IR/DebugInfoMetadata.h
index 20c212ca04e1..22dd5ee6efac 100644
--- a/llvm/include/llvm/IR/DebugInfoMetadata.h
+++ b/llvm/include/llvm/IR/DebugInfoMetadata.h
@@ -2052,6 +2052,10 @@ class DISubprogram : public DILocalScope {
 return getNumOperands() > 10 ? getOperandAs(10) : nullptr;
   }
 
+  void replaceRawLinkageName(MDString *LinkageName) {
+replaceOperandWith(3, LinkageName);
+  }
+
   /// Check if this subprogram describes the given function.
   ///
   /// FIXME: Should this be looking through bitcasts?

diff  --git a/llvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp 
b/llvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp
index 29ad0b6fcae5..2909403fdb10 100644
--- a/llvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp
+++ b/llvm/lib/Transforms/Utils/UniqueInternalLinkageNames.cpp
@@ -13,8 +13,11 @@
 
 #include "llvm/Transforms/Utils/UniqueInternalLinkageNames.h"
 #include "llvm/ADT/SmallString.h"
+#include "llvm/IR/DebugInfoMetadata.h"
+#include "llvm/IR/MDBuilder.h"
 #include "llvm/IR/Module.h"
 #include "llvm/InitializePasses.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/MD5.h"
 #include "llvm/Transforms/Utils/ModuleUtils.h"
 
@@ -34,11 +37,23 @@ static bool uniqueifyInternalLinkageNames(Module &M) {
   // this symbol is of internal linkage type.
   std::string ModuleNameHash = (Twine(".__uniq.") + Twine(IntHash.toString(10, 
false))).str();
   bool Changed = false;
+  MDBuilder MDB(M.getContext());
 
   // Append the module hash to all internal linkage functions.
   for (auto &F : M) {
 if (F.hasInternalLinkage()) {
   F.setName(F.getName() + ModuleNameHash);
+  // Replace linkage names in the debug metadata.
+  if (DISubprogram *SP = F.getSubprogram()) {
+if (SP->getRawLinkageName()) {
+  auto *Name = MDB.createString(F.getName());
+  SP->replaceRawLinkageName(Name);
+  if (DISubprogram *SPDecl = SP->getDeclaration()) {
+if (SPDecl->getRawLinkageName())
+  SPDecl->replaceRawLinkageName(Name);
+  }
+}
+  }
   Changed = true;
 }
   }

diff  --git 
a/llvm/test/Transforms/UniqueInternalLinkageNames/unique-internal-linkage-names.ll
 
b/llvm/test/Transforms/UniqueInternalLinkageNames/unique-internal-linkage-names.ll
new file mode 100644
index ..d07440d1b940
--- /dev/null
+++ 
b/llvm/test/Transforms/UniqueInternalLinkageNames/unique-internal-linkage-names.ll
@@ -0,0 +1,50 @@
+; RUN: opt -S -passes='default' -new-pm-pseudo-probe-for-profiling 
-new-pm-unique-internal-linkage-names -debug-pass-manager < %s 2>&1 | FileCheck 
%s --check-prefix=O0 --check-prefix=UNIQUE
+; RUN: opt -S -passes='default' -new-pm-pseudo-probe-for-profiling 
-new-pm-unique-internal-linkage-names -debug-pass-manager < %s 2>&1 | FileCheck 
%s --check-prefix=O2 --check-prefix=UNIQUE
+; RUN: opt -S -passes='default' -new-pm-pseudo-probe-for-profiling 
-new-pm-unique-internal-linkage-names -debug-pass-manager < %s 2>&1 | FileCheck 
%s --check-prefix=O2 --check-prefix=UNIQUE
+; RUN: opt -S -passes='thinlto-pre-link' 
-new-pm-pseudo-probe-for-profiling -new-pm-unique-internal-linkage-names 
-debug-pass-manager < %s 2>&1 | FileCheck %s --check-prefix=O2 
--check-prefix=UNIQUE
+; RUN: opt -S -passes='thinlto-pre-link' 
-new-pm-pseudo-probe-for-profiling -new-pm-unique-internal-linkage-names 
-debug-pass-manager < %s 2>&1 | FileCheck %s --check-prefix=O2 
--check-prefix=UNIQUE
+; RUN: opt -S -passes=unique-internal-linkage-names < %s -o - | FileCheck %s 
--check-prefix=DBG
+
+define internal i32 @foo() !dbg !15 {
+entry:
+  ret i32 0
+}
+
+define dso_local i32 (...)* @bar() {
+entry:
+  ret i32 (...)* bitcast (i32 ()* @foo to i32 (...)*)
+}
+
+define internal i32 @go() !dbg !19 {
+entry:
+  ret i32 0
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4, !5}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, enums: !2)
+!1 = !DIFile(filename: "test.c", directory: "")
+!2 =

[llvm-branch-commits] [openmp] a81c68a - [OpenMP] Take elf_common.c as a interface library

[Shilei Tian via llvm-branch-commits]

Author: Shilei Tian
Date: 2021-01-11T17:34:26-05:00
New Revision: a81c68ae6be58efa24e2573e155d5ef20260399b

URL: 
https://github.com/llvm/llvm-project/commit/a81c68ae6be58efa24e2573e155d5ef20260399b
DIFF: 
https://github.com/llvm/llvm-project/commit/a81c68ae6be58efa24e2573e155d5ef20260399b.diff

LOG: [OpenMP] Take elf_common.c as a interface library

For now `elf_common.c` is taken as a common part included into
different plugin implementations directly via
`#include "../../common/elf_common.c"`, which is not a best practice. Since it
is simple enough such that we don't need to create a real library for it, we 
just
take it as a interface library so that other targets can link it directly. 
Another
advantage of this method is, we don't need to add the folder into header search
path which can potentially pollute the search path.

VE and AMD platforms have not been tested because I don't have target machines.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D94443

Added: 
openmp/libomptarget/plugins/common/CMakeLists.txt
openmp/libomptarget/plugins/common/elf_common/CMakeLists.txt
openmp/libomptarget/plugins/common/elf_common/elf_common.h

Modified: 
openmp/libomptarget/plugins/CMakeLists.txt
openmp/libomptarget/plugins/amdgpu/CMakeLists.txt
openmp/libomptarget/plugins/amdgpu/src/rtl.cpp
openmp/libomptarget/plugins/cuda/CMakeLists.txt
openmp/libomptarget/plugins/cuda/src/rtl.cpp
openmp/libomptarget/plugins/generic-elf-64bit/src/rtl.cpp
openmp/libomptarget/plugins/ve/CMakeLists.txt
openmp/libomptarget/plugins/ve/src/rtl.cpp

Removed: 
openmp/libomptarget/plugins/common/elf_common.c



diff  --git a/openmp/libomptarget/plugins/CMakeLists.txt 
b/openmp/libomptarget/plugins/CMakeLists.txt
index f8372b619407..85b5d62742bd 100644
--- a/openmp/libomptarget/plugins/CMakeLists.txt
+++ b/openmp/libomptarget/plugins/CMakeLists.txt
@@ -1,15 +1,17 @@
 
##===--===##
-# 
+#
 # Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-# 
+#
 
##===--===##
 #
 # Build plugins for the user system if available.
 #
 
##===--===##
 
+add_subdirectory(common)
+
 # void build_generic_elf64(string tmachine, string tmachine_name, string 
tmachine_libname, string elf_machine_id);
 # - build a plugin for an ELF based generic 64-bit target based on libffi.
 # - tmachine: name of the machine processor as used in the cmake build system.
@@ -19,41 +21,42 @@ macro(build_generic_elf64 tmachine tmachine_name 
tmachine_libname tmachine_tripl
 if(CMAKE_SYSTEM_PROCESSOR MATCHES "${tmachine}$")
   if(LIBOMPTARGET_DEP_LIBELF_FOUND)
 if(LIBOMPTARGET_DEP_LIBFFI_FOUND)
-
+
   libomptarget_say("Building ${tmachine_name} offloading plugin.")
-
+
   include_directories(${LIBOMPTARGET_DEP_LIBFFI_INCLUDE_DIR})
   include_directories(${LIBOMPTARGET_DEP_LIBELF_INCLUDE_DIR})
-  
+
   # Define macro to be used as prefix of the runtime messages for this 
target.
   add_definitions("-DTARGET_NAME=${tmachine_name}")
-  
+
   # Define macro with the ELF ID for this target.
   add_definitions("-DTARGET_ELF_ID=${elf_machine_id}")
-
-  add_library("omptarget.rtl.${tmachine_libname}" SHARED 
+
+  add_library("omptarget.rtl.${tmachine_libname}" SHARED
 ${CMAKE_CURRENT_SOURCE_DIR}/../generic-elf-64bit/src/rtl.cpp)
-
+
   # Install plugin under the lib destination folder.
-  install(TARGETS "omptarget.rtl.${tmachine_libname}" 
+  install(TARGETS "omptarget.rtl.${tmachine_libname}"
 LIBRARY DESTINATION "${OPENMP_INSTALL_LIBDIR}")
-
+
   target_link_libraries(
 "omptarget.rtl.${tmachine_libname}"
-${LIBOMPTARGET_DEP_LIBFFI_LIBRARIES} 
+elf_common
+${LIBOMPTARGET_DEP_LIBFFI_LIBRARIES}
 ${LIBOMPTARGET_DEP_LIBELF_LIBRARIES}
 dl
 "-Wl,--version-script=${CMAKE_CURRENT_SOURCE_DIR}/../exports")
-
+
   list(APPEND LIBOMPTARGET_TESTED_PLUGINS
 "omptarget.rtl.${tmachine_libname}")
 
   # Report to the parent scope that we are building a plugin.
-  set(LIBOMPTARGET_SYSTEM_TARGETS 
+  set(LIBOMPTARGET_SYSTEM_TARGETS
 "${LIBOMPTARGET_SYSTEM_TARGETS} ${tmachine_triple}" PARENT_SCOPE)
   set(LIBOMPTARGET_TESTED_PLUGINS
 "${LIBOMPTARGET_TESTED_PLUGINS}" PARENT_SCOPE)
-  
+
 else(LIBOMPTARGET_DEP_LIBFFI_FOUND)
   libomptarget_say("Not building ${tmachine_name} offloading plugin: 
libffi dependency not found.")
 endif(LIBOMPTARGET_DEP_LIBFFI_FOUND)

diff  --git a/openmp

[llvm-branch-commits] [clang] 0a23fbd - clang: Always pass PowerPC endian information to GNU as

[Nick Desaulniers via llvm-branch-commits]

Author: Nathan Chancellor
Date: 2021-01-11T14:50:28-08:00
New Revision: 0a23fbd28c7509f2f980946091e6055bf27164d2

URL: 
https://github.com/llvm/llvm-project/commit/0a23fbd28c7509f2f980946091e6055bf27164d2
DIFF: 
https://github.com/llvm/llvm-project/commit/0a23fbd28c7509f2f980946091e6055bf27164d2.diff

LOG: clang: Always pass PowerPC endian information to GNU as

When building a 64-bit big endian PowerPC Linux kernel with a 64-bit
little endian PowerPC target, the 32-bit vDSO errors:

```
$ make ARCH=powerpc CC=clang CROSS_COMPILE=powerpc64le-linux-gnu- \
   pseries_defconfig arch/powerpc/kernel/vdso32/
ld.lld: error: arch/powerpc/kernel/vdso32/sigtramp.o is incompatible with 
elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/gettimeofday.o is incompatible with 
elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/datapage.o is incompatible with 
elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/cacheflush.o is incompatible with 
elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/note.o is incompatible with 
elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/getcpu.o is incompatible with 
elf32-powerpc
ld.lld: error: arch/powerpc/kernel/vdso32/vgettimeofday.o is incompatible with 
elf32-powerpc
...
```

This happens because the endian information is missing from the call to
the assembler, even though it was explicitly passed to clang. See the
below example.

```
$ echo | clang --target=powerpc64le-linux-gnu \
   --prefix=/usr/bin/powerpc64le-linux-gnu- \
   -no-integrated-as -m32 -mbig-endian -### -x c -c -
 ".../clang-12" "-cc1" "-triple" "powerpc-unknown-linux-gnu" ...
...
  "/usr/bin/powerpc64le-linux-gnu-as" "-a32" "-mppc" "-many" "-o" "-.o" 
"/tmp/--e69e28.s"
```

clang sets the right target with -m32 and -mbig-endian but -mbig-endian
does not make it to the assembler, resulting in a 32-bit little endian
binary. This differs from the little endian targets, which always pass
-mlittle-endian.

```
$ echo | clang --target=powerpc64-linux-gnu \
   --prefix=/usr/bin/powerpc64-linux-gnu- \
   -no-integrated-as -m32 -mlittle-endian -### -x c -c -
 ".../clang-12" "-cc1" "-triple" "powerpcle-unknown-linux-gnu" ...
...
 "/usr/bin/powerpc64-linux-gnu-as" "-a32" "-mppc" "-mlittle-endian" "-many" 
"-o" "-.o" "/tmp/--405dbd.s"
```

Do the same thing for the big endian targets so that there is no more
error. This matches GCC's behavior, where -mbig and -mlittle are always
passed along to GNU as.

```
$ echo | powerpc64-linux-gcc -### -x c -c -
...
.../powerpc64-linux/bin/as -a64 -mpower4 -many -mbig -o -.o /tmp/ccVn7NAm.s
...

$ echo | powerpc64le-linux-gcc -### -x c -c -
...
.../powerpc64le-linux/bin/as -a64 -mpower8 -many -mlittle -o -.o /tmp/ccPN9ato.s
...
```

Reviewed By: nickdesaulniers, MaskRay

Differential Revision: https://reviews.llvm.org/D94442

Added: 


Modified: 
clang/lib/Driver/ToolChains/Gnu.cpp
clang/test/Driver/ppc-features.cpp

Removed: 




diff  --git a/clang/lib/Driver/ToolChains/Gnu.cpp 
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 164cf6e7..1d8a3cdce92a 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -731,6 +731,7 @@ void tools::gnutools::Assembler::ConstructJob(Compilation 
&C,
   case llvm::Triple::ppc: {
 CmdArgs.push_back("-a32");
 CmdArgs.push_back("-mppc");
+CmdArgs.push_back("-mbig-endian");
 CmdArgs.push_back(
   ppc::getPPCAsmModeForCPU(getCPUName(Args, getToolChain().getTriple(;
 break;
@@ -746,6 +747,7 @@ void tools::gnutools::Assembler::ConstructJob(Compilation 
&C,
   case llvm::Triple::ppc64: {
 CmdArgs.push_back("-a64");
 CmdArgs.push_back("-mppc64");
+CmdArgs.push_back("-mbig-endian");
 CmdArgs.push_back(
   ppc::getPPCAsmModeForCPU(getCPUName(Args, getToolChain().getTriple(;
 break;

diff  --git a/clang/test/Driver/ppc-features.cpp 
b/clang/test/Driver/ppc-features.cpp
index 05d71b95dba7..85060951aa16 100644
--- a/clang/test/Driver/ppc-features.cpp
+++ b/clang/test/Driver/ppc-features.cpp
@@ -156,14 +156,25 @@
 // CHECK-NOSPE: "-target-feature" "-spe"
 
 // Assembler features
-// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -o %t.o 
-no-integrated-as 2>&1 | FileCheck -check-prefix=CHECK_BE_AS_ARGS %s
-// CHECK_BE_AS_ARGS: "-mppc64"
-// CHECK_BE_AS_ARGS: "-many"
-
-// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -o %t.o 
-no-integrated-as 2>&1 | FileCheck -check-prefix=CHECK_LE_AS_ARGS %s
-// CHECK_LE_AS_ARGS: "-mppc64"
-// CHECK_LE_AS_ARGS: "-mlittle-endian"
-// CHECK_LE_AS_ARGS: "-mpower8"
+// RUN: %clang -target powerpc-unknown-linux-gnu %s -### -o %t.o 
-no-integrated-as 2>&1 | FileCheck -check-prefix=CHECK_32_BE_AS_ARGS %s
+// CHECK_32_BE_AS_ARGS: "-mppc"
+// CHECK_32_BE_AS_ARGS-SAME: "-mbig-endian"
+// CHECK_32_BE_AS_ARGS-SAME: "-many"
+
+// RUN: %clang -target powerpcle-u

[llvm-branch-commits] [mlir] 762ffc9 - Update syntax for tensor and memref types to match parser.

[Mehdi Amini via llvm-branch-commits]

Author: Richard Uhler
Date: 2021-01-11T22:57:14Z
New Revision: 762ffc95550c32606e771b630fcab2e521873419

URL: 
https://github.com/llvm/llvm-project/commit/762ffc95550c32606e771b630fcab2e521873419
DIFF: 
https://github.com/llvm/llvm-project/commit/762ffc95550c32606e771b630fcab2e521873419.diff

LOG: Update syntax for tensor and memref types to match parser.

Based on the comments in lib/Parser/TypeParser.cpp on the
parseMemRefType and parseTensorType functions.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D94262

Added: 


Modified: 
mlir/docs/LangRef.md
mlir/lib/Parser/TypeParser.cpp

Removed: 




diff  --git a/mlir/docs/LangRef.md b/mlir/docs/LangRef.md
index 28962a8893ee..017ec02af7ae 100644
--- a/mlir/docs/LangRef.md
+++ b/mlir/docs/LangRef.md
@@ -929,15 +929,15 @@ Syntax:
 ```
 memref-type ::= ranked-memref-type | unranked-memref-type
 
-ranked-memref-type ::= `memref` `<` dimension-list-ranked 
tensor-memref-element-type
+ranked-memref-type ::= `memref` `<` dimension-list-ranked type
   (`,` layout-specification)? (`,` memory-space)? `>`
 
-unranked-memref-type ::= `memref` `<*x` tensor-memref-element-type
- (`,` memory-space)? `>`
+unranked-memref-type ::= `memref` `<*x` type (`,` memory-space)? `>`
 
 stride-list ::= `[` (dimension (`,` dimension)*)? `]`
 strided-layout ::= `offset:` dimension `,` `strides: ` stride-list
-layout-specification ::= semi-affine-map | strided-layout
+semi-affine-map-composition ::= (semi-affine-map `,` )* semi-affine-map
+layout-specification ::= semi-affine-map-composition | strided-layout
 memory-space ::= integer-literal /* | TODO: address-space-id */
 ```
 
@@ -1201,10 +1201,8 @@ where its value does not have a defined dynamic 
representation.
 Syntax:
 
 ```
-tensor-type ::= `tensor` `<` dimension-list tensor-memref-element-type `>`
-tensor-memref-element-type ::= vector-element-type | vector-type | complex-type
+tensor-type ::= `tensor` `<` dimension-list type `>`
 
-// memref requires a known rank, but tensor does not.
 dimension-list ::= dimension-list-ranked | (`*` `x`)
 dimension-list-ranked ::= (dimension `x`)*
 dimension ::= `?` | decimal-literal

diff  --git a/mlir/lib/Parser/TypeParser.cpp b/mlir/lib/Parser/TypeParser.cpp
index ab7f85a645e4..c258cc8b6d29 100644
--- a/mlir/lib/Parser/TypeParser.cpp
+++ b/mlir/lib/Parser/TypeParser.cpp
@@ -181,12 +181,14 @@ ParseResult Parser::parseStridedLayout(int64_t &offset,
 ///   memref-type ::= ranked-memref-type | unranked-memref-type
 ///
 ///   ranked-memref-type ::= `memref` `<` dimension-list-ranked type
-///  (`,` semi-affine-map-composition)? (`,`
-///  memory-space)? `>`
+///  (`,` layout-specification)? (`,` memory-space)? 
`>`
 ///
 ///   unranked-memref-type ::= `memref` `<*x` type (`,` memory-space)? `>`
 ///
+///   stride-list ::= `[` (dimension (`,` dimension)*)? `]`
+///   strided-layout ::= `offset:` dimension `,` `strides: ` stride-list
 ///   semi-affine-map-composition ::= (semi-affine-map `,` )* semi-affine-map
+///   layout-specification ::= semi-affine-map-composition | strided-layout
 ///   memory-space ::= integer-literal /* | TODO: address-space-id */
 ///
 Type Parser::parseMemRefType() {



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[llvm-branch-commits] [llvm] 278a3ea - [RISCV] Use vmv.v.i vd, 0 instead of vmv.v.x vd, x0 for llvm.riscv.vfmv.v.f with 0.0

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2021-01-11T15:08:05-08:00
New Revision: 278a3ea1b27089dbc7060e02f612c8a3bf137bb2

URL: 
https://github.com/llvm/llvm-project/commit/278a3ea1b27089dbc7060e02f612c8a3bf137bb2
DIFF: 
https://github.com/llvm/llvm-project/commit/278a3ea1b27089dbc7060e02f612c8a3bf137bb2.diff

LOG: [RISCV] Use vmv.v.i vd, 0 instead of vmv.v.x vd, x0 for 
llvm.riscv.vfmv.v.f with 0.0

This matches what we use for integer 0. It's also consistent with
the scalar 'mv' pseudo that uses addi rather than add with x0.

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 8f494d54ee64..32d208046174 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3363,8 +3363,8 @@ foreach fvti = AllFloatVectors in {
   // If we're splatting fpimm0, use vmv.v.x vd, x0.
   def : Pat<(fvti.Vector (int_riscv_vfmv_v_f
  (fvti.Scalar (fpimm0)), GPR:$vl)),
-(!cast("PseudoVMV_V_X_"#fvti.LMul.MX)
- X0, (NoX0 GPR:$vl), fvti.SEW)>;
+(!cast("PseudoVMV_V_I_"#fvti.LMul.MX)
+ 0, (NoX0 GPR:$vl), fvti.SEW)>;
 
   def : Pat<(fvti.Vector (int_riscv_vfmv_v_f
  (fvti.Scalar fvti.ScalarRegClass:$rs2), GPR:$vl)),

diff  --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll 
b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll
index b3a095d34572..1a49ad3f67a7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll
@@ -244,7 +244,7 @@ define  
@intrinsic_vfmv.v.f_zero_nxv1f16(i32 %0) nounwind {
 entry:
 ; CHECK-LABEL: intrinsic_vfmv.v.f_zero_nxv1f16
 ; CHECK:   vsetvli {{.*}}, a0, e16,mf4,ta,mu
-; CHECK:   vmv.v.x {{v[0-9]+}}, zero
+; CHECK:   vmv.v.i {{v[0-9]+}}, 0
   %a = call  @llvm.riscv.vfmv.v.f.nxv1f16(
 half 0.0,
 i32 %0)
@@ -252,11 +252,11 @@ entry:
   ret  %a
 }
 
-define  @intrinsic_vmv.v.x_zero_nxv2f16(i32 %0) nounwind {
+define  @intrinsic_vmv.v.i_zero_nxv2f16(i32 %0) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv2f16
+; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f16
 ; CHECK:   vsetvli {{.*}}, a0, e16,mf2,ta,mu
-; CHECK:   vmv.v.x {{v[0-9]+}}, zero
+; CHECK:   vmv.v.i {{v[0-9]+}}, 0
   %a = call  @llvm.riscv.vfmv.v.f.nxv2f16(
 half 0.0,
 i32 %0)
@@ -264,11 +264,11 @@ entry:
   ret  %a
 }
 
-define  @intrinsic_vmv.v.x_zero_nxv4f16(i32 %0) nounwind {
+define  @intrinsic_vmv.v.i_zero_nxv4f16(i32 %0) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv4f16
+; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f16
 ; CHECK:   vsetvli {{.*}}, a0, e16,m1,ta,mu
-; CHECK:   vmv.v.x {{v[0-9]+}}, zero
+; CHECK:   vmv.v.i {{v[0-9]+}}, 0
   %a = call  @llvm.riscv.vfmv.v.f.nxv4f16(
 half 0.0,
 i32 %0)
@@ -276,11 +276,11 @@ entry:
   ret  %a
 }
 
-define  @intrinsic_vmv.v.x_zero_nxv8f16(i32 %0) nounwind {
+define  @intrinsic_vmv.v.i_zero_nxv8f16(i32 %0) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv8f16
+; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f16
 ; CHECK:   vsetvli {{.*}}, a0, e16,m2,ta,mu
-; CHECK:   vmv.v.x {{v[0-9]+}}, zero
+; CHECK:   vmv.v.i {{v[0-9]+}}, 0
   %a = call  @llvm.riscv.vfmv.v.f.nxv8f16(
 half 0.0,
 i32 %0)
@@ -288,11 +288,11 @@ entry:
   ret  %a
 }
 
-define  @intrinsic_vmv.v.x_zero_nxv16f16(i32 %0) nounwind {
+define  @intrinsic_vmv.v.i_zero_nxv16f16(i32 %0) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv16f16
+; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f16
 ; CHECK:   vsetvli {{.*}}, a0, e16,m4,ta,mu
-; CHECK:   vmv.v.x {{v[0-9]+}}, zero
+; CHECK:   vmv.v.i {{v[0-9]+}}, 0
   %a = call  @llvm.riscv.vfmv.v.f.nxv16f16(
 half 0.0,
 i32 %0)
@@ -300,11 +300,11 @@ entry:
   ret  %a
 }
 
-define  @intrinsic_vmv.v.x_zero_nxv32f16(i32 %0) nounwind {
+define  @intrinsic_vmv.v.i_zero_nxv32f16(i32 %0) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv32f16
+; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv32f16
 ; CHECK:   vsetvli {{.*}}, a0, e16,m8,ta,mu
-; CHECK:   vmv.v.x {{v[0-9]+}}, zero
+; CHECK:   vmv.v.i {{v[0-9]+}}, 0
   %a = call  @llvm.riscv.vfmv.v.f.nxv32f16(
 half 0.0,
 i32 %0)
@@ -312,11 +312,11 @@ entry:
   ret  %a
 }
 
-define  @intrinsic_vmv.v.x_zero_nxv1f32(i32 %0) nounwind {
+define  @intrinsic_vmv.v.i_zero_nxv1f32(i32 %0) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv1f32
+; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f32
 ; CHECK:   vsetvli {{.*}}, a0, e32,mf2,ta,mu
-; CHECK:   vmv.v.x {{v[0-9]+}}, zero
+; CHECK:   vmv.v.i {{v[0-9]+}}, 0
   %a = call  @llvm.riscv.vfmv.v.f.nxv1f32(
 float 0.0,
   

[llvm-branch-commits] [llvm] c22bc5f - [SimplifyCFG] SwitchToLookupTable(): don't insert a DomTree edge that already exists

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2021-01-12T02:09:46+03:00
New Revision: c22bc5f1f8b295674aa3a62dced8a39ad3d2aa02

URL: 
https://github.com/llvm/llvm-project/commit/c22bc5f1f8b295674aa3a62dced8a39ad3d2aa02
DIFF: 
https://github.com/llvm/llvm-project/commit/c22bc5f1f8b295674aa3a62dced8a39ad3d2aa02.diff

LOG: [SimplifyCFG] SwitchToLookupTable(): don't insert a DomTree edge that 
already exists

SI is the terminator of BB, so the edge we are adding obviously already existed.

Indeed, this change does not have a test coverage change.
This failure has been exposed in an existing test coverage
by a follow-up patch that switches to lazy domtreeupdater mode,
and removes domtree verification from
SimplifyCFGOpt::simplifyOnce()/SimplifyCFGOpt::run(),
IOW it does not appear feasible to add dedicated test coverage here.

Added: 


Modified: 
llvm/lib/Transforms/Utils/SimplifyCFG.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp 
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 62cab573a819..747eb522df11 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -5973,7 +5973,6 @@ static bool SwitchToLookupTable(SwitchInst *SI, 
IRBuilder<> &Builder,
 RangeCheckBranch =
 Builder.CreateCondBr(Cmp, LookupBB, SI->getDefaultDest());
 Updates.push_back({DominatorTree::Insert, BB, LookupBB});
-Updates.push_back({DominatorTree::Insert, BB, SI->getDefaultDest()});
   }
 
   // Populate the BB that does the lookups.



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[llvm-branch-commits] [llvm] c0de0a1 - [SimplifyCFG] SimplifyBranchOnICmpChain(): don't insert a DomTree edge that already exists

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2021-01-12T02:09:46+03:00
New Revision: c0de0a1b72c08783141c430b583e04e5107ebc0a

URL: 
https://github.com/llvm/llvm-project/commit/c0de0a1b72c08783141c430b583e04e5107ebc0a
DIFF: 
https://github.com/llvm/llvm-project/commit/c0de0a1b72c08783141c430b583e04e5107ebc0a.diff

LOG: [SimplifyCFG] SimplifyBranchOnICmpChain(): don't insert a DomTree edge 
that already exists

BB was already always branching to EdgeBB, there is no edge to add.

Indeed, this change does not have a test coverage change.
This failure has been exposed in an existing test coverage
by a follow-up patch that switches to lazy domtreeupdater mode,
and removes domtree verification from
SimplifyCFGOpt::simplifyOnce()/SimplifyCFGOpt::run(),
IOW it does not appear feasible to add dedicated test coverage here.

Added: 


Modified: 
llvm/lib/Transforms/Utils/SimplifyCFG.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp 
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 747eb522df11..7158133f177a 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -4229,7 +4229,6 @@ bool SimplifyCFGOpt::SimplifyBranchOnICmpChain(BranchInst 
*BI,
   // We added edges from PI to the EdgeBB.  As such, if there were any
   // PHI nodes in EdgeBB, they need entries to be added corresponding to
   // the number of edges added.
-  Updates.push_back({DominatorTree::Insert, BB, EdgeBB});
   for (BasicBlock::iterator BBI = EdgeBB->begin(); isa(BBI); ++BBI) {
 PHINode *PN = cast(BBI);
 Value *InVal = PN->getIncomingValueForBlock(BB);



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[llvm-branch-commits] [llvm] f9ba347 - [SimplifyCFG] FoldValueComparisonIntoPredecessors(): don't insert a DomTree edge if it already exists

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2021-01-12T02:09:47+03:00
New Revision: f9ba34770638389ee9b251f6ab801c7411601c77

URL: 
https://github.com/llvm/llvm-project/commit/f9ba34770638389ee9b251f6ab801c7411601c77
DIFF: 
https://github.com/llvm/llvm-project/commit/f9ba34770638389ee9b251f6ab801c7411601c77.diff

LOG: [SimplifyCFG] FoldValueComparisonIntoPredecessors(): don't insert a 
DomTree edge if it already exists

When we are adding edges to the terminator and potentially turning it
into a switch (if it wasn't already), it is possible that the
case we're adding will share it's destination with one of the
preexisting cases, in which case there is no domtree edge to add.

Indeed, this change does not have a test coverage change.
This failure has been exposed in an existing test coverage
by a follow-up patch that switches to lazy domtreeupdater mode,
and removes domtree verification from
SimplifyCFGOpt::simplifyOnce()/SimplifyCFGOpt::run(),
IOW it does not appear feasible to add dedicated test coverage here.

Added: 


Modified: 
llvm/lib/Transforms/Utils/SimplifyCFG.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp 
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 7158133f177a..880d0e7e6e13 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -1267,7 +1267,8 @@ bool 
SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(Instruction *TI,
   (void)I;
   AddPredecessorToBlock(NewSuccessor.first, Pred, BB);
 }
-Updates.push_back({DominatorTree::Insert, Pred, NewSuccessor.first});
+if (!is_contained(successors(Pred), NewSuccessor.first))
+  Updates.push_back({DominatorTree::Insert, Pred, NewSuccessor.first});
   }
 
   Builder.SetInsertPoint(PTI);



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[llvm-branch-commits] [llvm] 90a92f8 - [NFCI][Utils/Local] removeUnreachableBlocks(): cleanup support for lazy DomTreeUpdater

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2021-01-12T02:09:47+03:00
New Revision: 90a92f8b4d783cb08443a22f0dd2fa3adcb43807

URL: 
https://github.com/llvm/llvm-project/commit/90a92f8b4d783cb08443a22f0dd2fa3adcb43807
DIFF: 
https://github.com/llvm/llvm-project/commit/90a92f8b4d783cb08443a22f0dd2fa3adcb43807.diff

LOG: [NFCI][Utils/Local] removeUnreachableBlocks(): cleanup support for lazy 
DomTreeUpdater

When DomTreeUpdater is in lazy update mode, the blocks
that were scheduled to be removed, won't be removed
until the updates are flushed, e.g. by asking
DomTreeUpdater for a up-to-date DomTree.

>From the function's current code, it is pretty evident
that the support for the lazy mode is an afterthought,
see e.g. how we roll-back NumRemoved statistic..

So instead of considering all the unreachable blocks
as the blocks-to-be-removed, simply additionally skip
all the blocks that are already scheduled to be removed

Added: 


Modified: 
llvm/lib/Transforms/Utils/Local.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Utils/Local.cpp 
b/llvm/lib/Transforms/Utils/Local.cpp
index 52e71ad164a5..6e526cc4f105 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -2362,33 +2362,40 @@ bool llvm::removeUnreachableBlocks(Function &F, 
DomTreeUpdater *DTU,
 return Changed;
 
   assert(Reachable.size() < F.size());
-  NumRemoved += F.size() - Reachable.size();
 
-  SmallSetVector DeadBlockSet;
+  // Are there any blocks left to actually delete?
+  SmallSetVector BlocksToRemove;
   for (BasicBlock &BB : F) {
 // Skip reachable basic blocks
 if (Reachable.count(&BB))
   continue;
-DeadBlockSet.insert(&BB);
+// Skip already-deleted blocks
+if (DTU && DTU->isBBPendingDeletion(&BB))
+  continue;
+BlocksToRemove.insert(&BB);
   }
 
+  if (BlocksToRemove.empty())
+return Changed;
+
+  Changed = true;
+  NumRemoved += BlocksToRemove.size();
+
   if (MSSAU)
-MSSAU->removeBlocks(DeadBlockSet);
+MSSAU->removeBlocks(BlocksToRemove);
 
-  // Loop over all of the basic blocks that are not reachable, dropping all of
+  // Loop over all of the basic blocks that are up for removal, dropping all of
   // their internal references. Update DTU if available.
   std::vector Updates;
-  for (auto *BB : DeadBlockSet) {
+  for (auto *BB : BlocksToRemove) {
 SmallSetVector UniqueSuccessors;
 for (BasicBlock *Successor : successors(BB)) {
-  if (!DeadBlockSet.count(Successor))
+  // Only remove references to BB in reachable successors of BB.
+  if (Reachable.count(Successor))
 Successor->removePredecessor(BB);
   if (DTU)
 UniqueSuccessors.insert(Successor);
 }
-if (DTU)
-  for (auto *UniqueSuccessor : UniqueSuccessors)
-Updates.push_back({DominatorTree::Delete, BB, UniqueSuccessor});
 BB->dropAllReferences();
 if (DTU) {
   Instruction *TI = BB->getTerminator();
@@ -2401,27 +2408,22 @@ bool llvm::removeUnreachableBlocks(Function &F, 
DomTreeUpdater *DTU,
   new UnreachableInst(BB->getContext(), BB);
   assert(succ_empty(BB) && "The successor list of BB isn't empty before "
"applying corresponding DTU updates.");
+  Updates.reserve(Updates.size() + UniqueSuccessors.size());
+  for (auto *UniqueSuccessor : UniqueSuccessors)
+Updates.push_back({DominatorTree::Delete, BB, UniqueSuccessor});
 }
   }
 
   if (DTU) {
 DTU->applyUpdates(Updates);
-bool Deleted = false;
-for (auto *BB : DeadBlockSet) {
-  if (DTU->isBBPendingDeletion(BB))
---NumRemoved;
-  else
-Deleted = true;
+for (auto *BB : BlocksToRemove)
   DTU->deleteBB(BB);
-}
-if (!Deleted)
-  return false;
   } else {
-for (auto *BB : DeadBlockSet)
+for (auto *BB : BlocksToRemove)
   BB->eraseFromParent();
   }
 
-  return true;
+  return Changed;
 }
 
 void llvm::combineMetadata(Instruction *K, const Instruction *J,



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[llvm-branch-commits] [llvm] 81afeac - [SimplifyCFGPass] mergeEmptyReturnBlocks(): skip blocks scheduled for removal as per DomTreeUpdater

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2021-01-12T02:09:47+03:00
New Revision: 81afeacd379f160495718438d6dd5e9b848a169d

URL: 
https://github.com/llvm/llvm-project/commit/81afeacd379f160495718438d6dd5e9b848a169d
DIFF: 
https://github.com/llvm/llvm-project/commit/81afeacd379f160495718438d6dd5e9b848a169d.diff

LOG: [SimplifyCFGPass] mergeEmptyReturnBlocks(): skip blocks scheduled for 
removal as per DomTreeUpdater

Thus supporting lazy DomTreeUpdater mode,
where the domtree updates (and thus block removals)
aren't applied immediately, but are delayed
until last possible moment.

Added: 


Modified: 
llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp 
b/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
index 44b9ddd3e1ee..944331932495 100644
--- a/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
+++ b/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
@@ -86,8 +86,9 @@ static bool mergeEmptyReturnBlocks(Function &F, 
DomTreeUpdater *DTU) {
   BasicBlock *RetBlock = nullptr;
 
   // Scan all the blocks in the function, looking for empty return blocks.
-  for (Function::iterator BBI = F.begin(), E = F.end(); BBI != E; ) {
-BasicBlock &BB = *BBI++;
+  for (BasicBlock &BB : make_early_inc_range(F)) {
+if (DTU && DTU->isBBPendingDeletion(&BB))
+  continue;
 
 // Only look at return blocks.
 ReturnInst *Ret = dyn_cast(BB.getTerminator());



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[llvm-branch-commits] [llvm] ec8a6c1 - [SimplifyCFGPass] iterativelySimplifyCFG(): support lazy DomTreeUpdater

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2021-01-12T02:09:47+03:00
New Revision: ec8a6c11db4102ec249ce90084b3f615c5de15e5

URL: 
https://github.com/llvm/llvm-project/commit/ec8a6c11db4102ec249ce90084b3f615c5de15e5
DIFF: 
https://github.com/llvm/llvm-project/commit/ec8a6c11db4102ec249ce90084b3f615c5de15e5.diff

LOG: [SimplifyCFGPass] iterativelySimplifyCFG(): support lazy DomTreeUpdater

This boils down to how we deal with early-increment iterator
over function's basic blocks: not only we need to early-increment,
after that we also need to skip all the blocks
that are scheduled for removal, as per DomTreeUpdater.

Added: 


Modified: 
llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp 
b/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
index 944331932495..0e1ec7194527 100644
--- a/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
+++ b/llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
@@ -209,7 +209,17 @@ static bool iterativelySimplifyCFG(Function &F, const 
TargetTransformInfo &TTI,
 
 // Loop over all of the basic blocks and remove them if they are unneeded.
 for (Function::iterator BBIt = F.begin(); BBIt != F.end(); ) {
-  if (simplifyCFG(&*BBIt++, TTI, DTU, Options, &LoopHeaders)) {
+  BasicBlock &BB = *BBIt++;
+  if (DTU) {
+assert(
+!DTU->isBBPendingDeletion(&BB) &&
+"Should not end up trying to simplify blocks marked for removal.");
+// Make sure that the advanced iterator does not point at the blocks
+// that are marked for removal, skip over all such blocks.
+while (BBIt != F.end() && DTU->isBBPendingDeletion(&*BBIt))
+  ++BBIt;
+  }
+  if (simplifyCFG(&BB, TTI, DTU, Options, &LoopHeaders)) {
 LocalChange = true;
 ++NumSimpl;
   }



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[llvm-branch-commits] [llvm] 5ccff5a - ADT: Fix pointer comparison UB in SmallVector

[Duncan P. N. Exon Smith via llvm-branch-commits]

Author: Duncan P. N. Exon Smith
Date: 2021-01-11T15:31:04-08:00
New Revision: 5ccff5aaa68ab789834c4463ce05b05e57593b34

URL: 
https://github.com/llvm/llvm-project/commit/5ccff5aaa68ab789834c4463ce05b05e57593b34
DIFF: 
https://github.com/llvm/llvm-project/commit/5ccff5aaa68ab789834c4463ce05b05e57593b34.diff

LOG: ADT: Fix pointer comparison UB in SmallVector

The standard requires comparisons of pointers to unrelated storage to
use `std::less`. Split out some helpers that do that and update all the
code that was comparing using `<` and friends (mostly assertions).

Differential Revision: https://reviews.llvm.org/D93777

Added: 


Modified: 
llvm/include/llvm/ADT/SmallVector.h

Removed: 




diff  --git a/llvm/include/llvm/ADT/SmallVector.h 
b/llvm/include/llvm/ADT/SmallVector.h
index 3bbde2d9c0fb..803588143d81 100644
--- a/llvm/include/llvm/ADT/SmallVector.h
+++ b/llvm/include/llvm/ADT/SmallVector.h
@@ -136,11 +136,32 @@ class SmallVectorTemplateCommon
 this->Size = this->Capacity = 0; // FIXME: Setting Capacity to 0 is 
suspect.
   }
 
+  /// Return true if V is an internal reference to the given range.
+  bool isReferenceToRange(const void *V, const void *First, const void *Last) 
const {
+// Use std::less to avoid UB.
+std::less<> LessThan;
+return !LessThan(V, First) && LessThan(V, Last);
+  }
+
+  /// Return true if V is an internal reference to this vector.
+  bool isReferenceToStorage(const void *V) const {
+return isReferenceToRange(V, this->begin(), this->end());
+  }
+
+  /// Return true if First and Last form a valid (possibly empty) range in this
+  /// vector's storage.
+  bool isRangeInStorage(const void *First, const void *Last) const {
+// Use std::less to avoid UB.
+std::less<> LessThan;
+return !LessThan(First, this->begin()) && !LessThan(Last, First) &&
+   !LessThan(this->end(), Last);
+  }
+
   /// Return true unless Elt will be invalidated by resizing the vector to
   /// NewSize.
   bool isSafeToReferenceAfterResize(const void *Elt, size_t NewSize) {
 // Past the end.
-if (LLVM_LIKELY(Elt < this->begin() || Elt >= this->end()))
+if (LLVM_LIKELY(!isReferenceToStorage(Elt)))
   return true;
 
 // Return false if Elt will be destroyed by shrinking.
@@ -579,8 +600,7 @@ class SmallVectorImpl : public SmallVectorTemplateBase {
 // Just cast away constness because this is a non-const member function.
 iterator I = const_cast(CI);
 
-assert(I >= this->begin() && "Iterator to erase is out of bounds.");
-assert(I < this->end() && "Erasing at past-the-end iterator.");
+assert(this->isReferenceToStorage(CI) && "Iterator to erase is out of 
bounds.");
 
 iterator N = I;
 // Shift all elts down one.
@@ -595,9 +615,7 @@ class SmallVectorImpl : public SmallVectorTemplateBase {
 iterator S = const_cast(CS);
 iterator E = const_cast(CE);
 
-assert(S >= this->begin() && "Range to erase is out of bounds.");
-assert(S <= E && "Trying to erase invalid range.");
-assert(E <= this->end() && "Trying to erase past the end.");
+assert(this->isRangeInStorage(S, E) && "Range to erase is out of bounds.");
 
 iterator N = S;
 // Shift all elts down.
@@ -615,8 +633,7 @@ class SmallVectorImpl : public SmallVectorTemplateBase {
   return this->end()-1;
 }
 
-assert(I >= this->begin() && "Insertion iterator is out of bounds.");
-assert(I <= this->end() && "Inserting past the end of the vector.");
+assert(this->isReferenceToStorage(I) && "Insertion iterator is out of 
bounds.");
 
 // Check that adding an element won't invalidate Elt.
 this->assertSafeToAdd(&Elt);
@@ -635,7 +652,7 @@ class SmallVectorImpl : public SmallVectorTemplateBase {
 // If we just moved the element we're inserting, be sure to update
 // the reference.
 std::remove_reference_t *EltPtr = &Elt;
-if (I <= EltPtr && EltPtr < this->end())
+if (this->isReferenceToRange(EltPtr, I, this->end()))
   ++EltPtr;
 
 *I = ::std::forward(*EltPtr);
@@ -658,8 +675,7 @@ class SmallVectorImpl : public SmallVectorTemplateBase {
   return this->begin()+InsertElt;
 }
 
-assert(I >= this->begin() && "Insertion iterator is out of bounds.");
-assert(I <= this->end() && "Inserting past the end of the vector.");
+assert(this->isReferenceToStorage(I) && "Insertion iterator is out of 
bounds.");
 
 // Check that adding NumToInsert elements won't invalidate Elt.
 this->assertSafeToAdd(&Elt, NumToInsert);
@@ -716,8 +732,7 @@ class SmallVectorImpl : public SmallVectorTemplateBase {
   return this->begin()+InsertElt;
 }
 
-assert(I >= this->begin() && "Insertion iterator is out of bounds.");
-assert(I <= this->end() && "Inserting past the end of the vector.");
+assert(this->isReferenceToStorage(I) && "Insertion iterator is out of 
bounds.");
 
 // Check that the re

[llvm-branch-commits] [llvm] 7470017 - [RISCV] Define the vfclass RVV intrinsics

[Evandro Menezes via llvm-branch-commits]

Author: Evandro Menezes
Date: 2021-01-11T17:40:09-06:00
New Revision: 7470017f2472411e8e03151b5016d612ac6648dd

URL: 
https://github.com/llvm/llvm-project/commit/7470017f2472411e8e03151b5016d612ac6648dd
DIFF: 
https://github.com/llvm/llvm-project/commit/7470017f2472411e8e03151b5016d612ac6648dd.diff

LOG: [RISCV] Define the vfclass RVV intrinsics

Define the `vfclass` IR intrinsics for the respective V instructions.

Authored-by: Roger Ferrer Ibanez 
Co-Authored-by: Evandro Menezes 

Differential Revision: https://reviews.llvm.org/D94356

Added: 
llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll

Modified: 
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Removed: 




diff  --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td 
b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index a28f8eb5ab08..8171be8a1ca8 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -299,7 +299,21 @@ let TargetPrefix = "riscv" in {
 [IntrNoMem]>, RISCVVIntrinsic {
 let ExtendOperand = 3;
   }
-
+  // For FP classify operations.
+  // Output: (bit mask type output)
+  // Input: (vector_in, vl)
+  class RISCVClassifyNoMask
+: Intrinsic<[LLVMVectorOfBitcastsToInt<0>],
+[llvm_anyvector_ty, llvm_anyint_ty],
+[IntrNoMem]>, RISCVVIntrinsic;
+  // For FP classify operations with mask.
+  // Output: (bit mask type output)
+  // Input: (maskedoff, vector_in, mask, vl)
+  class RISCVClassifyMask
+: Intrinsic<[LLVMVectorOfBitcastsToInt<0>],
+[LLVMVectorOfBitcastsToInt<0>, llvm_anyvector_ty,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, 
llvm_anyint_ty],
+[IntrNoMem]>, RISCVVIntrinsic;
   // For Saturating binary operations.
   // The destination vector type is the same as first source vector.
   // Input: (vector_in, vector_in/scalar_in, vl)
@@ -485,6 +499,10 @@ let TargetPrefix = "riscv" in {
 def "int_riscv_" # NAME : RISCVUnaryAANoMask;
 def "int_riscv_" # NAME # "_mask" : RISCVUnaryAAMask;
   }
+  multiclass RISCVUnaryAB {
+def "int_riscv_" # NAME : RISCVUnaryABNoMask;
+def "int_riscv_" # NAME # "_mask" : RISCVUnaryABMask;
+  }
   // AAX means the destination type(A) is the same as the first source
   // type(A). X means any type for the second source operand.
   multiclass RISCVBinaryAAX {
@@ -526,6 +544,10 @@ let TargetPrefix = "riscv" in {
 def "int_riscv_" # NAME : RISCVCompareNoMask;
 def "int_riscv_" # NAME # "_mask" : RISCVCompareMask;
   }
+  multiclass RISCVClassify {
+def "int_riscv_" # NAME : RISCVClassifyNoMask;
+def "int_riscv_" # NAME # "_mask" : RISCVClassifyMask;
+  }
   multiclass RISCVTernaryWide {
 def "int_riscv_" # NAME : RISCVTernaryWideNoMask;
 def "int_riscv_" # NAME # "_mask" : RISCVTernaryWideMask;
@@ -538,10 +560,6 @@ let TargetPrefix = "riscv" in {
 def "int_riscv_" # NAME : RISCVMaskUnarySOutNoMask;
 def "int_riscv_" # NAME # "_mask" : RISCVMaskUnarySOutMask;
   }
-  multiclass RISCVUnaryAB {
-def "int_riscv_" # NAME : RISCVUnaryABNoMask;
-def "int_riscv_" # NAME # "_mask" : RISCVUnaryABMask;
-  }
   multiclass RISCVMaskUnaryMOut {
 def "int_riscv_" # NAME : RISCVUnaryNoMask;
 def "int_riscv_" # NAME # "_mask" : RISCVMaskUnaryMOutMask;
@@ -708,6 +726,8 @@ let TargetPrefix = "riscv" in {
   defm vfsgnjn : RISCVBinaryAAX;
   defm vfsgnjx : RISCVBinaryAAX;
 
+  defm vfclass : RISCVClassify;
+
   defm vfmerge : RISCVBinaryWithV0;
 
   defm vslideup : RISCVTernaryAAAX;

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 32d208046174..bf5ee06bce35 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2706,6 +2706,11 @@ defm PseudoVMFLE   : 
VPseudoBinaryM_VV_VX;
 defm PseudoVMFGT   : VPseudoBinaryM_VX;
 defm PseudoVMFGE   : VPseudoBinaryM_VX;
 
+//===--===//
+// 14.14. Vector Floating-Point Classify Instruction
+//===--===//
+defm PseudoVFCLASS : VPseudoUnaryV_V;
+
 
//===--===//
 // 14.15. Vector Floating-Point Merge Instruction
 
//===--===//
@@ -2785,6 +2790,7 @@ defm PseudoVFREDMAX: VPseudoReductionV_VS;
 
//===--===//
 defm PseudoVFWREDSUM   : VPseudoReductionV_VS;
 defm PseudoVFWREDOSUM  : VPseudoReductionV_VS;
+
 } // Predicates = [HasStdExtV, HasStdExtF]
 
 
//===-