[llvm-branch-commits] [llvm-branch] r259206 - Merging r257666:
Author: tstellar
Date: Fri Jan 29 10:45:52 2016
New Revision: 259206
URL: http://llvm.org/viewvc/llvm-project?rev=259206&view=rev
Log:
Merging r257666:
r257666 | changpeng.fang | 2016-01-13 15:39:25 -0500 (Wed, 13 Jan 2016) | 2
lines
AMDGPU/SI: Update ISA version for FIJI
Modified:
llvm/branches/release_38/lib/Target/AMDGPU/AMDGPU.td
llvm/branches/release_38/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/branches/release_38/lib/Target/AMDGPU/Processors.td
llvm/branches/release_38/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/branches/release_38/test/CodeGen/AMDGPU/hsa-note-no-func.ll
Modified: llvm/branches/release_38/lib/Target/AMDGPU/AMDGPU.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/AMDGPU.td?rev=259206&r1=259205&r2=259206&view=diff
==
--- llvm/branches/release_38/lib/Target/AMDGPU/AMDGPU.td (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/AMDGPU.td Fri Jan 29 10:45:52
2016
@@ -183,6 +183,7 @@ def FeatureISAVersion7_0_0 : SubtargetFe
def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
+def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3>;
class SubtargetFeatureLocalMemorySize : SubtargetFeature<
"localmemorysize"#Value,
Modified: llvm/branches/release_38/lib/Target/AMDGPU/AMDGPUSubtarget.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=259206&r1=259205&r2=259206&view=diff
==
--- llvm/branches/release_38/lib/Target/AMDGPU/AMDGPUSubtarget.h (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/AMDGPUSubtarget.h Fri Jan 29
10:45:52 2016
@@ -53,7 +53,8 @@ public:
ISAVersion7_0_0,
ISAVersion7_0_1,
ISAVersion8_0_0,
-ISAVersion8_0_1
+ISAVersion8_0_1,
+ISAVersion8_0_3
};
private:
Modified: llvm/branches/release_38/lib/Target/AMDGPU/Processors.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/Processors.td?rev=259206&r1=259205&r2=259206&view=diff
==
--- llvm/branches/release_38/lib/Target/AMDGPU/Processors.td (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/Processors.td Fri Jan 29
10:45:52 2016
@@ -140,7 +140,7 @@ def : ProcessorModel<"carrizo", SIQuarte
>;
def : ProcessorModel<"fiji", SIQuarterSpeedModel,
- [FeatureVolcanicIslands, FeatureISAVersion8_0_1]
+ [FeatureVolcanicIslands, FeatureISAVersion8_0_3]
>;
def : ProcessorModel<"stoney", SIQuarterSpeedModel,
Modified: llvm/branches/release_38/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=259206&r1=259205&r2=259206&view=diff
==
--- llvm/branches/release_38/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
(original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Fri Jan
29 10:45:52 2016
@@ -41,6 +41,9 @@ IsaVersion getIsaVersion(const FeatureBi
if (Features.test(FeatureISAVersion8_0_1))
return {8, 0, 1};
+ if (Features.test(FeatureISAVersion8_0_3))
+return {8, 0, 3};
+
return {0, 0, 0};
}
Modified: llvm/branches/release_38/test/CodeGen/AMDGPU/hsa-note-no-func.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/AMDGPU/hsa-note-no-func.ll?rev=259206&r1=259205&r2=259206&view=diff
==
--- llvm/branches/release_38/test/CodeGen/AMDGPU/hsa-note-no-func.ll (original)
+++ llvm/branches/release_38/test/CodeGen/AMDGPU/hsa-note-no-func.ll Fri Jan 29
10:45:52 2016
@@ -1,6 +1,8 @@
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck
--check-prefix=HSA --check-prefix=HSA-CI %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck
--check-prefix=HSA --check-prefix=HSA-VI %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji | FileCheck
--check-prefix=HSA --check-prefix=HSA-FIJI %s
; HSA: .hsa_code_object_version 1,0
; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
+; HSA-FIJI: .hsa_code_object_isa 8,0,3,"AMD","AMDGPU"
___
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[llvm-branch-commits] [llvm-branch] r259207 - Merging r258922:
Author: tstellar
Date: Fri Jan 29 10:45:55 2016
New Revision: 259207
URL: http://llvm.org/viewvc/llvm-project?rev=259207&view=rev
Log:
Merging r258922:
r258922 | marek.olsak | 2016-01-27 06:19:45 -0500 (Wed, 27 Jan 2016) |
12 lines
AMDGPU/SI: Stoney has only 16 LDS banks
Summary:
This is a candidate for stable, along with all patches that add the
"stoney"
processor.
Reviewers: tstellarAMD
Subscribers: arsenm
Differential Revision: http://reviews.llvm.org/D16485
Modified:
llvm/branches/release_38/lib/Target/AMDGPU/AMDGPU.td
llvm/branches/release_38/lib/Target/AMDGPU/Processors.td
llvm/branches/release_38/test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll
Modified: llvm/branches/release_38/lib/Target/AMDGPU/AMDGPU.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/AMDGPU.td?rev=259207&r1=259206&r2=259207&view=diff
==
--- llvm/branches/release_38/lib/Target/AMDGPU/AMDGPU.td (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/AMDGPU.td Fri Jan 29 10:45:55
2016
@@ -253,7 +253,7 @@ def FeatureSeaIslands : SubtargetFeature
def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
- FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
+ FeatureGCN3Encoding, FeatureCIInsts]>;
//===--===//
Modified: llvm/branches/release_38/lib/Target/AMDGPU/Processors.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/Processors.td?rev=259207&r1=259206&r2=259207&view=diff
==
--- llvm/branches/release_38/lib/Target/AMDGPU/Processors.td (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/Processors.td Fri Jan 29
10:45:55 2016
@@ -128,21 +128,23 @@ def : ProcessorModel<"mullins",SIQua
//===--===//
def : ProcessorModel<"tonga", SIQuarterSpeedModel,
- [FeatureVolcanicIslands, FeatureSGPRInitBug, FeatureISAVersion8_0_0]
+ [FeatureVolcanicIslands, FeatureSGPRInitBug, FeatureISAVersion8_0_0,
+ FeatureLDSBankCount32]
>;
def : ProcessorModel<"iceland", SIQuarterSpeedModel,
- [FeatureVolcanicIslands, FeatureSGPRInitBug, FeatureISAVersion8_0_0]
+ [FeatureVolcanicIslands, FeatureSGPRInitBug, FeatureISAVersion8_0_0,
+ FeatureLDSBankCount32]
>;
def : ProcessorModel<"carrizo", SIQuarterSpeedModel,
- [FeatureVolcanicIslands, FeatureISAVersion8_0_1]
+ [FeatureVolcanicIslands, FeatureISAVersion8_0_1, FeatureLDSBankCount32]
>;
def : ProcessorModel<"fiji", SIQuarterSpeedModel,
- [FeatureVolcanicIslands, FeatureISAVersion8_0_3]
+ [FeatureVolcanicIslands, FeatureISAVersion8_0_3, FeatureLDSBankCount32]
>;
def : ProcessorModel<"stoney", SIQuarterSpeedModel,
- [FeatureVolcanicIslands, FeatureISAVersion8_0_1]
+ [FeatureVolcanicIslands, FeatureISAVersion8_0_1, FeatureLDSBankCount16]
>;
Modified: llvm/branches/release_38/test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll?rev=259207&r1=259206&r2=259207&view=diff
==
--- llvm/branches/release_38/test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll (original)
+++ llvm/branches/release_38/test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll Fri Jan
29 10:45:55 2016
@@ -1,5 +1,6 @@
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck
--check-prefix=GCN %s
;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck
--check-prefix=GCN --check-prefix=16BANK %s
+;RUN: llc < %s -march=amdgcn -mcpu=stoney -verify-machineinstrs | FileCheck
--check-prefix=GCN --check-prefix=16BANK %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck
--check-prefix=GCN %s
;GCN-LABEL: {{^}}main:
___
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[llvm-branch-commits] [lldb] r259241 - Merging r259188:
Author: hans
Date: Fri Jan 29 15:01:49 2016
New Revision: 259241
URL: http://llvm.org/viewvc/llvm-project?rev=259241&view=rev
Log:
Merging r259188:
r259188 | labath | 2016-01-29 03:59:57 -0800 (Fri, 29 Jan 2016) | 17 lines
Fix linking of lldb-server with BUILD_SHARED_LIBS
Summary:
The BUILD_SHARED_LIBS branch of lldb-server link flags was hopelessly broken,
at least since we
started restricting the symbols exported by liblldb. lldb-server depends on
symbols from the
lldb_private namespace, so it cannot link to the public interface of liblldb.
Instead I make it
link to the individual libraries constituting liblldb, just like it does in the
!BUILD_SHARED_LIBS case.
This does not make the BUILD_SHARED_LIBS build of lldb fully functional yet,
due to the way
liblldb dependencies are managed, but it's a step in that direction.
Reviewers: zturner, tfiala
Subscribers: lldb-commits
Differential Revision: http://reviews.llvm.org/D16678
Modified:
lldb/branches/release_38/ (props changed)
lldb/branches/release_38/tools/lldb-server/CMakeLists.txt
Propchange: lldb/branches/release_38/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Jan 29 15:01:49 2016
@@ -1,3 +1,3 @@
/lldb/branches/apple/python-GIL:156467-162159
/lldb/branches/iohandler:198360-200250
-/lldb/trunk:257691-257692
+/lldb/trunk:257691-257692,259188
Modified: lldb/branches/release_38/tools/lldb-server/CMakeLists.txt
URL:
http://llvm.org/viewvc/llvm-project/lldb/branches/release_38/tools/lldb-server/CMakeLists.txt?rev=259241&r1=259240&r2=259241&view=diff
==
--- lldb/branches/release_38/tools/lldb-server/CMakeLists.txt (original)
+++ lldb/branches/release_38/tools/lldb-server/CMakeLists.txt Fri Jan 29
15:01:49 2016
@@ -33,24 +33,19 @@ add_lldb_executable(lldb-server
LLDBServerUtilities.cpp
)
-if (BUILD_SHARED_LIBS )
- target_link_libraries(lldb-server liblldb)
- target_link_libraries(lldb-server ${LLDB_SYSTEM_LIBS})
+# The Darwin linker doesn't understand --start-group/--end-group.
+if (LLDB_LINKER_SUPPORTS_GROUPS)
+ target_link_libraries(lldb-server
+-Wl,--start-group ${LLDB_USED_LIBS} -Wl,--end-group)
+ target_link_libraries(lldb-server
+-Wl,--start-group ${CLANG_USED_LIBS} -Wl,--end-group)
else()
- # The Darwin linker doesn't understand --start-group/--end-group.
- if (LLDB_LINKER_SUPPORTS_GROUPS)
-target_link_libraries(lldb-server
- -Wl,--start-group ${LLDB_USED_LIBS} -Wl,--end-group)
-target_link_libraries(lldb-server
- -Wl,--start-group ${CLANG_USED_LIBS} -Wl,--end-group)
- else()
-target_link_libraries(lldb-server ${LLDB_USED_LIBS})
-target_link_libraries(lldb-server ${CLANG_USED_LIBS})
- endif()
- llvm_config(lldb-server ${LLVM_LINK_COMPONENTS})
-
- target_link_libraries(lldb-server ${LLDB_SYSTEM_LIBS})
+ target_link_libraries(lldb-server ${LLDB_USED_LIBS})
+ target_link_libraries(lldb-server ${CLANG_USED_LIBS})
endif()
+llvm_config(lldb-server ${LLVM_LINK_COMPONENTS})
+
+target_link_libraries(lldb-server ${LLDB_SYSTEM_LIBS})
set_target_properties(lldb-server PROPERTIES VERSION ${LLDB_VERSION})
___
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[llvm-branch-commits] [llvm-branch] r259245 - Merging r259236:
Author: hans
Date: Fri Jan 29 15:33:02 2016
New Revision: 259245
URL: http://llvm.org/viewvc/llvm-project?rev=259245&view=rev
Log:
Merging r259236:
r259236 | spatel | 2016-01-29 12:21:02 -0800 (Fri, 29 Jan 2016) | 8 lines
[InstCombine] avoid an insertelement transformation that induces the opposite
extractelement fold (PR26354)
We would infinite loop because we created a shufflevector that was wider than
needed and then failed to combine that with the insertelement. When subsequently
visiting the extractelement from that shuffle, we see that it's unnecessary,
delete it, and trigger another visit to the insertelement.
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
llvm/branches/release_38/test/Transforms/InstCombine/insert-extract-shuffle.ll
Propchange: llvm/branches/release_38/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Jan 29 15:33:02 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971,259236
Modified:
llvm/branches/release_38/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Transforms/InstCombine/InstCombineVectorOps.cpp?rev=259245&r1=259244&r2=259245&view=diff
==
---
llvm/branches/release_38/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
(original)
+++
llvm/branches/release_38/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
Fri Jan 29 15:33:02 2016
@@ -380,6 +380,23 @@ static void replaceExtractElements(Inser
ExtendMask.push_back(UndefValue::get(IntType));
Value *ExtVecOp = ExtElt->getVectorOperand();
+ auto *ExtVecOpInst = dyn_cast(ExtVecOp);
+ BasicBlock *InsertionBlock = (ExtVecOpInst && !isa(ExtVecOpInst))
+ ? ExtVecOpInst->getParent()
+ : ExtElt->getParent();
+
+ // TODO: This restriction matches the basic block check below when creating
+ // new extractelement instructions. If that limitation is removed, this one
+ // could also be removed. But for now, we just bail out to ensure that we
+ // will replace the extractelement instruction that is feeding our
+ // insertelement instruction. This allows the insertelement to then be
+ // replaced by a shufflevector. If the insertelement is not replaced, we can
+ // induce infinite looping because there's an optimization for extractelement
+ // that will delete our widening shuffle. This would trigger another attempt
+ // here to create that shuffle, and we spin forever.
+ if (InsertionBlock != InsElt->getParent())
+return;
+
auto *WideVec = new ShuffleVectorInst(ExtVecOp, UndefValue::get(ExtVecType),
ConstantVector::get(ExtendMask));
@@ -387,7 +404,6 @@ static void replaceExtractElements(Inser
// (as long as it's not a PHI) or at the start of the basic block of the
// extract, so any subsequent extracts in the same basic block can use it.
// TODO: Insert before the earliest ExtractElementInst that is replaced.
- auto *ExtVecOpInst = dyn_cast(ExtVecOp);
if (ExtVecOpInst && !isa(ExtVecOpInst))
WideVec->insertAfter(ExtVecOpInst);
else
Modified:
llvm/branches/release_38/test/Transforms/InstCombine/insert-extract-shuffle.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Transforms/InstCombine/insert-extract-shuffle.ll?rev=259245&r1=259244&r2=259245&view=diff
==
---
llvm/branches/release_38/test/Transforms/InstCombine/insert-extract-shuffle.ll
(original)
+++
llvm/branches/release_38/test/Transforms/InstCombine/insert-extract-shuffle.ll
Fri Jan 29 15:33:02 2016
@@ -175,3 +175,33 @@ bb3:
ret <4 x double> %tmp4
}
+; PR26354: https://llvm.org/bugs/show_bug.cgi?id=26354
+; Don't create a shufflevector if we know that we're not going to replace the
insertelement.
+
+define double @pr26354(<2 x double>* %tmp, i1 %B) {
+; CHECK-LABEL: @pr26354(
+; CHECK: %ld = load <2 x double>, <2 x double>* %tmp
+; CHECK-NEXT: %e1 = extractelement <2 x double> %ld, i32 0
[llvm-branch-commits] [llvm-branch] r259247 - Merging r259228:
Author: tnorthover
Date: Fri Jan 29 16:00:06 2016
New Revision: 259247
URL: http://llvm.org/viewvc/llvm-project?rev=259247&view=rev
Log:
Merging r259228:
r259228 | tnorthover | 2016-01-29 11:18:46 -0800 (Fri, 29 Jan 2016) | 13 lines
ARM: don't mangle DAG constant if it has more than one use
The basic optimisation was to convert (mul $LHS, $complex_constant) into
roughly "(shl (mul $LHS, $simple_constant), $simple_amt)" when it was expected
to be cheaper. The original logic checks that the mul only has one use (since
we're mangling $complex_constant), but when used in even more complex
addressing modes there may be an outer addition that can pick up the wrong
value too.
I *think* the ARM addressing-mode problem is actually unreachable at the
moment, but that depends on complex assessments of the profitability of
pre-increment addressing modes so I've put a real check in there instead of an
assertion.
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/branches/release_38/test/CodeGen/ARM/shifter_operand.ll
Propchange: llvm/branches/release_38/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Jan 29 16:00:06 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971,259236
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971,259228,259236
Modified: llvm/branches/release_38/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=259247&r1=259246&r2=259247&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Jan 29
16:00:06 2016
@@ -747,7 +747,7 @@ bool ARMDAGToDAGISel::SelectLdStSOReg(SD
// If Offset is a multiply-by-constant and it's profitable to extract a shift
// and use it in a shifted operand do so.
- if (Offset.getOpcode() == ISD::MUL) {
+ if (Offset.getOpcode() == ISD::MUL && N.hasOneUse()) {
unsigned PowerOfTwo = 0;
SDValue NewMulConst;
if (canExtractShiftFromMul(Offset, 31, PowerOfTwo, NewMulConst)) {
@@ -1422,7 +1422,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSo
// If OffReg is a multiply-by-constant and it's profitable to extract a shift
// and use it in a shifted operand do so.
- if (OffReg.getOpcode() == ISD::MUL) {
+ if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) {
unsigned PowerOfTwo = 0;
SDValue NewMulConst;
if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) {
Modified: llvm/branches/release_38/test/CodeGen/ARM/shifter_operand.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/ARM/shifter_operand.ll?rev=259247&r1=259246&r2=259247&view=diff
==
--- llvm/branches/release_38/test/CodeGen/ARM/shifter_operand.ll (original)
+++ llvm/branches/release_38/test/CodeGen/ARM/shifter_operand.ll Fri Jan 29
16:00:06 2016
@@ -239,3 +239,20 @@ define void @test_well_formed_dag(i32 %i
store i32 %add, i32* %addr
ret void
}
+
+define { i32, i32 } @test_multi_use_add(i32 %base, i32 %offset) {
+; CHECK-LABEL: test_multi_use_add:
+; CHECK-THUMB: movs [[CONST:r[0-9]+]], #28
+; CHECK-THUMB: movt [[CONST]], #1
+
+ %prod = mul i32 %offset, 65564
+ %sum = add i32 %base, %prod
+
+ %ptr = inttoptr i32 %sum to i32*
+ %loaded = load i32, i32* %ptr
+
+ %ret.tmp = insertvalue { i32, i32 } undef, i32 %sum, 0
+ %ret = insertvalue { i32, i32 } %ret.tmp, i32 %loaded, 1
+
+ ret { i32, i32 } %ret
+}
___
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