Author: tnorthover
Date: Fri Jan 29 16:00:06 2016
New Revision: 259247
URL: http://llvm.org/viewvc/llvm-project?rev=259247&view=rev
Log:
Merging r259228:
------------------------------------------------------------------------
r259228 | tnorthover | 2016-01-29 11:18:46 -0800 (Fri, 29 Jan 2016) | 13 lines
ARM: don't mangle DAG constant if it has more than one use
The basic optimisation was to convert (mul $LHS, $complex_constant) into
roughly "(shl (mul $LHS, $simple_constant), $simple_amt)" when it was expected
to be cheaper. The original logic checks that the mul only has one use (since
we're mangling $complex_constant), but when used in even more complex
addressing modes there may be an outer addition that can pick up the wrong
value too.
I *think* the ARM addressing-mode problem is actually unreachable at the
moment, but that depends on complex assessments of the profitability of
pre-increment addressing modes so I've put a real check in there instead of an
assertion.
------------------------------------------------------------------------
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/branches/release_38/test/CodeGen/ARM/shifter_operand.ll
Propchange: llvm/branches/release_38/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Jan 29 16:00:06 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971,259236
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971,259228,259236
Modified: llvm/branches/release_38/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=259247&r1=259246&r2=259247&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Jan 29
16:00:06 2016
@@ -747,7 +747,7 @@ bool ARMDAGToDAGISel::SelectLdStSOReg(SD
// If Offset is a multiply-by-constant and it's profitable to extract a shift
// and use it in a shifted operand do so.
- if (Offset.getOpcode() == ISD::MUL) {
+ if (Offset.getOpcode() == ISD::MUL && N.hasOneUse()) {
unsigned PowerOfTwo = 0;
SDValue NewMulConst;
if (canExtractShiftFromMul(Offset, 31, PowerOfTwo, NewMulConst)) {
@@ -1422,7 +1422,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSo
// If OffReg is a multiply-by-constant and it's profitable to extract a shift
// and use it in a shifted operand do so.
- if (OffReg.getOpcode() == ISD::MUL) {
+ if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) {
unsigned PowerOfTwo = 0;
SDValue NewMulConst;
if (canExtractShiftFromMul(OffReg, 3, PowerOfTwo, NewMulConst)) {
Modified: llvm/branches/release_38/test/CodeGen/ARM/shifter_operand.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/ARM/shifter_operand.ll?rev=259247&r1=259246&r2=259247&view=diff
==============================================================================
--- llvm/branches/release_38/test/CodeGen/ARM/shifter_operand.ll (original)
+++ llvm/branches/release_38/test/CodeGen/ARM/shifter_operand.ll Fri Jan 29
16:00:06 2016
@@ -239,3 +239,20 @@ define void @test_well_formed_dag(i32 %i
store i32 %add, i32* %addr
ret void
}
+
+define { i32, i32 } @test_multi_use_add(i32 %base, i32 %offset) {
+; CHECK-LABEL: test_multi_use_add:
+; CHECK-THUMB: movs [[CONST:r[0-9]+]], #28
+; CHECK-THUMB: movt [[CONST]], #1
+
+ %prod = mul i32 %offset, 65564
+ %sum = add i32 %base, %prod
+
+ %ptr = inttoptr i32 %sum to i32*
+ %loaded = load i32, i32* %ptr
+
+ %ret.tmp = insertvalue { i32, i32 } undef, i32 %sum, 0
+ %ret = insertvalue { i32, i32 } %ret.tmp, i32 %loaded, 1
+
+ ret { i32, i32 } %ret
+}
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