[Lldb-commits] [clang] [lldb] [HLSL] Implement intangible AST type (PR #97362)

[Xiang Li via lldb-commits]

@@ -2241,6 +2247,11 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T) 
const {
 Align = ALIGN; 
\
 break;
 #include "clang/Basic/AMDGPUTypes.def"
+#define HLSL_INTANGIBLE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/HLSLIntangibleTypes.def"
+  Width = 0;

python3kgae wrote:

Why the Width is 0?


https://github.com/llvm/llvm-project/pull/97362
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[Lldb-commits] [clang] [lldb] [HLSL] Implement intangible AST type (PR #97362)

[Xiang Li via lldb-commits]

@@ -757,7 +757,8 @@ void USRGenerator::VisitType(QualType T) {
 case BuiltinType::OCLReserveID:
   Out << "@BT@OCLReserveID"; break;
 case BuiltinType::OCLSampler:
-  Out << "@BT@OCLSampler"; break;
+  Out << "@BT@OCLSampler";
+  break;

python3kgae wrote:

Is this expected?

https://github.com/llvm/llvm-project/pull/97362
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[Lldb-commits] [clang] [lldb] [HLSL] Implement intangible AST type (PR #97362)

[Xiang Li via lldb-commits]

@@ -1390,7 +1390,8 @@ void ASTContext::InitBuiltinTypes(const TargetInfo 
&Target,
 #include "clang/Basic/HLSLIntangibleTypes.def"
   }
 
-  if (Target.hasAArch64SVETypes()) {
+  if (Target.hasAArch64SVETypes() ||

python3kgae wrote:

Is this expected change for intangible AST type?

https://github.com/llvm/llvm-project/pull/97362
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