[Lldb-commits] [PATCH] D13282: [MIPS] Emulate microMIPS instructions
bhushan created this revision. bhushan added reviewers: clayborg, tberghammer. bhushan added subscribers: lldb-commits, nitesh.jain, mohit.bhakkad, sagar, jaydeep. bhushan set the repository for this revision to rL LLVM. This patch includes: 1. Emulation of prologue/epilogue and branch instructions for microMIPS. 2. Setting up alternate disassembler (to be used for microMIPS). So there will be two disassembler instances, one for microMIPS and other for MIPS. Appropriate disassembler will be used based on the address class of instruction address. 3. Some of the branch instructions does not have fixed sized delay slot, that means delay slot instruction can be of 2-byte or 4-byte. For this "m_next_inst_size" has been introduced which stores the size of next instruction (i.e size of delay slot instruction in case of branch). This can be used wherever the size of next instruction is required. 4. A minor change to use mips32 register names instead of mips64 names. Repository: rL LLVM http://reviews.llvm.org/D13282 Files: source/Plugins/ABI/SysV-mips/ABISysV_mips.h source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h Index: source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h === --- source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h +++ source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h @@ -91,7 +91,12 @@ virtual bool EvaluateInstruction (uint32_t evaluate_options); - + +bool +SetInstruction (const lldb_private::Opcode &insn_opcode, +const lldb_private::Address &inst_addr, +lldb_private::Target *target) override; + virtual bool TestEmulation (lldb_private::Stream *out_stream, lldb_private::ArchSpec &arch, @@ -121,6 +126,9 @@ static MipsOpcode* GetOpcodeForInstruction (const char *op_name); +uint32_t +GetSizeOfInstruction (lldb_private::DataExtractor& data, uint64_t inst_addr); + bool Emulate_ADDiu (llvm::MCInst& insn); @@ -131,6 +139,27 @@ Emulate_LW (llvm::MCInst& insn); bool +Emulate_ADDIUSP (llvm::MCInst& insn); + +bool +Emulate_ADDIUS5 (llvm::MCInst& insn); + +bool +Emulate_SWSP (llvm::MCInst& insn); + +bool +Emulate_SWM16_32 (llvm::MCInst& insn); + +bool +Emulate_LWSP (llvm::MCInst& insn); + +bool +Emulate_LWM16_32 (llvm::MCInst& insn); + +bool +Emulate_JRADDIUSP (llvm::MCInst& insn); + +bool Emulate_LDST_Imm (llvm::MCInst& insn); bool @@ -338,18 +367,37 @@ Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz); bool +Emulate_B16_MM (llvm::MCInst& insn); + +bool +Emulate_Branch_MM (llvm::MCInst& insn); + +bool +Emulate_JALRx16_MM (llvm::MCInst& insn); + +bool +Emulate_JALx (llvm::MCInst& insn); + +bool +Emulate_JALRS (llvm::MCInst& insn); + +bool nonvolatile_reg_p (uint32_t regnum); const char * GetRegisterName (unsigned reg_num, bool altnernate_name); private: std::unique_ptr m_disasm; +std::unique_ptr m_alt_disasm; std::unique_ptr m_subtype_info; +std::unique_ptr m_alt_subtype_info; std::unique_ptr m_reg_info; std::unique_ptrm_asm_info; std::unique_ptrm_context; std::unique_ptr m_insn_info; +uint32_tm_next_inst_size; +boolm_use_alt_disaasm; }; #endif // EmulateInstructionMIPS_h_ Index: source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp === --- source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp +++ source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp @@ -29,6 +29,7 @@ #include "lldb/Core/DataExtractor.h" #include "lldb/Core/Stream.h" #include "lldb/Symbol/UnwindPlan.h" +#include "lldb/Target/Target.h" #include "llvm/ADT/STLExtras.h" @@ -132,10 +133,6 @@ features += "+dsp,"; if (arch_flags & ArchSpec::eMIPSAse_dspr2) features += "+dspr2,"; -if (arch_flags & ArchSpec::eMIPSAse_mips16) -features += "+mips16,"; -if (arch_flags & ArchSpec::eMIPSAse_micromips) -features += "+micromips,"; m_reg_info.reset (target->createMCRegInfo (triple.getTriple())); assert (m_reg_info.get()); @@ -152,6 +149,21 @@ m_disasm.reset (target->createMCDisassembler (*m_subtype_info, *m_context)); assert (m_disasm.get()); + +/* Create alternate disassembler for microMIPS */ +if (arch_flags & ArchSpec::eMIPSAse_mips16) +features += "+mips16,"; +else if (arch_flags & ArchSpec::eMIPSAse_micromips) +features += "+micromips,"; + +m_alt_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, features)); +assert (m_alt_subtype_info.get()); +
Re: [Lldb-commits] [PATCH] D12184: [MIPS] Avoid breakpoint in delay slot
bhushan closed this revision. bhushan added a comment. Closed by commit http://reviews.llvm.org/rL246015 Repository: rL LLVM http://reviews.llvm.org/D12184 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D14111: Use "_$" prefix instead of "$" for dynamic checker function inserted by LLDB during expression evaluation
bhushan created this revision.
bhushan added a reviewer: clayborg.
bhushan added subscribers: nitesh.jain, sagar, mohit.bhakkad, jaydeep,
lldb-commits.
bhushan set the repository for this revision to rL LLVM.
There is a issue (llvm assertion) in evaluating expressions for MIPS on Linux.
(lldb) p fooptr(a,b)
lldb: /home/battarde/git/llvm/lib/MC/ELFObjectWriter.cpp:791: void
{anonymous}::ELFObjectWriter::computeSymbolTable(llvm::MCAssembler&, const
llvm::MCAsmLayout&, const SectionIndexMapTy&, const RevGroupMapTy&,
{anonymous}::ELFObjectWriter::SectionOffsetsTy&): Assertion `Local ||
!Symbol.isTemporary()' failed.
This issue is caused due to the dynamic checker function’s name (hard-coded in
LLDB in lldb\source\Expression\IRDynamicChecks.cpp) that start with “$” i.e
“$__lldb_valid_pointer_check”.
The symbol "$" has a special meaning for MIPS i.e it is marker for temporary
symbols for MIPS.
The discussion on lldb mailing list regarding this issue is at :
http://lists.llvm.org/pipermail/lldb-dev/2015-October/008692.html
This patch fixes this issue by using "_$" prefix instead of "$" in dymanic
checker function’s name.
-Bhushan
Repository:
rL LLVM
http://reviews.llvm.org/D14111
Files:
source/Expression/IRDynamicChecks.cpp
Index: source/Expression/IRDynamicChecks.cpp
===
--- source/Expression/IRDynamicChecks.cpp
+++ source/Expression/IRDynamicChecks.cpp
@@ -31,12 +31,12 @@
static char ID;
-#define VALID_POINTER_CHECK_NAME "$__lldb_valid_pointer_check"
+#define VALID_POINTER_CHECK_NAME "_$__lldb_valid_pointer_check"
#define VALID_OBJC_OBJECT_CHECK_NAME "$__lldb_objc_object_check"
static const char g_valid_pointer_check_text[] =
"extern \"C\" void\n"
-"$__lldb_valid_pointer_check (unsigned char *$__lldb_arg_ptr)\n"
+"_$__lldb_valid_pointer_check (unsigned char *$__lldb_arg_ptr)\n"
"{\n"
"unsigned char $__lldb_local_val = *$__lldb_arg_ptr;\n"
"}";
Index: source/Expression/IRDynamicChecks.cpp
===
--- source/Expression/IRDynamicChecks.cpp
+++ source/Expression/IRDynamicChecks.cpp
@@ -31,12 +31,12 @@
static char ID;
-#define VALID_POINTER_CHECK_NAME "$__lldb_valid_pointer_check"
+#define VALID_POINTER_CHECK_NAME "_$__lldb_valid_pointer_check"
#define VALID_OBJC_OBJECT_CHECK_NAME "$__lldb_objc_object_check"
static const char g_valid_pointer_check_text[] =
"extern \"C\" void\n"
-"$__lldb_valid_pointer_check (unsigned char *$__lldb_arg_ptr)\n"
+"_$__lldb_valid_pointer_check (unsigned char *$__lldb_arg_ptr)\n"
"{\n"
"unsigned char $__lldb_local_val = *$__lldb_arg_ptr;\n"
"}";
___
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lldb-commits@lists.llvm.org
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Re: [Lldb-commits] [PATCH] D14111: Use "_$" prefix instead of "$" for dynamic checker function inserted by LLDB during expression evaluation
bhushan added a comment. Hi Sean/Jim Could you please find some time to review this? Thanks. Repository: rL LLVM http://reviews.llvm.org/D14111 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D15273: [LLDB][MIPS] Handle PIC calling convention for MIPS32
bhushan created this revision.
bhushan added a reviewer: clayborg.
bhushan added subscribers: lldb-commits, nitesh.jain, sagar, mohit.bhakkad,
jaydeep.
bhushan set the repository for this revision to rL LLVM.
This patch includes:
1. PrepareTrivialCall() to setup register r25 with the address of function to
be called.
This is needed because the PIC calling convention for MIPS requires that on
entry to
a function, the r25 (t9) register holds the address of the function’s entry
point.
2. RegisterIsCalleeSaved() to use name of a register instead of its byte_offset.
Repository:
rL LLVM
http://reviews.llvm.org/D15273
Files:
source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
Index: source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
===
--- source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
+++ source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
@@ -241,6 +241,7 @@
const RegisterInfo *pc_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
const RegisterInfo *ra_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
+const RegisterInfo *r25_info = reg_ctx->GetRegisterInfoByName("r25", 0);
if (log)
log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
@@ -262,7 +263,14 @@
// Set pc to the address of the called function.
if (!reg_ctx->WriteRegisterFromUnsigned (pc_reg_info, func_addr))
return false;
-
+
+if (log)
+log->Printf("Writing r25: 0x%" PRIx64, (uint64_t)func_addr);
+
+// All callers of position independent functions must place the address of
the called function in t9 (r25)
+if (!reg_ctx->WriteRegisterFromUnsigned (r25_info, func_addr))
+return false;
+
return true;
}
@@ -546,13 +554,36 @@
{
// Preserved registers are :
// r16-r23, r28, r29, r30, r31
+const char *name = reg_info->name;
-int reg = ((reg_info->byte_offset) / 4);
-
-bool save = (reg >= 16) && (reg <= 23);
- save |= (reg >= 28) && (reg <= 31);
+if (name[0] == 'r')
+{
+switch (name[1])
+{
+case '1':
+if (name[2] == '6' || name[2] == '7' || name[2] == '8' ||
name[2] == '9') // r16-r19
+return name[3] == '\0';
+break;
+case '2':
+if (name[2] == '0' || name[2] == '1' || name[2] == '2' ||
name[2] == '3' // r20-r23
+|| name[2] == '8' || name[2] == '9')
// r28 and r29
+return name[3] == '\0';
+break;
+case '3':
+if (name[2] == '0' || name[2] == '1') // r30 and r31
+return name[3] == '\0';
+break;
+}
-return save;
+if (name[0] == 'g' && name[1] == 'p' && name[2] == '\0') // gp
(r28)
+return true;
+if (name[0] == 's' && name[1] == 'p' && name[2] == '\0') // sp
(r29)
+return true;
+if (name[0] == 'f' && name[1] == 'p' && name[2] == '\0') // fp
(r30)
+return true;
+if (name[0] == 'r' && name[1] == 'a' && name[2] == '\0') // ra
(r31)
+return true;
+}
}
return false;
}
Index: source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
===
--- source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
+++ source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
@@ -241,6 +241,7 @@
const RegisterInfo *pc_reg_info = reg_ctx->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
const RegisterInfo *ra_reg_info = reg_ctx->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
+const RegisterInfo *r25_info = reg_ctx->GetRegisterInfoByName("r25", 0);
if (log)
log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
@@ -262,7 +263,14 @@
// Set pc to the address of the called function.
if (!reg_ctx->WriteRegisterFromUnsigned (pc_reg_info, func_addr))
return false;
-
+
+if (log)
+log->Printf("Writing r25: 0x%" PRIx64, (uint64_t)func_addr);
+
+// All callers of position independent functions must place the address of the called function in t9 (r25)
+if (!reg_ctx->WriteRegisterFromUnsigned (r25_info, func_addr))
+return false;
+
return true;
}
@@ -546,13 +554,36 @@
{
// Preserved registers are :
// r16-r23, r28, r29, r30, r31
+const char *name = reg_info->name;
-int reg = ((reg_info->byte_offset) / 4);
-
-
Re: [Lldb-commits] [PATCH] D15273: [LLDB][MIPS] Handle PIC calling convention for MIPS32
bhushan closed this revision. bhushan added a comment. Closed by commit http://reviews.llvm.org/rL255005 Repository: rL LLVM http://reviews.llvm.org/D15273 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D21064: [LLDB][MIPS] Fix Emulation of Compact branch and ADDIU instructions
bhushan accepted this revision. bhushan added a comment. Looks good. Repository: rL LLVM http://reviews.llvm.org/D21064 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D22851: [LLDB][MIPS] Add (D)SUBU, (D)ADDU, LUI instructions emulation . Fix emulation for (D)ADDIU, SD/SW and LW/LD instructions
bhushan accepted this revision. bhushan added a comment. LGTM https://reviews.llvm.org/D22851 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] [Accepted] D24498: [LLDB][MIPS] Fix TestReturnValue failure for MIPS
bhushan accepted this revision. bhushan added a comment. This revision is now accepted and ready to land. Looks good as far as correctness is concerned. https://reviews.llvm.org/D24498 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] [Commented On] D13154: [MIPS] Use Address::GetAddressClass() instead of elf flags to decide address space of an address
bhushan added a comment. Hi Eugene, I did not commit this patch because @zturner had asked for a testcase for this change. But the test will require to build it for micromips target (-mmicromips option) and currently I don't have any micromips hardware available. I had tested this patch with simulator. I can rebase and commit it if @clayborg and @zturner agrees. Repository: rL LLVM https://reviews.llvm.org/D13154 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D13282: [MIPS] Emulate microMIPS instructions
bhushan closed this revision. bhushan added a comment. This was committed on 6th Oct 15 by http://reviews.llvm.org/rL249381 ,closing it now. Repository: rL LLVM http://reviews.llvm.org/D13282 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D15886: [LLDB][MIPS32]Merge emulation of similar instructions
bhushan created this revision.
bhushan added a reviewer: clayborg.
bhushan added subscribers: lldb-commits, nitesh.jain, mohit.bhakkad, sagar,
jaydeep.
bhushan set the repository for this revision to rL LLVM.
Herald added a subscriber: dsanders.
Currently there is a separate emulation function for each branch instruction,
however the emulation logic is almost identical for many of these instructions.
This patch merges emulation of similar instructions into a single function
(wherever possible) to remove code duplication.
Repository:
rL LLVM
http://reviews.llvm.org/D15886
Files:
source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
Index: source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
===
--- source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
+++ source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
@@ -160,121 +160,37 @@
Emulate_LDST_Reg (llvm::MCInst& insn);
bool
-Emulate_BEQ (llvm::MCInst& insn);
+Emulate_BXX_3ops (llvm::MCInst& insn);
bool
-Emulate_BNE (llvm::MCInst& insn);
+Emulate_BXX_3ops_C (llvm::MCInst& insn);
bool
-Emulate_BEQL (llvm::MCInst& insn);
+Emulate_BXX_2ops (llvm::MCInst& insn);
bool
-Emulate_BNEL (llvm::MCInst& insn);
+Emulate_BXX_2ops_C (llvm::MCInst& insn);
bool
-Emulate_BGEZALL (llvm::MCInst& insn);
+Emulate_Bcond_Link_C (llvm::MCInst& insn);
bool
-Emulate_BAL (llvm::MCInst& insn);
-
-bool
-Emulate_BGEZAL (llvm::MCInst& insn);
-
-bool
-Emulate_BALC (llvm::MCInst& insn);
-
-bool
-Emulate_BC (llvm::MCInst& insn);
-
-bool
-Emulate_BGEZ (llvm::MCInst& insn);
-
-bool
-Emulate_BLEZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BGEZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BGTZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BEQZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BNEZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BEQC (llvm::MCInst& insn);
-
-bool
-Emulate_BNEC (llvm::MCInst& insn);
-
-bool
-Emulate_BLTC (llvm::MCInst& insn);
-
-bool
-Emulate_BGEC (llvm::MCInst& insn);
-
-bool
-Emulate_BLTUC (llvm::MCInst& insn);
-
-bool
-Emulate_BGEUC (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZC (llvm::MCInst& insn);
-
-bool
-Emulate_BLEZC (llvm::MCInst& insn);
+Emulate_Bcond_Link (llvm::MCInst& insn);
bool
-Emulate_BGEZC (llvm::MCInst& insn);
+Emulate_FP_branch (llvm::MCInst& insn);
bool
-Emulate_BGTZC (llvm::MCInst& insn);
+Emulate_3D_branch (llvm::MCInst& insn);
bool
-Emulate_BEQZC (llvm::MCInst& insn);
-
-bool
-Emulate_BNEZC (llvm::MCInst& insn);
-
-bool
-Emulate_BGEZL (llvm::MCInst& insn);
-
-bool
-Emulate_BGTZ (llvm::MCInst& insn);
-
-bool
-Emulate_BGTZL (llvm::MCInst& insn);
-
-bool
-Emulate_BLEZ (llvm::MCInst& insn);
-
-bool
-Emulate_BLEZL (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZ (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZAL (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZALL (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZL (llvm::MCInst& insn);
+Emulate_BAL (llvm::MCInst& insn);
bool
-Emulate_BOVC (llvm::MCInst& insn);
+Emulate_BALC (llvm::MCInst& insn);
bool
-Emulate_BNVC (llvm::MCInst& insn);
+Emulate_BC (llvm::MCInst& insn);
bool
Emulate_J (llvm::MCInst& insn);
@@ -295,36 +211,12 @@
Emulate_JR (llvm::MCInst& insn);
bool
-Emulate_BC1F (llvm::MCInst& insn);
-
-bool
-Emulate_BC1T (llvm::MCInst& insn);
-
-bool
-Emulate_BC1FL (llvm::MCInst& insn);
-
-bool
-Emulate_BC1TL (llvm::MCInst& insn);
-
-bool
Emulate_BC1EQZ (llvm::MCInst& insn);
bool
Emulate_BC1NEZ (llvm::MCInst& insn);
bool
-Emulate_BC1ANY2F (llvm::MCInst& insn);
-
-bool
-Emulate_BC1ANY2T (llvm::MCInst& insn);
-
-bool
-Emulate_BC1ANY4F (llvm::MCInst& insn);
-
-bool
-Emulate_BC1ANY4T (llvm::MCInst& insn);
-
-bool
Emulate_BNZB (llvm::MCInst& insn);
bool
Index: source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
===
--- source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
+++ source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
@@ -591,45 +591,45 @@
//--
// Branch instructions
//--
-{ "BEQ",&EmulateInstructionMIPS::Emulate_BEQ, "BEQ rs,rt,offset" },
-{ "BNE",&EmulateInstructionMIPS::Emulate_BNE, "BNE rs,rt,offset" },
-{ "BEQL"
Re: [Lldb-commits] [PATCH] D15886: [LLDB][MIPS32]Merge emulation of similar instructions
bhushan closed this revision. bhushan added a comment. Closed by commit http://reviews.llvm.org/rL256915 Repository: rL LLVM http://reviews.llvm.org/D15886 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D15886: [LLDB][MIPS32]Merge emulation of similar instructions
bhushan added a comment. Hi Pavel, Could you please confirm if http://reviews.llvm.org/rL256929 resolves the build warnings? Repository: rL LLVM http://reviews.llvm.org/D15886 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D16046: [LLDB][MIPS] Handle PIC calling convention for MIPS64
bhushan created this revision.
bhushan added a reviewer: clayborg.
bhushan added subscribers: lldb-commits, nitesh.jain, mohit.bhakkad, sagar,
jaydeep.
bhushan set the repository for this revision to rL LLVM.
The PIC calling convention for MIPS requires that on entry to a function,
register r25 (t9) holds the address of the function’s entry point.
This patch sets up register r25 with the address of function to be called in
PrepareTrivialCall().
Repository:
rL LLVM
http://reviews.llvm.org/D16046
Files:
source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
Index: source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
===
--- source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
+++ source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
@@ -206,6 +206,7 @@
const RegisterInfo *pc_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
const RegisterInfo *ra_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
+const RegisterInfo *r25_info = reg_ctx->GetRegisterInfoByName("r25", 0);
if (log)
log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
@@ -228,6 +229,13 @@
if (!reg_ctx->WriteRegisterFromUnsigned (pc_reg_info, func_addr))
return false;
+if (log)
+log->Printf("Writing r25: 0x%" PRIx64, (uint64_t)func_addr);
+
+// All callers of position independent functions must place the address of
the called function in t9 (r25)
+if (!reg_ctx->WriteRegisterFromUnsigned (r25_info, func_addr))
+return false;
+
return true;
}
Index: source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
===
--- source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
+++ source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
@@ -206,6 +206,7 @@
const RegisterInfo *pc_reg_info = reg_ctx->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
const RegisterInfo *ra_reg_info = reg_ctx->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
+const RegisterInfo *r25_info = reg_ctx->GetRegisterInfoByName("r25", 0);
if (log)
log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
@@ -228,6 +229,13 @@
if (!reg_ctx->WriteRegisterFromUnsigned (pc_reg_info, func_addr))
return false;
+if (log)
+log->Printf("Writing r25: 0x%" PRIx64, (uint64_t)func_addr);
+
+// All callers of position independent functions must place the address of the called function in t9 (r25)
+if (!reg_ctx->WriteRegisterFromUnsigned (r25_info, func_addr))
+return false;
+
return true;
}
___
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[Lldb-commits] [PATCH] D16049: [LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
bhushan created this revision.
bhushan added a reviewer: clayborg.
bhushan added subscribers: lldb-commits, nitesh.jain, mohit.bhakkad, sagar,
jaydeep.
bhushan set the repository for this revision to rL LLVM.
Repository:
rL LLVM
http://reviews.llvm.org/D16049
Files:
source/Target/Target.cpp
Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2442,18 +2442,18 @@
SymbolContext sc;
uint32_t resolve_scope = eSymbolContextFunction |
eSymbolContextSymbol;
temp_addr_module_sp->ResolveSymbolContextForAddress(resolved_addr,
resolve_scope, sc);
+Address sym_addr;
if (sc.function)
-{
-function_start =
sc.function->GetAddressRange().GetBaseAddress().GetLoadAddress(this);
-if (function_start == LLDB_INVALID_ADDRESS)
-function_start =
sc.function->GetAddressRange().GetBaseAddress().GetFileAddress();
-}
+sym_addr = sc.function->GetAddressRange().GetBaseAddress();
else if (sc.symbol)
-{
-Address sym_addr = sc.symbol->GetAddress();
+sym_addr = sc.symbol->GetAddress();
+
+function_start = sym_addr.GetLoadAddress(this);
+if (function_start == LLDB_INVALID_ADDRESS)
function_start = sym_addr.GetFileAddress();
-}
-current_offset = addr - function_start;
+
+if (function_start)
+current_offset = addr - function_start;
}
// If breakpoint address is start of function then we dont have to do
anything.
Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2442,18 +2442,18 @@
SymbolContext sc;
uint32_t resolve_scope = eSymbolContextFunction | eSymbolContextSymbol;
temp_addr_module_sp->ResolveSymbolContextForAddress(resolved_addr, resolve_scope, sc);
+Address sym_addr;
if (sc.function)
-{
-function_start = sc.function->GetAddressRange().GetBaseAddress().GetLoadAddress(this);
-if (function_start == LLDB_INVALID_ADDRESS)
-function_start = sc.function->GetAddressRange().GetBaseAddress().GetFileAddress();
-}
+sym_addr = sc.function->GetAddressRange().GetBaseAddress();
else if (sc.symbol)
-{
-Address sym_addr = sc.symbol->GetAddress();
+sym_addr = sc.symbol->GetAddress();
+
+function_start = sym_addr.GetLoadAddress(this);
+if (function_start == LLDB_INVALID_ADDRESS)
function_start = sym_addr.GetFileAddress();
-}
-current_offset = addr - function_start;
+
+if (function_start)
+current_offset = addr - function_start;
}
// If breakpoint address is start of function then we dont have to do anything.
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Re: [Lldb-commits] [PATCH] D16049: [LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
bhushan added a comment. Summary: Get the load address for the address given by 'symbol' and 'function'. Earlier, this was done for 'function' only, this patch does it for 'symbol' too. Repository: rL LLVM http://reviews.llvm.org/D16049 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D16051: [LLDB][MIPS] Merge emulation of similar instructions for MIPS64
bhushan created this revision.
bhushan added a reviewer: clayborg.
bhushan added subscribers: lldb-commits, nitesh.jain, mohit.bhakkad, sagar,
jaydeep.
bhushan set the repository for this revision to rL LLVM.
Currently there is a separate emulation function for each branch instruction,
however the emulation logic is almost identical for many of these instructions.
This patch merges emulation of similar instructions into a single function
(wherever possible) to remove code duplication.
Repository:
rL LLVM
http://reviews.llvm.org/D16051
Files:
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
@@ -133,121 +133,37 @@
Emulate_LDST_Reg (llvm::MCInst& insn);
bool
-Emulate_BEQ (llvm::MCInst& insn);
+Emulate_BXX_3ops (llvm::MCInst& insn);
bool
-Emulate_BNE (llvm::MCInst& insn);
+Emulate_BXX_3ops_C (llvm::MCInst& insn);
bool
-Emulate_BEQL (llvm::MCInst& insn);
+Emulate_BXX_2ops (llvm::MCInst& insn);
bool
-Emulate_BNEL (llvm::MCInst& insn);
+Emulate_BXX_2ops_C (llvm::MCInst& insn);
bool
-Emulate_BGEZALL (llvm::MCInst& insn);
+Emulate_Bcond_Link_C (llvm::MCInst& insn);
bool
-Emulate_BAL (llvm::MCInst& insn);
-
-bool
-Emulate_BGEZAL (llvm::MCInst& insn);
-
-bool
-Emulate_BALC (llvm::MCInst& insn);
-
-bool
-Emulate_BC (llvm::MCInst& insn);
-
-bool
-Emulate_BGEZ (llvm::MCInst& insn);
-
-bool
-Emulate_BLEZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BGEZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BGTZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BEQZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BNEZALC (llvm::MCInst& insn);
-
-bool
-Emulate_BEQC (llvm::MCInst& insn);
-
-bool
-Emulate_BNEC (llvm::MCInst& insn);
-
-bool
-Emulate_BLTC (llvm::MCInst& insn);
-
-bool
-Emulate_BGEC (llvm::MCInst& insn);
-
-bool
-Emulate_BLTUC (llvm::MCInst& insn);
-
-bool
-Emulate_BGEUC (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZC (llvm::MCInst& insn);
-
-bool
-Emulate_BLEZC (llvm::MCInst& insn);
+Emulate_Bcond_Link (llvm::MCInst& insn);
bool
-Emulate_BGEZC (llvm::MCInst& insn);
+Emulate_FP_branch (llvm::MCInst& insn);
bool
-Emulate_BGTZC (llvm::MCInst& insn);
+Emulate_3D_branch (llvm::MCInst& insn);
bool
-Emulate_BEQZC (llvm::MCInst& insn);
-
-bool
-Emulate_BNEZC (llvm::MCInst& insn);
-
-bool
-Emulate_BGEZL (llvm::MCInst& insn);
-
-bool
-Emulate_BGTZ (llvm::MCInst& insn);
-
-bool
-Emulate_BGTZL (llvm::MCInst& insn);
-
-bool
-Emulate_BLEZ (llvm::MCInst& insn);
-
-bool
-Emulate_BLEZL (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZ (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZAL (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZALL (llvm::MCInst& insn);
-
-bool
-Emulate_BLTZL (llvm::MCInst& insn);
+Emulate_BAL (llvm::MCInst& insn);
bool
-Emulate_BOVC (llvm::MCInst& insn);
+Emulate_BALC (llvm::MCInst& insn);
bool
-Emulate_BNVC (llvm::MCInst& insn);
+Emulate_BC (llvm::MCInst& insn);
bool
Emulate_J (llvm::MCInst& insn);
@@ -268,36 +184,12 @@
Emulate_JR (llvm::MCInst& insn);
bool
-Emulate_BC1F (llvm::MCInst& insn);
-
-bool
-Emulate_BC1T (llvm::MCInst& insn);
-
-bool
-Emulate_BC1FL (llvm::MCInst& insn);
-
-bool
-Emulate_BC1TL (llvm::MCInst& insn);
-
-bool
Emulate_BC1EQZ (llvm::MCInst& insn);
bool
Emulate_BC1NEZ (llvm::MCInst& insn);
bool
-Emulate_BC1ANY2F (llvm::MCInst& insn);
-
-bool
-Emulate_BC1ANY2T (llvm::MCInst& insn);
-
-bool
-Emulate_BC1ANY4F (llvm::MCInst& insn);
-
-bool
-Emulate_BC1ANY4T (llvm::MCInst& insn);
-
-bool
Emulate_BNZB (llvm::MCInst& insn);
bool
Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -549,45 +549,45 @@
//--
// Branch instructions
//--
-{ "BEQ",&EmulateInstructionMIPS64::Emulate_BEQ, "BEQ rs,rt,offset" },
-{ "BNE",&EmulateInstructionMIPS64::Emulate_BNE, "BNE rs,rt,offset" },
-{ "BEQL",
Re: [Lldb-commits] [PATCH] D16051: [LLDB][MIPS] Merge emulation of similar instructions for MIPS64
bhushan closed this revision. bhushan added a comment. Closed by commit http://reviews.llvm.org/rL257442 Repository: rL LLVM http://reviews.llvm.org/D16051 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D16046: [LLDB][MIPS] Handle PIC calling convention for MIPS64
bhushan closed this revision. bhushan added a comment. Closed by commit http://reviews.llvm.org/rL257441 Repository: rL LLVM http://reviews.llvm.org/D16046 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D16049: [LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
bhushan updated this revision to Diff 44723.
bhushan added a comment.
This diff adds a testcase to test this patch.
The test gets all assembly instructions from the function and finds out the
address of instruction in delay slot.
Then it tries to place a breakpoint on that address and verifies if breakpoint
has been adjusted correctly.
The breakpoint should get placed on branch instruction instead of delay slot
instruction.
Repository:
rL LLVM
http://reviews.llvm.org/D16049
Files:
include/lldb/API/SBInstruction.h
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
packages/Python/lldbsuite/test/lldbtest.py
scripts/interface/SBInstruction.i
source/API/SBInstruction.cpp
Index: packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
@@ -0,0 +1,21 @@
+#include
+
+foo (int a, int b)
+{
+int c;
+if (a<=b)
+c=b-a;
+else
+c=b+a;
+return c;
+}
+
+int main()
+{
+int a=7, b=8, c;
+
+c = foo(a, b);
+
+return 0;
+}
+
Index: packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
@@ -0,0 +1,82 @@
+"""
+Test specific to MIPS
+"""
+
+import os, time
+import re
+import unittest2
+import lldb
+import lldbsuite.test.lldbutil as lldbutil
+from lldbsuite.test.lldbtest import *
+
+class AvoidBreakpointInDelaySlotAPITestCase(TestBase):
+
+mydir = TestBase.compute_mydir(__file__)
+
+@skipUnlessMips
+def test(self):
+self.build()
+exe = os.path.join(os.getcwd(), "a.out")
+self.expect("file " + exe,
+patterns = [ "Current executable set to .*a.out.*" ])
+
+# Create a target by the debugger.
+target = self.dbg.CreateTarget(exe)
+self.assertTrue(target, VALID_TARGET)
+
+breakpoint = target.BreakpointCreateByName('main', 'a.out')
+self.assertTrue(breakpoint and
+breakpoint.GetNumLocations() == 1,
+VALID_BREAKPOINT)
+
+# Now launch the process, and do not stop at entry point.
+process = target.LaunchSimple (None, None, self.get_process_working_directory())
+self.assertTrue(process, PROCESS_IS_VALID)
+
+list = target.FindFunctions('foo', lldb.eFunctionNameTypeAuto)
+self.assertTrue(list.GetSize() == 1)
+sc = list.GetContextAtIndex(0)
+self.assertTrue(sc.GetSymbol().GetName() == "foo")
+function = sc.GetFunction()
+self.assertTrue(function)
+self.function(function, target)
+
+def function (self, function, target):
+"""Iterate over instructions in function and place a breakpoint on delay slot instruction"""
+# Get the list of all instructions in the function
+insts = function.GetInstructions(target)
+print insts
+i = 0
+for inst in insts:
+if (inst.HasDelaySlot()):
+# Remember the address of branch instruction.
+branchinstaddress = inst.GetAddress().GetLoadAddress(target)
+
+# Get next instruction i.e delay slot instruction.
+delayinst = insts.GetInstructionAtIndex(i+1)
+delayinstaddr = delayinst.GetAddress().GetLoadAddress(target)
+
+# Set breakpoint on delay slot instruction
+breakpoint = target.BreakpointCreateByAddress(delayinstaddr)
+
+# Verify the breakpoint.
+self.assertTrue(breakpoint and
+breakpoint.GetNumLocations() == 1,
+VALID_BREAKPOINT)
+# Get the location from breakpoint
+location = breakpoint.GetLocationAtIndex(0)
+
+# Get the address where breakpoint is actually set.
+bpaddr = location.GetLoadAddress()
+
+# Breakpoint address should be adjusted to the address of branch instruction.
+self.assertTrue(branchinstaddress == bpaddr)
+i += 1
+else:
+i += 1
+
+if __name__ == '__main__':
+import atexit
+lldb.SBDebugger.Initialize()
+atexit.register(lambda: lldb.SBDebugger.Terminate())
+unittest2.main()
Index: packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
===
Re: [Lldb-commits] [PATCH] D16049: [LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
bhushan updated the summary for this revision.
bhushan added a reviewer: zturner.
bhushan updated this revision to Diff 44841.
bhushan added a comment.
Hi Zachary,
If we use @skipIf then the list would require to contain all possible MIPS
variations and the list will grow long.
for ex: @skipIf(archs=not_in(['mips32','mips32r2', 'mips32r3',
'mips64','mips64r2', 'mips64r3', 'mips64r6' ..]))
@skipUnlessMips covers all these possible values using regular expression
matching.
Repository:
rL LLVM
http://reviews.llvm.org/D16049
Files:
include/lldb/API/SBInstruction.h
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
packages/Python/lldbsuite/test/lldbtest.py
scripts/interface/SBInstruction.i
source/API/SBInstruction.cpp
source/Target/Target.cpp
Index: packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
@@ -0,0 +1,21 @@
+#include
+
+foo (int a, int b)
+{
+int c;
+if (a<=b)
+c=b-a;
+else
+c=b+a;
+return c;
+}
+
+int main()
+{
+int a=7, b=8, c;
+
+c = foo(a, b);
+
+return 0;
+}
+
Index: packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
@@ -0,0 +1,82 @@
+"""
+Test specific to MIPS
+"""
+
+import os, time
+import re
+import unittest2
+import lldb
+import lldbsuite.test.lldbutil as lldbutil
+from lldbsuite.test.lldbtest import *
+
+class AvoidBreakpointInDelaySlotAPITestCase(TestBase):
+
+mydir = TestBase.compute_mydir(__file__)
+
+@skipUnlessMips
+def test(self):
+self.build()
+exe = os.path.join(os.getcwd(), "a.out")
+self.expect("file " + exe,
+patterns = [ "Current executable set to .*a.out.*" ])
+
+# Create a target by the debugger.
+target = self.dbg.CreateTarget(exe)
+self.assertTrue(target, VALID_TARGET)
+
+breakpoint = target.BreakpointCreateByName('main', 'a.out')
+self.assertTrue(breakpoint and
+breakpoint.GetNumLocations() == 1,
+VALID_BREAKPOINT)
+
+# Now launch the process, and do not stop at entry point.
+process = target.LaunchSimple (None, None, self.get_process_working_directory())
+self.assertTrue(process, PROCESS_IS_VALID)
+
+list = target.FindFunctions('foo', lldb.eFunctionNameTypeAuto)
+self.assertTrue(list.GetSize() == 1)
+sc = list.GetContextAtIndex(0)
+self.assertTrue(sc.GetSymbol().GetName() == "foo")
+function = sc.GetFunction()
+self.assertTrue(function)
+self.function(function, target)
+
+def function (self, function, target):
+"""Iterate over instructions in function and place a breakpoint on delay slot instruction"""
+# Get the list of all instructions in the function
+insts = function.GetInstructions(target)
+print insts
+i = 0
+for inst in insts:
+if (inst.HasDelaySlot()):
+# Remember the address of branch instruction.
+branchinstaddress = inst.GetAddress().GetLoadAddress(target)
+
+# Get next instruction i.e delay slot instruction.
+delayinst = insts.GetInstructionAtIndex(i+1)
+delayinstaddr = delayinst.GetAddress().GetLoadAddress(target)
+
+# Set breakpoint on delay slot instruction
+breakpoint = target.BreakpointCreateByAddress(delayinstaddr)
+
+# Verify the breakpoint.
+self.assertTrue(breakpoint and
+breakpoint.GetNumLocations() == 1,
+VALID_BREAKPOINT)
+# Get the location from breakpoint
+location = breakpoint.GetLocationAtIndex(0)
+
+# Get the address where breakpoint is actually set.
+bpaddr = location.GetLoadAddress()
+
+# Breakpoint address should be adjusted to the address of branch instruction.
+self.assertTrue(branchinstaddress == bpaddr)
+i += 1
+else:
+i += 1
+
+if __name__ == '__main__':
+import atexit
+lldb.SBDebugger.Initialize()
+atexit.register(lambda: lldb.SBDebugger.Terminate())
+unittest2.main()
Index: packages/Python/lld
Re: [Lldb-commits] [PATCH] D16049: [LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
bhushan added a comment.
In http://reviews.llvm.org/D16049#326634, @labath wrote:
> In http://reviews.llvm.org/D16049#326631, @bhushan wrote:
>
> > Hi Zachary,
> >
> > If we use @skipIf then the list would require to contain all possible MIPS
> > variations and the list will grow long.
> > for ex: @skipIf(archs=not_in(['mips32','mips32r2', 'mips32r3',
> > 'mips64','mips64r2', 'mips64r3', 'mips64r6' ..]))
> >
> > @skipUnlessMips covers all these possible values using regular expression
> > matching.
>
>
> I agree with Zachary that we have too many decorators and we shouldn't be
> expanding their number, it's simply not sustainable. I see two options here:
>
> - add a `getMipsArchitectures()` function and then write
> `archs=not_in(getMipsArchitectures())`
> - add a `not_regex()` function and write `archs=not_regex('mips.*')` How does
> that sound?
I think adding `not_ regex()` sounds better option to me just because in future
if MIPS adds another architecture variation then `getMipsArchitectures()` would
require an update.
`not_regex` will look like this:
def not_regex(pattern):
return lambda x : not re.match(pattern, x)`
and python test file will use it as:
`@skipIf(archs=not_regex('mips*'))`
If Greg and Zachary also agrees then I will submit a patch for this.
Repository:
rL LLVM
http://reviews.llvm.org/D16049
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Re: [Lldb-commits] [PATCH] D14111: Use "_$" prefix instead of "$" for dynamic checker function inserted by LLDB during expression evaluation
bhushan added a reviewer: clayborg. bhushan added a comment. Hi Greg, Can you have look into this? This patch is important to clear expression related tests for MIPS. Repository: rL LLVM http://reviews.llvm.org/D14111 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D16049: [LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
bhushan updated the summary for this revision.
bhushan updated this revision to Diff 45237.
bhushan added a comment.
Addressed review comments.
Instead of adding new decorator, this patch modifies existing `skipUnlessArch`
to detect the type of the "archs" variable and do the things according to the
type.
This handles regular expressions as well.
The python test file then uses this decorator as
`@skipUnlessArch(archs=re.compile('mips*'))` to skip any architectures other
than mips.
Repository:
rL LLVM
http://reviews.llvm.org/D16049
Files:
include/lldb/API/SBInstruction.h
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
packages/Python/lldbsuite/test/lldbtest.py
scripts/interface/SBInstruction.i
source/API/SBInstruction.cpp
source/Target/Target.cpp
Index: packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
@@ -0,0 +1,21 @@
+#include
+
+foo (int a, int b)
+{
+int c;
+if (a<=b)
+c=b-a;
+else
+c=b+a;
+return c;
+}
+
+int main()
+{
+int a=7, b=8, c;
+
+c = foo(a, b);
+
+return 0;
+}
+
Index: packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
@@ -0,0 +1,82 @@
+"""
+Test specific to MIPS
+"""
+
+import os, time
+import re
+import unittest2
+import lldb
+import lldbsuite.test.lldbutil as lldbutil
+from lldbsuite.test.lldbtest import *
+
+class AvoidBreakpointInDelaySlotAPITestCase(TestBase):
+
+mydir = TestBase.compute_mydir(__file__)
+
+@skipUnlessArch(archs=re.compile('mips*'))
+def test(self):
+self.build()
+exe = os.path.join(os.getcwd(), "a.out")
+self.expect("file " + exe,
+patterns = [ "Current executable set to .*a.out.*" ])
+
+# Create a target by the debugger.
+target = self.dbg.CreateTarget(exe)
+self.assertTrue(target, VALID_TARGET)
+
+breakpoint = target.BreakpointCreateByName('main', 'a.out')
+self.assertTrue(breakpoint and
+breakpoint.GetNumLocations() == 1,
+VALID_BREAKPOINT)
+
+# Now launch the process, and do not stop at entry point.
+process = target.LaunchSimple (None, None, self.get_process_working_directory())
+self.assertTrue(process, PROCESS_IS_VALID)
+
+list = target.FindFunctions('foo', lldb.eFunctionNameTypeAuto)
+self.assertTrue(list.GetSize() == 1)
+sc = list.GetContextAtIndex(0)
+self.assertTrue(sc.GetSymbol().GetName() == "foo")
+function = sc.GetFunction()
+self.assertTrue(function)
+self.function(function, target)
+
+def function (self, function, target):
+"""Iterate over instructions in function and place a breakpoint on delay slot instruction"""
+# Get the list of all instructions in the function
+insts = function.GetInstructions(target)
+print insts
+i = 0
+for inst in insts:
+if (inst.HasDelaySlot()):
+# Remember the address of branch instruction.
+branchinstaddress = inst.GetAddress().GetLoadAddress(target)
+
+# Get next instruction i.e delay slot instruction.
+delayinst = insts.GetInstructionAtIndex(i+1)
+delayinstaddr = delayinst.GetAddress().GetLoadAddress(target)
+
+# Set breakpoint on delay slot instruction
+breakpoint = target.BreakpointCreateByAddress(delayinstaddr)
+
+# Verify the breakpoint.
+self.assertTrue(breakpoint and
+breakpoint.GetNumLocations() == 1,
+VALID_BREAKPOINT)
+# Get the location from breakpoint
+location = breakpoint.GetLocationAtIndex(0)
+
+# Get the address where breakpoint is actually set.
+bpaddr = location.GetLoadAddress()
+
+# Breakpoint address should be adjusted to the address of branch instruction.
+self.assertTrue(branchinstaddress == bpaddr)
+i += 1
+else:
+i += 1
+
+if __name__ == '__main__':
+import atexit
+lldb.SBDebugger.Initialize()
+atexit.register(lambda: lldb.SBDebugger.Terminate())
+unittest2.
Re: [Lldb-commits] [PATCH] D14111: Use "_$" prefix instead of "$" for dynamic checker function inserted by LLDB during expression evaluation
bhushan added a comment. In http://reviews.llvm.org/D14111#330305, @spyffe wrote: > That looks fine to me as far as it goes, but it doesn't cover other places > where $ is used in function names, e.g. the name of the expression itself, > and classes it's placed in. Could you have a look at > ExpressionSourceCode.cpp and see if there is anything there that needs a $ as > well? The other function names in ExpressionSourceCode.cpp e.g. `$__lldb_expr` does not require to be prefixed with an additional underscore like `_$__lldb_expr`. This is because these names get mangled by the compiler to something like `_Z12$__lldb_exprPv`, so they does not start with "$" and hence not marked as ‘temporary’ symbols. The additional `_` prefix is only needed for "$__lldb_valid_pointer_check" since this name does not get mangled by compiler (may be because it has C Language linkage). Repository: rL LLVM http://reviews.llvm.org/D14111 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D16049: [LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
bhushan updated this revision to Diff 45364.
bhushan added a comment.
As suggested by Greg, added new function `matchArchitectures(archs)` which
handles "archs".
This function can be used by other decorator functions for testing "archs".
Repository:
rL LLVM
http://reviews.llvm.org/D16049
Files:
include/lldb/API/SBInstruction.h
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
packages/Python/lldbsuite/test/lldbtest.py
scripts/interface/SBInstruction.i
source/API/SBInstruction.cpp
source/Target/Target.cpp
Index: packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
@@ -0,0 +1,21 @@
+#include
+
+foo (int a, int b)
+{
+int c;
+if (a<=b)
+c=b-a;
+else
+c=b+a;
+return c;
+}
+
+int main()
+{
+int a=7, b=8, c;
+
+c = foo(a, b);
+
+return 0;
+}
+
Index: packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
@@ -0,0 +1,82 @@
+"""
+Test specific to MIPS
+"""
+
+import os, time
+import re
+import unittest2
+import lldb
+import lldbsuite.test.lldbutil as lldbutil
+from lldbsuite.test.lldbtest import *
+
+class AvoidBreakpointInDelaySlotAPITestCase(TestBase):
+
+mydir = TestBase.compute_mydir(__file__)
+
+@skipUnlessArch(archs=re.compile('mips*'))
+def test(self):
+self.build()
+exe = os.path.join(os.getcwd(), "a.out")
+self.expect("file " + exe,
+patterns = [ "Current executable set to .*a.out.*" ])
+
+# Create a target by the debugger.
+target = self.dbg.CreateTarget(exe)
+self.assertTrue(target, VALID_TARGET)
+
+breakpoint = target.BreakpointCreateByName('main', 'a.out')
+self.assertTrue(breakpoint and
+breakpoint.GetNumLocations() == 1,
+VALID_BREAKPOINT)
+
+# Now launch the process, and do not stop at entry point.
+process = target.LaunchSimple (None, None, self.get_process_working_directory())
+self.assertTrue(process, PROCESS_IS_VALID)
+
+list = target.FindFunctions('foo', lldb.eFunctionNameTypeAuto)
+self.assertTrue(list.GetSize() == 1)
+sc = list.GetContextAtIndex(0)
+self.assertTrue(sc.GetSymbol().GetName() == "foo")
+function = sc.GetFunction()
+self.assertTrue(function)
+self.function(function, target)
+
+def function (self, function, target):
+"""Iterate over instructions in function and place a breakpoint on delay slot instruction"""
+# Get the list of all instructions in the function
+insts = function.GetInstructions(target)
+print insts
+i = 0
+for inst in insts:
+if (inst.HasDelaySlot()):
+# Remember the address of branch instruction.
+branchinstaddress = inst.GetAddress().GetLoadAddress(target)
+
+# Get next instruction i.e delay slot instruction.
+delayinst = insts.GetInstructionAtIndex(i+1)
+delayinstaddr = delayinst.GetAddress().GetLoadAddress(target)
+
+# Set breakpoint on delay slot instruction
+breakpoint = target.BreakpointCreateByAddress(delayinstaddr)
+
+# Verify the breakpoint.
+self.assertTrue(breakpoint and
+breakpoint.GetNumLocations() == 1,
+VALID_BREAKPOINT)
+# Get the location from breakpoint
+location = breakpoint.GetLocationAtIndex(0)
+
+# Get the address where breakpoint is actually set.
+bpaddr = location.GetLoadAddress()
+
+# Breakpoint address should be adjusted to the address of branch instruction.
+self.assertTrue(branchinstaddress == bpaddr)
+i += 1
+else:
+i += 1
+
+if __name__ == '__main__':
+import atexit
+lldb.SBDebugger.Initialize()
+atexit.register(lambda: lldb.SBDebugger.Terminate())
+unittest2.main()
Index: packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/breakpoint/bre
Re: [Lldb-commits] [PATCH] D14111: Use "_$" prefix instead of "$" for dynamic checker function inserted by LLDB during expression evaluation
bhushan closed this revision. bhushan added a comment. Closed by commit http://reviews.llvm.org/rL258485 Repository: rL LLVM http://reviews.llvm.org/D14111 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [lldb] r258485 - Use "_$" prefix instead of "$" for dynamic checker function inserted by LLDB during expression evaluation
Hi Hans,
Could you please add this to the release branch?
Thanks,
Bhushan
-Original Message-
From: lldb-commits [mailto:lldb-commits-boun...@lists.llvm.org] On Behalf Of
Bhushan D. Attarde via lldb-commits
Sent: 22 January 2016 10:32
To: lldb-commits@lists.llvm.org
Subject: [Lldb-commits] [lldb] r258485 - Use "_$" prefix instead of "$" for
dynamic checker function inserted by LLDB during expression evaluation
Author: bhushan.attarde
Date: Thu Jan 21 23:02:02 2016
New Revision: 258485
URL: http://llvm.org/viewvc/llvm-project?rev=258485&view=rev
Log:
Use "_$" prefix instead of "$" for dynamic checker function inserted by LLDB
during expression evaluation
SUMMARY:
The symbol "$" has a special meaning for MIPS i.e it is marker for
temporary symbols for MIPS.
So this patch uses additional _ prefix for "$__lldb_valid_pointer_check" so
that it wont be marked as temporary symbol in case of MIPS.
Reviewers: clayborg, spyffe
Subscribers: dean, emaste, mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential http://reviews.llvm.org/D14111
Modified:
lldb/trunk/source/Expression/IRDynamicChecks.cpp
Modified: lldb/trunk/source/Expression/IRDynamicChecks.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Expression/IRDynamicChecks.cpp?rev=258485&r1=258484&r2=258485&view=diff
==
--- lldb/trunk/source/Expression/IRDynamicChecks.cpp (original)
+++ lldb/trunk/source/Expression/IRDynamicChecks.cpp Thu Jan 21 23:02:02
+++ 2016
@@ -35,12 +35,12 @@ using namespace lldb_private;
static char ID;
-#define VALID_POINTER_CHECK_NAME "$__lldb_valid_pointer_check"
+#define VALID_POINTER_CHECK_NAME "_$__lldb_valid_pointer_check"
#define VALID_OBJC_OBJECT_CHECK_NAME "$__lldb_objc_object_check"
static const char g_valid_pointer_check_text[] = "extern \"C\" void\n"
-"$__lldb_valid_pointer_check (unsigned char *$__lldb_arg_ptr)\n"
+"_$__lldb_valid_pointer_check (unsigned char *$__lldb_arg_ptr)\n"
"{\n"
"unsigned char $__lldb_local_val = *$__lldb_arg_ptr;\n"
"}";
___
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___
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Re: [Lldb-commits] [lldb] r258919 - [LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
Hi Hans,
Could you please add this (r258919) to the release branch?
Also commit r258967 (on top of this) by Zachary which fixes some python 3
incompatibilities.
Thanks,
Bhushan
-Original Message-
From: lldb-commits [mailto:lldb-commits-boun...@lists.llvm.org] On Behalf Of
Bhushan D. Attarde via lldb-commits
Sent: 27 January 2016 15:47
To: lldb-commits@lists.llvm.org
Subject: [Lldb-commits] [lldb] r258919 - [LLDB][MIPS] A small fix in
GetBreakableLoadAddress() for MIPS
Author: bhushan.attarde
Date: Wed Jan 27 04:16:30 2016
New Revision: 258919
URL: http://llvm.org/viewvc/llvm-project?rev=258919&view=rev
Log:
[LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
SUMMARY:
Get the load address for the address given by symbol and function.
Earlier, this was done for function only, this patch does it for symbol too.
This patch also adds TestAvoidBreakpointInDelaySlot.py to test this change.
Reviewers: clayborg
Subscribers: labath, zturner, mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential Revision: http://reviews.llvm.org/D16049
Added:
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/main.c
Modified:
lldb/trunk/include/lldb/API/SBInstruction.h
lldb/trunk/packages/Python/lldbsuite/test/lldbtest.py
lldb/trunk/scripts/interface/SBInstruction.i
lldb/trunk/source/API/SBInstruction.cpp
lldb/trunk/source/Target/Target.cpp
Modified: lldb/trunk/include/lldb/API/SBInstruction.h
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/API/SBInstruction.h?rev=258919&r1=258918&r2=258919&view=diff
==
--- lldb/trunk/include/lldb/API/SBInstruction.h (original)
+++ lldb/trunk/include/lldb/API/SBInstruction.h Wed Jan 27 04:16:30 2016
@@ -60,6 +60,9 @@ public:
bool
DoesBranch ();
+bool
+HasDelaySlot ();
+
void
Print (FILE *out);
Added:
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile?rev=258919&view=auto
==
---
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/Makefile
(added)
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint
+++ /breakpoint_in_delayslot/Makefile Wed Jan 27 04:16:30 2016
@@ -0,0 +1,6 @@
+LEVEL = ../../../make
+
+C_SOURCES := main.c
+
+include $(LEVEL)/Makefile.rules
+
Added:
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py?rev=258919&view=auto
==
---
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py
(added)
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint
+++ /breakpoint_in_delayslot/TestAvoidBreakpointInDelaySlot.py Wed Jan
+++ 27 04:16:30 2016
@@ -0,0 +1,82 @@
+"""
+Test specific to MIPS
+"""
+
+import os, time
+import re
+import unittest2
+import lldb
+import lldbsuite.test.lldbutil as lldbutil from lldbsuite.test.lldbtest
+import *
+
+class AvoidBreakpointInDelaySlotAPITestCase(TestBase):
+
+mydir = TestBase.compute_mydir(__file__)
+
+@skipUnlessArch(archs=re.compile('mips*'))
+def test(self):
+self.build()
+exe = os.path.join(os.getcwd(), "a.out")
+self.expect("file " + exe,
+patterns = [ "Current executable set to .*a.out.*"
+ ])
+
+# Create a target by the debugger.
+target = self.dbg.CreateTarget(exe)
+self.assertTrue(target, VALID_TARGET)
+
+breakpoint = target.BreakpointCreateByName('main', 'a.out')
+self.assertTrue(breakpoint and
+breakpoint.GetNumLocations() == 1,
+VALID_BREAKPOINT)
+
+# Now launch the process, and do not stop at entry point.
+process = target.LaunchSimple (None, None,
self.get_process_working_directory())
+self.assertTrue(process, PROCESS_IS_VALID)
+
+list = target.FindFunctions('foo', lldb.eFunctionNameTypeAuto)
+self.assertTrue(list.GetSize() == 1)
+
Re: [Lldb-commits] [PATCH] D16049: [LLDB][MIPS] A small fix in GetBreakableLoadAddress() for MIPS
bhushan closed this revision. bhushan added a comment. Closed by commit http://reviews.llvm.org/rL258919 Repository: rL LLVM http://reviews.llvm.org/D16049 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D16916: [LLDB][MIPS] Fix TestExpressionInSyscall.py for MIPS
bhushan created this revision.
bhushan added a reviewer: clayborg.
bhushan added subscribers: lldb-commits, nitesh.jain, mohit.bhakkad, sagar,
jaydeep.
bhushan set the repository for this revision to rL LLVM.
This test (TestExpressionInSyscall.py) checks if we are able to evaluate
expressions when the inferior is blocked in a syscall.
As a part of expression evaluation LLDB checks for memory allocation on target
(by executing mmap).
So we setup call to mmap by setting argument registers and PC.
Now the process is stopped in the syscall and when it continue to allocate
memory, the system call is restarted.
In MIPS, to restart a syscall, kernel decreases the PC by 4 so the resulting PC
now points to mmap-4
and also register R7 that provides 'flags' argument to mmap gets clobbered to 0
and hence mmap fails.
A fix to this issue is to postpone the syscall restart until the expression is
evaluated.
In MIPS, register R0 controls syscall restart. This patch writes 0 into
register R0 when preparing call to mmap.
This setting avoids a syscall restart and prevents automatic decrement of the
PC so that expression can be evaluated correctly.
Once the expression completes the registers are restored and program resumes
the interrupted syscall when the continue command is issued.
This fixes TestExpressionInSyscall.py and solves bug 23659 for MIPS.
Repository:
rL LLVM
http://reviews.llvm.org/D16916
Files:
source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
Index: source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
===
--- source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
+++ source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
@@ -207,6 +207,17 @@
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
const RegisterInfo *ra_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
const RegisterInfo *r25_info = reg_ctx->GetRegisterInfoByName("r25", 0);
+const RegisterInfo *r0_info = reg_ctx->GetRegisterInfoByName("zero", 0);
+
+if (log)
+log->Printf("Writing R0: 0x%" PRIx64, (uint64_t)0);
+
+/* Write r0 with 0, in case we are stopped in syscall,
+ * such setting prevents automatic decrement of the PC.
+ * This clears the bug 23659 for MIPS.
+*/
+if (!reg_ctx->WriteRegisterFromUnsigned (r0_info, (uint64_t)0))
+return false;
if (log)
log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
Index: source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
===
--- source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
+++ source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
@@ -242,6 +242,17 @@
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
const RegisterInfo *ra_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
const RegisterInfo *r25_info = reg_ctx->GetRegisterInfoByName("r25", 0);
+const RegisterInfo *r0_info = reg_ctx->GetRegisterInfoByName("zero", 0);
+
+if (log)
+log->Printf("Writing R0: 0x%" PRIx64, (uint64_t)0);
+
+/* Write r0 with 0, in case we are stopped in syscall,
+ * such setting prevents automatic decrement of the PC.
+ * This clears the bug 23659 for MIPS.
+*/
+if (!reg_ctx->WriteRegisterFromUnsigned (r0_info, (uint64_t)0))
+return false;
if (log)
log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
Index: source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
===
--- source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
+++ source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
@@ -207,6 +207,17 @@
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
const RegisterInfo *ra_reg_info = reg_ctx->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
const RegisterInfo *r25_info = reg_ctx->GetRegisterInfoByName("r25", 0);
+const RegisterInfo *r0_info = reg_ctx->GetRegisterInfoByName("zero", 0);
+
+if (log)
+log->Printf("Writing R0: 0x%" PRIx64, (uint64_t)0);
+
+/* Write r0 with 0, in case we are stopped in syscall,
+ * such setting prevents automatic decrement of the PC.
+ * This clears the bug 23659 for MIPS.
+*/
+if (!reg_ctx->WriteRegisterFromUnsigned (r0_info, (uint64_t)0))
+return false;
if (log)
log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
Index: source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
===
--- source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
+++ source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
@@ -242,6 +242,17 @@
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo (eRegisterKindGene
Re: [Lldb-commits] [PATCH] D16916: [LLDB][MIPS] Fix TestExpressionInSyscall.py for MIPS
bhushan closed this revision. bhushan added a comment. Closed by commit http://reviews.llvm.org/rL260072 Repository: rL LLVM http://reviews.llvm.org/D16916 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [lldb] r260072 - [LLDB][MIPS] Fix TestExpressionInSyscall.py for MIPS
Hi Hans,
Could you please add this (r260072) to the release branch?
Thanks,
Bhushan
-Original Message-
From: lldb-commits [mailto:lldb-commits-boun...@lists.llvm.org] On Behalf Of
Bhushan D. Attarde via lldb-commits
Sent: 08 February 2016 10:06
To: lldb-commits@lists.llvm.org
Subject: [Lldb-commits] [lldb] r260072 - [LLDB][MIPS] Fix
TestExpressionInSyscall.py for MIPS
Author: bhushan.attarde
Date: Sun Feb 7 22:35:51 2016
New Revision: 260072
URL: http://llvm.org/viewvc/llvm-project?rev=260072&view=rev
Log:
[LLDB][MIPS] Fix TestExpressionInSyscall.py for MIPS
SUMMARY:
This patch fixes TestExpressionInSyscall.py and solves bug 23659 for MIPS.
Corrected indentation at couple of places.
Reviewers: clayborg
Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential Revision: http://reviews.llvm.org/D16916
Modified:
lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
Modified: lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp?rev=260072&r1=260071&r2=260072&view=diff
==
--- lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp (original)
+++ lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp Sun Feb 7
22:35:51 2016
@@ -242,16 +242,27 @@ ABISysV_mips::PrepareTrivialCall (Thread
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
const RegisterInfo *ra_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
const RegisterInfo *r25_info = reg_ctx->GetRegisterInfoByName("r25", 0);
+const RegisterInfo *r0_info = reg_ctx->GetRegisterInfoByName("zero", 0);
if (log)
-log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
+log->Printf("Writing R0: 0x%" PRIx64, (uint64_t)0);
+
+/* Write r0 with 0, in case we are stopped in syscall,
+ * such setting prevents automatic decrement of the PC.
+ * This clears the bug 23659 for MIPS.
+*/
+if (!reg_ctx->WriteRegisterFromUnsigned (r0_info, (uint64_t)0))
+return false;
+
+if (log)
+log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
// Set "sp" to the requested value
if (!reg_ctx->WriteRegisterFromUnsigned (sp_reg_info, sp))
return false;
if (log)
-log->Printf("Writing RA: 0x%" PRIx64, (uint64_t)return_addr);
+log->Printf("Writing RA: 0x%" PRIx64, (uint64_t)return_addr);
// Set "ra" to the return address
if (!reg_ctx->WriteRegisterFromUnsigned (ra_reg_info, return_addr))
Modified: lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp?rev=260072&r1=260071&r2=260072&view=diff
==
--- lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp (original)
+++ lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp Sun Feb 7
22:35:51 2016
@@ -207,16 +207,27 @@ ABISysV_mips64::PrepareTrivialCall (Thre
const RegisterInfo *sp_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
const RegisterInfo *ra_reg_info = reg_ctx->GetRegisterInfo
(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA);
const RegisterInfo *r25_info = reg_ctx->GetRegisterInfoByName("r25", 0);
+const RegisterInfo *r0_info = reg_ctx->GetRegisterInfoByName("zero", 0);
if (log)
-log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
+log->Printf("Writing R0: 0x%" PRIx64, (uint64_t)0);
+
+/* Write r0 with 0, in case we are stopped in syscall,
+ * such setting prevents automatic decrement of the PC.
+ * This clears the bug 23659 for MIPS.
+*/
+if (!reg_ctx->WriteRegisterFromUnsigned (r0_info, (uint64_t)0))
+return false;
+
+if (log)
+log->Printf("Writing SP: 0x%" PRIx64, (uint64_t)sp);
// Set "sp" to the requested value
if (!reg_ctx->WriteRegisterFromUnsigned (sp_reg_info, sp))
return false;
if (log)
-log->Printf("Writing RA: 0x%" PRIx64, (uint64_t)return_addr);
+log->Printf("Writing RA: 0x%" PRIx64, (uint64_t)return_addr);
// Set "ra" to the return address
if (!reg_ctx->WriteRegisterFromUnsigned (ra_reg_info, return_addr))
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[Lldb-commits] [PATCH] D17022: [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
bhushan created this revision.
bhushan added reviewers: clayborg, spyffe.
bhushan added subscribers: lldb-commits, nitesh.jain, jaydeep, sagar,
mohit.bhakkad.
bhushan set the repository for this revision to rL LLVM.
Currently, LLDB (ClangExpressionParser) does not pass
`clang::TargetOptions::CPU` to clang which is supposed to contain the name of
the target CPU to generate code for.
So, compiler generates the code for its default CPU (mips32r2 and mips64r2 for
MIPS32 and MIPS64 respectively).
This causes problems in evaluating expressions in some cases.
For example, if we are debugging MIPS revision 6 (R6) application, as we do not
pass CPU information to the compiler so compiler chooses default target and
generates code for mips32r2/mips64r2.
The code generated for expression then fails to run on R6 because instruction
set differs for R2 and R6 (few instructions in R2 are not available in R6).
The causes expression to fail.
This patch sets `clang::TargetOptions::CPU` with appropriate string so that
compiler can generate correct code for that target.
Repository:
rL LLVM
http://reviews.llvm.org/D17022
Files:
source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
Index: source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
===
--- source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
+++ source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
@@ -175,6 +175,10 @@
if (exe_scope)
target_sp = exe_scope->CalculateTarget();
+ArchSpec arch;
+if (target_sp)
+arch = target_sp->GetArchitecture();
+
// TODO: figure out what to really do when we don't have a valid target.
// Sometimes this will be ok to just use the host target triple (when we
// evaluate say "2+3", but other expressions like breakpoint conditions
@@ -197,6 +201,50 @@
m_compiler->getTargetOpts().Features.push_back("+sse2");
}
+if (arch.GetMachine() == llvm::Triple::mips ||
+arch.GetMachine() == llvm::Triple::mipsel ||
+arch.GetMachine() == llvm::Triple::mips64 ||
+arch.GetMachine() == llvm::Triple::mips64el)
+{
+std::string cpu;
+switch (arch.GetCore())
+{
+case ArchSpec::eCore_mips32:
+case ArchSpec::eCore_mips32el:
+cpu = "mips32"; break;
+case ArchSpec::eCore_mips32r2:
+case ArchSpec::eCore_mips32r2el:
+cpu = "mips32r2"; break;
+case ArchSpec::eCore_mips32r3:
+case ArchSpec::eCore_mips32r3el:
+cpu = "mips32r3"; break;
+case ArchSpec::eCore_mips32r5:
+case ArchSpec::eCore_mips32r5el:
+cpu = "mips32r5"; break;
+case ArchSpec::eCore_mips32r6:
+case ArchSpec::eCore_mips32r6el:
+cpu = "mips32r6"; break;
+case ArchSpec::eCore_mips64:
+case ArchSpec::eCore_mips64el:
+cpu = "mips64"; break;
+case ArchSpec::eCore_mips64r2:
+case ArchSpec::eCore_mips64r2el:
+cpu = "mips64r2"; break;
+case ArchSpec::eCore_mips64r3:
+case ArchSpec::eCore_mips64r3el:
+cpu = "mips64r3"; break;
+case ArchSpec::eCore_mips64r5:
+case ArchSpec::eCore_mips64r5el:
+cpu = "mips64r5"; break;
+case ArchSpec::eCore_mips64r6:
+case ArchSpec::eCore_mips64r6el:
+cpu = "mips64r6"; break;
+default:
+cpu = "generic"; break;
+}
+m_compiler->getTargetOpts().CPU = cpu;
+}
+
// Any arm32 iOS environment, but not on arm64
if (m_compiler->getTargetOpts().Triple.find("arm64") == std::string::npos
&&
m_compiler->getTargetOpts().Triple.find("arm") != std::string::npos &&
Index: source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
===
--- source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
+++ source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
@@ -175,6 +175,10 @@
if (exe_scope)
target_sp = exe_scope->CalculateTarget();
+ArchSpec arch;
+if (target_sp)
+arch = target_sp->GetArchitecture();
+
// TODO: figure out what to really do when we don't have a valid target.
// Sometimes this will be ok to just use the host target triple (when we
// evaluate say "2+3", but other expressions like breakpoint conditions
@@ -197,6 +201,50 @@
m_compiler->getTargetOpts().Features.push_back("+sse2");
}
+if (arch.GetMachine() == llvm::Triple::mips ||
+arch.GetMachine() == llvm::Triple::mipsel ||
+arch.GetMachine() == llvm::Triple::mips64 ||
+arch.GetMachine() == llvm::Triple::mips64el)
+{
+std::string cpu;
+switch (arch.GetCore())
+{
+case ArchSpec::eCore_mips32:
+case ArchSpec::eCore_mips32el:
+cpu = "mips32"; b
Re: [Lldb-commits] [PATCH] D17022: [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
bhushan updated this revision to Diff 47422.
bhushan added a comment.
Addresses review comments.
Used local variables instead of calling accessors each time.
Repository:
rL LLVM
http://reviews.llvm.org/D17022
Files:
source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
Index: source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
===
--- source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
+++ source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
@@ -175,28 +175,78 @@
if (exe_scope)
target_sp = exe_scope->CalculateTarget();
+ArchSpec target_arch;
+if (target_sp)
+target_arch = target_sp->GetArchitecture();
+
+const auto target_machine = target_arch.GetMachine();
+
// TODO: figure out what to really do when we don't have a valid target.
// Sometimes this will be ok to just use the host target triple (when we
// evaluate say "2+3", but other expressions like breakpoint conditions
// and other things that _are_ target specific really shouldn't just be
// using the host triple. This needs to be fixed in a better way.
-if (target_sp && target_sp->GetArchitecture().IsValid())
+if (target_sp && target_arch.IsValid())
{
-std::string triple = target_sp->GetArchitecture().GetTriple().str();
+std::string triple = target_arch.GetTriple().str();
m_compiler->getTargetOpts().Triple = triple;
}
else
{
m_compiler->getTargetOpts().Triple =
llvm::sys::getDefaultTargetTriple();
}
-if (target_sp->GetArchitecture().GetMachine() == llvm::Triple::x86 ||
-target_sp->GetArchitecture().GetMachine() == llvm::Triple::x86_64)
+if (target_machine == llvm::Triple::x86 ||
+target_machine == llvm::Triple::x86_64)
{
m_compiler->getTargetOpts().Features.push_back("+sse");
m_compiler->getTargetOpts().Features.push_back("+sse2");
}
+if (target_machine == llvm::Triple::mips ||
+target_machine == llvm::Triple::mipsel ||
+target_machine == llvm::Triple::mips64 ||
+target_machine == llvm::Triple::mips64el)
+{
+std::string cpu;
+switch (target_arch.GetCore())
+{
+case ArchSpec::eCore_mips32:
+case ArchSpec::eCore_mips32el:
+cpu = "mips32"; break;
+case ArchSpec::eCore_mips32r2:
+case ArchSpec::eCore_mips32r2el:
+cpu = "mips32r2"; break;
+case ArchSpec::eCore_mips32r3:
+case ArchSpec::eCore_mips32r3el:
+cpu = "mips32r3"; break;
+case ArchSpec::eCore_mips32r5:
+case ArchSpec::eCore_mips32r5el:
+cpu = "mips32r5"; break;
+case ArchSpec::eCore_mips32r6:
+case ArchSpec::eCore_mips32r6el:
+cpu = "mips32r6"; break;
+case ArchSpec::eCore_mips64:
+case ArchSpec::eCore_mips64el:
+cpu = "mips64"; break;
+case ArchSpec::eCore_mips64r2:
+case ArchSpec::eCore_mips64r2el:
+cpu = "mips64r2"; break;
+case ArchSpec::eCore_mips64r3:
+case ArchSpec::eCore_mips64r3el:
+cpu = "mips64r3"; break;
+case ArchSpec::eCore_mips64r5:
+case ArchSpec::eCore_mips64r5el:
+cpu = "mips64r5"; break;
+case ArchSpec::eCore_mips64r6:
+case ArchSpec::eCore_mips64r6el:
+cpu = "mips64r6"; break;
+default:
+cpu = "generic"; break;
+}
+m_compiler->getTargetOpts().CPU = cpu;
+}
+
// Any arm32 iOS environment, but not on arm64
if (m_compiler->getTargetOpts().Triple.find("arm64") == std::string::npos
&&
m_compiler->getTargetOpts().Triple.find("arm") != std::string::npos &&
Index: source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
===
--- source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
+++ source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
@@ -175,28 +175,78 @@
if (exe_scope)
target_sp = exe_scope->CalculateTarget();
+ArchSpec target_arch;
+if (target_sp)
+target_arch = target_sp->GetArchitecture();
+
+const auto target_machine = target_arch.GetMachine();
+
// TODO: figure out what to really do when we don't have a valid target.
// Sometimes this will be ok to just use the host target triple (when we
// evaluate say "2+3", but other expressions like breakpoint conditions
// and other things that _are_ target specific really shouldn't just be
// using the host triple. This needs to be fixed in a better way.
-if (target_sp && target_sp->GetArchitecture().IsValid())
+if (target_sp && target_arch.IsValid())
{
-std::string triple = target_sp->GetArchitecture().GetTriple().str();
+std::string triple = target_arch.GetTriple().st
Re: [Lldb-commits] [PATCH] D17022: [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
bhushan updated this revision to Diff 47621.
bhushan added a comment.
Addressed review comments:
- Rebased this patch off top of tree
- Added ArchSpec::GetClangTargetCPU() as suggested and moved large switch
statement into it.
Repository:
rL LLVM
http://reviews.llvm.org/D17022
Files:
include/lldb/Core/ArchSpec.h
source/Core/ArchSpec.cpp
source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
Index: source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
===
--- source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
+++ source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
@@ -179,6 +179,12 @@
if (exe_scope)
target_sp = exe_scope->CalculateTarget();
+ArchSpec target_arch;
+if (target_sp)
+target_arch = target_sp->GetArchitecture();
+
+const auto target_machine = target_arch.GetMachine();
+
// If the expression is being evaluated in the context of an existing
// stack frame, we introspect to see if the language runtime is available.
auto frame = exe_scope->CalculateStackFrame();
@@ -197,9 +203,9 @@
// 2. Configure the compiler with a set of default options that are appropriate
// for most situations.
-if (target_sp && target_sp->GetArchitecture().IsValid())
+if (target_sp && target_arch.IsValid())
{
-std::string triple = target_sp->GetArchitecture().GetTriple().str();
+std::string triple = target_arch.GetTriple().str();
m_compiler->getTargetOpts().Triple = triple;
if (log)
log->Printf("Using %s as the target triple", m_compiler->getTargetOpts().Triple.c_str());
@@ -224,13 +230,21 @@
m_compiler->getTargetOpts().ABI = "apcs-gnu";
}
// Supported subsets of x86
-if (target_sp->GetArchitecture().GetMachine() == llvm::Triple::x86 ||
-target_sp->GetArchitecture().GetMachine() == llvm::Triple::x86_64)
+if (target_machine == llvm::Triple::x86 ||
+target_machine == llvm::Triple::x86_64)
{
m_compiler->getTargetOpts().Features.push_back("+sse");
m_compiler->getTargetOpts().Features.push_back("+sse2");
}
+if (target_machine == llvm::Triple::mips ||
+target_machine == llvm::Triple::mipsel ||
+target_machine == llvm::Triple::mips64 ||
+target_machine == llvm::Triple::mips64el)
+{
+m_compiler->getTargetOpts().CPU = target_arch.GetClangTargetCPU();
+}
+
// 3. Now allow the runtime to provide custom configuration options for the target.
// In this case, a specialized language runtime is available and we can query it for extra options.
// For 99% of use cases, this will not be needed and should be provided when basic platform detection is not enough.
Index: source/Core/ArchSpec.cpp
===
--- source/Core/ArchSpec.cpp
+++ source/Core/ArchSpec.cpp
@@ -511,6 +511,57 @@
return "unknown";
}
+std::string
+ArchSpec::GetClangTargetCPU ()
+{
+std::string cpu;
+const llvm::Triple::ArchType machine = GetMachine();
+
+if (machine == llvm::Triple::mips ||
+machine == llvm::Triple::mipsel ||
+machine == llvm::Triple::mips64 ||
+machine == llvm::Triple::mips64el)
+{
+switch (m_core)
+{
+case ArchSpec::eCore_mips32:
+case ArchSpec::eCore_mips32el:
+cpu = "mips32"; break;
+case ArchSpec::eCore_mips32r2:
+case ArchSpec::eCore_mips32r2el:
+cpu = "mips32r2"; break;
+case ArchSpec::eCore_mips32r3:
+case ArchSpec::eCore_mips32r3el:
+cpu = "mips32r3"; break;
+case ArchSpec::eCore_mips32r5:
+case ArchSpec::eCore_mips32r5el:
+cpu = "mips32r5"; break;
+case ArchSpec::eCore_mips32r6:
+case ArchSpec::eCore_mips32r6el:
+cpu = "mips32r6"; break;
+case ArchSpec::eCore_mips64:
+case ArchSpec::eCore_mips64el:
+cpu = "mips64"; break;
+case ArchSpec::eCore_mips64r2:
+case ArchSpec::eCore_mips64r2el:
+cpu = "mips64r2"; break;
+case ArchSpec::eCore_mips64r3:
+case ArchSpec::eCore_mips64r3el:
+cpu = "mips64r3"; break;
+case ArchSpec::eCore_mips64r5:
+case ArchSpec::eCore_mips64r5el:
+cpu = "mips64r5"; break;
+case ArchSpec::eCore_mips64r6:
+case ArchSpec::eCore_mips64r6el:
+cpu = "mips64r6"; break;
+default:
+assert(false && "unexpected core");
+break;
+}
+}
+return cpu;
+}
+
uint32_t
ArchSpec::GetMachOCPUType () const
{
Index: include/lldb/Core/ArchSpec.h
===
--- include/lldb/Core/ArchSpec.h
+++ include/lldb/Core/ArchSpec.h
@@ -288,6 +288,16 @@
GetArchitectureName () const;
//--
Re: [Lldb-commits] [PATCH] D17022: [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
bhushan updated this revision to Diff 47765.
bhushan added a comment.
Removed assert statement so now "ArchSpec::GetClangTargetCPU ()" returns an
empty string (instead of crashing) for any CPU that doesn't really need to make
a special CPU string.
Removed the "if (is_mips)".
Repository:
rL LLVM
http://reviews.llvm.org/D17022
Files:
include/lldb/Core/ArchSpec.h
source/Core/ArchSpec.cpp
source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
Index: source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
===
--- source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
+++ source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
@@ -179,6 +179,12 @@
if (exe_scope)
target_sp = exe_scope->CalculateTarget();
+ArchSpec target_arch;
+if (target_sp)
+target_arch = target_sp->GetArchitecture();
+
+const auto target_machine = target_arch.GetMachine();
+
// If the expression is being evaluated in the context of an existing
// stack frame, we introspect to see if the language runtime is available.
auto frame = exe_scope->CalculateStackFrame();
@@ -197,9 +203,9 @@
// 2. Configure the compiler with a set of default options that are appropriate
// for most situations.
-if (target_sp && target_sp->GetArchitecture().IsValid())
+if (target_sp && target_arch.IsValid())
{
-std::string triple = target_sp->GetArchitecture().GetTriple().str();
+std::string triple = target_arch.GetTriple().str();
m_compiler->getTargetOpts().Triple = triple;
if (log)
log->Printf("Using %s as the target triple", m_compiler->getTargetOpts().Triple.c_str());
@@ -224,13 +230,17 @@
m_compiler->getTargetOpts().ABI = "apcs-gnu";
}
// Supported subsets of x86
-if (target_sp->GetArchitecture().GetMachine() == llvm::Triple::x86 ||
-target_sp->GetArchitecture().GetMachine() == llvm::Triple::x86_64)
+if (target_machine == llvm::Triple::x86 ||
+target_machine == llvm::Triple::x86_64)
{
m_compiler->getTargetOpts().Features.push_back("+sse");
m_compiler->getTargetOpts().Features.push_back("+sse2");
}
+// Set the target CPU to generate code for.
+// This will be empty for any CPU that doesn't really need to make a special CPU string.
+m_compiler->getTargetOpts().CPU = target_arch.GetClangTargetCPU();
+
// 3. Now allow the runtime to provide custom configuration options for the target.
// In this case, a specialized language runtime is available and we can query it for extra options.
// For 99% of use cases, this will not be needed and should be provided when basic platform detection is not enough.
Index: source/Core/ArchSpec.cpp
===
--- source/Core/ArchSpec.cpp
+++ source/Core/ArchSpec.cpp
@@ -511,6 +511,56 @@
return "unknown";
}
+std::string
+ArchSpec::GetClangTargetCPU ()
+{
+std::string cpu;
+const llvm::Triple::ArchType machine = GetMachine();
+
+if (machine == llvm::Triple::mips ||
+machine == llvm::Triple::mipsel ||
+machine == llvm::Triple::mips64 ||
+machine == llvm::Triple::mips64el)
+{
+switch (m_core)
+{
+case ArchSpec::eCore_mips32:
+case ArchSpec::eCore_mips32el:
+cpu = "mips32"; break;
+case ArchSpec::eCore_mips32r2:
+case ArchSpec::eCore_mips32r2el:
+cpu = "mips32r2"; break;
+case ArchSpec::eCore_mips32r3:
+case ArchSpec::eCore_mips32r3el:
+cpu = "mips32r3"; break;
+case ArchSpec::eCore_mips32r5:
+case ArchSpec::eCore_mips32r5el:
+cpu = "mips32r5"; break;
+case ArchSpec::eCore_mips32r6:
+case ArchSpec::eCore_mips32r6el:
+cpu = "mips32r6"; break;
+case ArchSpec::eCore_mips64:
+case ArchSpec::eCore_mips64el:
+cpu = "mips64"; break;
+case ArchSpec::eCore_mips64r2:
+case ArchSpec::eCore_mips64r2el:
+cpu = "mips64r2"; break;
+case ArchSpec::eCore_mips64r3:
+case ArchSpec::eCore_mips64r3el:
+cpu = "mips64r3"; break;
+case ArchSpec::eCore_mips64r5:
+case ArchSpec::eCore_mips64r5el:
+cpu = "mips64r5"; break;
+case ArchSpec::eCore_mips64r6:
+case ArchSpec::eCore_mips64r6el:
+cpu = "mips64r6"; break;
+default:
+break;
+}
+}
+return cpu;
+}
+
uint32_t
ArchSpec::GetMachOCPUType () const
{
Index: include/lldb/Core/ArchSpec.h
===
--- include/lldb/Core/ArchSpec.h
+++ include/lldb/Core/ArchSpec.h
@@ -288,6 +288,16 @@
GetArchitectureName () const;
//--
+/// Ret
Re: [Lldb-commits] [PATCH] D17022: [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
bhushan added a comment. @zturner, Ok to commit? Repository: rL LLVM http://reviews.llvm.org/D17022 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D17022: [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
bhushan added a comment. Hi Zachary, Can you please find some time to review this? Repository: rL LLVM http://reviews.llvm.org/D17022 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [lldb] r261206 - [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
Hi Hans,
Could you please add this (r261206) to the release branch?
Thanks,
Bhushan
-Original Message-
From: lldb-commits [mailto:lldb-commits-boun...@lists.llvm.org] On Behalf Of
Bhushan D. Attarde via lldb-commits
Sent: 18 February 2016 17:23
To: lldb-commits@lists.llvm.org
Subject: [Lldb-commits] [lldb] r261206 - [LLDB][MIPS] Provide CPU string to
compiler for appropriate code generation for MIPS
Author: bhushan.attarde
Date: Thu Feb 18 05:53:28 2016
New Revision: 261206
URL: http://llvm.org/viewvc/llvm-project?rev=261206&view=rev
Log:
[LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for
MIPS
SUMMARY:
This patch implements ArchSpec::GetClangTargetCPU() that provides string
representing current architecture as a target CPU.
This string is then passed to tools like clang so that they generate
correct code for that target.
Reviewers: clayborg, zturner
Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
Differential Revision: http://reviews.llvm.org/D17022
Modified:
lldb/trunk/include/lldb/Core/ArchSpec.h
lldb/trunk/source/Core/ArchSpec.cpp
lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
Modified: lldb/trunk/include/lldb/Core/ArchSpec.h
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/ArchSpec.h?rev=261206&r1=261205&r2=261206&view=diff
==
--- lldb/trunk/include/lldb/Core/ArchSpec.h (original)
+++ lldb/trunk/include/lldb/Core/ArchSpec.h Thu Feb 18 05:53:28 2016
@@ -288,6 +288,16 @@ public:
GetArchitectureName () const;
//--
+/// Returns a string representing current architecture as a target CPU
+/// for tools like compiler, disassembler etc.
+///
+/// @return A string representing target CPU for the current
+/// architecture.
+//--
+std::string
+GetClangTargetCPU ();
+
+
+ //--
/// Clears the object state.
///
/// Clears the object state back to a default invalid state.
Modified: lldb/trunk/source/Core/ArchSpec.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ArchSpec.cpp?rev=261206&r1=261205&r2=261206&view=diff
==
--- lldb/trunk/source/Core/ArchSpec.cpp (original)
+++ lldb/trunk/source/Core/ArchSpec.cpp Thu Feb 18 05:53:28 2016
@@ -511,6 +511,56 @@ ArchSpec::GetArchitectureName () const
return "unknown";
}
+std::string
+ArchSpec::GetClangTargetCPU ()
+{
+std::string cpu;
+const llvm::Triple::ArchType machine = GetMachine();
+
+if (machine == llvm::Triple::mips ||
+machine == llvm::Triple::mipsel ||
+machine == llvm::Triple::mips64 ||
+machine == llvm::Triple::mips64el)
+{
+switch (m_core)
+{
+case ArchSpec::eCore_mips32:
+case ArchSpec::eCore_mips32el:
+cpu = "mips32"; break;
+case ArchSpec::eCore_mips32r2:
+case ArchSpec::eCore_mips32r2el:
+cpu = "mips32r2"; break;
+case ArchSpec::eCore_mips32r3:
+case ArchSpec::eCore_mips32r3el:
+cpu = "mips32r3"; break;
+case ArchSpec::eCore_mips32r5:
+case ArchSpec::eCore_mips32r5el:
+cpu = "mips32r5"; break;
+case ArchSpec::eCore_mips32r6:
+case ArchSpec::eCore_mips32r6el:
+cpu = "mips32r6"; break;
+case ArchSpec::eCore_mips64:
+case ArchSpec::eCore_mips64el:
+cpu = "mips64"; break;
+case ArchSpec::eCore_mips64r2:
+case ArchSpec::eCore_mips64r2el:
+cpu = "mips64r2"; break;
+case ArchSpec::eCore_mips64r3:
+case ArchSpec::eCore_mips64r3el:
+cpu = "mips64r3"; break;
+case ArchSpec::eCore_mips64r5:
+case ArchSpec::eCore_mips64r5el:
+cpu = "mips64r5"; break;
+case ArchSpec::eCore_mips64r6:
+case ArchSpec::eCore_mips64r6el:
+cpu = "mips64r6"; break;
+default:
+break;
+}
+}
+return cpu;
+}
+
uint32_t
ArchSpec::GetMachOCPUType () const
{
Modified:
lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp?rev=261206&r1=261205&r2=261206&view=diff
==
--- lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
(original)
+++ lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionPars
+++ er.cpp Thu Feb 18 05:53:28 2016
@@ -179,6 +179,12 @@ ClangExpressionParser::ClangExpressionPa
if (exe_sco
[Lldb-commits] [PATCH] D17535: [LLDB][MIPS] Single step atomic sequences
bhushan created this revision.
bhushan added reviewers: clayborg, tberghammer.
bhushan added subscribers: lldb-commits, jaydeep, nitesh.jain, mohit.bhakkad,
sagar.
bhushan set the repository for this revision to rL LLVM.
This patch handles atomic sequences during single step.
LLDB should treat all instructions in the atomic sequence as if they are a
single instruction i.e as a "single instruction block".
So while single stepping, LLDB should detect and skip such sequence by placing
breakpoints only outside of such sequence i.e at the end of the sequence.
In MIPS, atomic sequence starts with LL (linked load) instruction and end with
SC (store conditional) instruction.
Example of atomic sequence in MIPS:
0x400c08 <+372>: ll $4, 0($2) > Start of sequence
0x400c0c <+376>: bne$4, $5, 28---> Atomic sequence can contain
branches that jump outside sequence range.
0x400c10 <+380>: addiu $3, $zero, 0
0x400c14 <+384>: move $1, $6
0x400c18 <+388>: sc $1, 0($2) -> End of sequence
0x400c1c <+392>: beqz $1, -20
0x400c20 <+396>: addiu $3, $zero, 1
0x400c24 <+400>: sync
0x400c28 <+404>: bnez $3, 16---> Target of branch from sequence
Considering above example, while single stepping from LL instruction, LLDB
should stop at instruction
after the end of sequence (instead of stopping at instruction next to LL).
There can be multiple exit/end points to atomic sequence.
1. SC instruction
2. Branch instructions in atomic sequence that jump outside sequence.
So to handle this, LLDB should place breakpoints at multiple locations:
1. Breakpoint at instruction after SC instruction (i.e at 0x400c1c in above ex)
2. Breakpoints at target addresses of branch instructions (if the branch target
address is outside the sequence)
i.e at 0x400c28, target of "bne $4, $5, 28" instruction.
These breakpoint addresses are determined by EmulateInstruction.
This patch makes few assumptions:
1. Assumes that no atomic sequence for mips is longer than 16 instructions. i.e
scan upto maximum 16 instructions from LL to find end of sequence.
2. Assumes that the atomic sequence ends with a sc/scd instruction. So if we
dont find "sc/scd" instruction then do not put any breakpoint.
i.e fallback to the standard single-step code.
Testcase:
This patch also adds a testcase "TestStepInAtomicSequence.py" to test this
change (currently enabled for MIPS only).
The test finds starting instruction of atomic sequence, runs till that
instruction then does a single step and
finally verifies that we have stopped after end of sequence.
Repository:
rL LLVM
http://reviews.llvm.org/D17535
Files:
packages/Python/lldbsuite/test/functionalities/single_step_atomic_sequence/Makefile
packages/Python/lldbsuite/test/functionalities/single_step_atomic_sequence/TestStepInAtomicSequence.py
packages/Python/lldbsuite/test/functionalities/single_step_atomic_sequence/main.cpp
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
source/Plugins/Process/Linux/NativeProcessLinux.cpp
source/Plugins/Process/Linux/NativeProcessLinux.h
Index: packages/Python/lldbsuite/test/functionalities/single_step_atomic_sequence/main.cpp
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/single_step_atomic_sequence/main.cpp
@@ -0,0 +1,21 @@
+#include
+using namespace std;
+
+std::atomic ai;
+
+int tst_val= 4;
+int new_val= 5;
+bool exchanged= false;
+
+int main()
+{
+ai= 3;
+
+// tst_val != ai ==> tst_val is modified
+exchanged= ai.compare_exchange_strong( tst_val, new_val );
+
+// tst_val == ai ==> ai is modified
+exchanged= ai.compare_exchange_strong( tst_val, new_val );
+
+return 0;
+}
Index: packages/Python/lldbsuite/test/functionalities/single_step_atomic_sequence/TestStepInAtomicSequence.py
===
--- /dev/null
+++ packages/Python/lldbsuite/test/functionalities/single_step_atomic_sequence/TestStepInAtomicSequence.py
@@ -0,0 +1,108 @@
+"""
+Test to single step from atomic sequence
+"""
+
+from __future__ import print_function
+
+import os, time
+import re
+import unittest2
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+class StepInAtomicSequenceAPITestCase(TestBase):
+
+mydir = TestBase.compute_mydir(__file__)
+
+@skipIf(archs=no_match(re.compile('mips*')))
+def test(self):
+self.build()
+exe = os.path.join(os.getcwd(), "a.out")
+self.expect("file " + exe,
+patterns = [ "Current executable set to .*a.out.*" ])
+
+# Create a target by the debugger.
+target = self.dbg.CreateTarget(exe)
+self.assertTrue(target, VALID_TARGET)
+
+breakpoint = target.BreakpointCreateByName('ma
Re: [Lldb-commits] [lldb] r261206 - [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
Hi Hans,
This change fixes expression related tests for MIPS release 6 architecture
(mipsr6).
Regards,
Bhushan
-Original Message-
From: hwennb...@google.com [mailto:hwennb...@google.com] On Behalf Of Hans
Wennborg
Sent: 23 February 2016 00:25
To: Bhushan Attarde
Cc: lldb-commits@lists.llvm.org; Greg Clayton (gclay...@apple.com);
ztur...@google.com
Subject: Re: [Lldb-commits] [lldb] r261206 - [LLDB][MIPS] Provide CPU string to
compiler for appropriate code generation for MIPS
Hi Bhushan,
This looks more like new functionality than a regression fix from 3.7.
As such, I'd rather not merge it to 3.8 this late in the process.
Thanks,
Hans
On Sun, Feb 21, 2016 at 9:08 PM, Bhushan Attarde
wrote:
> Hi Hans,
>
> Could you please add this (r261206) to the release branch?
>
> Thanks,
> Bhushan
>
>
> -Original Message-
> From: lldb-commits [mailto:lldb-commits-boun...@lists.llvm.org] On
> Behalf Of Bhushan D. Attarde via lldb-commits
> Sent: 18 February 2016 17:23
> To: lldb-commits@lists.llvm.org
> Subject: [Lldb-commits] [lldb] r261206 - [LLDB][MIPS] Provide CPU
> string to compiler for appropriate code generation for MIPS
>
> Author: bhushan.attarde
> Date: Thu Feb 18 05:53:28 2016
> New Revision: 261206
>
> URL: http://llvm.org/viewvc/llvm-project?rev=261206&view=rev
> Log:
> [LLDB][MIPS] Provide CPU string to compiler for appropriate code
> generation for MIPS
>
> SUMMARY:
> This patch implements ArchSpec::GetClangTargetCPU() that provides string
> representing current architecture as a target CPU.
> This string is then passed to tools like clang so that they generate
> correct code for that target.
>
> Reviewers: clayborg, zturner
> Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
> Differential Revision: http://reviews.llvm.org/D17022
>
> Modified:
> lldb/trunk/include/lldb/Core/ArchSpec.h
> lldb/trunk/source/Core/ArchSpec.cpp
>
> lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser
> .cpp
>
> Modified: lldb/trunk/include/lldb/Core/ArchSpec.h
> URL:
> http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/ArchS
> pec.h?rev=261206&r1=261205&r2=261206&view=diff
> ==
>
> --- lldb/trunk/include/lldb/Core/ArchSpec.h (original)
> +++ lldb/trunk/include/lldb/Core/ArchSpec.h Thu Feb 18 05:53:28 2016
> @@ -288,6 +288,16 @@ public:
> GetArchitectureName () const;
>
>
> //--
> +/// Returns a string representing current architecture as a target CPU
> +/// for tools like compiler, disassembler etc.
> +///
> +/// @return A string representing target CPU for the current
> +/// architecture.
> +//--
> +std::string
> +GetClangTargetCPU ();
> +
> +
> + //--
> /// Clears the object state.
> ///
> /// Clears the object state back to a default invalid state.
>
> Modified: lldb/trunk/source/Core/ArchSpec.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ArchSpec.cp
> p?rev=261206&r1=261205&r2=261206&view=diff
> ==
>
> --- lldb/trunk/source/Core/ArchSpec.cpp (original)
> +++ lldb/trunk/source/Core/ArchSpec.cpp Thu Feb 18 05:53:28 2016
> @@ -511,6 +511,56 @@ ArchSpec::GetArchitectureName () const
> return "unknown";
> }
>
> +std::string
> +ArchSpec::GetClangTargetCPU ()
> +{
> +std::string cpu;
> +const llvm::Triple::ArchType machine = GetMachine();
> +
> +if (machine == llvm::Triple::mips ||
> +machine == llvm::Triple::mipsel ||
> +machine == llvm::Triple::mips64 ||
> +machine == llvm::Triple::mips64el)
> +{
> +switch (m_core)
> +{
> +case ArchSpec::eCore_mips32:
> +case ArchSpec::eCore_mips32el:
> +cpu = "mips32"; break;
> +case ArchSpec::eCore_mips32r2:
> +case ArchSpec::eCore_mips32r2el:
> +cpu = "mips32r2"; break;
> +case ArchSpec::eCore_mips32r3:
> +case ArchSpec::eCore_mips32r3el:
> +cpu = "mips32r3"; break;
> +case ArchSpec::eCore_mips32r5:
> +case ArchSpec::eCore_mips32r5el:
> +cpu = "mips32r5"; break;
> +case ArchSpec::eCore_mips32r6:
> +case ArchSpec::eCore_mips32r6el:
> +cpu = "mips32r6"; break;
> +case ArchSpec::eCore_mips64:
> +case ArchSpec::eCore_mips64el:
> +cpu = "mips64"; break;
> +case ArchSpec::eCore_mips64r2:
> +case ArchSpec::eCore_mips64r2el:
> +cpu = "mips64r2"; break;
> +case ArchSpec::eCore_mips64r3:
> +case ArchSpec::eCore_mips64r3el:
> +cpu = "mips64r3"; break;
> +case ArchSpec::eCore
Re: [Lldb-commits] [lldb] r261206 - [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
These were failures with 3.7 for mipsr6.
Regards,
Bhushan
From: hwennb...@google.com [hwennb...@google.com] on behalf of Hans Wennborg
[h...@chromium.org]
Sent: Tuesday, February 23, 2016 10:29 PM
To: Bhushan Attarde
Cc: lldb-commits@lists.llvm.org; Greg Clayton (gclay...@apple.com);
ztur...@google.com
Subject: Re: [Lldb-commits] [lldb] r261206 - [LLDB][MIPS] Provide CPU string to
compiler for appropriate code generation for MIPS
Did those tests pass for mipsr6 with 3.7?
On Tue, Feb 23, 2016 at 3:19 AM, Bhushan Attarde
wrote:
> Hi Hans,
>
> This change fixes expression related tests for MIPS release 6 architecture
> (mipsr6).
>
>
> Regards,
> Bhushan
>
> -Original Message-
> From: hwennb...@google.com [mailto:hwennb...@google.com] On Behalf Of Hans
> Wennborg
> Sent: 23 February 2016 00:25
> To: Bhushan Attarde
> Cc: lldb-commits@lists.llvm.org; Greg Clayton (gclay...@apple.com);
> ztur...@google.com
> Subject: Re: [Lldb-commits] [lldb] r261206 - [LLDB][MIPS] Provide CPU string
> to compiler for appropriate code generation for MIPS
>
> Hi Bhushan,
>
> This looks more like new functionality than a regression fix from 3.7.
> As such, I'd rather not merge it to 3.8 this late in the process.
>
> Thanks,
> Hans
>
> On Sun, Feb 21, 2016 at 9:08 PM, Bhushan Attarde
> wrote:
>> Hi Hans,
>>
>> Could you please add this (r261206) to the release branch?
>>
>> Thanks,
>> Bhushan
>>
>>
>> -Original Message-
>> From: lldb-commits [mailto:lldb-commits-boun...@lists.llvm.org] On
>> Behalf Of Bhushan D. Attarde via lldb-commits
>> Sent: 18 February 2016 17:23
>> To: lldb-commits@lists.llvm.org
>> Subject: [Lldb-commits] [lldb] r261206 - [LLDB][MIPS] Provide CPU
>> string to compiler for appropriate code generation for MIPS
>>
>> Author: bhushan.attarde
>> Date: Thu Feb 18 05:53:28 2016
>> New Revision: 261206
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=261206&view=rev
>> Log:
>> [LLDB][MIPS] Provide CPU string to compiler for appropriate code
>> generation for MIPS
>>
>> SUMMARY:
>> This patch implements ArchSpec::GetClangTargetCPU() that provides string
>> representing current architecture as a target CPU.
>> This string is then passed to tools like clang so that they generate
>> correct code for that target.
>>
>> Reviewers: clayborg, zturner
>> Subscribers: mohit.bhakkad, sagar, jaydeep, lldb-commits
>> Differential Revision: http://reviews.llvm.org/D17022
>>
>> Modified:
>> lldb/trunk/include/lldb/Core/ArchSpec.h
>> lldb/trunk/source/Core/ArchSpec.cpp
>>
>> lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser
>> .cpp
>>
>> Modified: lldb/trunk/include/lldb/Core/ArchSpec.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/ArchS
>> pec.h?rev=261206&r1=261205&r2=261206&view=diff
>> ==
>>
>> --- lldb/trunk/include/lldb/Core/ArchSpec.h (original)
>> +++ lldb/trunk/include/lldb/Core/ArchSpec.h Thu Feb 18 05:53:28 2016
>> @@ -288,6 +288,16 @@ public:
>> GetArchitectureName () const;
>>
>>
>> //--
>> +/// Returns a string representing current architecture as a target CPU
>> +/// for tools like compiler, disassembler etc.
>> +///
>> +/// @return A string representing target CPU for the current
>> +/// architecture.
>> +//--
>> +std::string
>> +GetClangTargetCPU ();
>> +
>> +
>> + //--
>> /// Clears the object state.
>> ///
>> /// Clears the object state back to a default invalid state.
>>
>> Modified: lldb/trunk/source/Core/ArchSpec.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ArchSpec.cp
>> p?rev=261206&r1=261205&r2=261206&view=diff
>> ==
>>
>> --- lldb/trunk/source/Core/ArchSpec.cpp (original)
>> +++ lldb/trunk/source/Core/ArchSpec.cpp Thu Feb 18 05:53:28 2016
>> @@ -511,6 +511,56 @@ ArchSpec::GetArchitectureName () const
>> return "unknown";
>> }
>>
>> +std::string
>> +ArchSpec::GetClangTargetCPU ()
>> +{
>> +std::string cpu;
>> +const llvm::Triple::ArchType machine = GetMachine();
>> +
>> +if (machine == llvm::Triple::mips ||
>> +machine == llvm::Triple::mipsel ||
>> +machine == llvm::Triple::mips64 ||
>> +machine == llvm::Triple::mips64el)
>> +{
>> +switch (m_core)
>> +{
>> +case ArchSpec::eCore_mips32:
>> +case ArchSpec::eCore_mips32el:
>> +cpu = "mips32"; break;
>> +case ArchSpec::eCore_mips32r2:
>> +case ArchSpec::eCore_mips32r2el:
>> +cpu = "mips32r2"; break;
>> +case ArchSpec::eCore_mips32r3:
>> +case ArchSp
Re: [Lldb-commits] [PATCH] D17535: [LLDB][MIPS] Single step atomic sequences
bhushan added a comment. In MIPS, we can not put a breakpoint in middle of an atomic sequence. If we do so (and that breakpoint is hit) then continuing from breakpoint address will cause "SC" to fail due to a breakpoint exception. SC fails when there’s been any exception serviced since the LL. This will then become a "never ending" sequence. Similarly when doing assembly level debugging of an atomic sequence if we step only 1 instruction (as we are debugging assembly code) we will end up putting breakpoint on next instruction (within atomic sequence) and will cause "SC" to fail because of reason mentioned above. That means an atomic sequence, starting with LL and ending with SC needs to be treated as a "single instruction block". Repository: rL LLVM http://reviews.llvm.org/D17535 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D17022: [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
bhushan added a comment. Hi @zturner, Can you please "accept" this revision so that I can "close" this one? Repository: rL LLVM http://reviews.llvm.org/D17022 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D17022: [LLDB][MIPS] Provide CPU string to compiler for appropriate code generation for MIPS
bhushan closed this revision. bhushan added a comment. Closed by commit http://reviews.llvm.org/rL261206 Repository: rL LLVM http://reviews.llvm.org/D17022 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D11930: [MIPS]Handle floating point and aggregate return types in SysV-mips [32 bit] ABI
bhushan created this revision.
bhushan added a reviewer: clayborg.
bhushan added subscribers: lldb-commits, jaydeep, sagar, nitesh.jain,
mohit.bhakkad.
bhushan set the repository for this revision to rL LLVM.
This patch adds support of floating point and aggregate return types in
GetReturnValueObjectImpl() for mips32
Repository:
rL LLVM
http://reviews.llvm.org/D11930
Files:
source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
Index: source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
===
--- source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
+++ source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
@@ -424,14 +424,15 @@
return return_valobj_sp;
bool is_signed;
+bool is_complex;
+uint32_t count;
// In MIPS register "r2" (v0) holds the integer function return values
const RegisterInfo *r2_reg_info = reg_ctx->GetRegisterInfoByName("r2", 0);
+size_t bit_width = return_clang_type.GetBitSize(&thread);
if (return_clang_type.IsIntegerType (is_signed))
{
-size_t bit_width = return_clang_type.GetBitSize(&thread);
-
switch (bit_width)
{
default:
@@ -473,6 +474,52 @@
uint32_t ptr =
thread.GetRegisterContext()->ReadRegisterAsUnsigned(r2_reg_info, 0) &
UINT32_MAX;
value.GetScalar() = ptr;
}
+else if (return_clang_type.IsAggregateType ())
+{
+// Structure/Vector is always passed in memory and pointer to that
memory is passed in r2.
+uint64_t mem_address =
reg_ctx->ReadRegisterAsUnsigned(reg_ctx->GetRegisterInfoByName("r2", 0), 0);
+// We have got the address. Create a memory object out of it
+return_valobj_sp = ValueObjectMemory::Create (&thread,
+ "",
+ Address (mem_address,
NULL),
+ return_clang_type);
+return return_valobj_sp;
+}
+else if (return_clang_type.IsFloatingPointType (count, is_complex))
+{
+const RegisterInfo *f0_info = reg_ctx->GetRegisterInfoByName("f0", 0);
+const RegisterInfo *f1_info = reg_ctx->GetRegisterInfoByName("f1", 0);
+
+if (count == 1 && !is_complex)
+{
+switch (bit_width)
+{
+default:
+return return_valobj_sp;
+case 64:
+{
+static_assert(sizeof(double) == sizeof(uint64_t), "");
+uint64_t raw_value;
+raw_value = reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) &
UINT32_MAX;
+raw_value |=
((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(f1_info, 0) & UINT32_MAX)) << 32;
+value.GetScalar() = *reinterpret_cast(&raw_value);
+break;
+}
+case 32:
+{
+static_assert(sizeof(float) == sizeof(uint32_t), "");
+uint32_t raw_value =
reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) & UINT32_MAX;
+value.GetScalar() = *reinterpret_cast(&raw_value);
+break;
+}
+}
+}
+else
+{
+// not handled yet
+return return_valobj_sp;
+}
+}
else
{
// not handled yet
Index: source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
===
--- source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
+++ source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
@@ -424,14 +424,15 @@
return return_valobj_sp;
bool is_signed;
+bool is_complex;
+uint32_t count;
// In MIPS register "r2" (v0) holds the integer function return values
const RegisterInfo *r2_reg_info = reg_ctx->GetRegisterInfoByName("r2", 0);
+size_t bit_width = return_clang_type.GetBitSize(&thread);
if (return_clang_type.IsIntegerType (is_signed))
{
-size_t bit_width = return_clang_type.GetBitSize(&thread);
-
switch (bit_width)
{
default:
@@ -473,6 +474,52 @@
uint32_t ptr = thread.GetRegisterContext()->ReadRegisterAsUnsigned(r2_reg_info, 0) & UINT32_MAX;
value.GetScalar() = ptr;
}
+else if (return_clang_type.IsAggregateType ())
+{
+// Structure/Vector is always passed in memory and pointer to that memory is passed in r2.
+uint64_t mem_address = reg_ctx->ReadRegisterAsUnsigned(reg_ctx->GetRegisterInfoByName("r2", 0), 0);
+// We have got the address. Create a memory object out of it
+return_valobj_sp = ValueObjectMemory::Create (&thread,
+ "",
+ Address (mem_address, NULL),
+
Re: [Lldb-commits] [PATCH] D11930: [MIPS]Handle floating point and aggregate return types in SysV-mips [32 bit] ABI
bhushan updated this revision to Diff 32038.
bhushan added a comment.
Addresses review comments. (Initialized variables with default values).
Repository:
rL LLVM
http://reviews.llvm.org/D11930
Files:
source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
Index: source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
===
--- source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
+++ source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
@@ -424,14 +424,15 @@
return return_valobj_sp;
bool is_signed;
+bool is_complex = false;
+uint32_t count = 0;
// In MIPS register "r2" (v0) holds the integer function return values
const RegisterInfo *r2_reg_info = reg_ctx->GetRegisterInfoByName("r2", 0);
+size_t bit_width = return_clang_type.GetBitSize(&thread);
if (return_clang_type.IsIntegerType (is_signed))
{
-size_t bit_width = return_clang_type.GetBitSize(&thread);
-
switch (bit_width)
{
default:
@@ -473,6 +474,52 @@
uint32_t ptr =
thread.GetRegisterContext()->ReadRegisterAsUnsigned(r2_reg_info, 0) &
UINT32_MAX;
value.GetScalar() = ptr;
}
+else if (return_clang_type.IsAggregateType ())
+{
+// Structure/Vector is always passed in memory and pointer to that
memory is passed in r2.
+uint64_t mem_address =
reg_ctx->ReadRegisterAsUnsigned(reg_ctx->GetRegisterInfoByName("r2", 0), 0);
+// We have got the address. Create a memory object out of it
+return_valobj_sp = ValueObjectMemory::Create (&thread,
+ "",
+ Address (mem_address,
NULL),
+ return_clang_type);
+return return_valobj_sp;
+}
+else if (return_clang_type.IsFloatingPointType (count, is_complex))
+{
+const RegisterInfo *f0_info = reg_ctx->GetRegisterInfoByName("f0", 0);
+const RegisterInfo *f1_info = reg_ctx->GetRegisterInfoByName("f1", 0);
+
+if (count == 1 && !is_complex)
+{
+switch (bit_width)
+{
+default:
+return return_valobj_sp;
+case 64:
+{
+static_assert(sizeof(double) == sizeof(uint64_t), "");
+uint64_t raw_value;
+raw_value = reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) &
UINT32_MAX;
+raw_value |=
((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(f1_info, 0) & UINT32_MAX)) << 32;
+value.GetScalar() = *reinterpret_cast(&raw_value);
+break;
+}
+case 32:
+{
+static_assert(sizeof(float) == sizeof(uint32_t), "");
+uint32_t raw_value =
reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) & UINT32_MAX;
+value.GetScalar() = *reinterpret_cast(&raw_value);
+break;
+}
+}
+}
+else
+{
+// not handled yet
+return return_valobj_sp;
+}
+}
else
{
// not handled yet
Index: source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
===
--- source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
+++ source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
@@ -424,14 +424,15 @@
return return_valobj_sp;
bool is_signed;
+bool is_complex = false;
+uint32_t count = 0;
// In MIPS register "r2" (v0) holds the integer function return values
const RegisterInfo *r2_reg_info = reg_ctx->GetRegisterInfoByName("r2", 0);
+size_t bit_width = return_clang_type.GetBitSize(&thread);
if (return_clang_type.IsIntegerType (is_signed))
{
-size_t bit_width = return_clang_type.GetBitSize(&thread);
-
switch (bit_width)
{
default:
@@ -473,6 +474,52 @@
uint32_t ptr = thread.GetRegisterContext()->ReadRegisterAsUnsigned(r2_reg_info, 0) & UINT32_MAX;
value.GetScalar() = ptr;
}
+else if (return_clang_type.IsAggregateType ())
+{
+// Structure/Vector is always passed in memory and pointer to that memory is passed in r2.
+uint64_t mem_address = reg_ctx->ReadRegisterAsUnsigned(reg_ctx->GetRegisterInfoByName("r2", 0), 0);
+// We have got the address. Create a memory object out of it
+return_valobj_sp = ValueObjectMemory::Create (&thread,
+ "",
+ Address (mem_address, NULL),
+ return_clang_type);
+return return_valobj_sp;
+}
+else if (return_clang_type.IsFloatingPointType (count, is_complex))
+{
+
Re: [Lldb-commits] [PATCH] D11930: [MIPS]Handle floating point and aggregate return types in SysV-mips [32 bit] ABI
bhushan closed this revision. bhushan added a comment. Committed in revision 245020 Repository: rL LLVM http://reviews.llvm.org/D11930 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D11641: Handle floating point and aggregate return types in SysV-mips64 ABI
bhushan closed this revision. bhushan added a comment. Committed in revision 245026 Repository: rL LLVM http://reviews.llvm.org/D11641 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [PATCH] D11449: Handle old style 'S' packet correctly
bhushan closed this revision. bhushan added a comment. Closed by Commit http://reviews.llvm.org/rL243091 Repository: rL LLVM http://reviews.llvm.org/D11449 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
Re: [Lldb-commits] [lldb] r245020 - [MIPS]Handle floating point and aggregate return types in SysV-mips [32 bit] ABI
Hi Hans,
Could you please merge this to the release branch?
Thanks
Bhushan
-Original Message-
From: lldb-commits [mailto:lldb-commits-boun...@lists.llvm.org] On Behalf Of
Bhushan D. Attarde via lldb-commits
Sent: 14 August 2015 09:11
To: lldb-commits@lists.llvm.org
Subject: [Lldb-commits] [lldb] r245020 - [MIPS]Handle floating point and
aggregate return types in SysV-mips [32 bit] ABI
Author: bhushan.attarde
Date: Thu Aug 13 22:40:31 2015
New Revision: 245020
URL: http://llvm.org/viewvc/llvm-project?rev=245020&view=rev
Log:
[MIPS]Handle floating point and aggregate return types in SysV-mips [32 bit] ABI
SUMMARY:
This patch adds support of floating point and aggregate return types in
GetReturnValueObjectImpl() for mips32
Reviewers: clayborg
Subscribers: mohit.bhakkad, nitesh.jain, sagar, jaydeep, lldb-commits
Differential Revision: http://reviews.llvm.org/D11930
Modified:
lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
Modified: lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp?rev=245020&r1=245019&r2=245020&view=diff
==
--- lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp (original)
+++ lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp Thu Aug 13
22:40:31 2015
@@ -423,15 +423,16 @@ ABISysV_mips::GetReturnValueObjectImpl (
if (!reg_ctx)
return return_valobj_sp;
-bool is_signed;
+bool is_signed = false;
+bool is_complex = false;
+uint32_t count = 0;
// In MIPS register "r2" (v0) holds the integer function return values
const RegisterInfo *r2_reg_info = reg_ctx->GetRegisterInfoByName("r2", 0);
+size_t bit_width = return_clang_type.GetBitSize(&thread);
if (return_clang_type.IsIntegerType (is_signed))
{
-size_t bit_width = return_clang_type.GetBitSize(&thread);
-
switch (bit_width)
{
default:
@@ -473,6 +474,52 @@ ABISysV_mips::GetReturnValueObjectImpl (
uint32_t ptr =
thread.GetRegisterContext()->ReadRegisterAsUnsigned(r2_reg_info, 0) &
UINT32_MAX;
value.GetScalar() = ptr;
}
+else if (return_clang_type.IsAggregateType ())
+{
+// Structure/Vector is always passed in memory and pointer to that
memory is passed in r2.
+uint64_t mem_address =
reg_ctx->ReadRegisterAsUnsigned(reg_ctx->GetRegisterInfoByName("r2", 0), 0);
+// We have got the address. Create a memory object out of it
+return_valobj_sp = ValueObjectMemory::Create (&thread,
+ "",
+ Address (mem_address,
NULL),
+ return_clang_type);
+return return_valobj_sp;
+}
+else if (return_clang_type.IsFloatingPointType (count, is_complex))
+{
+const RegisterInfo *f0_info = reg_ctx->GetRegisterInfoByName("f0", 0);
+const RegisterInfo *f1_info = reg_ctx->GetRegisterInfoByName("f1", 0);
+
+if (count == 1 && !is_complex)
+{
+switch (bit_width)
+{
+default:
+return return_valobj_sp;
+case 64:
+{
+static_assert(sizeof(double) == sizeof(uint64_t), "");
+uint64_t raw_value;
+raw_value = reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) &
UINT32_MAX;
+raw_value |=
((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(f1_info, 0) & UINT32_MAX)) << 32;
+value.GetScalar() = *reinterpret_cast(&raw_value);
+break;
+}
+case 32:
+{
+static_assert(sizeof(float) == sizeof(uint32_t), "");
+uint32_t raw_value =
reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) & UINT32_MAX;
+value.GetScalar() = *reinterpret_cast(&raw_value);
+break;
+}
+}
+}
+else
+{
+// not handled yet
+return return_valobj_sp;
+}
+}
else
{
// not handled yet
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[Lldb-commits] [PATCH] D12184: [MIPS] Avoid breakpoint in delay slot
bhushan created this revision.
bhushan added a reviewer: clayborg.
bhushan added subscribers: lldb-commits, jaydeep, sagar, nitesh.jain,
mohit.bhakkad.
bhushan set the repository for this revision to rL LLVM.
In MIPS, when a breakpoint is hit in a delay slot then the PC points to the
previous branch/jump instruction. In this case, CAUSE.BD bit is set and we can
correct the PC accordingly.
However doing a single step at this point will continue execution from the
current PC and not from the target of previous branch/jump instruction.
Solution to this is to not allow breakpoint in a delay slot and move it to
previous branch/jump instruction (which will have same effect).
When user tries to set breakpoint by address then this patch checks if the
instruction at that address is a delay slot instruction and if it is then the
breakpoint is moved to its previous instruction.
Repository:
rL LLVM
http://reviews.llvm.org/D12184
Files:
include/lldb/Core/Disassembler.h
include/lldb/Target/Target.h
source/Core/Disassembler.cpp
source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h
source/Target/Target.cpp
Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -44,6 +44,8 @@
#include "lldb/Interpreter/Property.h"
#include "lldb/Symbol/ClangASTContext.h"
#include "lldb/Symbol/ObjectFile.h"
+#include "lldb/Symbol/Function.h"
+#include "lldb/Symbol/Symbol.h"
#include "lldb/Target/LanguageRuntime.h"
#include "lldb/Target/ObjCLanguageRuntime.h"
#include "lldb/Target/Process.h"
@@ -344,6 +346,10 @@
Target::CreateBreakpoint (lldb::addr_t addr, bool internal, bool hardware)
{
Address so_addr;
+uint32_t shift_size = 0;
+
+Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_BREAKPOINTS));
+
// Attempt to resolve our load address if possible, though it is ok if
// it doesn't resolve to section/offset.
@@ -354,6 +360,17 @@
// The address didn't resolve, so just set this as an absolute address
so_addr.SetOffset (addr);
}
+
+// Check if the instruction at this address is in delay slot.
+// If it is, then move the breakpoint to it's previous instruction.
+shift_size = AdjustBreakpointInDelaySlot (addr);
+if (shift_size)
+{
+so_addr.SetOffset (so_addr.GetOffset () - shift_size);
+if (log)
+log->Printf ("Target::%s Breakpoint at 0x%8.8" PRIx64 " is shifted to 0x%8.8" PRIx64 " \n", __FUNCTION__, addr, (addr - shift_size));
+}
+
BreakpointSP bp_sp (CreateBreakpoint(so_addr, internal, hardware));
return bp_sp;
}
@@ -2134,6 +2151,163 @@
return opcode_addr;
}
+uint32_t
+Target::AdjustBreakpointInDelaySlot (lldb::addr_t addr)
+{
+uint32_t shift_size = 0;
+Address resolved_addr;
+SectionLoadList §ion_load_list = GetSectionLoadList();
+
+if (section_load_list.IsEmpty())
+// No sections are loaded, so we must assume we are not running yet
+// and need to operate only on file address.
+m_images.ResolveFileAddress (addr, resolved_addr);
+else
+section_load_list.ResolveLoadAddress(addr, resolved_addr);
+
+switch (m_arch.GetMachine())
+{
+default:
+break;
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+{
+addr_t function_start = 0;
+addr_t current_offset = 0;
+uint32_t loop_count = 0;
+uint32_t arch_flags = m_arch.GetFlags ();
+bool IsMips16 = arch_flags & ArchSpec::eMIPSAse_mips16;
+bool IsMicromips = arch_flags & ArchSpec::eMIPSAse_micromips;
+
+// Get the function boundaries to make sure we don't scan back before the beginning of the current function.
+ModuleSP temp_addr_module_sp (resolved_addr.GetModule());
+if (temp_addr_module_sp)
+{
+SymbolContext sc;
+uint32_t resolve_scope = eSymbolContextFunction | eSymbolContextSymbol;
+uint32_t resolved_mask = temp_addr_module_sp->ResolveSymbolContextForAddress(resolved_addr, resolve_scope, sc);
+if (sc.function)
+{
+function_start = sc.function->GetAddressRange().GetBaseAddress().GetLoadAddress(this);
+if (function_start == LLDB_INVALID_ADDRESS)
+function_start = sc.function->GetAddressRange().GetBaseAddress().GetFileAddress();
+}
+else if (sc.symbol)
+{
+Address sym_addr = sc.symbol->GetAddress();
+function_start = sym_addr.GetFileAddress();
+}
+current_offset = addr - function_start;
+}
+
+// If breakpoint address is start of function then we dont have to do anything.
+if (current_offset == 0)
+return shift_siz
Re: [Lldb-commits] [PATCH] D12184: [MIPS] Avoid breakpoint in delay slot
bhushan updated this revision to Diff 33063.
bhushan added a comment.
Addressed review comments.
1. Introduced Target::GetBreakableLoadAddress() instead of
Target::AdjustBreakpointInDelaySlot() so that it should look more generic and
targets can calculate the new breakpoint address based on whatever reason
applicable to them (not restricting it to a delay-slot only).
2. Target::GetBreakableLoadAddress() does not do any work unless a target
requires it.
3. Logging is enabled (under the breakpoint channel) and now mentions a reason
why we changed the original breakpoint address. (In case of MIPS, the reason is
a delay slot).
Repository:
rL LLVM
http://reviews.llvm.org/D12184
Files:
include/lldb/Core/Disassembler.h
include/lldb/Target/Target.h
source/Core/Disassembler.cpp
source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h
source/Target/Target.cpp
Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -44,6 +44,8 @@
#include "lldb/Interpreter/Property.h"
#include "lldb/Symbol/ClangASTContext.h"
#include "lldb/Symbol/ObjectFile.h"
+#include "lldb/Symbol/Function.h"
+#include "lldb/Symbol/Symbol.h"
#include "lldb/Target/LanguageRuntime.h"
#include "lldb/Target/ObjCLanguageRuntime.h"
#include "lldb/Target/Process.h"
@@ -344,6 +346,10 @@
Target::CreateBreakpoint (lldb::addr_t addr, bool internal, bool hardware)
{
Address so_addr;
+
+// Check for any reason we want to move this breakpoint to other address.
+addr = GetBreakableLoadAddress(addr);
+
// Attempt to resolve our load address if possible, though it is ok if
// it doesn't resolve to section/offset.
@@ -2134,6 +2140,170 @@
return opcode_addr;
}
+lldb::addr_t
+Target::GetBreakableLoadAddress (lldb::addr_t addr)
+{
+addr_t breakable_addr = addr;
+Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_BREAKPOINTS));
+
+switch (m_arch.GetMachine())
+{
+default:
+break;
+case llvm::Triple::mips:
+case llvm::Triple::mipsel:
+case llvm::Triple::mips64:
+case llvm::Triple::mips64el:
+{
+addr_t function_start = 0;
+addr_t current_offset = 0;
+uint32_t loop_count = 0;
+Address resolved_addr;
+uint32_t arch_flags = m_arch.GetFlags ();
+bool IsMips16 = arch_flags & ArchSpec::eMIPSAse_mips16;
+bool IsMicromips = arch_flags & ArchSpec::eMIPSAse_micromips;
+SectionLoadList §ion_load_list = GetSectionLoadList();
+
+if (section_load_list.IsEmpty())
+// No sections are loaded, so we must assume we are not running yet
+// and need to operate only on file address.
+m_images.ResolveFileAddress (addr, resolved_addr);
+else
+section_load_list.ResolveLoadAddress(addr, resolved_addr);
+
+// Get the function boundaries to make sure we don't scan back before the beginning of the current function.
+ModuleSP temp_addr_module_sp (resolved_addr.GetModule());
+if (temp_addr_module_sp)
+{
+SymbolContext sc;
+uint32_t resolve_scope = eSymbolContextFunction | eSymbolContextSymbol;
+uint32_t resolved_mask = temp_addr_module_sp->ResolveSymbolContextForAddress(resolved_addr, resolve_scope, sc);
+if (sc.function)
+{
+function_start = sc.function->GetAddressRange().GetBaseAddress().GetLoadAddress(this);
+if (function_start == LLDB_INVALID_ADDRESS)
+function_start = sc.function->GetAddressRange().GetBaseAddress().GetFileAddress();
+}
+else if (sc.symbol)
+{
+Address sym_addr = sc.symbol->GetAddress();
+function_start = sym_addr.GetFileAddress();
+}
+current_offset = addr - function_start;
+}
+
+// If breakpoint address is start of function then we dont have to do anything.
+if (current_offset == 0)
+return breakable_addr;
+else
+loop_count = current_offset / 2;
+
+if (loop_count > 3)
+{
+// Scan previous 6 bytes
+if (IsMips16 | IsMicromips)
+loop_count = 3;
+// For mips-only, instructions are always 4 bytes, so scan previous 4 bytes only.
+else
+loop_count = 2;
+}
+
+// Create Disassembler Instance
+lldb::DisassemblerSP disasm_sp (Disassembler::FindPlugin(m_arch, NULL, NULL));
+
+ExecutionContext exe_ctx;
+CalculateExecutionContext(exe_ctx);
+InstructionList instruction_list;
+InstructionSP prev_insn;
+bool prefer_file_cache = true; // Read from file
+uint32_t inst_to_choose = 0;
+
+for (uint32_t i = 1; i <= loop_count; i++)
+
[Lldb-commits] [PATCH] D12794: [MIPS] Add support for DT_MIPS_RLD_MAP_REL
bhushan created this revision.
bhushan added a reviewer: clayborg.
bhushan added subscribers: lldb-commits, jaydeep, sagar, mohit.bhakkad,
nitesh.jain.
bhushan set the repository for this revision to rL LLVM.
MIPS executables now uses DT_MIPS_RLD_MAP_REL to support PIE.
This tag allows debugging of MIPS position independent executables and provides
access to shared library information.
DT_MIPS_RLD_MAP_REL contains an offset from the address of the DT slot to the
address of the dynamic link structure.
This patch provides support for DT_MIPS_RLD_MAP_REL tag in LLDB.
Repository:
rL LLVM
http://reviews.llvm.org/D12794
Files:
source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
Index: source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1097,16 +1097,34 @@
addr_t offset = i * dynsym_hdr->sh_entsize + GetAddressByteSize();
return Address(dynsym_section_sp, offset);
}
-else if (symbol.d_tag == DT_MIPS_RLD_MAP && target)
+// MIPS executables uses DT_MIPS_RLD_MAP_REL to support PIE.
DT_MIPS_RLD_MAP exists in non-PIE.
+else if ((symbol.d_tag == DT_MIPS_RLD_MAP || symbol.d_tag ==
DT_MIPS_RLD_MAP_REL) && target)
{
addr_t offset = i * dynsym_hdr->sh_entsize + GetAddressByteSize();
addr_t dyn_base = dynsym_section_sp->GetLoadBaseAddress(target);
if (dyn_base == LLDB_INVALID_ADDRESS)
return Address();
-Address addr;
Error error;
-if (target->ReadPointerFromMemory(dyn_base + offset, false, error,
addr))
-return addr;
+if (symbol.d_tag == DT_MIPS_RLD_MAP)
+{
+// DT_MIPS_RLD_MAP tag stores an absolute address of the debug
pointer.
+Address addr;
+if (target->ReadPointerFromMemory(dyn_base + offset, false,
error, addr))
+return addr;
+}
+if (symbol.d_tag == DT_MIPS_RLD_MAP_REL)
+{
+// DT_MIPS_RLD_MAP_REL tag stores the offset to the debug
pointer, relative to the address of the tag.
+uint64_t rel_offset;
+rel_offset = target->ReadUnsignedIntegerFromMemory(dyn_base +
offset, false, GetAddressByteSize(), UINT64_MAX, error);
+if (error.Success() && rel_offset != UINT64_MAX)
+{
+Address addr;
+addr_t debug_ptr_address = dyn_base + (offset -
GetAddressByteSize()) + rel_offset;
+addr.SetOffset (debug_ptr_address);
+return addr;
+}
+}
}
}
Index: source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1097,16 +1097,34 @@
addr_t offset = i * dynsym_hdr->sh_entsize + GetAddressByteSize();
return Address(dynsym_section_sp, offset);
}
-else if (symbol.d_tag == DT_MIPS_RLD_MAP && target)
+// MIPS executables uses DT_MIPS_RLD_MAP_REL to support PIE. DT_MIPS_RLD_MAP exists in non-PIE.
+else if ((symbol.d_tag == DT_MIPS_RLD_MAP || symbol.d_tag == DT_MIPS_RLD_MAP_REL) && target)
{
addr_t offset = i * dynsym_hdr->sh_entsize + GetAddressByteSize();
addr_t dyn_base = dynsym_section_sp->GetLoadBaseAddress(target);
if (dyn_base == LLDB_INVALID_ADDRESS)
return Address();
-Address addr;
Error error;
-if (target->ReadPointerFromMemory(dyn_base + offset, false, error, addr))
-return addr;
+if (symbol.d_tag == DT_MIPS_RLD_MAP)
+{
+// DT_MIPS_RLD_MAP tag stores an absolute address of the debug pointer.
+Address addr;
+if (target->ReadPointerFromMemory(dyn_base + offset, false, error, addr))
+return addr;
+}
+if (symbol.d_tag == DT_MIPS_RLD_MAP_REL)
+{
+// DT_MIPS_RLD_MAP_REL tag stores the offset to the debug pointer, relative to the address of the tag.
+uint64_t rel_offset;
+rel_offset = target->ReadUnsignedIntegerFromMemory(dyn_base + offset, false, GetAddressByteSize(), UINT64_MAX, error);
+if (error.Success() && rel_offset != UINT64_MAX)
+{
+Address addr;
+addr_t debug_ptr_address = dyn_base + (offset - GetAddressByteSize()) + rel_offset;
+addr.SetOffset (debug_ptr_address);
+return addr;
+}
+}
}
}
_
Re: [Lldb-commits] [PATCH] D12794: [MIPS] Add support for DT_MIPS_RLD_MAP_REL
bhushan closed this revision. bhushan added a comment. Closed by commit http://reviews.llvm.org/rL247666 Repository: rL LLVM http://reviews.llvm.org/D12794 ___ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D13154: [MIPS] Use Address::GetAddressClass() instead of elf flags to decide address space of an address
bhushan created this revision.
bhushan added a reviewer: clayborg.
bhushan added subscribers: lldb-commits, nitesh.jain, mohit.bhakkad, sagar,
jaydeep.
bhushan set the repository for this revision to rL LLVM.
In MIPS, an application elf can contain mixed code (mips + micromips) i.e some
functions in the application can be "micromips" and some functions can be
MIPS-only (non-micromips).
Micromips functions has compressed addresses (bit #0 set) and MIPS functions
has un-compressed addresses (bit #0 clear).
Such mixed-mode elf will have micromips specific bits set in its flags. That
means "IsMicromips" will be true even for non-micromips address.
This patch fixes this by using Address::GetAddressClass() to decide which
address space the address belongs to (instead of deciding this from elf's
flags).
Repository:
rL LLVM
http://reviews.llvm.org/D13154
Files:
source/Target/Target.cpp
Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2269,10 +2269,12 @@
uint32_t loop_count = 0;
Address resolved_addr;
uint32_t arch_flags = m_arch.GetFlags ();
-bool IsMips16 = arch_flags & ArchSpec::eMIPSAse_mips16;
-bool IsMicromips = arch_flags & ArchSpec::eMIPSAse_micromips;
SectionLoadList §ion_load_list = GetSectionLoadList();
+// Get opcode address
+addr = GetOpcodeLoadAddress (addr, eAddressClassCode);
+breakable_addr = addr;
+
if (section_load_list.IsEmpty())
// No sections are loaded, so we must assume we are not running yet
// and need to operate only on file address.
@@ -2310,7 +2312,7 @@
if (loop_count > 3)
{
// Scan previous 6 bytes
-if (IsMips16 | IsMicromips)
+if (resolved_addr.GetAddressClass() ==
eAddressClassCodeAlternateISA)
loop_count = 3;
// For mips-only, instructions are always 4 bytes, so scan
previous 4 bytes only.
else
Index: source/Target/Target.cpp
===
--- source/Target/Target.cpp
+++ source/Target/Target.cpp
@@ -2269,10 +2269,12 @@
uint32_t loop_count = 0;
Address resolved_addr;
uint32_t arch_flags = m_arch.GetFlags ();
-bool IsMips16 = arch_flags & ArchSpec::eMIPSAse_mips16;
-bool IsMicromips = arch_flags & ArchSpec::eMIPSAse_micromips;
SectionLoadList §ion_load_list = GetSectionLoadList();
+// Get opcode address
+addr = GetOpcodeLoadAddress (addr, eAddressClassCode);
+breakable_addr = addr;
+
if (section_load_list.IsEmpty())
// No sections are loaded, so we must assume we are not running yet
// and need to operate only on file address.
@@ -2310,7 +2312,7 @@
if (loop_count > 3)
{
// Scan previous 6 bytes
-if (IsMips16 | IsMicromips)
+if (resolved_addr.GetAddressClass() == eAddressClassCodeAlternateISA)
loop_count = 3;
// For mips-only, instructions are always 4 bytes, so scan previous 4 bytes only.
else
___
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