bhushan added a comment. In MIPS, we can not put a breakpoint in middle of an atomic sequence. If we do so (and that breakpoint is hit) then continuing from breakpoint address will cause "SC" to fail due to a breakpoint exception. SC fails when there’s been any exception serviced since the LL. This will then become a "never ending" sequence.
Similarly when doing assembly level debugging of an atomic sequence if we step only 1 instruction (as we are debugging assembly code) we will end up putting breakpoint on next instruction (within atomic sequence) and will cause "SC" to fail because of reason mentioned above. That means an atomic sequence, starting with LL and ending with SC needs to be treated as a "single instruction block". Repository: rL LLVM http://reviews.llvm.org/D17535 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
